1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDValue Res = SDValue();
37 // See if the target wants to custom expand this node.
38 if (CustomLowerNode(N, N->getValueType(ResNo), true))
41 switch (N->getOpcode()) {
44 cerr << "PromoteIntegerResult #" << ResNo << ": ";
45 N->dump(&DAG); cerr << "\n";
47 assert(0 && "Do not know how to promote this operator!");
49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
55 case ISD::CONVERT_RNDSAT:
56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
60 case ISD::EXTRACT_VECTOR_ELT:
61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
67 case ISD::SIGN_EXTEND_INREG:
68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
75 case ISD::SIGN_EXTEND:
76 case ISD::ZERO_EXTEND:
77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
102 case ISD::ATOMIC_LOAD_ADD:
103 case ISD::ATOMIC_LOAD_SUB:
104 case ISD::ATOMIC_LOAD_AND:
105 case ISD::ATOMIC_LOAD_OR:
106 case ISD::ATOMIC_LOAD_XOR:
107 case ISD::ATOMIC_LOAD_NAND:
108 case ISD::ATOMIC_LOAD_MIN:
109 case ISD::ATOMIC_LOAD_MAX:
110 case ISD::ATOMIC_LOAD_UMIN:
111 case ISD::ATOMIC_LOAD_UMAX:
112 case ISD::ATOMIC_SWAP:
113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
115 case ISD::ATOMIC_CMP_SWAP:
116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
119 // If the result is null then the sub-method took care of registering it.
121 SetPromotedInteger(SDValue(N, ResNo), Res);
124 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
125 // Sign-extend the new bits, and continue the assertion.
126 SDValue Op = SExtPromotedInteger(N->getOperand(0));
127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
128 Op.getValueType(), Op, N->getOperand(1));
131 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
132 // Zero the new bits, and continue the assertion.
133 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
135 Op.getValueType(), Op, N->getOperand(1));
138 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
139 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
142 N->getChain(), N->getBasePtr(),
143 Op2, N->getSrcValue(), N->getAlignment());
144 // Legalized the chain result - switch anything that used the old chain to
146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
150 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
151 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
152 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
154 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
155 Op2, Op3, N->getSrcValue(), N->getAlignment());
156 // Legalized the chain result - switch anything that used the old chain to
158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
162 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
163 SDValue InOp = N->getOperand(0);
164 MVT InVT = InOp.getValueType();
165 MVT NInVT = TLI.getTypeToTransformTo(InVT);
166 MVT OutVT = N->getValueType(0);
167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
168 DebugLoc dl = N->getDebugLoc();
170 switch (getTypeAction(InVT)) {
172 assert(false && "Unknown type action!");
177 if (NOutVT.bitsEq(NInVT))
178 // The input promotes to the same size. Convert the promoted value.
179 return DAG.getNode(ISD::BIT_CONVERT, dl,
180 NOutVT, GetPromotedInteger(InOp));
183 // Promote the integer operand by hand.
184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
188 case ScalarizeVector:
189 // Convert the element to an integer and promote it by hand.
190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
191 BitConvertToInteger(GetScalarizedVector(InOp)));
193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
194 // pieces of the input into integers and reassemble in the final type.
196 GetSplitVector(N->getOperand(0), Lo, Hi);
197 Lo = BitConvertToInteger(Lo);
198 Hi = BitConvertToInteger(Hi);
200 if (TLI.isBigEndian())
203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
204 MVT::getIntegerVT(NOutVT.getSizeInBits()),
205 JoinIntegers(Lo, Hi));
206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
209 if (OutVT.bitsEq(NInVT))
210 // The input is widened to the same size. Convert to the widened value.
211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
214 // Otherwise, lower the bit-convert to a store/load from the stack.
215 // Create the stack frame object. Make sure it is aligned for both
216 // the source and destination types.
217 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT);
218 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
219 const Value *SV = PseudoSourceValue::getFixedStack(FI);
221 // Emit a store to the stack slot.
222 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
224 // Result is an extending load from the stack slot.
225 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT);
228 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
229 SDValue Op = GetPromotedInteger(N->getOperand(0));
230 MVT OVT = N->getValueType(0);
231 MVT NVT = Op.getValueType();
232 DebugLoc dl = N->getDebugLoc();
234 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
235 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
236 DAG.getConstant(DiffBits, TLI.getPointerTy()));
239 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
240 // The pair element type may be legal, or may not promote to the same type as
241 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
242 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
243 TLI.getTypeToTransformTo(N->getValueType(0)),
244 JoinIntegers(N->getOperand(0), N->getOperand(1)));
247 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
248 MVT VT = N->getValueType(0);
249 // FIXME there is no actual debug info here
250 DebugLoc dl = N->getDebugLoc();
251 // Zero extend things like i1, sign extend everything else. It shouldn't
252 // matter in theory which one we pick, but this tends to give better code?
253 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
254 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
256 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
260 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
261 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
262 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
263 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
264 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
265 "can only promote integers");
266 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
267 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
268 N->getOperand(1), N->getOperand(2),
269 N->getOperand(3), N->getOperand(4), CvtCode);
272 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
273 // Zero extend to the promoted type and do the count there.
274 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
275 DebugLoc dl = N->getDebugLoc();
276 MVT OVT = N->getValueType(0);
277 MVT NVT = Op.getValueType();
278 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
279 // Subtract off the extra leading bits in the bigger type.
280 return DAG.getNode(ISD::SUB, dl, NVT, Op,
281 DAG.getConstant(NVT.getSizeInBits() -
282 OVT.getSizeInBits(), NVT));
285 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
286 // Zero extend to the promoted type and do the count there.
287 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
288 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
291 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
292 SDValue Op = GetPromotedInteger(N->getOperand(0));
293 MVT OVT = N->getValueType(0);
294 MVT NVT = Op.getValueType();
295 DebugLoc dl = N->getDebugLoc();
296 // The count is the same in the promoted type except if the original
297 // value was zero. This can be handled by setting the bit just off
298 // the top of the original type.
299 APInt TopBit(NVT.getSizeInBits(), 0);
300 TopBit.set(OVT.getSizeInBits());
301 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
302 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
305 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
306 MVT OldVT = N->getValueType(0);
307 SDValue OldVec = N->getOperand(0);
308 if (getTypeAction(OldVec.getValueType()) == WidenVector)
309 OldVec = GetWidenedVector(N->getOperand(0));
310 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
311 DebugLoc dl = N->getDebugLoc();
314 assert(!isTypeLegal(OldVec.getValueType()) &&
315 "Legal one-element vector of a type needing promotion!");
316 // It is tempting to follow GetScalarizedVector by a call to
317 // GetPromotedInteger, but this would be wrong because the
318 // scalarized value may not yet have been processed.
319 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT),
320 GetScalarizedVector(OldVec));
323 // Convert to a vector half as long with an element type of twice the width,
324 // for example <4 x i16> -> <2 x i32>.
325 assert(!(OldElts & 1) && "Odd length vectors not supported!");
326 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
327 assert(OldVT.isSimple() && NewVT.isSimple());
329 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
330 MVT::getVectorVT(NewVT, OldElts / 2),
333 // Extract the element at OldIdx / 2 from the new vector.
334 SDValue OldIdx = N->getOperand(1);
335 SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx,
336 DAG.getConstant(1, TLI.getPointerTy()));
337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx);
339 // Select the appropriate half of the element: Lo if OldIdx was even,
342 SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt,
343 DAG.getConstant(OldVT.getSizeInBits(),
344 TLI.getPointerTy()));
345 if (TLI.isBigEndian())
348 // Extend to the promoted type.
349 SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx);
350 SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo);
351 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res);
354 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
355 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
356 unsigned NewOpc = N->getOpcode();
357 DebugLoc dl = N->getDebugLoc();
359 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
360 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
361 // and SINT conversions are Custom, there is no way to tell which is preferable.
362 // We choose SINT because that's the right thing on PPC.)
363 if (N->getOpcode() == ISD::FP_TO_UINT &&
364 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
365 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
366 NewOpc = ISD::FP_TO_SINT;
368 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
370 // Assert that the converted value fits in the original type. If it doesn't
371 // (eg: because the value being converted is too big), then the result of the
372 // original operation was undefined anyway, so the assert is still correct.
373 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
374 ISD::AssertZext : ISD::AssertSext, dl,
375 NVT, Res, DAG.getValueType(N->getValueType(0)));
378 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
379 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
380 DebugLoc dl = N->getDebugLoc();
382 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
383 SDValue Res = GetPromotedInteger(N->getOperand(0));
384 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
386 // If the result and operand types are the same after promotion, simplify
387 // to an in-register extension.
388 if (NVT == Res.getValueType()) {
389 // The high bits are not guaranteed to be anything. Insert an extend.
390 if (N->getOpcode() == ISD::SIGN_EXTEND)
391 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
392 DAG.getValueType(N->getOperand(0).getValueType()));
393 if (N->getOpcode() == ISD::ZERO_EXTEND)
394 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
395 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
400 // Otherwise, just extend the original operand all the way to the larger type.
401 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
404 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
405 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
406 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
407 ISD::LoadExtType ExtType =
408 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
409 DebugLoc dl = N->getDebugLoc();
410 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
411 N->getSrcValue(), N->getSrcValueOffset(),
412 N->getMemoryVT(), N->isVolatile(),
415 // Legalized the chain result - switch anything that used the old chain to
417 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
421 /// Promote the overflow flag of an overflowing arithmetic node.
422 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
423 // Simply change the return type of the boolean result.
424 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
425 MVT ValueVTs[] = { N->getValueType(0), NVT };
426 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
427 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
428 DAG.getVTList(ValueVTs, 2), Ops, 2);
430 // Modified the sum result - switch anything that used the old sum to use
432 ReplaceValueWith(SDValue(N, 0), Res);
434 return SDValue(Res.getNode(), 1);
437 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
439 return PromoteIntRes_Overflow(N);
441 // The operation overflowed iff the result in the larger type is not the
442 // sign extension of its truncation to the original type.
443 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
444 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
445 MVT OVT = N->getOperand(0).getValueType();
446 MVT NVT = LHS.getValueType();
447 DebugLoc dl = N->getDebugLoc();
449 // Do the arithmetic in the larger type.
450 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
451 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
453 // Calculate the overflow flag: sign extend the arithmetic result from
454 // the original type.
455 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
456 DAG.getValueType(OVT));
457 // Overflowed if and only if this is not equal to Res.
458 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
460 // Use the calculated overflow everywhere.
461 ReplaceValueWith(SDValue(N, 1), Ofl);
466 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
467 // Sign extend the input.
468 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
469 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
470 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
471 LHS.getValueType(), LHS, RHS);
474 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
475 SDValue LHS = GetPromotedInteger(N->getOperand(1));
476 SDValue RHS = GetPromotedInteger(N->getOperand(2));
477 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
478 LHS.getValueType(), N->getOperand(0),LHS,RHS);
481 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
482 SDValue LHS = GetPromotedInteger(N->getOperand(2));
483 SDValue RHS = GetPromotedInteger(N->getOperand(3));
484 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
485 LHS.getValueType(), N->getOperand(0),
486 N->getOperand(1), LHS, RHS, N->getOperand(4));
489 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
490 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
491 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
492 DebugLoc dl = N->getDebugLoc();
494 // Get the SETCC result using the canonical SETCC type.
495 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
496 N->getOperand(1), N->getOperand(2));
498 // Convert to the expected type.
499 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
500 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
501 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
504 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
505 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
506 TLI.getTypeToTransformTo(N->getValueType(0)),
507 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
510 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
511 SDValue Op = GetPromotedInteger(N->getOperand(0));
512 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
513 Op.getValueType(), Op, N->getOperand(1));
516 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
517 // The input may have strange things in the top bits of the registers, but
518 // these operations don't care. They may have weird bits going out, but
519 // that too is okay if they are integer operations.
520 SDValue LHS = GetPromotedInteger(N->getOperand(0));
521 SDValue RHS = GetPromotedInteger(N->getOperand(1));
522 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
523 LHS.getValueType(), LHS, RHS);
526 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
527 // The input value must be properly sign extended.
528 SDValue Res = SExtPromotedInteger(N->getOperand(0));
529 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
530 Res.getValueType(), Res, N->getOperand(1));
533 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
534 // The input value must be properly zero extended.
535 MVT VT = N->getValueType(0);
536 MVT NVT = TLI.getTypeToTransformTo(VT);
537 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
538 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
541 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
542 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
545 switch (getTypeAction(N->getOperand(0).getValueType())) {
546 default: assert(0 && "Unknown type action!");
549 Res = N->getOperand(0);
552 Res = GetPromotedInteger(N->getOperand(0));
556 // Truncate to NVT instead of VT
557 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
560 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
562 return PromoteIntRes_Overflow(N);
564 // The operation overflowed iff the result in the larger type is not the
565 // zero extension of its truncation to the original type.
566 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
567 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
568 MVT OVT = N->getOperand(0).getValueType();
569 MVT NVT = LHS.getValueType();
570 DebugLoc dl = N->getDebugLoc();
572 // Do the arithmetic in the larger type.
573 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
574 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
576 // Calculate the overflow flag: zero extend the arithmetic result from
577 // the original type.
578 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
579 // Overflowed if and only if this is not equal to Res.
580 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
582 // Use the calculated overflow everywhere.
583 ReplaceValueWith(SDValue(N, 1), Ofl);
588 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
589 // Zero extend the input.
590 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
591 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
592 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
593 LHS.getValueType(), LHS, RHS);
596 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
597 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
600 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
601 SDValue Chain = N->getOperand(0); // Get the chain.
602 SDValue Ptr = N->getOperand(1); // Get the pointer.
603 MVT VT = N->getValueType(0);
604 DebugLoc dl = N->getDebugLoc();
606 MVT RegVT = TLI.getRegisterType(VT);
607 unsigned NumRegs = TLI.getNumRegisters(VT);
608 // The argument is passed as NumRegs registers of type RegVT.
610 SmallVector<SDValue, 8> Parts(NumRegs);
611 for (unsigned i = 0; i < NumRegs; ++i) {
612 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
613 Chain = Parts[i].getValue(1);
616 // Handle endianness of the load.
617 if (TLI.isBigEndian())
618 std::reverse(Parts.begin(), Parts.end());
620 // Assemble the parts in the promoted type.
621 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
622 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
623 for (unsigned i = 1; i < NumRegs; ++i) {
624 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
625 // Shift it to the right position and "or" it in.
626 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
627 DAG.getConstant(i * RegVT.getSizeInBits(),
628 TLI.getPointerTy()));
629 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
632 // Modified the chain result - switch anything that used the old chain to
634 ReplaceValueWith(SDValue(N, 1), Chain);
639 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
640 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
641 return PromoteIntRes_Overflow(N);
644 //===----------------------------------------------------------------------===//
645 // Integer Operand Promotion
646 //===----------------------------------------------------------------------===//
648 /// PromoteIntegerOperand - This method is called when the specified operand of
649 /// the specified node is found to need promotion. At this point, all of the
650 /// result types of the node are known to be legal, but other operands of the
651 /// node may need promotion or expansion as well as the specified one.
652 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
653 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
654 SDValue Res = SDValue();
656 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
659 switch (N->getOpcode()) {
662 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
663 N->dump(&DAG); cerr << "\n";
665 assert(0 && "Do not know how to promote this operator's operand!");
668 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
669 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
670 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
671 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
672 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
673 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
674 case ISD::CONVERT_RNDSAT:
675 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
676 case ISD::INSERT_VECTOR_ELT:
677 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
678 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
679 case ISD::SCALAR_TO_VECTOR:
680 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
681 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
682 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
683 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
684 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
685 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
686 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
688 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
689 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
690 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
696 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
699 // If the result is null, the sub-method took care of registering results etc.
700 if (!Res.getNode()) return false;
702 // If the result is N, the sub-method updated N in place. Tell the legalizer
704 if (Res.getNode() == N)
707 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
708 "Invalid operand expansion");
710 ReplaceValueWith(SDValue(N, 0), Res);
714 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
715 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
716 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
717 ISD::CondCode CCCode) {
718 // We have to insert explicit sign or zero extends. Note that we could
719 // insert sign extends for ALL conditions, but zero extend is cheaper on
720 // many machines (an AND instead of two shifts), so prefer it.
722 default: assert(0 && "Unknown integer comparison!");
729 // ALL of these operations will work if we either sign or zero extend
730 // the operands (including the unsigned comparisons!). Zero extend is
731 // usually a simpler/cheaper operation, so prefer it.
732 NewLHS = ZExtPromotedInteger(NewLHS);
733 NewRHS = ZExtPromotedInteger(NewRHS);
739 NewLHS = SExtPromotedInteger(NewLHS);
740 NewRHS = SExtPromotedInteger(NewRHS);
745 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
746 SDValue Op = GetPromotedInteger(N->getOperand(0));
747 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
750 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
751 // This should only occur in unusual situations like bitcasting to an
752 // x86_fp80, so just turn it into a store+load
753 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
756 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
757 assert(OpNo == 2 && "Don't know how to promote this operand!");
759 SDValue LHS = N->getOperand(2);
760 SDValue RHS = N->getOperand(3);
761 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
763 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
765 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
766 N->getOperand(1), LHS, RHS, N->getOperand(4));
769 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
770 assert(OpNo == 1 && "only know how to promote condition");
772 // Promote all the way up to the canonical SetCC type.
773 MVT SVT = TLI.getSetCCResultType(MVT::Other);
774 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
776 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
777 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
781 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
782 // Since the result type is legal, the operands must promote to it.
783 MVT OVT = N->getOperand(0).getValueType();
784 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
785 SDValue Hi = GetPromotedInteger(N->getOperand(1));
786 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
787 DebugLoc dl = N->getDebugLoc();
789 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
790 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
791 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
794 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
795 // The vector type is legal but the element type is not. This implies
796 // that the vector is a power-of-two in length and that the element
797 // type does not have a strange size (eg: it is not i1).
798 MVT VecVT = N->getValueType(0);
799 unsigned NumElts = VecVT.getVectorNumElements();
800 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
802 // Promote the inserted value. The type does not need to match the
803 // vector element type. Check that any extra bits introduced will be
805 assert(N->getOperand(0).getValueType().getSizeInBits() >=
806 N->getValueType(0).getVectorElementType().getSizeInBits() &&
807 "Type of inserted value narrower than vector element type!");
809 SmallVector<SDValue, 16> NewOps;
810 for (unsigned i = 0; i < NumElts; ++i)
811 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
813 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts);
816 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
817 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
818 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
819 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
820 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
821 "can only promote integer arguments");
822 SDValue InOp = GetPromotedInteger(N->getOperand(0));
823 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
824 N->getOperand(1), N->getOperand(2),
825 N->getOperand(3), N->getOperand(4), CvtCode);
828 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
831 // Promote the inserted value. This is valid because the type does not
832 // have to match the vector element type.
834 // Check that any extra bits introduced will be truncated away.
835 assert(N->getOperand(1).getValueType().getSizeInBits() >=
836 N->getValueType(0).getVectorElementType().getSizeInBits() &&
837 "Type of inserted value narrower than vector element type!");
838 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
839 GetPromotedInteger(N->getOperand(1)),
843 assert(OpNo == 2 && "Different operand and result vector types?");
845 // Promote the index.
846 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
847 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
848 N->getOperand(1), Idx);
851 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
853 DebugLoc dl = N->getDebugLoc();
854 NewOps[0] = N->getOperand(0);
855 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
856 SDValue Flag = GetPromotedInteger(N->getOperand(i));
857 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
859 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
860 array_lengthof(NewOps));
863 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
864 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
865 // the operand in place.
866 return DAG.UpdateNodeOperands(SDValue(N, 0),
867 GetPromotedInteger(N->getOperand(0)));
870 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
871 assert(OpNo == 0 && "Only know how to promote condition");
873 // Promote all the way up to the canonical SetCC type.
874 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
875 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
877 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
878 N->getOperand(1), N->getOperand(2));
881 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
882 assert(OpNo == 0 && "Don't know how to promote this operand!");
884 SDValue LHS = N->getOperand(0);
885 SDValue RHS = N->getOperand(1);
886 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
888 // The CC (#4) and the possible return values (#2 and #3) have legal types.
889 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
890 N->getOperand(3), N->getOperand(4));
893 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
894 assert(OpNo == 0 && "Don't know how to promote this operand!");
896 SDValue LHS = N->getOperand(0);
897 SDValue RHS = N->getOperand(1);
898 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
900 // The CC (#2) is always legal.
901 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
904 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
905 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
906 ZExtPromotedInteger(N->getOperand(1)));
909 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
910 SDValue Op = GetPromotedInteger(N->getOperand(0));
911 DebugLoc dl = N->getDebugLoc();
912 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
913 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
914 Op, DAG.getValueType(N->getOperand(0).getValueType()));
917 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
918 return DAG.UpdateNodeOperands(SDValue(N, 0),
919 SExtPromotedInteger(N->getOperand(0)));
922 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
923 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
924 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
925 int SVOffset = N->getSrcValueOffset();
926 unsigned Alignment = N->getAlignment();
927 bool isVolatile = N->isVolatile();
928 DebugLoc dl = N->getDebugLoc();
930 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
932 // Truncate the value and store the result.
933 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
934 SVOffset, N->getMemoryVT(),
935 isVolatile, Alignment);
938 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
939 SDValue Op = GetPromotedInteger(N->getOperand(0));
940 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
943 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
944 return DAG.UpdateNodeOperands(SDValue(N, 0),
945 ZExtPromotedInteger(N->getOperand(0)));
948 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
949 DebugLoc dl = N->getDebugLoc();
950 SDValue Op = GetPromotedInteger(N->getOperand(0));
951 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
952 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
956 //===----------------------------------------------------------------------===//
957 // Integer Result Expansion
958 //===----------------------------------------------------------------------===//
960 /// ExpandIntegerResult - This method is called when the specified result of the
961 /// specified node is found to need expansion. At this point, the node may also
962 /// have invalid operands or may have other results that need promotion, we just
963 /// know that (at least) one result needs expansion.
964 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
965 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
969 // See if the target wants to custom expand this node.
970 if (CustomLowerNode(N, N->getValueType(ResNo), true))
973 switch (N->getOpcode()) {
976 cerr << "ExpandIntegerResult #" << ResNo << ": ";
977 N->dump(&DAG); cerr << "\n";
979 assert(0 && "Do not know how to expand the result of this operator!");
982 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
983 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
984 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
985 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
987 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
988 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
989 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
990 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
991 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
993 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
994 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
995 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
996 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
997 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
998 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
999 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1000 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1001 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1002 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1003 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1004 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1005 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1006 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1007 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1008 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1009 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1010 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1011 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1012 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1016 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1019 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1022 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1025 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1029 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1032 // If Lo/Hi is null, the sub-method took care of registering results etc.
1034 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1037 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1038 /// and the shift amount is a constant 'Amt'. Expand the operation.
1039 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1040 SDValue &Lo, SDValue &Hi) {
1041 DebugLoc dl = N->getDebugLoc();
1042 // Expand the incoming operand to be shifted, so that we have its parts
1044 GetExpandedInteger(N->getOperand(0), InL, InH);
1046 MVT NVT = InL.getValueType();
1047 unsigned VTBits = N->getValueType(0).getSizeInBits();
1048 unsigned NVTBits = NVT.getSizeInBits();
1049 MVT ShTy = N->getOperand(1).getValueType();
1051 if (N->getOpcode() == ISD::SHL) {
1053 Lo = Hi = DAG.getConstant(0, NVT);
1054 } else if (Amt > NVTBits) {
1055 Lo = DAG.getConstant(0, NVT);
1056 Hi = DAG.getNode(ISD::SHL, dl,
1057 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1058 } else if (Amt == NVTBits) {
1059 Lo = DAG.getConstant(0, NVT);
1061 } else if (Amt == 1 &&
1062 TLI.isOperationLegalOrCustom(ISD::ADDC,
1063 TLI.getTypeToExpandTo(NVT))) {
1064 // Emit this X << 1 as X+X.
1065 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1066 SDValue LoOps[2] = { InL, InL };
1067 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1068 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1069 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1071 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1072 Hi = DAG.getNode(ISD::OR, dl, NVT,
1073 DAG.getNode(ISD::SHL, dl, NVT, InH,
1074 DAG.getConstant(Amt, ShTy)),
1075 DAG.getNode(ISD::SRL, dl, NVT, InL,
1076 DAG.getConstant(NVTBits-Amt, ShTy)));
1081 if (N->getOpcode() == ISD::SRL) {
1083 Lo = DAG.getConstant(0, NVT);
1084 Hi = DAG.getConstant(0, NVT);
1085 } else if (Amt > NVTBits) {
1086 Lo = DAG.getNode(ISD::SRL, dl,
1087 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1088 Hi = DAG.getConstant(0, NVT);
1089 } else if (Amt == NVTBits) {
1091 Hi = DAG.getConstant(0, NVT);
1093 Lo = DAG.getNode(ISD::OR, dl, NVT,
1094 DAG.getNode(ISD::SRL, dl, NVT, InL,
1095 DAG.getConstant(Amt, ShTy)),
1096 DAG.getNode(ISD::SHL, dl, NVT, InH,
1097 DAG.getConstant(NVTBits-Amt, ShTy)));
1098 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1103 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1105 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1106 DAG.getConstant(NVTBits-1, ShTy));
1107 } else if (Amt > NVTBits) {
1108 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1109 DAG.getConstant(Amt-NVTBits, ShTy));
1110 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1111 DAG.getConstant(NVTBits-1, ShTy));
1112 } else if (Amt == NVTBits) {
1114 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1115 DAG.getConstant(NVTBits-1, ShTy));
1117 Lo = DAG.getNode(ISD::OR, dl, NVT,
1118 DAG.getNode(ISD::SRL, dl, NVT, InL,
1119 DAG.getConstant(Amt, ShTy)),
1120 DAG.getNode(ISD::SHL, dl, NVT, InH,
1121 DAG.getConstant(NVTBits-Amt, ShTy)));
1122 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1126 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1127 /// this shift based on knowledge of the high bit of the shift amount. If we
1128 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1130 bool DAGTypeLegalizer::
1131 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1132 SDValue Amt = N->getOperand(1);
1133 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1134 MVT ShTy = Amt.getValueType();
1135 unsigned ShBits = ShTy.getSizeInBits();
1136 unsigned NVTBits = NVT.getSizeInBits();
1137 assert(isPowerOf2_32(NVTBits) &&
1138 "Expanded integer type size not a power of two!");
1139 DebugLoc dl = N->getDebugLoc();
1141 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1142 APInt KnownZero, KnownOne;
1143 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1145 // If we don't know anything about the high bits, exit.
1146 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1149 // Get the incoming operand to be shifted.
1151 GetExpandedInteger(N->getOperand(0), InL, InH);
1153 // If we know that any of the high bits of the shift amount are one, then we
1154 // can do this as a couple of simple shifts.
1155 if (KnownOne.intersects(HighBitMask)) {
1156 // Mask out the high bit, which we know is set.
1157 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1158 DAG.getConstant(~HighBitMask, ShTy));
1160 switch (N->getOpcode()) {
1161 default: assert(0 && "Unknown shift");
1163 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1164 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1167 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1168 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1171 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1172 DAG.getConstant(NVTBits-1, ShTy));
1173 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1179 // FIXME: This code is broken for shifts with a zero amount!
1180 // If we know that all of the high bits of the shift amount are zero, then we
1181 // can do this as a couple of simple shifts.
1182 if ((KnownZero & HighBitMask) == HighBitMask) {
1184 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1185 DAG.getConstant(NVTBits, ShTy),
1188 switch (N->getOpcode()) {
1189 default: assert(0 && "Unknown shift");
1190 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1192 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1195 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1196 Hi = DAG.getNode(ISD::OR, NVT,
1197 DAG.getNode(Op1, NVT, InH, Amt),
1198 DAG.getNode(Op2, NVT, InL, Amt2));
1206 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1208 bool DAGTypeLegalizer::
1209 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1210 SDValue Amt = N->getOperand(1);
1211 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1212 MVT ShTy = Amt.getValueType();
1213 unsigned NVTBits = NVT.getSizeInBits();
1214 assert(isPowerOf2_32(NVTBits) &&
1215 "Expanded integer type size not a power of two!");
1216 DebugLoc dl = N->getDebugLoc();
1218 // Get the incoming operand to be shifted.
1220 GetExpandedInteger(N->getOperand(0), InL, InH);
1222 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1223 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1224 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1225 Amt, NVBitsNode, ISD::SETULT);
1227 SDValue Lo1, Hi1, Lo2, Hi2;
1228 switch (N->getOpcode()) {
1229 default: assert(0 && "Unknown shift");
1232 Lo1 = DAG.getConstant(0, NVT); // Low part is zero.
1233 Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1236 Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1237 Hi2 = DAG.getNode(ISD::OR, dl, NVT,
1238 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1239 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
1241 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1242 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1246 Hi1 = DAG.getConstant(0, NVT); // Hi part is zero.
1247 Lo1 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1250 Hi2 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1251 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1252 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1253 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1255 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1256 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1260 Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1261 DAG.getConstant(NVTBits-1, ShTy));
1262 Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1265 Hi2 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1266 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1267 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1268 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1270 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1271 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1278 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1279 SDValue &Lo, SDValue &Hi) {
1280 DebugLoc dl = N->getDebugLoc();
1281 // Expand the subcomponents.
1282 SDValue LHSL, LHSH, RHSL, RHSH;
1283 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1284 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1286 MVT NVT = LHSL.getValueType();
1287 SDValue LoOps[2] = { LHSL, RHSL };
1288 SDValue HiOps[3] = { LHSH, RHSH };
1290 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1291 // them. TODO: Teach operation legalization how to expand unsupported
1292 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1293 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1294 // generate a value of this type in the expanded code sequence.
1296 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1297 ISD::ADDC : ISD::SUBC,
1298 TLI.getTypeToExpandTo(NVT));
1301 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1302 if (N->getOpcode() == ISD::ADD) {
1303 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1304 HiOps[2] = Lo.getValue(1);
1305 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1307 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1308 HiOps[2] = Lo.getValue(1);
1309 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1312 if (N->getOpcode() == ISD::ADD) {
1313 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1314 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1315 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1317 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1318 DAG.getConstant(1, NVT),
1319 DAG.getConstant(0, NVT));
1320 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1322 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1323 DAG.getConstant(1, NVT), Carry1);
1324 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1326 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1327 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1329 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1330 LoOps[0], LoOps[1], ISD::SETULT);
1331 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1332 DAG.getConstant(1, NVT),
1333 DAG.getConstant(0, NVT));
1334 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1339 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1340 SDValue &Lo, SDValue &Hi) {
1341 // Expand the subcomponents.
1342 SDValue LHSL, LHSH, RHSL, RHSH;
1343 DebugLoc dl = N->getDebugLoc();
1344 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1345 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1346 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1347 SDValue LoOps[2] = { LHSL, RHSL };
1348 SDValue HiOps[3] = { LHSH, RHSH };
1350 if (N->getOpcode() == ISD::ADDC) {
1351 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1352 HiOps[2] = Lo.getValue(1);
1353 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1355 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1356 HiOps[2] = Lo.getValue(1);
1357 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1360 // Legalized the flag result - switch anything that used the old flag to
1362 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1365 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1366 SDValue &Lo, SDValue &Hi) {
1367 // Expand the subcomponents.
1368 SDValue LHSL, LHSH, RHSL, RHSH;
1369 DebugLoc dl = N->getDebugLoc();
1370 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1371 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1372 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1373 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1374 SDValue HiOps[3] = { LHSH, RHSH };
1376 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1377 HiOps[2] = Lo.getValue(1);
1378 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1380 // Legalized the flag result - switch anything that used the old flag to
1382 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1385 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1386 SDValue &Lo, SDValue &Hi) {
1387 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1388 DebugLoc dl = N->getDebugLoc();
1389 SDValue Op = N->getOperand(0);
1390 if (Op.getValueType().bitsLE(NVT)) {
1391 // The low part is any extension of the input (which degenerates to a copy).
1392 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1393 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1395 // For example, extension of an i48 to an i64. The operand type necessarily
1396 // promotes to the result type, so will end up being expanded too.
1397 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1398 "Only know how to promote this result!");
1399 SDValue Res = GetPromotedInteger(Op);
1400 assert(Res.getValueType() == N->getValueType(0) &&
1401 "Operand over promoted?");
1402 // Split the promoted operand. This will simplify when it is expanded.
1403 SplitInteger(Res, Lo, Hi);
1407 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1408 SDValue &Lo, SDValue &Hi) {
1409 DebugLoc dl = N->getDebugLoc();
1410 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1411 MVT NVT = Lo.getValueType();
1412 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1413 unsigned NVTBits = NVT.getSizeInBits();
1414 unsigned EVTBits = EVT.getSizeInBits();
1416 if (NVTBits < EVTBits) {
1417 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1418 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1420 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1421 // The high part replicates the sign bit of Lo, make it explicit.
1422 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1423 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1427 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1428 SDValue &Lo, SDValue &Hi) {
1429 DebugLoc dl = N->getDebugLoc();
1430 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1431 MVT NVT = Lo.getValueType();
1432 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1433 unsigned NVTBits = NVT.getSizeInBits();
1434 unsigned EVTBits = EVT.getSizeInBits();
1436 if (NVTBits < EVTBits) {
1437 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1438 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1440 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1441 // The high part must be zero, make it explicit.
1442 Hi = DAG.getConstant(0, NVT);
1446 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1447 SDValue &Lo, SDValue &Hi) {
1448 DebugLoc dl = N->getDebugLoc();
1449 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1450 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1451 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1454 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1455 SDValue &Lo, SDValue &Hi) {
1456 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1457 unsigned NBitWidth = NVT.getSizeInBits();
1458 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1459 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1460 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1463 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1464 SDValue &Lo, SDValue &Hi) {
1465 DebugLoc dl = N->getDebugLoc();
1466 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1467 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1468 MVT NVT = Lo.getValueType();
1470 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1471 DAG.getConstant(0, NVT), ISD::SETNE);
1473 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1474 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1476 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1477 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1478 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1479 Hi = DAG.getConstant(0, NVT);
1482 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1483 SDValue &Lo, SDValue &Hi) {
1484 DebugLoc dl = N->getDebugLoc();
1485 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1486 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1487 MVT NVT = Lo.getValueType();
1488 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1489 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1490 Hi = DAG.getConstant(0, NVT);
1493 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1494 SDValue &Lo, SDValue &Hi) {
1495 DebugLoc dl = N->getDebugLoc();
1496 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1497 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1498 MVT NVT = Lo.getValueType();
1500 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1501 DAG.getConstant(0, NVT), ISD::SETNE);
1503 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1504 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1506 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1507 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1508 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1509 Hi = DAG.getConstant(0, NVT);
1512 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1514 DebugLoc dl = N->getDebugLoc();
1515 MVT VT = N->getValueType(0);
1516 SDValue Op = N->getOperand(0);
1517 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1518 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1519 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1522 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1524 DebugLoc dl = N->getDebugLoc();
1525 MVT VT = N->getValueType(0);
1526 SDValue Op = N->getOperand(0);
1527 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1528 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1529 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1532 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1533 SDValue &Lo, SDValue &Hi) {
1534 if (ISD::isNormalLoad(N)) {
1535 ExpandRes_NormalLoad(N, Lo, Hi);
1539 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1541 MVT VT = N->getValueType(0);
1542 MVT NVT = TLI.getTypeToTransformTo(VT);
1543 SDValue Ch = N->getChain();
1544 SDValue Ptr = N->getBasePtr();
1545 ISD::LoadExtType ExtType = N->getExtensionType();
1546 int SVOffset = N->getSrcValueOffset();
1547 unsigned Alignment = N->getAlignment();
1548 bool isVolatile = N->isVolatile();
1549 DebugLoc dl = N->getDebugLoc();
1551 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1553 if (N->getMemoryVT().bitsLE(NVT)) {
1554 MVT EVT = N->getMemoryVT();
1556 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1557 EVT, isVolatile, Alignment);
1559 // Remember the chain.
1560 Ch = Lo.getValue(1);
1562 if (ExtType == ISD::SEXTLOAD) {
1563 // The high part is obtained by SRA'ing all but one of the bits of the
1565 unsigned LoSize = Lo.getValueType().getSizeInBits();
1566 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1567 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1568 } else if (ExtType == ISD::ZEXTLOAD) {
1569 // The high part is just a zero.
1570 Hi = DAG.getConstant(0, NVT);
1572 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1573 // The high part is undefined.
1574 Hi = DAG.getUNDEF(NVT);
1576 } else if (TLI.isLittleEndian()) {
1577 // Little-endian - low bits are at low addresses.
1578 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1579 isVolatile, Alignment);
1581 unsigned ExcessBits =
1582 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1583 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1585 // Increment the pointer to the other half.
1586 unsigned IncrementSize = NVT.getSizeInBits()/8;
1587 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1588 DAG.getIntPtrConstant(IncrementSize));
1589 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1590 SVOffset+IncrementSize, NEVT,
1591 isVolatile, MinAlign(Alignment, IncrementSize));
1593 // Build a factor node to remember that this load is independent of the
1595 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1598 // Big-endian - high bits are at low addresses. Favor aligned loads at
1599 // the cost of some bit-fiddling.
1600 MVT EVT = N->getMemoryVT();
1601 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1602 unsigned IncrementSize = NVT.getSizeInBits()/8;
1603 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1605 // Load both the high bits and maybe some of the low bits.
1606 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1607 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1608 isVolatile, Alignment);
1610 // Increment the pointer to the other half.
1611 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1612 DAG.getIntPtrConstant(IncrementSize));
1613 // Load the rest of the low bits.
1614 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1615 SVOffset+IncrementSize,
1616 MVT::getIntegerVT(ExcessBits),
1617 isVolatile, MinAlign(Alignment, IncrementSize));
1619 // Build a factor node to remember that this load is independent of the
1621 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1624 if (ExcessBits < NVT.getSizeInBits()) {
1625 // Transfer low bits from the bottom of Hi to the top of Lo.
1626 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1627 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1628 DAG.getConstant(ExcessBits,
1629 TLI.getPointerTy())));
1630 // Move high bits to the right position in Hi.
1631 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1633 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1634 TLI.getPointerTy()));
1638 // Legalized the chain result - switch anything that used the old chain to
1640 ReplaceValueWith(SDValue(N, 1), Ch);
1643 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1644 SDValue &Lo, SDValue &Hi) {
1645 DebugLoc dl = N->getDebugLoc();
1646 SDValue LL, LH, RL, RH;
1647 GetExpandedInteger(N->getOperand(0), LL, LH);
1648 GetExpandedInteger(N->getOperand(1), RL, RH);
1649 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1650 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1653 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1654 SDValue &Lo, SDValue &Hi) {
1655 MVT VT = N->getValueType(0);
1656 MVT NVT = TLI.getTypeToTransformTo(VT);
1657 DebugLoc dl = N->getDebugLoc();
1659 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1660 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1661 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1662 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1663 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1664 SDValue LL, LH, RL, RH;
1665 GetExpandedInteger(N->getOperand(0), LL, LH);
1666 GetExpandedInteger(N->getOperand(1), RL, RH);
1667 unsigned OuterBitSize = VT.getSizeInBits();
1668 unsigned InnerBitSize = NVT.getSizeInBits();
1669 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1670 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1672 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1673 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1674 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1675 // The inputs are both zero-extended.
1677 // We can emit a umul_lohi.
1678 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1679 Hi = SDValue(Lo.getNode(), 1);
1683 // We can emit a mulhu+mul.
1684 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1685 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1689 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1690 // The input values are both sign-extended.
1692 // We can emit a smul_lohi.
1693 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1694 Hi = SDValue(Lo.getNode(), 1);
1698 // We can emit a mulhs+mul.
1699 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1700 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1705 // Lo,Hi = umul LHS, RHS.
1706 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1707 DAG.getVTList(NVT, NVT), LL, RL);
1709 Hi = UMulLOHI.getValue(1);
1710 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1711 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1712 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1713 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1717 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1718 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1719 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1720 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1721 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1722 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1727 // If nothing else, we can make a libcall.
1728 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1730 LC = RTLIB::MUL_I16;
1731 else if (VT == MVT::i32)
1732 LC = RTLIB::MUL_I32;
1733 else if (VT == MVT::i64)
1734 LC = RTLIB::MUL_I64;
1735 else if (VT == MVT::i128)
1736 LC = RTLIB::MUL_I128;
1737 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1739 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1740 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1743 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1744 SDValue &Lo, SDValue &Hi) {
1745 MVT VT = N->getValueType(0);
1746 DebugLoc dl = N->getDebugLoc();
1748 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1750 LC = RTLIB::SDIV_I16;
1751 else if (VT == MVT::i32)
1752 LC = RTLIB::SDIV_I32;
1753 else if (VT == MVT::i64)
1754 LC = RTLIB::SDIV_I64;
1755 else if (VT == MVT::i128)
1756 LC = RTLIB::SDIV_I128;
1757 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1759 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1760 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1763 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1764 SDValue &Lo, SDValue &Hi) {
1765 MVT VT = N->getValueType(0);
1766 DebugLoc dl = N->getDebugLoc();
1768 // If we can emit an efficient shift operation, do so now. Check to see if
1769 // the RHS is a constant.
1770 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1771 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1773 // If we can determine that the high bit of the shift is zero or one, even if
1774 // the low bits are variable, emit this shift in an optimized form.
1775 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1778 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1780 if (N->getOpcode() == ISD::SHL) {
1781 PartsOpc = ISD::SHL_PARTS;
1782 } else if (N->getOpcode() == ISD::SRL) {
1783 PartsOpc = ISD::SRL_PARTS;
1785 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1786 PartsOpc = ISD::SRA_PARTS;
1789 // Next check to see if the target supports this SHL_PARTS operation or if it
1790 // will custom expand it.
1791 MVT NVT = TLI.getTypeToTransformTo(VT);
1792 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1793 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1794 Action == TargetLowering::Custom) {
1795 // Expand the subcomponents.
1797 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1799 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1800 MVT VT = LHSL.getValueType();
1801 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1802 Hi = Lo.getValue(1);
1806 // Otherwise, emit a libcall.
1807 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1809 if (N->getOpcode() == ISD::SHL) {
1810 isSigned = false; /*sign irrelevant*/
1812 LC = RTLIB::SHL_I16;
1813 else if (VT == MVT::i32)
1814 LC = RTLIB::SHL_I32;
1815 else if (VT == MVT::i64)
1816 LC = RTLIB::SHL_I64;
1817 else if (VT == MVT::i128)
1818 LC = RTLIB::SHL_I128;
1819 } else if (N->getOpcode() == ISD::SRL) {
1822 LC = RTLIB::SRL_I16;
1823 else if (VT == MVT::i32)
1824 LC = RTLIB::SRL_I32;
1825 else if (VT == MVT::i64)
1826 LC = RTLIB::SRL_I64;
1827 else if (VT == MVT::i128)
1828 LC = RTLIB::SRL_I128;
1830 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1833 LC = RTLIB::SRA_I16;
1834 else if (VT == MVT::i32)
1835 LC = RTLIB::SRA_I32;
1836 else if (VT == MVT::i64)
1837 LC = RTLIB::SRA_I64;
1838 else if (VT == MVT::i128)
1839 LC = RTLIB::SRA_I128;
1842 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1843 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1844 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1848 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1849 assert(0 && "Unsupported shift!");
1852 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1853 SDValue &Lo, SDValue &Hi) {
1854 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1855 DebugLoc dl = N->getDebugLoc();
1856 SDValue Op = N->getOperand(0);
1857 if (Op.getValueType().bitsLE(NVT)) {
1858 // The low part is sign extension of the input (degenerates to a copy).
1859 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1860 // The high part is obtained by SRA'ing all but one of the bits of low part.
1861 unsigned LoSize = NVT.getSizeInBits();
1862 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1863 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1865 // For example, extension of an i48 to an i64. The operand type necessarily
1866 // promotes to the result type, so will end up being expanded too.
1867 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1868 "Only know how to promote this result!");
1869 SDValue Res = GetPromotedInteger(Op);
1870 assert(Res.getValueType() == N->getValueType(0) &&
1871 "Operand over promoted?");
1872 // Split the promoted operand. This will simplify when it is expanded.
1873 SplitInteger(Res, Lo, Hi);
1874 unsigned ExcessBits =
1875 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1876 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1877 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1881 void DAGTypeLegalizer::
1882 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1883 DebugLoc dl = N->getDebugLoc();
1884 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1885 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1887 if (EVT.bitsLE(Lo.getValueType())) {
1888 // sext_inreg the low part if needed.
1889 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1892 // The high part gets the sign extension from the lo-part. This handles
1893 // things like sextinreg V:i64 from i8.
1894 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1895 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1896 TLI.getPointerTy()));
1898 // For example, extension of an i48 to an i64. Leave the low part alone,
1899 // sext_inreg the high part.
1900 unsigned ExcessBits =
1901 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1902 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1903 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1907 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1908 SDValue &Lo, SDValue &Hi) {
1909 MVT VT = N->getValueType(0);
1910 DebugLoc dl = N->getDebugLoc();
1912 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1914 LC = RTLIB::SREM_I16;
1915 else if (VT == MVT::i32)
1916 LC = RTLIB::SREM_I32;
1917 else if (VT == MVT::i64)
1918 LC = RTLIB::SREM_I64;
1919 else if (VT == MVT::i128)
1920 LC = RTLIB::SREM_I128;
1921 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1923 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1924 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1927 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1928 SDValue &Lo, SDValue &Hi) {
1929 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1930 DebugLoc dl = N->getDebugLoc();
1931 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1932 Hi = DAG.getNode(ISD::SRL, dl,
1933 N->getOperand(0).getValueType(), N->getOperand(0),
1934 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1935 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1938 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1939 SDValue &Lo, SDValue &Hi) {
1940 MVT VT = N->getValueType(0);
1941 DebugLoc dl = N->getDebugLoc();
1943 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1945 LC = RTLIB::UDIV_I16;
1946 else if (VT == MVT::i32)
1947 LC = RTLIB::UDIV_I32;
1948 else if (VT == MVT::i64)
1949 LC = RTLIB::UDIV_I64;
1950 else if (VT == MVT::i128)
1951 LC = RTLIB::UDIV_I128;
1952 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1954 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1955 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1958 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1959 SDValue &Lo, SDValue &Hi) {
1960 MVT VT = N->getValueType(0);
1961 DebugLoc dl = N->getDebugLoc();
1963 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1965 LC = RTLIB::UREM_I16;
1966 else if (VT == MVT::i32)
1967 LC = RTLIB::UREM_I32;
1968 else if (VT == MVT::i64)
1969 LC = RTLIB::UREM_I64;
1970 else if (VT == MVT::i128)
1971 LC = RTLIB::UREM_I128;
1972 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1974 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1975 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1978 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1979 SDValue &Lo, SDValue &Hi) {
1980 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1981 DebugLoc dl = N->getDebugLoc();
1982 SDValue Op = N->getOperand(0);
1983 if (Op.getValueType().bitsLE(NVT)) {
1984 // The low part is zero extension of the input (degenerates to a copy).
1985 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1986 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1988 // For example, extension of an i48 to an i64. The operand type necessarily
1989 // promotes to the result type, so will end up being expanded too.
1990 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1991 "Only know how to promote this result!");
1992 SDValue Res = GetPromotedInteger(Op);
1993 assert(Res.getValueType() == N->getValueType(0) &&
1994 "Operand over promoted?");
1995 // Split the promoted operand. This will simplify when it is expanded.
1996 SplitInteger(Res, Lo, Hi);
1997 unsigned ExcessBits =
1998 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1999 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
2004 //===----------------------------------------------------------------------===//
2005 // Integer Operand Expansion
2006 //===----------------------------------------------------------------------===//
2008 /// ExpandIntegerOperand - This method is called when the specified operand of
2009 /// the specified node is found to need expansion. At this point, all of the
2010 /// result types of the node are known to be legal, but other operands of the
2011 /// node may need promotion or expansion as well as the specified one.
2012 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2013 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
2014 SDValue Res = SDValue();
2016 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2019 switch (N->getOpcode()) {
2022 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
2023 N->dump(&DAG); cerr << "\n";
2025 assert(0 && "Do not know how to expand this operator's operand!");
2028 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
2029 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2030 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2031 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2032 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2033 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2034 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2035 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2036 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2037 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2038 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2039 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2045 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2048 // If the result is null, the sub-method took care of registering results etc.
2049 if (!Res.getNode()) return false;
2051 // If the result is N, the sub-method updated N in place. Tell the legalizer
2053 if (Res.getNode() == N)
2056 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2057 "Invalid operand expansion");
2059 ReplaceValueWith(SDValue(N, 0), Res);
2063 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2064 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2065 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2067 ISD::CondCode &CCCode,
2069 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2070 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2071 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2073 MVT VT = NewLHS.getValueType();
2075 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2076 if (RHSLo == RHSHi) {
2077 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2078 if (RHSCST->isAllOnesValue()) {
2079 // Equality comparison to -1.
2080 NewLHS = DAG.getNode(ISD::AND, dl,
2081 LHSLo.getValueType(), LHSLo, LHSHi);
2088 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2089 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2090 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2091 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2095 // If this is a comparison of the sign bit, just look at the top part.
2097 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2098 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2099 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2105 // FIXME: This generated code sucks.
2106 ISD::CondCode LowCC;
2108 default: assert(0 && "Unknown integer setcc!");
2110 case ISD::SETULT: LowCC = ISD::SETULT; break;
2112 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2114 case ISD::SETULE: LowCC = ISD::SETULE; break;
2116 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2119 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2120 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2121 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2123 // NOTE: on targets without efficient SELECT of bools, we can always use
2124 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2125 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2127 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2128 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2129 if (!Tmp1.getNode())
2130 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2131 LHSLo, RHSLo, LowCC);
2132 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2133 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2134 if (!Tmp2.getNode())
2135 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2136 TLI.getSetCCResultType(LHSHi.getValueType()),
2137 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2139 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2140 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2141 if ((Tmp1C && Tmp1C->isNullValue()) ||
2142 (Tmp2C && Tmp2C->isNullValue() &&
2143 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2144 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2145 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2146 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2147 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2148 // low part is known false, returns high part.
2149 // For LE / GE, if high part is known false, ignore the low part.
2150 // For LT / GT, if high part is known true, ignore the low part.
2156 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2157 LHSHi, RHSHi, ISD::SETEQ, false,
2158 DagCombineInfo, dl);
2159 if (!NewLHS.getNode())
2160 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2161 LHSHi, RHSHi, ISD::SETEQ);
2162 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2163 NewLHS, Tmp1, Tmp2);
2167 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2168 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2169 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2170 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2172 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2173 // against zero to select between true and false values.
2174 if (NewRHS.getNode() == 0) {
2175 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2176 CCCode = ISD::SETNE;
2179 // Update N to have the operands specified.
2180 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2181 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2185 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2186 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2187 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2188 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2190 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2191 // against zero to select between true and false values.
2192 if (NewRHS.getNode() == 0) {
2193 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2194 CCCode = ISD::SETNE;
2197 // Update N to have the operands specified.
2198 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2199 N->getOperand(2), N->getOperand(3),
2200 DAG.getCondCode(CCCode));
2203 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2204 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2205 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2206 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2208 // If ExpandSetCCOperands returned a scalar, use it.
2209 if (NewRHS.getNode() == 0) {
2210 assert(NewLHS.getValueType() == N->getValueType(0) &&
2211 "Unexpected setcc expansion!");
2215 // Otherwise, update N to have the operands specified.
2216 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2217 DAG.getCondCode(CCCode));
2220 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2221 // The value being shifted is legal, but the shift amount is too big.
2222 // It follows that either the result of the shift is undefined, or the
2223 // upper half of the shift amount is zero. Just use the lower half.
2225 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2226 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2229 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2230 SDValue Op = N->getOperand(0);
2231 MVT DstVT = N->getValueType(0);
2232 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2233 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2234 "Don't know how to expand this SINT_TO_FP!");
2235 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2238 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2239 if (ISD::isNormalStore(N))
2240 return ExpandOp_NormalStore(N, OpNo);
2242 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2243 assert(OpNo == 1 && "Can only expand the stored value so far");
2245 MVT VT = N->getOperand(1).getValueType();
2246 MVT NVT = TLI.getTypeToTransformTo(VT);
2247 SDValue Ch = N->getChain();
2248 SDValue Ptr = N->getBasePtr();
2249 int SVOffset = N->getSrcValueOffset();
2250 unsigned Alignment = N->getAlignment();
2251 bool isVolatile = N->isVolatile();
2252 DebugLoc dl = N->getDebugLoc();
2255 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2257 if (N->getMemoryVT().bitsLE(NVT)) {
2258 GetExpandedInteger(N->getValue(), Lo, Hi);
2259 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2260 N->getMemoryVT(), isVolatile, Alignment);
2261 } else if (TLI.isLittleEndian()) {
2262 // Little-endian - low bits are at low addresses.
2263 GetExpandedInteger(N->getValue(), Lo, Hi);
2265 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2266 isVolatile, Alignment);
2268 unsigned ExcessBits =
2269 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2270 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2272 // Increment the pointer to the other half.
2273 unsigned IncrementSize = NVT.getSizeInBits()/8;
2274 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2275 DAG.getIntPtrConstant(IncrementSize));
2276 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2277 SVOffset+IncrementSize, NEVT,
2278 isVolatile, MinAlign(Alignment, IncrementSize));
2279 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2281 // Big-endian - high bits are at low addresses. Favor aligned stores at
2282 // the cost of some bit-fiddling.
2283 GetExpandedInteger(N->getValue(), Lo, Hi);
2285 MVT EVT = N->getMemoryVT();
2286 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2287 unsigned IncrementSize = NVT.getSizeInBits()/8;
2288 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2289 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2291 if (ExcessBits < NVT.getSizeInBits()) {
2292 // Transfer high bits from the top of Lo to the bottom of Hi.
2293 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2294 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2295 TLI.getPointerTy()));
2296 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2297 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2298 DAG.getConstant(ExcessBits,
2299 TLI.getPointerTy())));
2302 // Store both the high bits and maybe some of the low bits.
2303 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2304 SVOffset, HiVT, isVolatile, Alignment);
2306 // Increment the pointer to the other half.
2307 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2308 DAG.getIntPtrConstant(IncrementSize));
2309 // Store the lowest ExcessBits bits in the second half.
2310 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2311 SVOffset+IncrementSize,
2312 MVT::getIntegerVT(ExcessBits),
2313 isVolatile, MinAlign(Alignment, IncrementSize));
2314 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2318 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2320 GetExpandedInteger(N->getOperand(0), InL, InH);
2321 // Just truncate the low part of the source.
2322 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2325 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2326 SDValue Op = N->getOperand(0);
2327 MVT SrcVT = Op.getValueType();
2328 MVT DstVT = N->getValueType(0);
2329 DebugLoc dl = N->getDebugLoc();
2331 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2332 // Do a signed conversion then adjust the result.
2333 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2334 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2336 // The result of the signed conversion needs adjusting if the 'sign bit' of
2337 // the incoming integer was set. To handle this, we dynamically test to see
2338 // if it is set, and, if so, add a fudge factor.
2340 const uint64_t F32TwoE32 = 0x4F800000ULL;
2341 const uint64_t F32TwoE64 = 0x5F800000ULL;
2342 const uint64_t F32TwoE128 = 0x7F800000ULL;
2345 if (SrcVT == MVT::i32)
2346 FF = APInt(32, F32TwoE32);
2347 else if (SrcVT == MVT::i64)
2348 FF = APInt(32, F32TwoE64);
2349 else if (SrcVT == MVT::i128)
2350 FF = APInt(32, F32TwoE128);
2352 assert(false && "Unsupported UINT_TO_FP!");
2354 // Check whether the sign bit is set.
2356 GetExpandedInteger(Op, Lo, Hi);
2357 SDValue SignSet = DAG.getSetCC(dl,
2358 TLI.getSetCCResultType(Hi.getValueType()),
2359 Hi, DAG.getConstant(0, Hi.getValueType()),
2362 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2363 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2364 TLI.getPointerTy());
2366 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2367 SDValue Zero = DAG.getIntPtrConstant(0);
2368 SDValue Four = DAG.getIntPtrConstant(4);
2369 if (TLI.isBigEndian()) std::swap(Zero, Four);
2370 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2372 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2373 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2374 Alignment = std::min(Alignment, 4u);
2376 // Load the value out, extending it from f32 to the destination float type.
2377 // FIXME: Avoid the extend by constructing the right constant pool?
2378 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2379 FudgePtr, NULL, 0, MVT::f32,
2381 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2384 // Otherwise, use a libcall.
2385 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2386 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2387 "Don't know how to expand this UINT_TO_FP!");
2388 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);