1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
52 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
56 case ISD::CONVERT_RNDSAT:
57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
61 case ISD::EXTRACT_VECTOR_ELT:
62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
68 case ISD::SIGN_EXTEND_INREG:
69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
76 case ISD::EXTRACT_SUBVECTOR:
77 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
78 case ISD::VECTOR_SHUFFLE:
79 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
80 case ISD::INSERT_VECTOR_ELT:
81 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
82 case ISD::BUILD_VECTOR:
83 Res = PromoteIntRes_BUILD_VECTOR(N); break;
84 case ISD::SCALAR_TO_VECTOR:
85 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
87 case ISD::SIGN_EXTEND:
88 case ISD::ZERO_EXTEND:
89 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
92 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
94 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
101 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
104 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
107 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
110 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
112 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
114 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
116 case ISD::ATOMIC_LOAD_ADD:
117 case ISD::ATOMIC_LOAD_SUB:
118 case ISD::ATOMIC_LOAD_AND:
119 case ISD::ATOMIC_LOAD_OR:
120 case ISD::ATOMIC_LOAD_XOR:
121 case ISD::ATOMIC_LOAD_NAND:
122 case ISD::ATOMIC_LOAD_MIN:
123 case ISD::ATOMIC_LOAD_MAX:
124 case ISD::ATOMIC_LOAD_UMIN:
125 case ISD::ATOMIC_LOAD_UMAX:
126 case ISD::ATOMIC_SWAP:
127 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
129 case ISD::ATOMIC_CMP_SWAP:
130 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
133 // If the result is null then the sub-method took care of registering it.
135 SetPromotedInteger(SDValue(N, ResNo), Res);
138 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
139 // Sign-extend the new bits, and continue the assertion.
140 SDValue Op = SExtPromotedInteger(N->getOperand(0));
141 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
142 Op.getValueType(), Op, N->getOperand(1));
145 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
146 // Zero the new bits, and continue the assertion.
147 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
148 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
149 Op.getValueType(), Op, N->getOperand(1));
152 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
153 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
154 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
156 N->getChain(), N->getBasePtr(),
157 Op2, N->getMemOperand());
158 // Legalized the chain result - switch anything that used the old chain to
160 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
164 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
165 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
166 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
167 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
168 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
169 Op2, Op3, N->getMemOperand());
170 // Legalized the chain result - switch anything that used the old chain to
172 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
176 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
177 SDValue InOp = N->getOperand(0);
178 EVT InVT = InOp.getValueType();
179 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
180 EVT OutVT = N->getValueType(0);
181 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
182 DebugLoc dl = N->getDebugLoc();
184 switch (getTypeAction(InVT)) {
186 assert(false && "Unknown type action!");
188 case TargetLowering::TypeLegal:
190 case TargetLowering::TypePromoteInteger:
191 if (NOutVT.bitsEq(NInVT))
192 // The input promotes to the same size. Convert the promoted value.
193 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
194 if (NInVT.isVector())
195 // Promote vector element via memory load/store.
196 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
197 CreateStackStoreLoad(InOp, OutVT));
199 case TargetLowering::TypeSoftenFloat:
200 // Promote the integer operand by hand.
201 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
202 case TargetLowering::TypeExpandInteger:
203 case TargetLowering::TypeExpandFloat:
205 case TargetLowering::TypeScalarizeVector:
206 // Convert the element to an integer and promote it by hand.
207 if (!NOutVT.isVector())
208 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
209 BitConvertToInteger(GetScalarizedVector(InOp)));
211 case TargetLowering::TypeSplitVector: {
212 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
213 // pieces of the input into integers and reassemble in the final type.
215 GetSplitVector(N->getOperand(0), Lo, Hi);
216 Lo = BitConvertToInteger(Lo);
217 Hi = BitConvertToInteger(Hi);
219 if (TLI.isBigEndian())
222 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
223 EVT::getIntegerVT(*DAG.getContext(),
224 NOutVT.getSizeInBits()),
225 JoinIntegers(Lo, Hi));
226 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
228 case TargetLowering::TypeWidenVector:
229 if (OutVT.bitsEq(NInVT))
230 // The input is widened to the same size. Convert to the widened value.
231 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp));
234 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
235 CreateStackStoreLoad(InOp, OutVT));
238 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
239 SDValue Op = GetPromotedInteger(N->getOperand(0));
240 EVT OVT = N->getValueType(0);
241 EVT NVT = Op.getValueType();
242 DebugLoc dl = N->getDebugLoc();
244 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
245 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
246 DAG.getConstant(DiffBits, TLI.getPointerTy()));
249 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
250 // The pair element type may be legal, or may not promote to the same type as
251 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
252 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
253 TLI.getTypeToTransformTo(*DAG.getContext(),
254 N->getValueType(0)), JoinIntegers(N->getOperand(0),
258 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
259 EVT VT = N->getValueType(0);
260 // FIXME there is no actual debug info here
261 DebugLoc dl = N->getDebugLoc();
262 // Zero extend things like i1, sign extend everything else. It shouldn't
263 // matter in theory which one we pick, but this tends to give better code?
264 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
265 SDValue Result = DAG.getNode(Opc, dl,
266 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
268 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
272 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
273 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
274 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
275 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
276 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
277 "can only promote integers");
278 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
279 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
280 N->getOperand(1), N->getOperand(2),
281 N->getOperand(3), N->getOperand(4), CvtCode);
284 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
285 // Zero extend to the promoted type and do the count there.
286 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
287 DebugLoc dl = N->getDebugLoc();
288 EVT OVT = N->getValueType(0);
289 EVT NVT = Op.getValueType();
290 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
291 // Subtract off the extra leading bits in the bigger type.
292 return DAG.getNode(ISD::SUB, dl, NVT, Op,
293 DAG.getConstant(NVT.getSizeInBits() -
294 OVT.getSizeInBits(), NVT));
297 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
298 // Zero extend to the promoted type and do the count there.
299 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
300 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
303 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
304 SDValue Op = GetPromotedInteger(N->getOperand(0));
305 EVT OVT = N->getValueType(0);
306 EVT NVT = Op.getValueType();
307 DebugLoc dl = N->getDebugLoc();
308 // The count is the same in the promoted type except if the original
309 // value was zero. This can be handled by setting the bit just off
310 // the top of the original type.
311 APInt TopBit(NVT.getSizeInBits(), 0);
312 TopBit.setBit(OVT.getSizeInBits());
313 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
314 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
317 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
318 DebugLoc dl = N->getDebugLoc();
319 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
320 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
324 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
325 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
326 unsigned NewOpc = N->getOpcode();
327 DebugLoc dl = N->getDebugLoc();
329 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
330 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
331 // and SINT conversions are Custom, there is no way to tell which is
332 // preferable. We choose SINT because that's the right thing on PPC.)
333 if (N->getOpcode() == ISD::FP_TO_UINT &&
334 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
335 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
336 NewOpc = ISD::FP_TO_SINT;
338 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
340 // Assert that the converted value fits in the original type. If it doesn't
341 // (eg: because the value being converted is too big), then the result of the
342 // original operation was undefined anyway, so the assert is still correct.
343 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
344 ISD::AssertZext : ISD::AssertSext, dl,
345 NVT, Res, DAG.getValueType(N->getValueType(0)));
348 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
349 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
350 DebugLoc dl = N->getDebugLoc();
352 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
354 return DAG.getNode(ISD::AssertZext, dl,
355 NVT, Res, DAG.getValueType(N->getValueType(0)));
358 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
359 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
360 DebugLoc dl = N->getDebugLoc();
362 if (getTypeAction(N->getOperand(0).getValueType())
363 == TargetLowering::TypePromoteInteger) {
364 SDValue Res = GetPromotedInteger(N->getOperand(0));
365 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
367 // If the result and operand types are the same after promotion, simplify
368 // to an in-register extension.
369 if (NVT == Res.getValueType()) {
370 // The high bits are not guaranteed to be anything. Insert an extend.
371 if (N->getOpcode() == ISD::SIGN_EXTEND)
372 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
373 DAG.getValueType(N->getOperand(0).getValueType()));
374 if (N->getOpcode() == ISD::ZERO_EXTEND)
375 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
376 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
381 // Otherwise, just extend the original operand all the way to the larger type.
382 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
385 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
386 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
387 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
388 ISD::LoadExtType ExtType =
389 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
390 DebugLoc dl = N->getDebugLoc();
391 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
393 N->getMemoryVT(), N->isVolatile(),
394 N->isNonTemporal(), N->getAlignment());
396 // Legalized the chain result - switch anything that used the old chain to
398 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
402 /// Promote the overflow flag of an overflowing arithmetic node.
403 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
404 // Simply change the return type of the boolean result.
405 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
406 EVT ValueVTs[] = { N->getValueType(0), NVT };
407 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
408 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
409 DAG.getVTList(ValueVTs, 2), Ops, 2);
411 // Modified the sum result - switch anything that used the old sum to use
413 ReplaceValueWith(SDValue(N, 0), Res);
415 return SDValue(Res.getNode(), 1);
418 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
420 return PromoteIntRes_Overflow(N);
422 // The operation overflowed iff the result in the larger type is not the
423 // sign extension of its truncation to the original type.
424 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
425 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
426 EVT OVT = N->getOperand(0).getValueType();
427 EVT NVT = LHS.getValueType();
428 DebugLoc dl = N->getDebugLoc();
430 // Do the arithmetic in the larger type.
431 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
432 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
434 // Calculate the overflow flag: sign extend the arithmetic result from
435 // the original type.
436 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
437 DAG.getValueType(OVT));
438 // Overflowed if and only if this is not equal to Res.
439 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
441 // Use the calculated overflow everywhere.
442 ReplaceValueWith(SDValue(N, 1), Ofl);
447 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
448 // Sign extend the input.
449 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
450 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
451 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
452 LHS.getValueType(), LHS, RHS);
455 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
456 SDValue LHS = GetPromotedInteger(N->getOperand(1));
457 SDValue RHS = GetPromotedInteger(N->getOperand(2));
458 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
459 LHS.getValueType(), N->getOperand(0),LHS,RHS);
462 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
463 SDValue LHS = GetPromotedInteger(N->getOperand(2));
464 SDValue RHS = GetPromotedInteger(N->getOperand(3));
465 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
466 LHS.getValueType(), N->getOperand(0),
467 N->getOperand(1), LHS, RHS, N->getOperand(4));
470 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
471 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
472 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
473 DebugLoc dl = N->getDebugLoc();
475 // Get the SETCC result using the canonical SETCC type.
476 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
477 N->getOperand(1), N->getOperand(2));
479 // Convert to the expected type.
480 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
481 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
482 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
485 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
486 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
487 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
488 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
491 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
492 SDValue Op = GetPromotedInteger(N->getOperand(0));
493 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
494 Op.getValueType(), Op, N->getOperand(1));
497 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
498 // The input may have strange things in the top bits of the registers, but
499 // these operations don't care. They may have weird bits going out, but
500 // that too is okay if they are integer operations.
501 SDValue LHS = GetPromotedInteger(N->getOperand(0));
502 SDValue RHS = GetPromotedInteger(N->getOperand(1));
503 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
504 LHS.getValueType(), LHS, RHS);
507 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
508 // The input value must be properly sign extended.
509 SDValue Res = SExtPromotedInteger(N->getOperand(0));
510 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
511 Res.getValueType(), Res, N->getOperand(1));
514 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
515 // The input value must be properly zero extended.
516 EVT VT = N->getValueType(0);
517 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
518 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
519 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
522 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
523 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
526 switch (getTypeAction(N->getOperand(0).getValueType())) {
527 default: llvm_unreachable("Unknown type action!");
528 case TargetLowering::TypeLegal:
529 case TargetLowering::TypeExpandInteger:
530 Res = N->getOperand(0);
532 case TargetLowering::TypePromoteInteger:
533 Res = GetPromotedInteger(N->getOperand(0));
537 // Truncate to NVT instead of VT
538 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
541 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
543 return PromoteIntRes_Overflow(N);
545 // The operation overflowed iff the result in the larger type is not the
546 // zero extension of its truncation to the original type.
547 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
548 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
549 EVT OVT = N->getOperand(0).getValueType();
550 EVT NVT = LHS.getValueType();
551 DebugLoc dl = N->getDebugLoc();
553 // Do the arithmetic in the larger type.
554 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
555 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
557 // Calculate the overflow flag: zero extend the arithmetic result from
558 // the original type.
559 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
560 // Overflowed if and only if this is not equal to Res.
561 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
563 // Use the calculated overflow everywhere.
564 ReplaceValueWith(SDValue(N, 1), Ofl);
569 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
570 // Promote the overflow bit trivially.
572 return PromoteIntRes_Overflow(N);
574 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
575 DebugLoc DL = N->getDebugLoc();
576 EVT SmallVT = LHS.getValueType();
578 // To determine if the result overflowed in a larger type, we extend the
579 // input to the larger type, do the multiply, then check the high bits of
580 // the result to see if the overflow happened.
581 if (N->getOpcode() == ISD::SMULO) {
582 LHS = SExtPromotedInteger(LHS);
583 RHS = SExtPromotedInteger(RHS);
585 LHS = ZExtPromotedInteger(LHS);
586 RHS = ZExtPromotedInteger(RHS);
588 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
590 // Overflow occurred iff the high part of the result does not
591 // zero/sign-extend the low part.
593 if (N->getOpcode() == ISD::UMULO) {
594 // Unsigned overflow occurred iff the high part is non-zero.
595 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
596 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
597 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
598 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
600 // Signed overflow occurred iff the high part does not sign extend the low.
601 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
602 Mul, DAG.getValueType(SmallVT));
603 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
606 // Use the calculated overflow everywhere.
607 ReplaceValueWith(SDValue(N, 1), Overflow);
611 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
612 // Zero extend the input.
613 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
614 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
615 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
616 LHS.getValueType(), LHS, RHS);
619 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
620 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
621 N->getValueType(0)));
624 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
625 SDValue Chain = N->getOperand(0); // Get the chain.
626 SDValue Ptr = N->getOperand(1); // Get the pointer.
627 EVT VT = N->getValueType(0);
628 DebugLoc dl = N->getDebugLoc();
630 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
631 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
632 // The argument is passed as NumRegs registers of type RegVT.
634 SmallVector<SDValue, 8> Parts(NumRegs);
635 for (unsigned i = 0; i < NumRegs; ++i) {
636 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
637 N->getConstantOperandVal(3));
638 Chain = Parts[i].getValue(1);
641 // Handle endianness of the load.
642 if (TLI.isBigEndian())
643 std::reverse(Parts.begin(), Parts.end());
645 // Assemble the parts in the promoted type.
646 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
647 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
648 for (unsigned i = 1; i < NumRegs; ++i) {
649 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
650 // Shift it to the right position and "or" it in.
651 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
652 DAG.getConstant(i * RegVT.getSizeInBits(),
653 TLI.getPointerTy()));
654 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
657 // Modified the chain result - switch anything that used the old chain to
659 ReplaceValueWith(SDValue(N, 1), Chain);
664 //===----------------------------------------------------------------------===//
665 // Integer Operand Promotion
666 //===----------------------------------------------------------------------===//
668 /// PromoteIntegerOperand - This method is called when the specified operand of
669 /// the specified node is found to need promotion. At this point, all of the
670 /// result types of the node are known to be legal, but other operands of the
671 /// node may need promotion or expansion as well as the specified one.
672 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
673 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
674 SDValue Res = SDValue();
676 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
679 switch (N->getOpcode()) {
682 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
683 N->dump(&DAG); dbgs() << "\n";
685 llvm_unreachable("Do not know how to promote this operator's operand!");
687 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
688 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
689 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
690 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
691 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
692 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
693 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
694 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
695 case ISD::CONVERT_RNDSAT:
696 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
697 case ISD::INSERT_VECTOR_ELT:
698 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
699 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
700 case ISD::SCALAR_TO_VECTOR:
701 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
702 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
703 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
704 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
705 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
706 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
707 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
709 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
710 case ISD::FP16_TO_FP32:
711 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
712 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
718 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
721 // If the result is null, the sub-method took care of registering results etc.
722 if (!Res.getNode()) return false;
724 // If the result is N, the sub-method updated N in place. Tell the legalizer
726 if (Res.getNode() == N)
729 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
730 "Invalid operand expansion");
732 ReplaceValueWith(SDValue(N, 0), Res);
736 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
737 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
738 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
739 ISD::CondCode CCCode) {
740 // We have to insert explicit sign or zero extends. Note that we could
741 // insert sign extends for ALL conditions, but zero extend is cheaper on
742 // many machines (an AND instead of two shifts), so prefer it.
744 default: llvm_unreachable("Unknown integer comparison!");
751 // ALL of these operations will work if we either sign or zero extend
752 // the operands (including the unsigned comparisons!). Zero extend is
753 // usually a simpler/cheaper operation, so prefer it.
754 NewLHS = ZExtPromotedInteger(NewLHS);
755 NewRHS = ZExtPromotedInteger(NewRHS);
761 NewLHS = SExtPromotedInteger(NewLHS);
762 NewRHS = SExtPromotedInteger(NewRHS);
767 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
768 SDValue Op = GetPromotedInteger(N->getOperand(0));
769 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
772 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
773 // This should only occur in unusual situations like bitcasting to an
774 // x86_fp80, so just turn it into a store+load
775 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
778 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
779 assert(OpNo == 2 && "Don't know how to promote this operand!");
781 SDValue LHS = N->getOperand(2);
782 SDValue RHS = N->getOperand(3);
783 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
785 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
787 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
788 N->getOperand(1), LHS, RHS, N->getOperand(4)),
792 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
793 assert(OpNo == 1 && "only know how to promote condition");
795 // Promote all the way up to the canonical SetCC type.
796 EVT SVT = TLI.getSetCCResultType(MVT::Other);
797 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
799 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
800 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
801 N->getOperand(2)), 0);
804 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
805 // Since the result type is legal, the operands must promote to it.
806 EVT OVT = N->getOperand(0).getValueType();
807 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
808 SDValue Hi = GetPromotedInteger(N->getOperand(1));
809 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
810 DebugLoc dl = N->getDebugLoc();
812 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
813 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
814 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
817 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
818 // The vector type is legal but the element type is not. This implies
819 // that the vector is a power-of-two in length and that the element
820 // type does not have a strange size (eg: it is not i1).
821 EVT VecVT = N->getValueType(0);
822 unsigned NumElts = VecVT.getVectorNumElements();
823 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
825 // Promote the inserted value. The type does not need to match the
826 // vector element type. Check that any extra bits introduced will be
828 assert(N->getOperand(0).getValueType().getSizeInBits() >=
829 N->getValueType(0).getVectorElementType().getSizeInBits() &&
830 "Type of inserted value narrower than vector element type!");
832 SmallVector<SDValue, 16> NewOps;
833 for (unsigned i = 0; i < NumElts; ++i)
834 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
836 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
839 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
840 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
841 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
842 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
843 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
844 "can only promote integer arguments");
845 SDValue InOp = GetPromotedInteger(N->getOperand(0));
846 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
847 N->getOperand(1), N->getOperand(2),
848 N->getOperand(3), N->getOperand(4), CvtCode);
851 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
854 // Promote the inserted value. This is valid because the type does not
855 // have to match the vector element type.
857 // Check that any extra bits introduced will be truncated away.
858 assert(N->getOperand(1).getValueType().getSizeInBits() >=
859 N->getValueType(0).getVectorElementType().getSizeInBits() &&
860 "Type of inserted value narrower than vector element type!");
861 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
862 GetPromotedInteger(N->getOperand(1)),
867 assert(OpNo == 2 && "Different operand and result vector types?");
869 // Promote the index.
870 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
871 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
872 N->getOperand(1), Idx), 0);
875 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
877 DebugLoc dl = N->getDebugLoc();
878 NewOps[0] = N->getOperand(0);
879 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
880 SDValue Flag = GetPromotedInteger(N->getOperand(i));
881 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
883 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
886 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
887 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
888 // the operand in place.
889 return SDValue(DAG.UpdateNodeOperands(N,
890 GetPromotedInteger(N->getOperand(0))), 0);
893 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
894 assert(OpNo == 0 && "Only know how to promote condition");
896 // Promote all the way up to the canonical SetCC type.
897 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
898 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
900 return SDValue(DAG.UpdateNodeOperands(N, Cond,
901 N->getOperand(1), N->getOperand(2)), 0);
904 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
905 assert(OpNo == 0 && "Don't know how to promote this operand!");
907 SDValue LHS = N->getOperand(0);
908 SDValue RHS = N->getOperand(1);
909 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
911 // The CC (#4) and the possible return values (#2 and #3) have legal types.
912 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
913 N->getOperand(3), N->getOperand(4)), 0);
916 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
917 assert(OpNo == 0 && "Don't know how to promote this operand!");
919 SDValue LHS = N->getOperand(0);
920 SDValue RHS = N->getOperand(1);
921 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
923 // The CC (#2) is always legal.
924 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
927 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
928 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
929 ZExtPromotedInteger(N->getOperand(1))), 0);
932 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
933 SDValue Op = GetPromotedInteger(N->getOperand(0));
934 DebugLoc dl = N->getDebugLoc();
935 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
936 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
937 Op, DAG.getValueType(N->getOperand(0).getValueType()));
940 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
941 return SDValue(DAG.UpdateNodeOperands(N,
942 SExtPromotedInteger(N->getOperand(0))), 0);
945 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
946 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
947 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
948 unsigned Alignment = N->getAlignment();
949 bool isVolatile = N->isVolatile();
950 bool isNonTemporal = N->isNonTemporal();
951 DebugLoc dl = N->getDebugLoc();
953 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
955 // Truncate the value and store the result.
956 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
958 isVolatile, isNonTemporal, Alignment);
961 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
962 SDValue Op = GetPromotedInteger(N->getOperand(0));
963 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
966 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
967 return SDValue(DAG.UpdateNodeOperands(N,
968 ZExtPromotedInteger(N->getOperand(0))), 0);
971 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
972 DebugLoc dl = N->getDebugLoc();
973 SDValue Op = GetPromotedInteger(N->getOperand(0));
974 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
975 return DAG.getZeroExtendInReg(Op, dl,
976 N->getOperand(0).getValueType().getScalarType());
980 //===----------------------------------------------------------------------===//
981 // Integer Result Expansion
982 //===----------------------------------------------------------------------===//
984 /// ExpandIntegerResult - This method is called when the specified result of the
985 /// specified node is found to need expansion. At this point, the node may also
986 /// have invalid operands or may have other results that need promotion, we just
987 /// know that (at least) one result needs expansion.
988 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
989 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
993 // See if the target wants to custom expand this node.
994 if (CustomLowerNode(N, N->getValueType(ResNo), true))
997 switch (N->getOpcode()) {
1000 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1001 N->dump(&DAG); dbgs() << "\n";
1003 llvm_unreachable("Do not know how to expand the result of this operator!");
1005 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
1006 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1007 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1008 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1010 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1011 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1012 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1013 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1014 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1016 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1017 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1018 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1019 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1020 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1021 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1022 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1023 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1024 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1025 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1026 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1027 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1028 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1029 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1030 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1031 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1032 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1033 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1034 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1035 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1037 case ISD::ATOMIC_LOAD_ADD:
1038 case ISD::ATOMIC_LOAD_SUB:
1039 case ISD::ATOMIC_LOAD_AND:
1040 case ISD::ATOMIC_LOAD_OR:
1041 case ISD::ATOMIC_LOAD_XOR:
1042 case ISD::ATOMIC_LOAD_NAND:
1043 case ISD::ATOMIC_LOAD_MIN:
1044 case ISD::ATOMIC_LOAD_MAX:
1045 case ISD::ATOMIC_LOAD_UMIN:
1046 case ISD::ATOMIC_LOAD_UMAX:
1047 case ISD::ATOMIC_SWAP: {
1048 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1049 SplitInteger(Tmp.first, Lo, Hi);
1050 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1056 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1059 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1062 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1065 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1069 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1072 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1074 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1077 // If Lo/Hi is null, the sub-method took care of registering results etc.
1079 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1082 /// Lower an atomic node to the appropriate builtin call.
1083 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1084 unsigned Opc = Node->getOpcode();
1085 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1090 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1092 case ISD::ATOMIC_SWAP:
1093 switch (VT.SimpleTy) {
1094 default: llvm_unreachable("Unexpected value type for atomic!");
1095 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1096 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1097 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1098 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1101 case ISD::ATOMIC_CMP_SWAP:
1102 switch (VT.SimpleTy) {
1103 default: llvm_unreachable("Unexpected value type for atomic!");
1104 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1105 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1106 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1107 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1110 case ISD::ATOMIC_LOAD_ADD:
1111 switch (VT.SimpleTy) {
1112 default: llvm_unreachable("Unexpected value type for atomic!");
1113 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1114 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1115 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1116 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1119 case ISD::ATOMIC_LOAD_SUB:
1120 switch (VT.SimpleTy) {
1121 default: llvm_unreachable("Unexpected value type for atomic!");
1122 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1123 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1124 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1125 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1128 case ISD::ATOMIC_LOAD_AND:
1129 switch (VT.SimpleTy) {
1130 default: llvm_unreachable("Unexpected value type for atomic!");
1131 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1132 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1133 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1134 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1137 case ISD::ATOMIC_LOAD_OR:
1138 switch (VT.SimpleTy) {
1139 default: llvm_unreachable("Unexpected value type for atomic!");
1140 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1141 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1142 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1143 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1146 case ISD::ATOMIC_LOAD_XOR:
1147 switch (VT.SimpleTy) {
1148 default: llvm_unreachable("Unexpected value type for atomic!");
1149 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1150 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1151 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1152 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1155 case ISD::ATOMIC_LOAD_NAND:
1156 switch (VT.SimpleTy) {
1157 default: llvm_unreachable("Unexpected value type for atomic!");
1158 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1159 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1160 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1161 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1166 return ExpandChainLibCall(LC, Node, false);
1169 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1170 /// and the shift amount is a constant 'Amt'. Expand the operation.
1171 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1172 SDValue &Lo, SDValue &Hi) {
1173 DebugLoc DL = N->getDebugLoc();
1174 // Expand the incoming operand to be shifted, so that we have its parts
1176 GetExpandedInteger(N->getOperand(0), InL, InH);
1178 EVT NVT = InL.getValueType();
1179 unsigned VTBits = N->getValueType(0).getSizeInBits();
1180 unsigned NVTBits = NVT.getSizeInBits();
1181 EVT ShTy = N->getOperand(1).getValueType();
1183 if (N->getOpcode() == ISD::SHL) {
1185 Lo = Hi = DAG.getConstant(0, NVT);
1186 } else if (Amt > NVTBits) {
1187 Lo = DAG.getConstant(0, NVT);
1188 Hi = DAG.getNode(ISD::SHL, DL,
1189 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1190 } else if (Amt == NVTBits) {
1191 Lo = DAG.getConstant(0, NVT);
1193 } else if (Amt == 1 &&
1194 TLI.isOperationLegalOrCustom(ISD::ADDC,
1195 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1196 // Emit this X << 1 as X+X.
1197 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1198 SDValue LoOps[2] = { InL, InL };
1199 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1200 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1201 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1203 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1204 Hi = DAG.getNode(ISD::OR, DL, NVT,
1205 DAG.getNode(ISD::SHL, DL, NVT, InH,
1206 DAG.getConstant(Amt, ShTy)),
1207 DAG.getNode(ISD::SRL, DL, NVT, InL,
1208 DAG.getConstant(NVTBits-Amt, ShTy)));
1213 if (N->getOpcode() == ISD::SRL) {
1215 Lo = DAG.getConstant(0, NVT);
1216 Hi = DAG.getConstant(0, NVT);
1217 } else if (Amt > NVTBits) {
1218 Lo = DAG.getNode(ISD::SRL, DL,
1219 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1220 Hi = DAG.getConstant(0, NVT);
1221 } else if (Amt == NVTBits) {
1223 Hi = DAG.getConstant(0, NVT);
1225 Lo = DAG.getNode(ISD::OR, DL, NVT,
1226 DAG.getNode(ISD::SRL, DL, NVT, InL,
1227 DAG.getConstant(Amt, ShTy)),
1228 DAG.getNode(ISD::SHL, DL, NVT, InH,
1229 DAG.getConstant(NVTBits-Amt, ShTy)));
1230 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1235 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1237 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1238 DAG.getConstant(NVTBits-1, ShTy));
1239 } else if (Amt > NVTBits) {
1240 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1241 DAG.getConstant(Amt-NVTBits, ShTy));
1242 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1243 DAG.getConstant(NVTBits-1, ShTy));
1244 } else if (Amt == NVTBits) {
1246 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1247 DAG.getConstant(NVTBits-1, ShTy));
1249 Lo = DAG.getNode(ISD::OR, DL, NVT,
1250 DAG.getNode(ISD::SRL, DL, NVT, InL,
1251 DAG.getConstant(Amt, ShTy)),
1252 DAG.getNode(ISD::SHL, DL, NVT, InH,
1253 DAG.getConstant(NVTBits-Amt, ShTy)));
1254 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1258 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1259 /// this shift based on knowledge of the high bit of the shift amount. If we
1260 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1262 bool DAGTypeLegalizer::
1263 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1264 SDValue Amt = N->getOperand(1);
1265 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1266 EVT ShTy = Amt.getValueType();
1267 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1268 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1269 assert(isPowerOf2_32(NVTBits) &&
1270 "Expanded integer type size not a power of two!");
1271 DebugLoc dl = N->getDebugLoc();
1273 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1274 APInt KnownZero, KnownOne;
1275 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1277 // If we don't know anything about the high bits, exit.
1278 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1281 // Get the incoming operand to be shifted.
1283 GetExpandedInteger(N->getOperand(0), InL, InH);
1285 // If we know that any of the high bits of the shift amount are one, then we
1286 // can do this as a couple of simple shifts.
1287 if (KnownOne.intersects(HighBitMask)) {
1288 // Mask out the high bit, which we know is set.
1289 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1290 DAG.getConstant(~HighBitMask, ShTy));
1292 switch (N->getOpcode()) {
1293 default: llvm_unreachable("Unknown shift");
1295 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1296 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1299 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1300 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1303 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1304 DAG.getConstant(NVTBits-1, ShTy));
1305 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1311 // FIXME: This code is broken for shifts with a zero amount!
1312 // If we know that all of the high bits of the shift amount are zero, then we
1313 // can do this as a couple of simple shifts.
1314 if ((KnownZero & HighBitMask) == HighBitMask) {
1316 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1317 DAG.getConstant(NVTBits, ShTy),
1320 switch (N->getOpcode()) {
1321 default: llvm_unreachable("Unknown shift");
1322 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1324 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1327 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1328 Hi = DAG.getNode(ISD::OR, NVT,
1329 DAG.getNode(Op1, NVT, InH, Amt),
1330 DAG.getNode(Op2, NVT, InL, Amt2));
1338 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1340 bool DAGTypeLegalizer::
1341 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1342 SDValue Amt = N->getOperand(1);
1343 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1344 EVT ShTy = Amt.getValueType();
1345 unsigned NVTBits = NVT.getSizeInBits();
1346 assert(isPowerOf2_32(NVTBits) &&
1347 "Expanded integer type size not a power of two!");
1348 DebugLoc dl = N->getDebugLoc();
1350 // Get the incoming operand to be shifted.
1352 GetExpandedInteger(N->getOperand(0), InL, InH);
1354 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1355 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1356 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1357 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1358 Amt, NVBitsNode, ISD::SETULT);
1360 SDValue LoS, HiS, LoL, HiL;
1361 switch (N->getOpcode()) {
1362 default: llvm_unreachable("Unknown shift");
1364 // Short: ShAmt < NVTBits
1365 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1366 HiS = DAG.getNode(ISD::OR, dl, NVT,
1367 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1368 // FIXME: If Amt is zero, the following shift generates an undefined result
1369 // on some architectures.
1370 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1372 // Long: ShAmt >= NVTBits
1373 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1374 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1376 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1377 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1380 // Short: ShAmt < NVTBits
1381 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1382 LoS = DAG.getNode(ISD::OR, dl, NVT,
1383 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1384 // FIXME: If Amt is zero, the following shift generates an undefined result
1385 // on some architectures.
1386 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1388 // Long: ShAmt >= NVTBits
1389 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1390 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1392 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1393 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1396 // Short: ShAmt < NVTBits
1397 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1398 LoS = DAG.getNode(ISD::OR, dl, NVT,
1399 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1400 // FIXME: If Amt is zero, the following shift generates an undefined result
1401 // on some architectures.
1402 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1404 // Long: ShAmt >= NVTBits
1405 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1406 DAG.getConstant(NVTBits-1, ShTy));
1407 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1409 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1410 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1417 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1418 SDValue &Lo, SDValue &Hi) {
1419 DebugLoc dl = N->getDebugLoc();
1420 // Expand the subcomponents.
1421 SDValue LHSL, LHSH, RHSL, RHSH;
1422 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1423 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1425 EVT NVT = LHSL.getValueType();
1426 SDValue LoOps[2] = { LHSL, RHSL };
1427 SDValue HiOps[3] = { LHSH, RHSH };
1429 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1430 // them. TODO: Teach operation legalization how to expand unsupported
1431 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1432 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1433 // generate a value of this type in the expanded code sequence.
1435 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1436 ISD::ADDC : ISD::SUBC,
1437 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1440 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1441 if (N->getOpcode() == ISD::ADD) {
1442 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1443 HiOps[2] = Lo.getValue(1);
1444 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1446 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1447 HiOps[2] = Lo.getValue(1);
1448 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1453 if (N->getOpcode() == ISD::ADD) {
1454 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1455 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1456 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1458 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1459 DAG.getConstant(1, NVT),
1460 DAG.getConstant(0, NVT));
1461 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1463 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1464 DAG.getConstant(1, NVT), Carry1);
1465 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1467 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1468 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1470 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1471 LoOps[0], LoOps[1], ISD::SETULT);
1472 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1473 DAG.getConstant(1, NVT),
1474 DAG.getConstant(0, NVT));
1475 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1479 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1480 SDValue &Lo, SDValue &Hi) {
1481 // Expand the subcomponents.
1482 SDValue LHSL, LHSH, RHSL, RHSH;
1483 DebugLoc dl = N->getDebugLoc();
1484 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1485 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1486 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1487 SDValue LoOps[2] = { LHSL, RHSL };
1488 SDValue HiOps[3] = { LHSH, RHSH };
1490 if (N->getOpcode() == ISD::ADDC) {
1491 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1492 HiOps[2] = Lo.getValue(1);
1493 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1495 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1496 HiOps[2] = Lo.getValue(1);
1497 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1500 // Legalized the flag result - switch anything that used the old flag to
1502 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1505 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1506 SDValue &Lo, SDValue &Hi) {
1507 // Expand the subcomponents.
1508 SDValue LHSL, LHSH, RHSL, RHSH;
1509 DebugLoc dl = N->getDebugLoc();
1510 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1511 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1512 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1513 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1514 SDValue HiOps[3] = { LHSH, RHSH };
1516 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1517 HiOps[2] = Lo.getValue(1);
1518 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1520 // Legalized the flag result - switch anything that used the old flag to
1522 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1525 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1526 SDValue &Lo, SDValue &Hi) {
1527 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1528 DebugLoc dl = N->getDebugLoc();
1529 SDValue Op = N->getOperand(0);
1530 if (Op.getValueType().bitsLE(NVT)) {
1531 // The low part is any extension of the input (which degenerates to a copy).
1532 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1533 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1535 // For example, extension of an i48 to an i64. The operand type necessarily
1536 // promotes to the result type, so will end up being expanded too.
1537 assert(getTypeAction(Op.getValueType()) ==
1538 TargetLowering::TypePromoteInteger &&
1539 "Only know how to promote this result!");
1540 SDValue Res = GetPromotedInteger(Op);
1541 assert(Res.getValueType() == N->getValueType(0) &&
1542 "Operand over promoted?");
1543 // Split the promoted operand. This will simplify when it is expanded.
1544 SplitInteger(Res, Lo, Hi);
1548 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1549 SDValue &Lo, SDValue &Hi) {
1550 DebugLoc dl = N->getDebugLoc();
1551 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1552 EVT NVT = Lo.getValueType();
1553 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1554 unsigned NVTBits = NVT.getSizeInBits();
1555 unsigned EVTBits = EVT.getSizeInBits();
1557 if (NVTBits < EVTBits) {
1558 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1559 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1560 EVTBits - NVTBits)));
1562 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1563 // The high part replicates the sign bit of Lo, make it explicit.
1564 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1565 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1569 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1570 SDValue &Lo, SDValue &Hi) {
1571 DebugLoc dl = N->getDebugLoc();
1572 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1573 EVT NVT = Lo.getValueType();
1574 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1575 unsigned NVTBits = NVT.getSizeInBits();
1576 unsigned EVTBits = EVT.getSizeInBits();
1578 if (NVTBits < EVTBits) {
1579 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1580 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1581 EVTBits - NVTBits)));
1583 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1584 // The high part must be zero, make it explicit.
1585 Hi = DAG.getConstant(0, NVT);
1589 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1590 SDValue &Lo, SDValue &Hi) {
1591 DebugLoc dl = N->getDebugLoc();
1592 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1593 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1594 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1597 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1598 SDValue &Lo, SDValue &Hi) {
1599 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1600 unsigned NBitWidth = NVT.getSizeInBits();
1601 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1602 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1603 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1606 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1607 SDValue &Lo, SDValue &Hi) {
1608 DebugLoc dl = N->getDebugLoc();
1609 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1610 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1611 EVT NVT = Lo.getValueType();
1613 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1614 DAG.getConstant(0, NVT), ISD::SETNE);
1616 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1617 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1619 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1620 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1621 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1622 Hi = DAG.getConstant(0, NVT);
1625 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1626 SDValue &Lo, SDValue &Hi) {
1627 DebugLoc dl = N->getDebugLoc();
1628 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1629 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1630 EVT NVT = Lo.getValueType();
1631 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1632 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1633 Hi = DAG.getConstant(0, NVT);
1636 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1637 SDValue &Lo, SDValue &Hi) {
1638 DebugLoc dl = N->getDebugLoc();
1639 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1640 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1641 EVT NVT = Lo.getValueType();
1643 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1644 DAG.getConstant(0, NVT), ISD::SETNE);
1646 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1647 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1649 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1650 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1651 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1652 Hi = DAG.getConstant(0, NVT);
1655 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1657 DebugLoc dl = N->getDebugLoc();
1658 EVT VT = N->getValueType(0);
1659 SDValue Op = N->getOperand(0);
1660 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1661 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1662 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1665 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1667 DebugLoc dl = N->getDebugLoc();
1668 EVT VT = N->getValueType(0);
1669 SDValue Op = N->getOperand(0);
1670 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1671 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1672 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1675 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1676 SDValue &Lo, SDValue &Hi) {
1677 if (ISD::isNormalLoad(N)) {
1678 ExpandRes_NormalLoad(N, Lo, Hi);
1682 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1684 EVT VT = N->getValueType(0);
1685 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1686 SDValue Ch = N->getChain();
1687 SDValue Ptr = N->getBasePtr();
1688 ISD::LoadExtType ExtType = N->getExtensionType();
1689 unsigned Alignment = N->getAlignment();
1690 bool isVolatile = N->isVolatile();
1691 bool isNonTemporal = N->isNonTemporal();
1692 DebugLoc dl = N->getDebugLoc();
1694 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1696 if (N->getMemoryVT().bitsLE(NVT)) {
1697 EVT MemVT = N->getMemoryVT();
1699 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1700 MemVT, isVolatile, isNonTemporal, Alignment);
1702 // Remember the chain.
1703 Ch = Lo.getValue(1);
1705 if (ExtType == ISD::SEXTLOAD) {
1706 // The high part is obtained by SRA'ing all but one of the bits of the
1708 unsigned LoSize = Lo.getValueType().getSizeInBits();
1709 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1710 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1711 } else if (ExtType == ISD::ZEXTLOAD) {
1712 // The high part is just a zero.
1713 Hi = DAG.getConstant(0, NVT);
1715 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1716 // The high part is undefined.
1717 Hi = DAG.getUNDEF(NVT);
1719 } else if (TLI.isLittleEndian()) {
1720 // Little-endian - low bits are at low addresses.
1721 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1722 isVolatile, isNonTemporal, Alignment);
1724 unsigned ExcessBits =
1725 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1726 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1728 // Increment the pointer to the other half.
1729 unsigned IncrementSize = NVT.getSizeInBits()/8;
1730 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1731 DAG.getIntPtrConstant(IncrementSize));
1732 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1733 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1734 isVolatile, isNonTemporal,
1735 MinAlign(Alignment, IncrementSize));
1737 // Build a factor node to remember that this load is independent of the
1739 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1742 // Big-endian - high bits are at low addresses. Favor aligned loads at
1743 // the cost of some bit-fiddling.
1744 EVT MemVT = N->getMemoryVT();
1745 unsigned EBytes = MemVT.getStoreSize();
1746 unsigned IncrementSize = NVT.getSizeInBits()/8;
1747 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1749 // Load both the high bits and maybe some of the low bits.
1750 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1751 EVT::getIntegerVT(*DAG.getContext(),
1752 MemVT.getSizeInBits() - ExcessBits),
1753 isVolatile, isNonTemporal, Alignment);
1755 // Increment the pointer to the other half.
1756 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1757 DAG.getIntPtrConstant(IncrementSize));
1758 // Load the rest of the low bits.
1759 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1760 N->getPointerInfo().getWithOffset(IncrementSize),
1761 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1762 isVolatile, isNonTemporal,
1763 MinAlign(Alignment, IncrementSize));
1765 // Build a factor node to remember that this load is independent of the
1767 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1770 if (ExcessBits < NVT.getSizeInBits()) {
1771 // Transfer low bits from the bottom of Hi to the top of Lo.
1772 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1773 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1774 DAG.getConstant(ExcessBits,
1775 TLI.getPointerTy())));
1776 // Move high bits to the right position in Hi.
1777 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1779 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1780 TLI.getPointerTy()));
1784 // Legalized the chain result - switch anything that used the old chain to
1786 ReplaceValueWith(SDValue(N, 1), Ch);
1789 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1790 SDValue &Lo, SDValue &Hi) {
1791 DebugLoc dl = N->getDebugLoc();
1792 SDValue LL, LH, RL, RH;
1793 GetExpandedInteger(N->getOperand(0), LL, LH);
1794 GetExpandedInteger(N->getOperand(1), RL, RH);
1795 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1796 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1799 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1800 SDValue &Lo, SDValue &Hi) {
1801 EVT VT = N->getValueType(0);
1802 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1803 DebugLoc dl = N->getDebugLoc();
1805 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1806 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1807 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1808 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1809 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1810 SDValue LL, LH, RL, RH;
1811 GetExpandedInteger(N->getOperand(0), LL, LH);
1812 GetExpandedInteger(N->getOperand(1), RL, RH);
1813 unsigned OuterBitSize = VT.getSizeInBits();
1814 unsigned InnerBitSize = NVT.getSizeInBits();
1815 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1816 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1818 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1819 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1820 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1821 // The inputs are both zero-extended.
1823 // We can emit a umul_lohi.
1824 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1825 Hi = SDValue(Lo.getNode(), 1);
1829 // We can emit a mulhu+mul.
1830 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1831 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1835 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1836 // The input values are both sign-extended.
1838 // We can emit a smul_lohi.
1839 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1840 Hi = SDValue(Lo.getNode(), 1);
1844 // We can emit a mulhs+mul.
1845 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1846 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1851 // Lo,Hi = umul LHS, RHS.
1852 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1853 DAG.getVTList(NVT, NVT), LL, RL);
1855 Hi = UMulLOHI.getValue(1);
1856 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1857 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1858 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1859 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1863 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1864 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1865 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1866 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1867 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1868 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1873 // If nothing else, we can make a libcall.
1874 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1876 LC = RTLIB::MUL_I16;
1877 else if (VT == MVT::i32)
1878 LC = RTLIB::MUL_I32;
1879 else if (VT == MVT::i64)
1880 LC = RTLIB::MUL_I64;
1881 else if (VT == MVT::i128)
1882 LC = RTLIB::MUL_I128;
1883 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1885 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1886 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1889 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1890 SDValue &Lo, SDValue &Hi) {
1891 SDValue LHS = Node->getOperand(0);
1892 SDValue RHS = Node->getOperand(1);
1893 DebugLoc dl = Node->getDebugLoc();
1895 // Expand the result by simply replacing it with the equivalent
1896 // non-overflow-checking operation.
1897 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1898 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1900 SplitInteger(Sum, Lo, Hi);
1902 // Compute the overflow.
1904 // LHSSign -> LHS >= 0
1905 // RHSSign -> RHS >= 0
1906 // SumSign -> Sum >= 0
1909 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
1911 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
1913 EVT OType = Node->getValueType(1);
1914 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
1916 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
1917 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
1918 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
1919 Node->getOpcode() == ISD::SADDO ?
1920 ISD::SETEQ : ISD::SETNE);
1922 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
1923 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
1925 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
1927 // Use the calculated overflow everywhere.
1928 ReplaceValueWith(SDValue(Node, 1), Cmp);
1931 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1932 SDValue &Lo, SDValue &Hi) {
1933 EVT VT = N->getValueType(0);
1934 DebugLoc dl = N->getDebugLoc();
1936 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1938 LC = RTLIB::SDIV_I16;
1939 else if (VT == MVT::i32)
1940 LC = RTLIB::SDIV_I32;
1941 else if (VT == MVT::i64)
1942 LC = RTLIB::SDIV_I64;
1943 else if (VT == MVT::i128)
1944 LC = RTLIB::SDIV_I128;
1945 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1947 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1948 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1951 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1952 SDValue &Lo, SDValue &Hi) {
1953 EVT VT = N->getValueType(0);
1954 DebugLoc dl = N->getDebugLoc();
1956 // If we can emit an efficient shift operation, do so now. Check to see if
1957 // the RHS is a constant.
1958 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1959 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1961 // If we can determine that the high bit of the shift is zero or one, even if
1962 // the low bits are variable, emit this shift in an optimized form.
1963 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1966 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1968 if (N->getOpcode() == ISD::SHL) {
1969 PartsOpc = ISD::SHL_PARTS;
1970 } else if (N->getOpcode() == ISD::SRL) {
1971 PartsOpc = ISD::SRL_PARTS;
1973 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1974 PartsOpc = ISD::SRA_PARTS;
1977 // Next check to see if the target supports this SHL_PARTS operation or if it
1978 // will custom expand it.
1979 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1980 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1981 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1982 Action == TargetLowering::Custom) {
1983 // Expand the subcomponents.
1985 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1987 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1988 EVT VT = LHSL.getValueType();
1989 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1990 Hi = Lo.getValue(1);
1994 // Otherwise, emit a libcall.
1995 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1997 if (N->getOpcode() == ISD::SHL) {
1998 isSigned = false; /*sign irrelevant*/
2000 LC = RTLIB::SHL_I16;
2001 else if (VT == MVT::i32)
2002 LC = RTLIB::SHL_I32;
2003 else if (VT == MVT::i64)
2004 LC = RTLIB::SHL_I64;
2005 else if (VT == MVT::i128)
2006 LC = RTLIB::SHL_I128;
2007 } else if (N->getOpcode() == ISD::SRL) {
2010 LC = RTLIB::SRL_I16;
2011 else if (VT == MVT::i32)
2012 LC = RTLIB::SRL_I32;
2013 else if (VT == MVT::i64)
2014 LC = RTLIB::SRL_I64;
2015 else if (VT == MVT::i128)
2016 LC = RTLIB::SRL_I128;
2018 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2021 LC = RTLIB::SRA_I16;
2022 else if (VT == MVT::i32)
2023 LC = RTLIB::SRA_I32;
2024 else if (VT == MVT::i64)
2025 LC = RTLIB::SRA_I64;
2026 else if (VT == MVT::i128)
2027 LC = RTLIB::SRA_I128;
2030 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2031 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2032 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
2036 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2037 llvm_unreachable("Unsupported shift!");
2040 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2041 SDValue &Lo, SDValue &Hi) {
2042 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2043 DebugLoc dl = N->getDebugLoc();
2044 SDValue Op = N->getOperand(0);
2045 if (Op.getValueType().bitsLE(NVT)) {
2046 // The low part is sign extension of the input (degenerates to a copy).
2047 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2048 // The high part is obtained by SRA'ing all but one of the bits of low part.
2049 unsigned LoSize = NVT.getSizeInBits();
2050 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2051 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2053 // For example, extension of an i48 to an i64. The operand type necessarily
2054 // promotes to the result type, so will end up being expanded too.
2055 assert(getTypeAction(Op.getValueType()) ==
2056 TargetLowering::TypePromoteInteger &&
2057 "Only know how to promote this result!");
2058 SDValue Res = GetPromotedInteger(Op);
2059 assert(Res.getValueType() == N->getValueType(0) &&
2060 "Operand over promoted?");
2061 // Split the promoted operand. This will simplify when it is expanded.
2062 SplitInteger(Res, Lo, Hi);
2063 unsigned ExcessBits =
2064 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2065 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2066 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2071 void DAGTypeLegalizer::
2072 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2073 DebugLoc dl = N->getDebugLoc();
2074 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2075 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2077 if (EVT.bitsLE(Lo.getValueType())) {
2078 // sext_inreg the low part if needed.
2079 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2082 // The high part gets the sign extension from the lo-part. This handles
2083 // things like sextinreg V:i64 from i8.
2084 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2085 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2086 TLI.getPointerTy()));
2088 // For example, extension of an i48 to an i64. Leave the low part alone,
2089 // sext_inreg the high part.
2090 unsigned ExcessBits =
2091 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2092 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2093 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2098 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2099 SDValue &Lo, SDValue &Hi) {
2100 EVT VT = N->getValueType(0);
2101 DebugLoc dl = N->getDebugLoc();
2103 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2105 LC = RTLIB::SREM_I16;
2106 else if (VT == MVT::i32)
2107 LC = RTLIB::SREM_I32;
2108 else if (VT == MVT::i64)
2109 LC = RTLIB::SREM_I64;
2110 else if (VT == MVT::i128)
2111 LC = RTLIB::SREM_I128;
2112 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2114 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2115 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2118 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2119 SDValue &Lo, SDValue &Hi) {
2120 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2121 DebugLoc dl = N->getDebugLoc();
2122 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2123 Hi = DAG.getNode(ISD::SRL, dl,
2124 N->getOperand(0).getValueType(), N->getOperand(0),
2125 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2126 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2129 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2130 SDValue &Lo, SDValue &Hi) {
2131 SDValue LHS = N->getOperand(0);
2132 SDValue RHS = N->getOperand(1);
2133 DebugLoc dl = N->getDebugLoc();
2135 // Expand the result by simply replacing it with the equivalent
2136 // non-overflow-checking operation.
2137 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2138 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2140 SplitInteger(Sum, Lo, Hi);
2142 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2143 // overflows iff a - b > a.
2144 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2145 N->getOpcode () == ISD::UADDO ?
2146 ISD::SETULT : ISD::SETUGT);
2148 // Use the calculated overflow everywhere.
2149 ReplaceValueWith(SDValue(N, 1), Ofl);
2152 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2153 SDValue &Lo, SDValue &Hi) {
2154 EVT VT = N->getValueType(0);
2155 DebugLoc dl = N->getDebugLoc();
2157 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2159 LC = RTLIB::UDIV_I16;
2160 else if (VT == MVT::i32)
2161 LC = RTLIB::UDIV_I32;
2162 else if (VT == MVT::i64)
2163 LC = RTLIB::UDIV_I64;
2164 else if (VT == MVT::i128)
2165 LC = RTLIB::UDIV_I128;
2166 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2168 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2169 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2172 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2173 SDValue &Lo, SDValue &Hi) {
2174 EVT VT = N->getValueType(0);
2175 DebugLoc dl = N->getDebugLoc();
2177 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2179 LC = RTLIB::UREM_I16;
2180 else if (VT == MVT::i32)
2181 LC = RTLIB::UREM_I32;
2182 else if (VT == MVT::i64)
2183 LC = RTLIB::UREM_I64;
2184 else if (VT == MVT::i128)
2185 LC = RTLIB::UREM_I128;
2186 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2188 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2189 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2192 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2193 SDValue &Lo, SDValue &Hi) {
2194 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2195 DebugLoc dl = N->getDebugLoc();
2196 SDValue Op = N->getOperand(0);
2197 if (Op.getValueType().bitsLE(NVT)) {
2198 // The low part is zero extension of the input (degenerates to a copy).
2199 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2200 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2202 // For example, extension of an i48 to an i64. The operand type necessarily
2203 // promotes to the result type, so will end up being expanded too.
2204 assert(getTypeAction(Op.getValueType()) ==
2205 TargetLowering::TypePromoteInteger &&
2206 "Only know how to promote this result!");
2207 SDValue Res = GetPromotedInteger(Op);
2208 assert(Res.getValueType() == N->getValueType(0) &&
2209 "Operand over promoted?");
2210 // Split the promoted operand. This will simplify when it is expanded.
2211 SplitInteger(Res, Lo, Hi);
2212 unsigned ExcessBits =
2213 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2214 Hi = DAG.getZeroExtendInReg(Hi, dl,
2215 EVT::getIntegerVT(*DAG.getContext(),
2221 //===----------------------------------------------------------------------===//
2222 // Integer Operand Expansion
2223 //===----------------------------------------------------------------------===//
2225 /// ExpandIntegerOperand - This method is called when the specified operand of
2226 /// the specified node is found to need expansion. At this point, all of the
2227 /// result types of the node are known to be legal, but other operands of the
2228 /// node may need promotion or expansion as well as the specified one.
2229 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2230 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2231 SDValue Res = SDValue();
2233 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2236 switch (N->getOpcode()) {
2239 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2240 N->dump(&DAG); dbgs() << "\n";
2242 llvm_unreachable("Do not know how to expand this operator's operand!");
2244 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2245 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2246 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2247 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2248 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2249 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2250 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2251 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2252 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2253 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2254 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2255 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2261 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2262 case ISD::RETURNADDR:
2263 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2266 // If the result is null, the sub-method took care of registering results etc.
2267 if (!Res.getNode()) return false;
2269 // If the result is N, the sub-method updated N in place. Tell the legalizer
2271 if (Res.getNode() == N)
2274 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2275 "Invalid operand expansion");
2277 ReplaceValueWith(SDValue(N, 0), Res);
2281 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2282 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2283 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2285 ISD::CondCode &CCCode,
2287 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2288 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2289 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2291 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2292 if (RHSLo == RHSHi) {
2293 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2294 if (RHSCST->isAllOnesValue()) {
2295 // Equality comparison to -1.
2296 NewLHS = DAG.getNode(ISD::AND, dl,
2297 LHSLo.getValueType(), LHSLo, LHSHi);
2304 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2305 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2306 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2307 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2311 // If this is a comparison of the sign bit, just look at the top part.
2313 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2314 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2315 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2321 // FIXME: This generated code sucks.
2322 ISD::CondCode LowCC;
2324 default: llvm_unreachable("Unknown integer setcc!");
2326 case ISD::SETULT: LowCC = ISD::SETULT; break;
2328 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2330 case ISD::SETULE: LowCC = ISD::SETULE; break;
2332 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2335 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2336 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2337 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2339 // NOTE: on targets without efficient SELECT of bools, we can always use
2340 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2341 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2343 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2344 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2345 if (!Tmp1.getNode())
2346 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2347 LHSLo, RHSLo, LowCC);
2348 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2349 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2350 if (!Tmp2.getNode())
2351 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2352 TLI.getSetCCResultType(LHSHi.getValueType()),
2353 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2355 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2356 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2357 if ((Tmp1C && Tmp1C->isNullValue()) ||
2358 (Tmp2C && Tmp2C->isNullValue() &&
2359 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2360 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2361 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2362 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2363 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2364 // low part is known false, returns high part.
2365 // For LE / GE, if high part is known false, ignore the low part.
2366 // For LT / GT, if high part is known true, ignore the low part.
2372 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2373 LHSHi, RHSHi, ISD::SETEQ, false,
2374 DagCombineInfo, dl);
2375 if (!NewLHS.getNode())
2376 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2377 LHSHi, RHSHi, ISD::SETEQ);
2378 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2379 NewLHS, Tmp1, Tmp2);
2383 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2384 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2385 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2386 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2388 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2389 // against zero to select between true and false values.
2390 if (NewRHS.getNode() == 0) {
2391 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2392 CCCode = ISD::SETNE;
2395 // Update N to have the operands specified.
2396 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2397 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2398 N->getOperand(4)), 0);
2401 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2402 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2403 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2404 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2406 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2407 // against zero to select between true and false values.
2408 if (NewRHS.getNode() == 0) {
2409 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2410 CCCode = ISD::SETNE;
2413 // Update N to have the operands specified.
2414 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2415 N->getOperand(2), N->getOperand(3),
2416 DAG.getCondCode(CCCode)), 0);
2419 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2420 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2421 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2422 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2424 // If ExpandSetCCOperands returned a scalar, use it.
2425 if (NewRHS.getNode() == 0) {
2426 assert(NewLHS.getValueType() == N->getValueType(0) &&
2427 "Unexpected setcc expansion!");
2431 // Otherwise, update N to have the operands specified.
2432 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2433 DAG.getCondCode(CCCode)), 0);
2436 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2437 // The value being shifted is legal, but the shift amount is too big.
2438 // It follows that either the result of the shift is undefined, or the
2439 // upper half of the shift amount is zero. Just use the lower half.
2441 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2442 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2445 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2446 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2447 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2448 // constant to valid type.
2450 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2451 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2454 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2455 SDValue Op = N->getOperand(0);
2456 EVT DstVT = N->getValueType(0);
2457 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2458 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2459 "Don't know how to expand this SINT_TO_FP!");
2460 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2463 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2464 if (ISD::isNormalStore(N))
2465 return ExpandOp_NormalStore(N, OpNo);
2467 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2468 assert(OpNo == 1 && "Can only expand the stored value so far");
2470 EVT VT = N->getOperand(1).getValueType();
2471 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2472 SDValue Ch = N->getChain();
2473 SDValue Ptr = N->getBasePtr();
2474 unsigned Alignment = N->getAlignment();
2475 bool isVolatile = N->isVolatile();
2476 bool isNonTemporal = N->isNonTemporal();
2477 DebugLoc dl = N->getDebugLoc();
2480 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2482 if (N->getMemoryVT().bitsLE(NVT)) {
2483 GetExpandedInteger(N->getValue(), Lo, Hi);
2484 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2485 N->getMemoryVT(), isVolatile, isNonTemporal,
2489 if (TLI.isLittleEndian()) {
2490 // Little-endian - low bits are at low addresses.
2491 GetExpandedInteger(N->getValue(), Lo, Hi);
2493 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2494 isVolatile, isNonTemporal, Alignment);
2496 unsigned ExcessBits =
2497 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2498 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2500 // Increment the pointer to the other half.
2501 unsigned IncrementSize = NVT.getSizeInBits()/8;
2502 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2503 DAG.getIntPtrConstant(IncrementSize));
2504 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2505 N->getPointerInfo().getWithOffset(IncrementSize),
2506 NEVT, isVolatile, isNonTemporal,
2507 MinAlign(Alignment, IncrementSize));
2508 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2511 // Big-endian - high bits are at low addresses. Favor aligned stores at
2512 // the cost of some bit-fiddling.
2513 GetExpandedInteger(N->getValue(), Lo, Hi);
2515 EVT ExtVT = N->getMemoryVT();
2516 unsigned EBytes = ExtVT.getStoreSize();
2517 unsigned IncrementSize = NVT.getSizeInBits()/8;
2518 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2519 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2520 ExtVT.getSizeInBits() - ExcessBits);
2522 if (ExcessBits < NVT.getSizeInBits()) {
2523 // Transfer high bits from the top of Lo to the bottom of Hi.
2524 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2525 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2526 TLI.getPointerTy()));
2527 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2528 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2529 DAG.getConstant(ExcessBits,
2530 TLI.getPointerTy())));
2533 // Store both the high bits and maybe some of the low bits.
2534 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2535 HiVT, isVolatile, isNonTemporal, Alignment);
2537 // Increment the pointer to the other half.
2538 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2539 DAG.getIntPtrConstant(IncrementSize));
2540 // Store the lowest ExcessBits bits in the second half.
2541 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2542 N->getPointerInfo().getWithOffset(IncrementSize),
2543 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2544 isVolatile, isNonTemporal,
2545 MinAlign(Alignment, IncrementSize));
2546 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2549 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2551 GetExpandedInteger(N->getOperand(0), InL, InH);
2552 // Just truncate the low part of the source.
2553 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2556 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2557 switch (VT.getSimpleVT().SimpleTy) {
2558 default: llvm_unreachable("Unknown FP format");
2559 case MVT::f32: return &APFloat::IEEEsingle;
2560 case MVT::f64: return &APFloat::IEEEdouble;
2561 case MVT::f80: return &APFloat::x87DoubleExtended;
2562 case MVT::f128: return &APFloat::IEEEquad;
2563 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2567 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2568 SDValue Op = N->getOperand(0);
2569 EVT SrcVT = Op.getValueType();
2570 EVT DstVT = N->getValueType(0);
2571 DebugLoc dl = N->getDebugLoc();
2573 // The following optimization is valid only if every value in SrcVT (when
2574 // treated as signed) is representable in DstVT. Check that the mantissa
2575 // size of DstVT is >= than the number of bits in SrcVT -1.
2576 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2577 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2578 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2579 // Do a signed conversion then adjust the result.
2580 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2581 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2583 // The result of the signed conversion needs adjusting if the 'sign bit' of
2584 // the incoming integer was set. To handle this, we dynamically test to see
2585 // if it is set, and, if so, add a fudge factor.
2587 const uint64_t F32TwoE32 = 0x4F800000ULL;
2588 const uint64_t F32TwoE64 = 0x5F800000ULL;
2589 const uint64_t F32TwoE128 = 0x7F800000ULL;
2592 if (SrcVT == MVT::i32)
2593 FF = APInt(32, F32TwoE32);
2594 else if (SrcVT == MVT::i64)
2595 FF = APInt(32, F32TwoE64);
2596 else if (SrcVT == MVT::i128)
2597 FF = APInt(32, F32TwoE128);
2599 assert(false && "Unsupported UINT_TO_FP!");
2601 // Check whether the sign bit is set.
2603 GetExpandedInteger(Op, Lo, Hi);
2604 SDValue SignSet = DAG.getSetCC(dl,
2605 TLI.getSetCCResultType(Hi.getValueType()),
2606 Hi, DAG.getConstant(0, Hi.getValueType()),
2609 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2610 SDValue FudgePtr = DAG.getConstantPool(
2611 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2612 TLI.getPointerTy());
2614 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2615 SDValue Zero = DAG.getIntPtrConstant(0);
2616 SDValue Four = DAG.getIntPtrConstant(4);
2617 if (TLI.isBigEndian()) std::swap(Zero, Four);
2618 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2620 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2621 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2622 Alignment = std::min(Alignment, 4u);
2624 // Load the value out, extending it from f32 to the destination float type.
2625 // FIXME: Avoid the extend by constructing the right constant pool?
2626 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2628 MachinePointerInfo::getConstantPool(),
2630 false, false, Alignment);
2631 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2634 // Otherwise, use a libcall.
2635 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2636 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2637 "Don't know how to expand this UINT_TO_FP!");
2638 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);
2641 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2642 SDValue InOp0 = N->getOperand(0);
2643 EVT InVT = InOp0.getValueType();
2644 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
2646 EVT OutVT = N->getValueType(0);
2647 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2648 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2649 unsigned OutNumElems = N->getValueType(0).getVectorNumElements();
2650 EVT NOutVTElem = NOutVT.getVectorElementType();
2652 DebugLoc dl = N->getDebugLoc();
2653 SDValue BaseIdx = N->getOperand(1);
2655 SmallVector<SDValue, 8> Ops;
2656 for (unsigned i = 0; i != OutNumElems; ++i) {
2658 // Extract the element from the original vector.
2659 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2660 BaseIdx, DAG.getIntPtrConstant(i));
2661 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2662 InVT.getVectorElementType(), N->getOperand(0), Index);
2664 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2665 // Insert the converted element to the new vector.
2669 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2673 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2675 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2676 EVT VT = N->getValueType(0);
2677 DebugLoc dl = N->getDebugLoc();
2679 unsigned NumElts = VT.getVectorNumElements();
2680 SmallVector<int, 8> NewMask;
2681 for (unsigned i = 0; i != NumElts; ++i) {
2682 NewMask.push_back(SV->getMaskElt(i));
2685 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2686 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2687 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2689 return DAG.getVectorShuffle(OutVT, dl, V0,V1, &NewMask[0]);
2693 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2695 SDValue InOp0 = N->getOperand(0);
2696 EVT InVT = InOp0.getValueType();
2697 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
2699 EVT OutVT = N->getValueType(0);
2700 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2701 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2702 unsigned NumElems = N->getNumOperands();
2703 EVT NOutVTElem = NOutVT.getVectorElementType();
2705 DebugLoc dl = N->getDebugLoc();
2707 SmallVector<SDValue, 8> Ops;
2708 for (unsigned i = 0; i != NumElems; ++i) {
2709 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2713 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2716 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2718 DebugLoc dl = N->getDebugLoc();
2720 SDValue InOp0 = N->getOperand(0);
2721 EVT InVT = InOp0.getValueType();
2722 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
2723 assert(!InVT.isVector() && "Input must not be a scalar");
2725 EVT OutVT = N->getValueType(0);
2726 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2727 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2728 EVT NOutVTElem = NOutVT.getVectorElementType();
2730 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2732 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2735 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
2737 SDValue InOp0 = N->getOperand(0);
2738 EVT InVT = InOp0.getValueType();
2739 EVT InElVT = InVT.getVectorElementType();
2740 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
2742 EVT OutVT = N->getValueType(0);
2743 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2744 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2746 EVT NOutVTElem = NOutVT.getVectorElementType();
2748 DebugLoc dl = N->getDebugLoc();
2750 SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp0);
2752 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
2753 NOutVTElem, N->getOperand(1));
2754 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,NOutVT,
2755 ConvertedVector, ConvElem, N->getOperand(2));
2758 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2759 DebugLoc dl = N->getDebugLoc();
2760 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2761 SDValue V1 = N->getOperand(1);
2762 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2763 V0->getValueType(0).getScalarType(), V0, V1);
2765 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
2769 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
2771 DebugLoc dl = N->getDebugLoc();
2773 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
2775 SmallVector<SDValue, 8> NewOps;
2777 // For each incoming vector
2778 for (unsigned VecIdx = 0, E = N->getNumOperands(); VecIdx!= E; ++VecIdx) {
2779 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
2780 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
2781 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
2783 for (unsigned i=0; i<NumElem; ++i) {
2784 // Extract element from incoming vector
2785 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
2786 Incoming, DAG.getIntPtrConstant(i));
2787 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
2788 NewOps.push_back(Tr);
2792 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
2793 &NewOps[0], NewOps.size());