1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
57 case ISD::CONVERT_RNDSAT:
58 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
59 case ISD::CTLZ_ZERO_UNDEF:
60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
61 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
62 case ISD::CTTZ_ZERO_UNDEF:
63 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
64 case ISD::EXTRACT_VECTOR_ELT:
65 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
66 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
67 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
68 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
73 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
80 case ISD::EXTRACT_SUBVECTOR:
81 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
82 case ISD::VECTOR_SHUFFLE:
83 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
84 case ISD::INSERT_VECTOR_ELT:
85 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
86 case ISD::BUILD_VECTOR:
87 Res = PromoteIntRes_BUILD_VECTOR(N); break;
88 case ISD::SCALAR_TO_VECTOR:
89 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
90 case ISD::CONCAT_VECTORS:
91 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
93 case ISD::SIGN_EXTEND:
94 case ISD::ZERO_EXTEND:
95 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
98 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
100 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
107 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
110 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
113 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
116 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
118 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
120 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
122 case ISD::ATOMIC_LOAD:
123 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
125 case ISD::ATOMIC_LOAD_ADD:
126 case ISD::ATOMIC_LOAD_SUB:
127 case ISD::ATOMIC_LOAD_AND:
128 case ISD::ATOMIC_LOAD_OR:
129 case ISD::ATOMIC_LOAD_XOR:
130 case ISD::ATOMIC_LOAD_NAND:
131 case ISD::ATOMIC_LOAD_MIN:
132 case ISD::ATOMIC_LOAD_MAX:
133 case ISD::ATOMIC_LOAD_UMIN:
134 case ISD::ATOMIC_LOAD_UMAX:
135 case ISD::ATOMIC_SWAP:
136 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
138 case ISD::ATOMIC_CMP_SWAP:
139 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
142 // If the result is null then the sub-method took care of registering it.
144 SetPromotedInteger(SDValue(N, ResNo), Res);
147 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
149 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
150 return GetPromotedInteger(Op);
153 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
154 // Sign-extend the new bits, and continue the assertion.
155 SDValue Op = SExtPromotedInteger(N->getOperand(0));
156 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
157 Op.getValueType(), Op, N->getOperand(1));
160 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
161 // Zero the new bits, and continue the assertion.
162 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
163 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
164 Op.getValueType(), Op, N->getOperand(1));
167 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
169 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
170 N->getMemoryVT(), ResVT,
171 N->getChain(), N->getBasePtr(),
172 N->getMemOperand(), N->getOrdering(),
174 // Legalized the chain result - switch anything that used the old chain to
176 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
180 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
181 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
182 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
184 N->getChain(), N->getBasePtr(),
185 Op2, N->getMemOperand(), N->getOrdering(),
187 // Legalized the chain result - switch anything that used the old chain to
189 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
193 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
195 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
196 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
197 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
198 Op2, Op3, N->getMemOperand(), N->getOrdering(),
200 // Legalized the chain result - switch anything that used the old chain to
202 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
206 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
207 SDValue InOp = N->getOperand(0);
208 EVT InVT = InOp.getValueType();
209 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
210 EVT OutVT = N->getValueType(0);
211 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
212 DebugLoc dl = N->getDebugLoc();
214 switch (getTypeAction(InVT)) {
215 case TargetLowering::TypeLegal:
217 case TargetLowering::TypePromoteInteger:
218 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
219 // The input promotes to the same size. Convert the promoted value.
220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
222 case TargetLowering::TypeSoftenFloat:
223 // Promote the integer operand by hand.
224 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
225 case TargetLowering::TypeExpandInteger:
226 case TargetLowering::TypeExpandFloat:
228 case TargetLowering::TypeScalarizeVector:
229 // Convert the element to an integer and promote it by hand.
230 if (!NOutVT.isVector())
231 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
232 BitConvertToInteger(GetScalarizedVector(InOp)));
234 case TargetLowering::TypeSplitVector: {
235 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
236 // pieces of the input into integers and reassemble in the final type.
238 GetSplitVector(N->getOperand(0), Lo, Hi);
239 Lo = BitConvertToInteger(Lo);
240 Hi = BitConvertToInteger(Hi);
242 if (TLI.isBigEndian())
245 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
246 EVT::getIntegerVT(*DAG.getContext(),
247 NOutVT.getSizeInBits()),
248 JoinIntegers(Lo, Hi));
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
251 case TargetLowering::TypeWidenVector:
252 // The input is widened to the same size. Convert to the widened value.
253 // Make sure that the outgoing value is not a vector, because this would
254 // make us bitcast between two vectors which are legalized in different ways.
255 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
260 CreateStackStoreLoad(InOp, OutVT));
263 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
264 SDValue Op = GetPromotedInteger(N->getOperand(0));
265 EVT OVT = N->getValueType(0);
266 EVT NVT = Op.getValueType();
267 DebugLoc dl = N->getDebugLoc();
269 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
271 DAG.getConstant(DiffBits, TLI.getPointerTy()));
274 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
275 // The pair element type may be legal, or may not promote to the same type as
276 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
277 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
278 TLI.getTypeToTransformTo(*DAG.getContext(),
279 N->getValueType(0)), JoinIntegers(N->getOperand(0),
283 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
284 EVT VT = N->getValueType(0);
285 // FIXME there is no actual debug info here
286 DebugLoc dl = N->getDebugLoc();
287 // Zero extend things like i1, sign extend everything else. It shouldn't
288 // matter in theory which one we pick, but this tends to give better code?
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
290 SDValue Result = DAG.getNode(Opc, dl,
291 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
293 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
297 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
298 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
299 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
300 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
301 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
302 "can only promote integers");
303 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
304 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
305 N->getOperand(1), N->getOperand(2),
306 N->getOperand(3), N->getOperand(4), CvtCode);
309 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
310 // Zero extend to the promoted type and do the count there.
311 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
312 DebugLoc dl = N->getDebugLoc();
313 EVT OVT = N->getValueType(0);
314 EVT NVT = Op.getValueType();
315 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
316 // Subtract off the extra leading bits in the bigger type.
317 return DAG.getNode(ISD::SUB, dl, NVT, Op,
318 DAG.getConstant(NVT.getSizeInBits() -
319 OVT.getSizeInBits(), NVT));
322 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
323 // Zero extend to the promoted type and do the count there.
324 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
325 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
328 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
329 SDValue Op = GetPromotedInteger(N->getOperand(0));
330 EVT OVT = N->getValueType(0);
331 EVT NVT = Op.getValueType();
332 DebugLoc dl = N->getDebugLoc();
333 if (N->getOpcode() == ISD::CTTZ) {
334 // The count is the same in the promoted type except if the original
335 // value was zero. This can be handled by setting the bit just off
336 // the top of the original type.
337 APInt TopBit(NVT.getSizeInBits(), 0);
338 TopBit.setBit(OVT.getSizeInBits());
339 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
341 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
344 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
345 DebugLoc dl = N->getDebugLoc();
346 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
351 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
352 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
353 unsigned NewOpc = N->getOpcode();
354 DebugLoc dl = N->getDebugLoc();
356 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
357 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
358 // and SINT conversions are Custom, there is no way to tell which is
359 // preferable. We choose SINT because that's the right thing on PPC.)
360 if (N->getOpcode() == ISD::FP_TO_UINT &&
361 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
362 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
363 NewOpc = ISD::FP_TO_SINT;
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
367 // Assert that the converted value fits in the original type. If it doesn't
368 // (eg: because the value being converted is too big), then the result of the
369 // original operation was undefined anyway, so the assert is still correct.
370 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
371 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
372 DAG.getValueType(N->getValueType(0).getScalarType()));
375 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
376 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
377 DebugLoc dl = N->getDebugLoc();
379 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
381 return DAG.getNode(ISD::AssertZext, dl,
382 NVT, Res, DAG.getValueType(N->getValueType(0)));
385 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
387 DebugLoc dl = N->getDebugLoc();
389 if (getTypeAction(N->getOperand(0).getValueType())
390 == TargetLowering::TypePromoteInteger) {
391 SDValue Res = GetPromotedInteger(N->getOperand(0));
392 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
394 // If the result and operand types are the same after promotion, simplify
395 // to an in-register extension.
396 if (NVT == Res.getValueType()) {
397 // The high bits are not guaranteed to be anything. Insert an extend.
398 if (N->getOpcode() == ISD::SIGN_EXTEND)
399 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
400 DAG.getValueType(N->getOperand(0).getValueType()));
401 if (N->getOpcode() == ISD::ZERO_EXTEND)
402 return DAG.getZeroExtendInReg(Res, dl,
403 N->getOperand(0).getValueType().getScalarType());
404 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
409 // Otherwise, just extend the original operand all the way to the larger type.
410 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
413 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
414 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
416 ISD::LoadExtType ExtType =
417 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
418 DebugLoc dl = N->getDebugLoc();
419 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
421 N->getMemoryVT(), N->isVolatile(),
422 N->isNonTemporal(), N->getAlignment());
424 // Legalized the chain result - switch anything that used the old chain to
426 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
430 /// Promote the overflow flag of an overflowing arithmetic node.
431 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
432 // Simply change the return type of the boolean result.
433 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
434 EVT ValueVTs[] = { N->getValueType(0), NVT };
435 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
436 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
437 DAG.getVTList(ValueVTs, 2), Ops, 2);
439 // Modified the sum result - switch anything that used the old sum to use
441 ReplaceValueWith(SDValue(N, 0), Res);
443 return SDValue(Res.getNode(), 1);
446 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
448 return PromoteIntRes_Overflow(N);
450 // The operation overflowed iff the result in the larger type is not the
451 // sign extension of its truncation to the original type.
452 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
453 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
454 EVT OVT = N->getOperand(0).getValueType();
455 EVT NVT = LHS.getValueType();
456 DebugLoc dl = N->getDebugLoc();
458 // Do the arithmetic in the larger type.
459 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
460 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
462 // Calculate the overflow flag: sign extend the arithmetic result from
463 // the original type.
464 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
465 DAG.getValueType(OVT));
466 // Overflowed if and only if this is not equal to Res.
467 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
469 // Use the calculated overflow everywhere.
470 ReplaceValueWith(SDValue(N, 1), Ofl);
475 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
476 // Sign extend the input.
477 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
478 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
479 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
480 LHS.getValueType(), LHS, RHS);
483 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
484 SDValue LHS = GetPromotedInteger(N->getOperand(1));
485 SDValue RHS = GetPromotedInteger(N->getOperand(2));
486 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
487 LHS.getValueType(), N->getOperand(0),LHS,RHS);
490 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
491 SDValue Mask = N->getOperand(0);
492 EVT OpTy = N->getOperand(1).getValueType();
494 // Promote all the way up to the canonical SetCC type.
495 Mask = PromoteTargetBoolean(Mask, TLI.getSetCCResultType(OpTy));
496 SDValue LHS = GetPromotedInteger(N->getOperand(1));
497 SDValue RHS = GetPromotedInteger(N->getOperand(2));
498 return DAG.getNode(ISD::VSELECT, N->getDebugLoc(),
499 LHS.getValueType(), Mask, LHS, RHS);
502 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
503 SDValue LHS = GetPromotedInteger(N->getOperand(2));
504 SDValue RHS = GetPromotedInteger(N->getOperand(3));
505 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
506 LHS.getValueType(), N->getOperand(0),
507 N->getOperand(1), LHS, RHS, N->getOperand(4));
510 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
511 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
513 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
515 // Only use the result of getSetCCResultType if it is legal,
516 // otherwise just use the promoted result type (NVT).
517 if (!TLI.isTypeLegal(SVT))
520 DebugLoc dl = N->getDebugLoc();
521 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
522 "Vector compare must return a vector result!");
524 // Get the SETCC result using the canonical SETCC type.
525 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
526 N->getOperand(1), N->getOperand(2));
528 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
529 // Convert to the expected type.
530 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
533 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
534 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
535 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
536 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
539 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
540 SDValue Op = GetPromotedInteger(N->getOperand(0));
541 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
542 Op.getValueType(), Op, N->getOperand(1));
545 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
546 // The input may have strange things in the top bits of the registers, but
547 // these operations don't care. They may have weird bits going out, but
548 // that too is okay if they are integer operations.
549 SDValue LHS = GetPromotedInteger(N->getOperand(0));
550 SDValue RHS = GetPromotedInteger(N->getOperand(1));
551 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
552 LHS.getValueType(), LHS, RHS);
555 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
556 // The input value must be properly sign extended.
557 SDValue Res = SExtPromotedInteger(N->getOperand(0));
558 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
559 Res.getValueType(), Res, N->getOperand(1));
562 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
563 // The input value must be properly zero extended.
564 EVT VT = N->getValueType(0);
565 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
566 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
567 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
570 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
571 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
573 SDValue InOp = N->getOperand(0);
574 DebugLoc dl = N->getDebugLoc();
576 switch (getTypeAction(InOp.getValueType())) {
577 default: llvm_unreachable("Unknown type action!");
578 case TargetLowering::TypeLegal:
579 case TargetLowering::TypeExpandInteger:
582 case TargetLowering::TypePromoteInteger:
583 Res = GetPromotedInteger(InOp);
585 case TargetLowering::TypeSplitVector:
586 EVT InVT = InOp.getValueType();
587 assert(InVT.isVector() && "Cannot split scalar types");
588 unsigned NumElts = InVT.getVectorNumElements();
589 assert(NumElts == NVT.getVectorNumElements() &&
590 "Dst and Src must have the same number of elements");
591 EVT EltVT = InVT.getScalarType();
592 assert(isPowerOf2_32(NumElts) &&
593 "Promoted vector type must be a power of two");
595 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts/2);
596 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
599 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
600 DAG.getIntPtrConstant(0));
601 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
602 DAG.getIntPtrConstant(NumElts/2));
603 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
604 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
606 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
609 // Truncate to NVT instead of VT
610 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
613 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
615 return PromoteIntRes_Overflow(N);
617 // The operation overflowed iff the result in the larger type is not the
618 // zero extension of its truncation to the original type.
619 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
620 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
621 EVT OVT = N->getOperand(0).getValueType();
622 EVT NVT = LHS.getValueType();
623 DebugLoc dl = N->getDebugLoc();
625 // Do the arithmetic in the larger type.
626 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
627 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
629 // Calculate the overflow flag: zero extend the arithmetic result from
630 // the original type.
631 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
632 // Overflowed if and only if this is not equal to Res.
633 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
635 // Use the calculated overflow everywhere.
636 ReplaceValueWith(SDValue(N, 1), Ofl);
641 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
642 // Promote the overflow bit trivially.
644 return PromoteIntRes_Overflow(N);
646 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
647 DebugLoc DL = N->getDebugLoc();
648 EVT SmallVT = LHS.getValueType();
650 // To determine if the result overflowed in a larger type, we extend the
651 // input to the larger type, do the multiply, then check the high bits of
652 // the result to see if the overflow happened.
653 if (N->getOpcode() == ISD::SMULO) {
654 LHS = SExtPromotedInteger(LHS);
655 RHS = SExtPromotedInteger(RHS);
657 LHS = ZExtPromotedInteger(LHS);
658 RHS = ZExtPromotedInteger(RHS);
660 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
662 // Overflow occurred iff the high part of the result does not
663 // zero/sign-extend the low part.
665 if (N->getOpcode() == ISD::UMULO) {
666 // Unsigned overflow occurred iff the high part is non-zero.
667 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
668 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
669 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
670 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
672 // Signed overflow occurred iff the high part does not sign extend the low.
673 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
674 Mul, DAG.getValueType(SmallVT));
675 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
678 // Use the calculated overflow everywhere.
679 ReplaceValueWith(SDValue(N, 1), Overflow);
683 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
684 // Zero extend the input.
685 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
686 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
687 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
688 LHS.getValueType(), LHS, RHS);
691 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
692 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
693 N->getValueType(0)));
696 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
697 SDValue Chain = N->getOperand(0); // Get the chain.
698 SDValue Ptr = N->getOperand(1); // Get the pointer.
699 EVT VT = N->getValueType(0);
700 DebugLoc dl = N->getDebugLoc();
702 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
703 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
704 // The argument is passed as NumRegs registers of type RegVT.
706 SmallVector<SDValue, 8> Parts(NumRegs);
707 for (unsigned i = 0; i < NumRegs; ++i) {
708 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
709 N->getConstantOperandVal(3));
710 Chain = Parts[i].getValue(1);
713 // Handle endianness of the load.
714 if (TLI.isBigEndian())
715 std::reverse(Parts.begin(), Parts.end());
717 // Assemble the parts in the promoted type.
718 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
719 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
720 for (unsigned i = 1; i < NumRegs; ++i) {
721 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
722 // Shift it to the right position and "or" it in.
723 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
724 DAG.getConstant(i * RegVT.getSizeInBits(),
725 TLI.getPointerTy()));
726 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
729 // Modified the chain result - switch anything that used the old chain to
731 ReplaceValueWith(SDValue(N, 1), Chain);
736 //===----------------------------------------------------------------------===//
737 // Integer Operand Promotion
738 //===----------------------------------------------------------------------===//
740 /// PromoteIntegerOperand - This method is called when the specified operand of
741 /// the specified node is found to need promotion. At this point, all of the
742 /// result types of the node are known to be legal, but other operands of the
743 /// node may need promotion or expansion as well as the specified one.
744 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
745 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
746 SDValue Res = SDValue();
748 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
751 switch (N->getOpcode()) {
754 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
755 N->dump(&DAG); dbgs() << "\n";
757 llvm_unreachable("Do not know how to promote this operator's operand!");
759 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
760 case ISD::ATOMIC_STORE:
761 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
763 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
764 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
765 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
766 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
767 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
768 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
769 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
770 case ISD::CONVERT_RNDSAT:
771 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
772 case ISD::INSERT_VECTOR_ELT:
773 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
774 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
775 case ISD::SCALAR_TO_VECTOR:
776 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
778 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
779 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
780 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
781 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
782 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
783 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
785 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
786 case ISD::FP16_TO_FP32:
787 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
788 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
794 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
797 // If the result is null, the sub-method took care of registering results etc.
798 if (!Res.getNode()) return false;
800 // If the result is N, the sub-method updated N in place. Tell the legalizer
802 if (Res.getNode() == N)
805 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
806 "Invalid operand expansion");
808 ReplaceValueWith(SDValue(N, 0), Res);
812 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
813 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
814 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
815 ISD::CondCode CCCode) {
816 // We have to insert explicit sign or zero extends. Note that we could
817 // insert sign extends for ALL conditions, but zero extend is cheaper on
818 // many machines (an AND instead of two shifts), so prefer it.
820 default: llvm_unreachable("Unknown integer comparison!");
827 // ALL of these operations will work if we either sign or zero extend
828 // the operands (including the unsigned comparisons!). Zero extend is
829 // usually a simpler/cheaper operation, so prefer it.
830 NewLHS = ZExtPromotedInteger(NewLHS);
831 NewRHS = ZExtPromotedInteger(NewRHS);
837 NewLHS = SExtPromotedInteger(NewLHS);
838 NewRHS = SExtPromotedInteger(NewRHS);
843 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
844 SDValue Op = GetPromotedInteger(N->getOperand(0));
845 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
848 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
849 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
850 return DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), N->getMemoryVT(),
851 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
852 N->getOrdering(), N->getSynchScope());
855 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
856 // This should only occur in unusual situations like bitcasting to an
857 // x86_fp80, so just turn it into a store+load
858 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
861 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
862 assert(OpNo == 2 && "Don't know how to promote this operand!");
864 SDValue LHS = N->getOperand(2);
865 SDValue RHS = N->getOperand(3);
866 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
868 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
870 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
871 N->getOperand(1), LHS, RHS, N->getOperand(4)),
875 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
876 assert(OpNo == 1 && "only know how to promote condition");
878 // Promote all the way up to the canonical SetCC type.
879 EVT SVT = TLI.getSetCCResultType(MVT::Other);
880 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
882 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
883 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
884 N->getOperand(2)), 0);
887 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
888 // Since the result type is legal, the operands must promote to it.
889 EVT OVT = N->getOperand(0).getValueType();
890 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
891 SDValue Hi = GetPromotedInteger(N->getOperand(1));
892 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
893 DebugLoc dl = N->getDebugLoc();
895 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
896 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
897 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
900 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
901 // The vector type is legal but the element type is not. This implies
902 // that the vector is a power-of-two in length and that the element
903 // type does not have a strange size (eg: it is not i1).
904 EVT VecVT = N->getValueType(0);
905 unsigned NumElts = VecVT.getVectorNumElements();
906 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
908 // Promote the inserted value. The type does not need to match the
909 // vector element type. Check that any extra bits introduced will be
911 assert(N->getOperand(0).getValueType().getSizeInBits() >=
912 N->getValueType(0).getVectorElementType().getSizeInBits() &&
913 "Type of inserted value narrower than vector element type!");
915 SmallVector<SDValue, 16> NewOps;
916 for (unsigned i = 0; i < NumElts; ++i)
917 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
919 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
922 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
923 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
924 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
925 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
926 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
927 "can only promote integer arguments");
928 SDValue InOp = GetPromotedInteger(N->getOperand(0));
929 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
930 N->getOperand(1), N->getOperand(2),
931 N->getOperand(3), N->getOperand(4), CvtCode);
934 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
937 // Promote the inserted value. This is valid because the type does not
938 // have to match the vector element type.
940 // Check that any extra bits introduced will be truncated away.
941 assert(N->getOperand(1).getValueType().getSizeInBits() >=
942 N->getValueType(0).getVectorElementType().getSizeInBits() &&
943 "Type of inserted value narrower than vector element type!");
944 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
945 GetPromotedInteger(N->getOperand(1)),
950 assert(OpNo == 2 && "Different operand and result vector types?");
952 // Promote the index.
953 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
954 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
955 N->getOperand(1), Idx), 0);
958 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
960 DebugLoc dl = N->getDebugLoc();
961 NewOps[0] = N->getOperand(0);
962 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
963 SDValue Flag = GetPromotedInteger(N->getOperand(i));
964 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
966 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
969 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
970 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
971 // the operand in place.
972 return SDValue(DAG.UpdateNodeOperands(N,
973 GetPromotedInteger(N->getOperand(0))), 0);
976 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
977 assert(OpNo == 0 && "Only know how to promote the condition!");
978 SDValue Cond = N->getOperand(0);
979 EVT OpTy = N->getOperand(1).getValueType();
981 // Promote all the way up to the canonical SetCC type.
982 EVT SVT = TLI.getSetCCResultType(N->getOpcode() == ISD::SELECT ?
983 OpTy.getScalarType() : OpTy);
984 Cond = PromoteTargetBoolean(Cond, SVT);
986 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
987 N->getOperand(2)), 0);
990 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
991 assert(OpNo == 0 && "Don't know how to promote this operand!");
993 SDValue LHS = N->getOperand(0);
994 SDValue RHS = N->getOperand(1);
995 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
997 // The CC (#4) and the possible return values (#2 and #3) have legal types.
998 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
999 N->getOperand(3), N->getOperand(4)), 0);
1002 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1003 assert(OpNo == 0 && "Don't know how to promote this operand!");
1005 SDValue LHS = N->getOperand(0);
1006 SDValue RHS = N->getOperand(1);
1007 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1009 // The CC (#2) is always legal.
1010 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1013 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1014 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1015 ZExtPromotedInteger(N->getOperand(1))), 0);
1018 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1019 SDValue Op = GetPromotedInteger(N->getOperand(0));
1020 DebugLoc dl = N->getDebugLoc();
1021 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1022 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1023 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1026 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1027 return SDValue(DAG.UpdateNodeOperands(N,
1028 SExtPromotedInteger(N->getOperand(0))), 0);
1031 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1032 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1033 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1034 unsigned Alignment = N->getAlignment();
1035 bool isVolatile = N->isVolatile();
1036 bool isNonTemporal = N->isNonTemporal();
1037 DebugLoc dl = N->getDebugLoc();
1039 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1041 // Truncate the value and store the result.
1042 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
1044 isVolatile, isNonTemporal, Alignment);
1047 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1048 SDValue Op = GetPromotedInteger(N->getOperand(0));
1049 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
1052 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1053 return SDValue(DAG.UpdateNodeOperands(N,
1054 ZExtPromotedInteger(N->getOperand(0))), 0);
1057 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1058 DebugLoc dl = N->getDebugLoc();
1059 SDValue Op = GetPromotedInteger(N->getOperand(0));
1060 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1061 return DAG.getZeroExtendInReg(Op, dl,
1062 N->getOperand(0).getValueType().getScalarType());
1066 //===----------------------------------------------------------------------===//
1067 // Integer Result Expansion
1068 //===----------------------------------------------------------------------===//
1070 /// ExpandIntegerResult - This method is called when the specified result of the
1071 /// specified node is found to need expansion. At this point, the node may also
1072 /// have invalid operands or may have other results that need promotion, we just
1073 /// know that (at least) one result needs expansion.
1074 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1075 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1077 Lo = Hi = SDValue();
1079 // See if the target wants to custom expand this node.
1080 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1083 switch (N->getOpcode()) {
1086 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1087 N->dump(&DAG); dbgs() << "\n";
1089 llvm_unreachable("Do not know how to expand the result of this operator!");
1091 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1092 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1093 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1094 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1096 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1097 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1098 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1099 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1100 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1102 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1103 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1104 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1105 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1106 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1107 case ISD::CTLZ_ZERO_UNDEF:
1108 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1109 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1110 case ISD::CTTZ_ZERO_UNDEF:
1111 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1112 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1113 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1114 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1115 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1116 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1117 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1118 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1119 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1120 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1121 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1122 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1123 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1124 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1126 case ISD::ATOMIC_LOAD_ADD:
1127 case ISD::ATOMIC_LOAD_SUB:
1128 case ISD::ATOMIC_LOAD_AND:
1129 case ISD::ATOMIC_LOAD_OR:
1130 case ISD::ATOMIC_LOAD_XOR:
1131 case ISD::ATOMIC_LOAD_NAND:
1132 case ISD::ATOMIC_LOAD_MIN:
1133 case ISD::ATOMIC_LOAD_MAX:
1134 case ISD::ATOMIC_LOAD_UMIN:
1135 case ISD::ATOMIC_LOAD_UMAX:
1136 case ISD::ATOMIC_SWAP: {
1137 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1138 SplitInteger(Tmp.first, Lo, Hi);
1139 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1145 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1148 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1151 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1154 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1158 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1161 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1163 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1165 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1168 // If Lo/Hi is null, the sub-method took care of registering results etc.
1170 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1173 /// Lower an atomic node to the appropriate builtin call.
1174 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1175 unsigned Opc = Node->getOpcode();
1176 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1181 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1183 case ISD::ATOMIC_SWAP:
1184 switch (VT.SimpleTy) {
1185 default: llvm_unreachable("Unexpected value type for atomic!");
1186 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1187 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1188 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1189 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1192 case ISD::ATOMIC_CMP_SWAP:
1193 switch (VT.SimpleTy) {
1194 default: llvm_unreachable("Unexpected value type for atomic!");
1195 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1196 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1197 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1198 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1201 case ISD::ATOMIC_LOAD_ADD:
1202 switch (VT.SimpleTy) {
1203 default: llvm_unreachable("Unexpected value type for atomic!");
1204 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1205 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1206 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1207 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1210 case ISD::ATOMIC_LOAD_SUB:
1211 switch (VT.SimpleTy) {
1212 default: llvm_unreachable("Unexpected value type for atomic!");
1213 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1214 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1215 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1216 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1219 case ISD::ATOMIC_LOAD_AND:
1220 switch (VT.SimpleTy) {
1221 default: llvm_unreachable("Unexpected value type for atomic!");
1222 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1223 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1224 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1225 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1228 case ISD::ATOMIC_LOAD_OR:
1229 switch (VT.SimpleTy) {
1230 default: llvm_unreachable("Unexpected value type for atomic!");
1231 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1232 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1233 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1234 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1237 case ISD::ATOMIC_LOAD_XOR:
1238 switch (VT.SimpleTy) {
1239 default: llvm_unreachable("Unexpected value type for atomic!");
1240 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1241 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1242 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1243 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1246 case ISD::ATOMIC_LOAD_NAND:
1247 switch (VT.SimpleTy) {
1248 default: llvm_unreachable("Unexpected value type for atomic!");
1249 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1250 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1251 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1252 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1257 return ExpandChainLibCall(LC, Node, false);
1260 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1261 /// and the shift amount is a constant 'Amt'. Expand the operation.
1262 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1263 SDValue &Lo, SDValue &Hi) {
1264 DebugLoc DL = N->getDebugLoc();
1265 // Expand the incoming operand to be shifted, so that we have its parts
1267 GetExpandedInteger(N->getOperand(0), InL, InH);
1269 EVT NVT = InL.getValueType();
1270 unsigned VTBits = N->getValueType(0).getSizeInBits();
1271 unsigned NVTBits = NVT.getSizeInBits();
1272 EVT ShTy = N->getOperand(1).getValueType();
1274 if (N->getOpcode() == ISD::SHL) {
1276 Lo = Hi = DAG.getConstant(0, NVT);
1277 } else if (Amt > NVTBits) {
1278 Lo = DAG.getConstant(0, NVT);
1279 Hi = DAG.getNode(ISD::SHL, DL,
1280 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1281 } else if (Amt == NVTBits) {
1282 Lo = DAG.getConstant(0, NVT);
1284 } else if (Amt == 1 &&
1285 TLI.isOperationLegalOrCustom(ISD::ADDC,
1286 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1287 // Emit this X << 1 as X+X.
1288 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1289 SDValue LoOps[2] = { InL, InL };
1290 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1291 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1292 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1294 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1295 Hi = DAG.getNode(ISD::OR, DL, NVT,
1296 DAG.getNode(ISD::SHL, DL, NVT, InH,
1297 DAG.getConstant(Amt, ShTy)),
1298 DAG.getNode(ISD::SRL, DL, NVT, InL,
1299 DAG.getConstant(NVTBits-Amt, ShTy)));
1304 if (N->getOpcode() == ISD::SRL) {
1306 Lo = DAG.getConstant(0, NVT);
1307 Hi = DAG.getConstant(0, NVT);
1308 } else if (Amt > NVTBits) {
1309 Lo = DAG.getNode(ISD::SRL, DL,
1310 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1311 Hi = DAG.getConstant(0, NVT);
1312 } else if (Amt == NVTBits) {
1314 Hi = DAG.getConstant(0, NVT);
1316 Lo = DAG.getNode(ISD::OR, DL, NVT,
1317 DAG.getNode(ISD::SRL, DL, NVT, InL,
1318 DAG.getConstant(Amt, ShTy)),
1319 DAG.getNode(ISD::SHL, DL, NVT, InH,
1320 DAG.getConstant(NVTBits-Amt, ShTy)));
1321 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1326 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1328 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1329 DAG.getConstant(NVTBits-1, ShTy));
1330 } else if (Amt > NVTBits) {
1331 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1332 DAG.getConstant(Amt-NVTBits, ShTy));
1333 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1334 DAG.getConstant(NVTBits-1, ShTy));
1335 } else if (Amt == NVTBits) {
1337 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1338 DAG.getConstant(NVTBits-1, ShTy));
1340 Lo = DAG.getNode(ISD::OR, DL, NVT,
1341 DAG.getNode(ISD::SRL, DL, NVT, InL,
1342 DAG.getConstant(Amt, ShTy)),
1343 DAG.getNode(ISD::SHL, DL, NVT, InH,
1344 DAG.getConstant(NVTBits-Amt, ShTy)));
1345 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1349 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1350 /// this shift based on knowledge of the high bit of the shift amount. If we
1351 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1353 bool DAGTypeLegalizer::
1354 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1355 SDValue Amt = N->getOperand(1);
1356 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1357 EVT ShTy = Amt.getValueType();
1358 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1359 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1360 assert(isPowerOf2_32(NVTBits) &&
1361 "Expanded integer type size not a power of two!");
1362 DebugLoc dl = N->getDebugLoc();
1364 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1365 APInt KnownZero, KnownOne;
1366 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1368 // If we don't know anything about the high bits, exit.
1369 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1372 // Get the incoming operand to be shifted.
1374 GetExpandedInteger(N->getOperand(0), InL, InH);
1376 // If we know that any of the high bits of the shift amount are one, then we
1377 // can do this as a couple of simple shifts.
1378 if (KnownOne.intersects(HighBitMask)) {
1379 // Mask out the high bit, which we know is set.
1380 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1381 DAG.getConstant(~HighBitMask, ShTy));
1383 switch (N->getOpcode()) {
1384 default: llvm_unreachable("Unknown shift");
1386 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1387 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1390 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1391 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1394 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1395 DAG.getConstant(NVTBits-1, ShTy));
1396 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1402 // FIXME: This code is broken for shifts with a zero amount!
1403 // If we know that all of the high bits of the shift amount are zero, then we
1404 // can do this as a couple of simple shifts.
1405 if ((KnownZero & HighBitMask) == HighBitMask) {
1407 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1408 DAG.getConstant(NVTBits, ShTy),
1411 switch (N->getOpcode()) {
1412 default: llvm_unreachable("Unknown shift");
1413 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1415 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1418 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1419 Hi = DAG.getNode(ISD::OR, NVT,
1420 DAG.getNode(Op1, NVT, InH, Amt),
1421 DAG.getNode(Op2, NVT, InL, Amt2));
1429 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1431 bool DAGTypeLegalizer::
1432 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1433 SDValue Amt = N->getOperand(1);
1434 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1435 EVT ShTy = Amt.getValueType();
1436 unsigned NVTBits = NVT.getSizeInBits();
1437 assert(isPowerOf2_32(NVTBits) &&
1438 "Expanded integer type size not a power of two!");
1439 DebugLoc dl = N->getDebugLoc();
1441 // Get the incoming operand to be shifted.
1443 GetExpandedInteger(N->getOperand(0), InL, InH);
1445 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1446 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1447 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1448 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1449 Amt, NVBitsNode, ISD::SETULT);
1451 SDValue LoS, HiS, LoL, HiL;
1452 switch (N->getOpcode()) {
1453 default: llvm_unreachable("Unknown shift");
1455 // Short: ShAmt < NVTBits
1456 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1457 HiS = DAG.getNode(ISD::OR, dl, NVT,
1458 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1459 // FIXME: If Amt is zero, the following shift generates an undefined result
1460 // on some architectures.
1461 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1463 // Long: ShAmt >= NVTBits
1464 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1465 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1467 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1468 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1471 // Short: ShAmt < NVTBits
1472 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1473 LoS = DAG.getNode(ISD::OR, dl, NVT,
1474 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1475 // FIXME: If Amt is zero, the following shift generates an undefined result
1476 // on some architectures.
1477 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1479 // Long: ShAmt >= NVTBits
1480 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1481 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1483 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1484 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1487 // Short: ShAmt < NVTBits
1488 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1489 LoS = DAG.getNode(ISD::OR, dl, NVT,
1490 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1491 // FIXME: If Amt is zero, the following shift generates an undefined result
1492 // on some architectures.
1493 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1495 // Long: ShAmt >= NVTBits
1496 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1497 DAG.getConstant(NVTBits-1, ShTy));
1498 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1500 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1501 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1508 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1509 SDValue &Lo, SDValue &Hi) {
1510 DebugLoc dl = N->getDebugLoc();
1511 // Expand the subcomponents.
1512 SDValue LHSL, LHSH, RHSL, RHSH;
1513 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1514 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1516 EVT NVT = LHSL.getValueType();
1517 SDValue LoOps[2] = { LHSL, RHSL };
1518 SDValue HiOps[3] = { LHSH, RHSH };
1520 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1521 // them. TODO: Teach operation legalization how to expand unsupported
1522 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1523 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1524 // generate a value of this type in the expanded code sequence.
1526 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1527 ISD::ADDC : ISD::SUBC,
1528 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1531 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1532 if (N->getOpcode() == ISD::ADD) {
1533 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1534 HiOps[2] = Lo.getValue(1);
1535 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1537 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1538 HiOps[2] = Lo.getValue(1);
1539 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1544 if (N->getOpcode() == ISD::ADD) {
1545 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1546 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1547 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1549 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1550 DAG.getConstant(1, NVT),
1551 DAG.getConstant(0, NVT));
1552 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1554 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1555 DAG.getConstant(1, NVT), Carry1);
1556 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1558 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1559 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1561 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1562 LoOps[0], LoOps[1], ISD::SETULT);
1563 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1564 DAG.getConstant(1, NVT),
1565 DAG.getConstant(0, NVT));
1566 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1570 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1571 SDValue &Lo, SDValue &Hi) {
1572 // Expand the subcomponents.
1573 SDValue LHSL, LHSH, RHSL, RHSH;
1574 DebugLoc dl = N->getDebugLoc();
1575 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1576 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1577 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1578 SDValue LoOps[2] = { LHSL, RHSL };
1579 SDValue HiOps[3] = { LHSH, RHSH };
1581 if (N->getOpcode() == ISD::ADDC) {
1582 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1583 HiOps[2] = Lo.getValue(1);
1584 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1586 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1587 HiOps[2] = Lo.getValue(1);
1588 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1591 // Legalized the flag result - switch anything that used the old flag to
1593 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1596 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1597 SDValue &Lo, SDValue &Hi) {
1598 // Expand the subcomponents.
1599 SDValue LHSL, LHSH, RHSL, RHSH;
1600 DebugLoc dl = N->getDebugLoc();
1601 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1602 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1603 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1604 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1605 SDValue HiOps[3] = { LHSH, RHSH };
1607 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1608 HiOps[2] = Lo.getValue(1);
1609 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1611 // Legalized the flag result - switch anything that used the old flag to
1613 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1616 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1617 SDValue &Lo, SDValue &Hi) {
1618 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1619 SplitInteger(Res, Lo, Hi);
1622 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1623 SDValue &Lo, SDValue &Hi) {
1624 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1625 DebugLoc dl = N->getDebugLoc();
1626 SDValue Op = N->getOperand(0);
1627 if (Op.getValueType().bitsLE(NVT)) {
1628 // The low part is any extension of the input (which degenerates to a copy).
1629 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1630 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1632 // For example, extension of an i48 to an i64. The operand type necessarily
1633 // promotes to the result type, so will end up being expanded too.
1634 assert(getTypeAction(Op.getValueType()) ==
1635 TargetLowering::TypePromoteInteger &&
1636 "Only know how to promote this result!");
1637 SDValue Res = GetPromotedInteger(Op);
1638 assert(Res.getValueType() == N->getValueType(0) &&
1639 "Operand over promoted?");
1640 // Split the promoted operand. This will simplify when it is expanded.
1641 SplitInteger(Res, Lo, Hi);
1645 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1646 SDValue &Lo, SDValue &Hi) {
1647 DebugLoc dl = N->getDebugLoc();
1648 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1649 EVT NVT = Lo.getValueType();
1650 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1651 unsigned NVTBits = NVT.getSizeInBits();
1652 unsigned EVTBits = EVT.getSizeInBits();
1654 if (NVTBits < EVTBits) {
1655 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1656 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1657 EVTBits - NVTBits)));
1659 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1660 // The high part replicates the sign bit of Lo, make it explicit.
1661 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1662 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1666 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1667 SDValue &Lo, SDValue &Hi) {
1668 DebugLoc dl = N->getDebugLoc();
1669 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1670 EVT NVT = Lo.getValueType();
1671 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1672 unsigned NVTBits = NVT.getSizeInBits();
1673 unsigned EVTBits = EVT.getSizeInBits();
1675 if (NVTBits < EVTBits) {
1676 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1677 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1678 EVTBits - NVTBits)));
1680 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1681 // The high part must be zero, make it explicit.
1682 Hi = DAG.getConstant(0, NVT);
1686 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1687 SDValue &Lo, SDValue &Hi) {
1688 DebugLoc dl = N->getDebugLoc();
1689 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1690 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1691 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1694 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1695 SDValue &Lo, SDValue &Hi) {
1696 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1697 unsigned NBitWidth = NVT.getSizeInBits();
1698 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1699 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1700 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1703 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1704 SDValue &Lo, SDValue &Hi) {
1705 DebugLoc dl = N->getDebugLoc();
1706 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1707 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1708 EVT NVT = Lo.getValueType();
1710 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1711 DAG.getConstant(0, NVT), ISD::SETNE);
1713 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1714 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1716 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1717 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1718 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1719 Hi = DAG.getConstant(0, NVT);
1722 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1723 SDValue &Lo, SDValue &Hi) {
1724 DebugLoc dl = N->getDebugLoc();
1725 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1726 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1727 EVT NVT = Lo.getValueType();
1728 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1729 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1730 Hi = DAG.getConstant(0, NVT);
1733 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1734 SDValue &Lo, SDValue &Hi) {
1735 DebugLoc dl = N->getDebugLoc();
1736 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1737 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1738 EVT NVT = Lo.getValueType();
1740 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1741 DAG.getConstant(0, NVT), ISD::SETNE);
1743 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1744 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1746 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1747 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1748 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1749 Hi = DAG.getConstant(0, NVT);
1752 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1754 DebugLoc dl = N->getDebugLoc();
1755 EVT VT = N->getValueType(0);
1756 SDValue Op = N->getOperand(0);
1757 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1758 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1759 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1762 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1764 DebugLoc dl = N->getDebugLoc();
1765 EVT VT = N->getValueType(0);
1766 SDValue Op = N->getOperand(0);
1767 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1768 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1769 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1772 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1773 SDValue &Lo, SDValue &Hi) {
1774 if (ISD::isNormalLoad(N)) {
1775 ExpandRes_NormalLoad(N, Lo, Hi);
1779 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1781 EVT VT = N->getValueType(0);
1782 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1783 SDValue Ch = N->getChain();
1784 SDValue Ptr = N->getBasePtr();
1785 ISD::LoadExtType ExtType = N->getExtensionType();
1786 unsigned Alignment = N->getAlignment();
1787 bool isVolatile = N->isVolatile();
1788 bool isNonTemporal = N->isNonTemporal();
1789 bool isInvariant = N->isInvariant();
1790 DebugLoc dl = N->getDebugLoc();
1792 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1794 if (N->getMemoryVT().bitsLE(NVT)) {
1795 EVT MemVT = N->getMemoryVT();
1797 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1798 MemVT, isVolatile, isNonTemporal, Alignment);
1800 // Remember the chain.
1801 Ch = Lo.getValue(1);
1803 if (ExtType == ISD::SEXTLOAD) {
1804 // The high part is obtained by SRA'ing all but one of the bits of the
1806 unsigned LoSize = Lo.getValueType().getSizeInBits();
1807 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1808 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1809 } else if (ExtType == ISD::ZEXTLOAD) {
1810 // The high part is just a zero.
1811 Hi = DAG.getConstant(0, NVT);
1813 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1814 // The high part is undefined.
1815 Hi = DAG.getUNDEF(NVT);
1817 } else if (TLI.isLittleEndian()) {
1818 // Little-endian - low bits are at low addresses.
1819 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1820 isVolatile, isNonTemporal, isInvariant, Alignment);
1822 unsigned ExcessBits =
1823 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1824 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1826 // Increment the pointer to the other half.
1827 unsigned IncrementSize = NVT.getSizeInBits()/8;
1828 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1829 DAG.getIntPtrConstant(IncrementSize));
1830 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1831 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1832 isVolatile, isNonTemporal,
1833 MinAlign(Alignment, IncrementSize));
1835 // Build a factor node to remember that this load is independent of the
1837 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1840 // Big-endian - high bits are at low addresses. Favor aligned loads at
1841 // the cost of some bit-fiddling.
1842 EVT MemVT = N->getMemoryVT();
1843 unsigned EBytes = MemVT.getStoreSize();
1844 unsigned IncrementSize = NVT.getSizeInBits()/8;
1845 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1847 // Load both the high bits and maybe some of the low bits.
1848 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1849 EVT::getIntegerVT(*DAG.getContext(),
1850 MemVT.getSizeInBits() - ExcessBits),
1851 isVolatile, isNonTemporal, Alignment);
1853 // Increment the pointer to the other half.
1854 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1855 DAG.getIntPtrConstant(IncrementSize));
1856 // Load the rest of the low bits.
1857 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1858 N->getPointerInfo().getWithOffset(IncrementSize),
1859 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1860 isVolatile, isNonTemporal,
1861 MinAlign(Alignment, IncrementSize));
1863 // Build a factor node to remember that this load is independent of the
1865 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1868 if (ExcessBits < NVT.getSizeInBits()) {
1869 // Transfer low bits from the bottom of Hi to the top of Lo.
1870 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1871 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1872 DAG.getConstant(ExcessBits,
1873 TLI.getPointerTy())));
1874 // Move high bits to the right position in Hi.
1875 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1877 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1878 TLI.getPointerTy()));
1882 // Legalized the chain result - switch anything that used the old chain to
1884 ReplaceValueWith(SDValue(N, 1), Ch);
1887 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1888 SDValue &Lo, SDValue &Hi) {
1889 DebugLoc dl = N->getDebugLoc();
1890 SDValue LL, LH, RL, RH;
1891 GetExpandedInteger(N->getOperand(0), LL, LH);
1892 GetExpandedInteger(N->getOperand(1), RL, RH);
1893 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1894 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1897 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1898 SDValue &Lo, SDValue &Hi) {
1899 EVT VT = N->getValueType(0);
1900 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1901 DebugLoc dl = N->getDebugLoc();
1903 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1904 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1905 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1906 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1907 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1908 SDValue LL, LH, RL, RH;
1909 GetExpandedInteger(N->getOperand(0), LL, LH);
1910 GetExpandedInteger(N->getOperand(1), RL, RH);
1911 unsigned OuterBitSize = VT.getSizeInBits();
1912 unsigned InnerBitSize = NVT.getSizeInBits();
1913 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1914 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1916 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1917 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1918 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1919 // The inputs are both zero-extended.
1921 // We can emit a umul_lohi.
1922 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1923 Hi = SDValue(Lo.getNode(), 1);
1927 // We can emit a mulhu+mul.
1928 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1929 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1933 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1934 // The input values are both sign-extended.
1936 // We can emit a smul_lohi.
1937 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1938 Hi = SDValue(Lo.getNode(), 1);
1942 // We can emit a mulhs+mul.
1943 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1944 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1949 // Lo,Hi = umul LHS, RHS.
1950 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1951 DAG.getVTList(NVT, NVT), LL, RL);
1953 Hi = UMulLOHI.getValue(1);
1954 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1955 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1956 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1957 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1961 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1962 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1963 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1964 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1965 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1966 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1971 // If nothing else, we can make a libcall.
1972 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1974 LC = RTLIB::MUL_I16;
1975 else if (VT == MVT::i32)
1976 LC = RTLIB::MUL_I32;
1977 else if (VT == MVT::i64)
1978 LC = RTLIB::MUL_I64;
1979 else if (VT == MVT::i128)
1980 LC = RTLIB::MUL_I128;
1981 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1983 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1984 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1987 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1988 SDValue &Lo, SDValue &Hi) {
1989 SDValue LHS = Node->getOperand(0);
1990 SDValue RHS = Node->getOperand(1);
1991 DebugLoc dl = Node->getDebugLoc();
1993 // Expand the result by simply replacing it with the equivalent
1994 // non-overflow-checking operation.
1995 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1996 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1998 SplitInteger(Sum, Lo, Hi);
2000 // Compute the overflow.
2002 // LHSSign -> LHS >= 0
2003 // RHSSign -> RHS >= 0
2004 // SumSign -> Sum >= 0
2007 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2009 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2011 EVT OType = Node->getValueType(1);
2012 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2014 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2015 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2016 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2017 Node->getOpcode() == ISD::SADDO ?
2018 ISD::SETEQ : ISD::SETNE);
2020 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2021 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2023 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2025 // Use the calculated overflow everywhere.
2026 ReplaceValueWith(SDValue(Node, 1), Cmp);
2029 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2030 SDValue &Lo, SDValue &Hi) {
2031 EVT VT = N->getValueType(0);
2032 DebugLoc dl = N->getDebugLoc();
2034 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2036 LC = RTLIB::SDIV_I16;
2037 else if (VT == MVT::i32)
2038 LC = RTLIB::SDIV_I32;
2039 else if (VT == MVT::i64)
2040 LC = RTLIB::SDIV_I64;
2041 else if (VT == MVT::i128)
2042 LC = RTLIB::SDIV_I128;
2043 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2045 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2046 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2049 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2050 SDValue &Lo, SDValue &Hi) {
2051 EVT VT = N->getValueType(0);
2052 DebugLoc dl = N->getDebugLoc();
2054 // If we can emit an efficient shift operation, do so now. Check to see if
2055 // the RHS is a constant.
2056 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2057 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2059 // If we can determine that the high bit of the shift is zero or one, even if
2060 // the low bits are variable, emit this shift in an optimized form.
2061 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2064 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2066 if (N->getOpcode() == ISD::SHL) {
2067 PartsOpc = ISD::SHL_PARTS;
2068 } else if (N->getOpcode() == ISD::SRL) {
2069 PartsOpc = ISD::SRL_PARTS;
2071 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2072 PartsOpc = ISD::SRA_PARTS;
2075 // Next check to see if the target supports this SHL_PARTS operation or if it
2076 // will custom expand it.
2077 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2078 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2079 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2080 Action == TargetLowering::Custom) {
2081 // Expand the subcomponents.
2083 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2085 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
2086 EVT VT = LHSL.getValueType();
2087 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
2088 Hi = Lo.getValue(1);
2092 // Otherwise, emit a libcall.
2093 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2095 if (N->getOpcode() == ISD::SHL) {
2096 isSigned = false; /*sign irrelevant*/
2098 LC = RTLIB::SHL_I16;
2099 else if (VT == MVT::i32)
2100 LC = RTLIB::SHL_I32;
2101 else if (VT == MVT::i64)
2102 LC = RTLIB::SHL_I64;
2103 else if (VT == MVT::i128)
2104 LC = RTLIB::SHL_I128;
2105 } else if (N->getOpcode() == ISD::SRL) {
2108 LC = RTLIB::SRL_I16;
2109 else if (VT == MVT::i32)
2110 LC = RTLIB::SRL_I32;
2111 else if (VT == MVT::i64)
2112 LC = RTLIB::SRL_I64;
2113 else if (VT == MVT::i128)
2114 LC = RTLIB::SRL_I128;
2116 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2119 LC = RTLIB::SRA_I16;
2120 else if (VT == MVT::i32)
2121 LC = RTLIB::SRA_I32;
2122 else if (VT == MVT::i64)
2123 LC = RTLIB::SRA_I64;
2124 else if (VT == MVT::i128)
2125 LC = RTLIB::SRA_I128;
2128 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2129 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2130 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
2134 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2135 llvm_unreachable("Unsupported shift!");
2138 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2139 SDValue &Lo, SDValue &Hi) {
2140 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2141 DebugLoc dl = N->getDebugLoc();
2142 SDValue Op = N->getOperand(0);
2143 if (Op.getValueType().bitsLE(NVT)) {
2144 // The low part is sign extension of the input (degenerates to a copy).
2145 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2146 // The high part is obtained by SRA'ing all but one of the bits of low part.
2147 unsigned LoSize = NVT.getSizeInBits();
2148 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2149 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2151 // For example, extension of an i48 to an i64. The operand type necessarily
2152 // promotes to the result type, so will end up being expanded too.
2153 assert(getTypeAction(Op.getValueType()) ==
2154 TargetLowering::TypePromoteInteger &&
2155 "Only know how to promote this result!");
2156 SDValue Res = GetPromotedInteger(Op);
2157 assert(Res.getValueType() == N->getValueType(0) &&
2158 "Operand over promoted?");
2159 // Split the promoted operand. This will simplify when it is expanded.
2160 SplitInteger(Res, Lo, Hi);
2161 unsigned ExcessBits =
2162 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2163 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2164 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2169 void DAGTypeLegalizer::
2170 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2171 DebugLoc dl = N->getDebugLoc();
2172 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2173 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2175 if (EVT.bitsLE(Lo.getValueType())) {
2176 // sext_inreg the low part if needed.
2177 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2180 // The high part gets the sign extension from the lo-part. This handles
2181 // things like sextinreg V:i64 from i8.
2182 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2183 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2184 TLI.getPointerTy()));
2186 // For example, extension of an i48 to an i64. Leave the low part alone,
2187 // sext_inreg the high part.
2188 unsigned ExcessBits =
2189 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2190 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2191 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2196 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2197 SDValue &Lo, SDValue &Hi) {
2198 EVT VT = N->getValueType(0);
2199 DebugLoc dl = N->getDebugLoc();
2201 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2203 LC = RTLIB::SREM_I16;
2204 else if (VT == MVT::i32)
2205 LC = RTLIB::SREM_I32;
2206 else if (VT == MVT::i64)
2207 LC = RTLIB::SREM_I64;
2208 else if (VT == MVT::i128)
2209 LC = RTLIB::SREM_I128;
2210 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2212 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2213 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2216 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2217 SDValue &Lo, SDValue &Hi) {
2218 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2219 DebugLoc dl = N->getDebugLoc();
2220 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2221 Hi = DAG.getNode(ISD::SRL, dl,
2222 N->getOperand(0).getValueType(), N->getOperand(0),
2223 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2224 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2227 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2228 SDValue &Lo, SDValue &Hi) {
2229 SDValue LHS = N->getOperand(0);
2230 SDValue RHS = N->getOperand(1);
2231 DebugLoc dl = N->getDebugLoc();
2233 // Expand the result by simply replacing it with the equivalent
2234 // non-overflow-checking operation.
2235 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2236 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2238 SplitInteger(Sum, Lo, Hi);
2240 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2241 // overflows iff a - b > a.
2242 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2243 N->getOpcode () == ISD::UADDO ?
2244 ISD::SETULT : ISD::SETUGT);
2246 // Use the calculated overflow everywhere.
2247 ReplaceValueWith(SDValue(N, 1), Ofl);
2250 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2251 SDValue &Lo, SDValue &Hi) {
2252 EVT VT = N->getValueType(0);
2253 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2254 EVT PtrVT = TLI.getPointerTy();
2255 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2256 DebugLoc dl = N->getDebugLoc();
2258 // A divide for UMULO should be faster than a function call.
2259 if (N->getOpcode() == ISD::UMULO) {
2260 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2261 DebugLoc DL = N->getDebugLoc();
2263 SDValue MUL = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
2264 SplitInteger(MUL, Lo, Hi);
2266 // A divide for UMULO will be faster than a function call. Select to
2267 // make sure we aren't using 0.
2268 SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2269 RHS, DAG.getConstant(0, VT), ISD::SETNE);
2270 SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
2271 DAG.getConstant(1, VT), RHS);
2272 SDValue DIV = DAG.getNode(ISD::UDIV, DL, LHS.getValueType(), MUL, NotZero);
2274 Overflow = DAG.getSetCC(DL, N->getValueType(1), DIV, LHS, ISD::SETNE);
2275 ReplaceValueWith(SDValue(N, 1), Overflow);
2279 // Replace this with a libcall that will check overflow.
2280 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2282 LC = RTLIB::MULO_I32;
2283 else if (VT == MVT::i64)
2284 LC = RTLIB::MULO_I64;
2285 else if (VT == MVT::i128)
2286 LC = RTLIB::MULO_I128;
2287 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2289 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2290 // Temporary for the overflow value, default it to zero.
2291 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2292 DAG.getConstant(0, PtrVT), Temp,
2293 MachinePointerInfo(), false, false, 0);
2295 TargetLowering::ArgListTy Args;
2296 TargetLowering::ArgListEntry Entry;
2297 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2298 EVT ArgVT = N->getOperand(i).getValueType();
2299 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2300 Entry.Node = N->getOperand(i);
2302 Entry.isSExt = true;
2303 Entry.isZExt = false;
2304 Args.push_back(Entry);
2307 // Also pass the address of the overflow check.
2309 Entry.Ty = PtrTy->getPointerTo();
2310 Entry.isSExt = true;
2311 Entry.isZExt = false;
2312 Args.push_back(Entry);
2314 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2315 std::pair<SDValue, SDValue> CallInfo =
2316 TLI.LowerCallTo(Chain, RetTy, true, false, false, false,
2317 0, TLI.getLibcallCallingConv(LC), false,
2318 true, Func, Args, DAG, dl);
2320 SplitInteger(CallInfo.first, Lo, Hi);
2321 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2322 MachinePointerInfo(), false, false, false, 0);
2323 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2324 DAG.getConstant(0, PtrVT),
2326 // Use the overflow from the libcall everywhere.
2327 ReplaceValueWith(SDValue(N, 1), Ofl);
2330 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2331 SDValue &Lo, SDValue &Hi) {
2332 EVT VT = N->getValueType(0);
2333 DebugLoc dl = N->getDebugLoc();
2335 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2337 LC = RTLIB::UDIV_I16;
2338 else if (VT == MVT::i32)
2339 LC = RTLIB::UDIV_I32;
2340 else if (VT == MVT::i64)
2341 LC = RTLIB::UDIV_I64;
2342 else if (VT == MVT::i128)
2343 LC = RTLIB::UDIV_I128;
2344 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2346 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2347 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2350 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2351 SDValue &Lo, SDValue &Hi) {
2352 EVT VT = N->getValueType(0);
2353 DebugLoc dl = N->getDebugLoc();
2355 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2357 LC = RTLIB::UREM_I16;
2358 else if (VT == MVT::i32)
2359 LC = RTLIB::UREM_I32;
2360 else if (VT == MVT::i64)
2361 LC = RTLIB::UREM_I64;
2362 else if (VT == MVT::i128)
2363 LC = RTLIB::UREM_I128;
2364 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2366 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2367 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2370 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2371 SDValue &Lo, SDValue &Hi) {
2372 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2373 DebugLoc dl = N->getDebugLoc();
2374 SDValue Op = N->getOperand(0);
2375 if (Op.getValueType().bitsLE(NVT)) {
2376 // The low part is zero extension of the input (degenerates to a copy).
2377 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2378 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2380 // For example, extension of an i48 to an i64. The operand type necessarily
2381 // promotes to the result type, so will end up being expanded too.
2382 assert(getTypeAction(Op.getValueType()) ==
2383 TargetLowering::TypePromoteInteger &&
2384 "Only know how to promote this result!");
2385 SDValue Res = GetPromotedInteger(Op);
2386 assert(Res.getValueType() == N->getValueType(0) &&
2387 "Operand over promoted?");
2388 // Split the promoted operand. This will simplify when it is expanded.
2389 SplitInteger(Res, Lo, Hi);
2390 unsigned ExcessBits =
2391 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2392 Hi = DAG.getZeroExtendInReg(Hi, dl,
2393 EVT::getIntegerVT(*DAG.getContext(),
2398 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2399 SDValue &Lo, SDValue &Hi) {
2400 DebugLoc dl = N->getDebugLoc();
2401 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2402 SDValue Zero = DAG.getConstant(0, VT);
2403 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
2405 N->getOperand(1), Zero, Zero,
2406 cast<AtomicSDNode>(N)->getMemOperand(),
2407 cast<AtomicSDNode>(N)->getOrdering(),
2408 cast<AtomicSDNode>(N)->getSynchScope());
2409 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2410 ReplaceValueWith(SDValue(N, 1), Swap.getValue(1));
2413 //===----------------------------------------------------------------------===//
2414 // Integer Operand Expansion
2415 //===----------------------------------------------------------------------===//
2417 /// ExpandIntegerOperand - This method is called when the specified operand of
2418 /// the specified node is found to need expansion. At this point, all of the
2419 /// result types of the node are known to be legal, but other operands of the
2420 /// node may need promotion or expansion as well as the specified one.
2421 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2422 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2423 SDValue Res = SDValue();
2425 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2428 switch (N->getOpcode()) {
2431 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2432 N->dump(&DAG); dbgs() << "\n";
2434 llvm_unreachable("Do not know how to expand this operator's operand!");
2436 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2437 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2438 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2439 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2440 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2441 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2442 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2443 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2444 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2445 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2446 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2447 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2453 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2454 case ISD::RETURNADDR:
2455 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2457 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2460 // If the result is null, the sub-method took care of registering results etc.
2461 if (!Res.getNode()) return false;
2463 // If the result is N, the sub-method updated N in place. Tell the legalizer
2465 if (Res.getNode() == N)
2468 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2469 "Invalid operand expansion");
2471 ReplaceValueWith(SDValue(N, 0), Res);
2475 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2476 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2477 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2479 ISD::CondCode &CCCode,
2481 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2482 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2483 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2485 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2486 if (RHSLo == RHSHi) {
2487 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2488 if (RHSCST->isAllOnesValue()) {
2489 // Equality comparison to -1.
2490 NewLHS = DAG.getNode(ISD::AND, dl,
2491 LHSLo.getValueType(), LHSLo, LHSHi);
2498 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2499 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2500 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2501 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2505 // If this is a comparison of the sign bit, just look at the top part.
2507 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2508 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2509 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2515 // FIXME: This generated code sucks.
2516 ISD::CondCode LowCC;
2518 default: llvm_unreachable("Unknown integer setcc!");
2520 case ISD::SETULT: LowCC = ISD::SETULT; break;
2522 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2524 case ISD::SETULE: LowCC = ISD::SETULE; break;
2526 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2529 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2530 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2531 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2533 // NOTE: on targets without efficient SELECT of bools, we can always use
2534 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2535 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2537 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2538 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2539 if (!Tmp1.getNode())
2540 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2541 LHSLo, RHSLo, LowCC);
2542 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2543 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2544 if (!Tmp2.getNode())
2545 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2546 TLI.getSetCCResultType(LHSHi.getValueType()),
2547 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2549 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2550 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2551 if ((Tmp1C && Tmp1C->isNullValue()) ||
2552 (Tmp2C && Tmp2C->isNullValue() &&
2553 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2554 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2555 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2556 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2557 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2558 // low part is known false, returns high part.
2559 // For LE / GE, if high part is known false, ignore the low part.
2560 // For LT / GT, if high part is known true, ignore the low part.
2566 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2567 LHSHi, RHSHi, ISD::SETEQ, false,
2568 DagCombineInfo, dl);
2569 if (!NewLHS.getNode())
2570 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2571 LHSHi, RHSHi, ISD::SETEQ);
2572 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2573 NewLHS, Tmp1, Tmp2);
2577 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2578 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2579 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2580 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2582 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2583 // against zero to select between true and false values.
2584 if (NewRHS.getNode() == 0) {
2585 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2586 CCCode = ISD::SETNE;
2589 // Update N to have the operands specified.
2590 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2591 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2592 N->getOperand(4)), 0);
2595 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2596 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2597 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2598 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2600 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2601 // against zero to select between true and false values.
2602 if (NewRHS.getNode() == 0) {
2603 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2604 CCCode = ISD::SETNE;
2607 // Update N to have the operands specified.
2608 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2609 N->getOperand(2), N->getOperand(3),
2610 DAG.getCondCode(CCCode)), 0);
2613 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2614 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2615 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2616 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2618 // If ExpandSetCCOperands returned a scalar, use it.
2619 if (NewRHS.getNode() == 0) {
2620 assert(NewLHS.getValueType() == N->getValueType(0) &&
2621 "Unexpected setcc expansion!");
2625 // Otherwise, update N to have the operands specified.
2626 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2627 DAG.getCondCode(CCCode)), 0);
2630 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2631 // The value being shifted is legal, but the shift amount is too big.
2632 // It follows that either the result of the shift is undefined, or the
2633 // upper half of the shift amount is zero. Just use the lower half.
2635 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2636 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2639 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2640 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2641 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2642 // constant to valid type.
2644 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2645 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2648 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2649 SDValue Op = N->getOperand(0);
2650 EVT DstVT = N->getValueType(0);
2651 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2652 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2653 "Don't know how to expand this SINT_TO_FP!");
2654 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2657 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2658 if (ISD::isNormalStore(N))
2659 return ExpandOp_NormalStore(N, OpNo);
2661 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2662 assert(OpNo == 1 && "Can only expand the stored value so far");
2664 EVT VT = N->getOperand(1).getValueType();
2665 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2666 SDValue Ch = N->getChain();
2667 SDValue Ptr = N->getBasePtr();
2668 unsigned Alignment = N->getAlignment();
2669 bool isVolatile = N->isVolatile();
2670 bool isNonTemporal = N->isNonTemporal();
2671 DebugLoc dl = N->getDebugLoc();
2674 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2676 if (N->getMemoryVT().bitsLE(NVT)) {
2677 GetExpandedInteger(N->getValue(), Lo, Hi);
2678 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2679 N->getMemoryVT(), isVolatile, isNonTemporal,
2683 if (TLI.isLittleEndian()) {
2684 // Little-endian - low bits are at low addresses.
2685 GetExpandedInteger(N->getValue(), Lo, Hi);
2687 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2688 isVolatile, isNonTemporal, Alignment);
2690 unsigned ExcessBits =
2691 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2692 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2694 // Increment the pointer to the other half.
2695 unsigned IncrementSize = NVT.getSizeInBits()/8;
2696 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2697 DAG.getIntPtrConstant(IncrementSize));
2698 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2699 N->getPointerInfo().getWithOffset(IncrementSize),
2700 NEVT, isVolatile, isNonTemporal,
2701 MinAlign(Alignment, IncrementSize));
2702 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2705 // Big-endian - high bits are at low addresses. Favor aligned stores at
2706 // the cost of some bit-fiddling.
2707 GetExpandedInteger(N->getValue(), Lo, Hi);
2709 EVT ExtVT = N->getMemoryVT();
2710 unsigned EBytes = ExtVT.getStoreSize();
2711 unsigned IncrementSize = NVT.getSizeInBits()/8;
2712 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2713 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2714 ExtVT.getSizeInBits() - ExcessBits);
2716 if (ExcessBits < NVT.getSizeInBits()) {
2717 // Transfer high bits from the top of Lo to the bottom of Hi.
2718 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2719 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2720 TLI.getPointerTy()));
2721 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2722 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2723 DAG.getConstant(ExcessBits,
2724 TLI.getPointerTy())));
2727 // Store both the high bits and maybe some of the low bits.
2728 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2729 HiVT, isVolatile, isNonTemporal, Alignment);
2731 // Increment the pointer to the other half.
2732 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2733 DAG.getIntPtrConstant(IncrementSize));
2734 // Store the lowest ExcessBits bits in the second half.
2735 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2736 N->getPointerInfo().getWithOffset(IncrementSize),
2737 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2738 isVolatile, isNonTemporal,
2739 MinAlign(Alignment, IncrementSize));
2740 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2743 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2745 GetExpandedInteger(N->getOperand(0), InL, InH);
2746 // Just truncate the low part of the source.
2747 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2750 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2751 switch (VT.getSimpleVT().SimpleTy) {
2752 default: llvm_unreachable("Unknown FP format");
2753 case MVT::f32: return &APFloat::IEEEsingle;
2754 case MVT::f64: return &APFloat::IEEEdouble;
2755 case MVT::f80: return &APFloat::x87DoubleExtended;
2756 case MVT::f128: return &APFloat::IEEEquad;
2757 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2761 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2762 SDValue Op = N->getOperand(0);
2763 EVT SrcVT = Op.getValueType();
2764 EVT DstVT = N->getValueType(0);
2765 DebugLoc dl = N->getDebugLoc();
2767 // The following optimization is valid only if every value in SrcVT (when
2768 // treated as signed) is representable in DstVT. Check that the mantissa
2769 // size of DstVT is >= than the number of bits in SrcVT -1.
2770 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2771 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2772 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2773 // Do a signed conversion then adjust the result.
2774 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2775 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2777 // The result of the signed conversion needs adjusting if the 'sign bit' of
2778 // the incoming integer was set. To handle this, we dynamically test to see
2779 // if it is set, and, if so, add a fudge factor.
2781 const uint64_t F32TwoE32 = 0x4F800000ULL;
2782 const uint64_t F32TwoE64 = 0x5F800000ULL;
2783 const uint64_t F32TwoE128 = 0x7F800000ULL;
2786 if (SrcVT == MVT::i32)
2787 FF = APInt(32, F32TwoE32);
2788 else if (SrcVT == MVT::i64)
2789 FF = APInt(32, F32TwoE64);
2790 else if (SrcVT == MVT::i128)
2791 FF = APInt(32, F32TwoE128);
2793 assert(false && "Unsupported UINT_TO_FP!");
2795 // Check whether the sign bit is set.
2797 GetExpandedInteger(Op, Lo, Hi);
2798 SDValue SignSet = DAG.getSetCC(dl,
2799 TLI.getSetCCResultType(Hi.getValueType()),
2800 Hi, DAG.getConstant(0, Hi.getValueType()),
2803 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2804 SDValue FudgePtr = DAG.getConstantPool(
2805 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2806 TLI.getPointerTy());
2808 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2809 SDValue Zero = DAG.getIntPtrConstant(0);
2810 SDValue Four = DAG.getIntPtrConstant(4);
2811 if (TLI.isBigEndian()) std::swap(Zero, Four);
2812 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2814 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2815 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2816 Alignment = std::min(Alignment, 4u);
2818 // Load the value out, extending it from f32 to the destination float type.
2819 // FIXME: Avoid the extend by constructing the right constant pool?
2820 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2822 MachinePointerInfo::getConstantPool(),
2824 false, false, Alignment);
2825 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2828 // Otherwise, use a libcall.
2829 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2830 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2831 "Don't know how to expand this UINT_TO_FP!");
2832 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);
2835 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2836 DebugLoc dl = N->getDebugLoc();
2837 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2838 cast<AtomicSDNode>(N)->getMemoryVT(),
2840 N->getOperand(1), N->getOperand(2),
2841 cast<AtomicSDNode>(N)->getMemOperand(),
2842 cast<AtomicSDNode>(N)->getOrdering(),
2843 cast<AtomicSDNode>(N)->getSynchScope());
2844 return Swap.getValue(1);
2848 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2849 SDValue InOp0 = N->getOperand(0);
2850 EVT InVT = InOp0.getValueType();
2852 EVT OutVT = N->getValueType(0);
2853 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2854 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2855 unsigned OutNumElems = OutVT.getVectorNumElements();
2856 EVT NOutVTElem = NOutVT.getVectorElementType();
2858 DebugLoc dl = N->getDebugLoc();
2859 SDValue BaseIdx = N->getOperand(1);
2861 SmallVector<SDValue, 8> Ops;
2862 Ops.reserve(OutNumElems);
2863 for (unsigned i = 0; i != OutNumElems; ++i) {
2865 // Extract the element from the original vector.
2866 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2867 BaseIdx, DAG.getIntPtrConstant(i));
2868 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2869 InVT.getVectorElementType(), N->getOperand(0), Index);
2871 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2872 // Insert the converted element to the new vector.
2876 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2880 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2881 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2882 EVT VT = N->getValueType(0);
2883 DebugLoc dl = N->getDebugLoc();
2885 unsigned NumElts = VT.getVectorNumElements();
2886 SmallVector<int, 8> NewMask;
2887 for (unsigned i = 0; i != NumElts; ++i) {
2888 NewMask.push_back(SV->getMaskElt(i));
2891 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2892 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2893 EVT OutVT = V0.getValueType();
2895 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2899 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2900 EVT OutVT = N->getValueType(0);
2901 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2902 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2903 unsigned NumElems = N->getNumOperands();
2904 EVT NOutVTElem = NOutVT.getVectorElementType();
2906 DebugLoc dl = N->getDebugLoc();
2908 SmallVector<SDValue, 8> Ops;
2909 Ops.reserve(NumElems);
2910 for (unsigned i = 0; i != NumElems; ++i) {
2911 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2915 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2918 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2920 DebugLoc dl = N->getDebugLoc();
2922 assert(!N->getOperand(0).getValueType().isVector() &&
2923 "Input must be a scalar");
2925 EVT OutVT = N->getValueType(0);
2926 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2927 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2928 EVT NOutVTElem = NOutVT.getVectorElementType();
2930 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2932 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2935 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
2936 DebugLoc dl = N->getDebugLoc();
2938 EVT OutVT = N->getValueType(0);
2939 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2940 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2942 EVT InElemTy = OutVT.getVectorElementType();
2943 EVT OutElemTy = NOutVT.getVectorElementType();
2945 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
2946 unsigned NumOutElem = NOutVT.getVectorNumElements();
2947 unsigned NumOperands = N->getNumOperands();
2948 assert(NumElem * NumOperands == NumOutElem &&
2949 "Unexpected number of elements");
2951 // Take the elements from the first vector.
2952 SmallVector<SDValue, 8> Ops(NumOutElem);
2953 for (unsigned i = 0; i < NumOperands; ++i) {
2954 SDValue Op = N->getOperand(i);
2955 for (unsigned j = 0; j < NumElem; ++j) {
2956 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2957 InElemTy, Op, DAG.getIntPtrConstant(j));
2958 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
2962 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2965 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
2966 EVT OutVT = N->getValueType(0);
2967 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2968 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2970 EVT NOutVTElem = NOutVT.getVectorElementType();
2972 DebugLoc dl = N->getDebugLoc();
2973 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2975 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
2976 NOutVTElem, N->getOperand(1));
2977 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
2978 V0, ConvElem, N->getOperand(2));
2981 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2982 DebugLoc dl = N->getDebugLoc();
2983 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2984 SDValue V1 = N->getOperand(1);
2985 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2986 V0->getValueType(0).getScalarType(), V0, V1);
2988 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
2989 // element types. If this is the case then we need to expand the outgoing
2990 // value and not truncate it.
2991 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
2994 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
2995 DebugLoc dl = N->getDebugLoc();
2996 unsigned NumElems = N->getNumOperands();
2998 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3000 SmallVector<SDValue, 8> NewOps;
3001 NewOps.reserve(NumElems);
3003 // For each incoming vector
3004 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3005 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3006 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3007 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3009 for (unsigned i=0; i<NumElem; ++i) {
3010 // Extract element from incoming vector
3011 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3012 Incoming, DAG.getIntPtrConstant(i));
3013 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3014 NewOps.push_back(Tr);
3018 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
3019 &NewOps[0], NewOps.size());