1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDValue Result = SDValue();
36 // See if the target wants to custom expand this node.
37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
38 TargetLowering::Custom) {
39 // If the target wants to, allow it to lower this itself.
40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
41 // Everything that once used N now uses P. We are guaranteed that the
42 // result value types of N and the result value types of P match.
43 ReplaceNodeWith(N, P);
48 switch (N->getOpcode()) {
51 cerr << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); cerr << "\n";
54 assert(0 && "Do not know how to promote this operator!");
56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break;
57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break;
58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break;
60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
62 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
65 case ISD::EXTRACT_VECTOR_ELT:
66 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
67 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
68 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
69 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
73 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break;
80 case ISD::SIGN_EXTEND:
81 case ISD::ZERO_EXTEND:
82 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
85 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
92 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
95 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
98 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
100 case ISD::ATOMIC_LOAD_ADD_8:
101 case ISD::ATOMIC_LOAD_SUB_8:
102 case ISD::ATOMIC_LOAD_AND_8:
103 case ISD::ATOMIC_LOAD_OR_8:
104 case ISD::ATOMIC_LOAD_XOR_8:
105 case ISD::ATOMIC_LOAD_NAND_8:
106 case ISD::ATOMIC_LOAD_MIN_8:
107 case ISD::ATOMIC_LOAD_MAX_8:
108 case ISD::ATOMIC_LOAD_UMIN_8:
109 case ISD::ATOMIC_LOAD_UMAX_8:
110 case ISD::ATOMIC_SWAP_8:
111 case ISD::ATOMIC_LOAD_ADD_16:
112 case ISD::ATOMIC_LOAD_SUB_16:
113 case ISD::ATOMIC_LOAD_AND_16:
114 case ISD::ATOMIC_LOAD_OR_16:
115 case ISD::ATOMIC_LOAD_XOR_16:
116 case ISD::ATOMIC_LOAD_NAND_16:
117 case ISD::ATOMIC_LOAD_MIN_16:
118 case ISD::ATOMIC_LOAD_MAX_16:
119 case ISD::ATOMIC_LOAD_UMIN_16:
120 case ISD::ATOMIC_LOAD_UMAX_16:
121 case ISD::ATOMIC_SWAP_16:
122 case ISD::ATOMIC_LOAD_ADD_32:
123 case ISD::ATOMIC_LOAD_SUB_32:
124 case ISD::ATOMIC_LOAD_AND_32:
125 case ISD::ATOMIC_LOAD_OR_32:
126 case ISD::ATOMIC_LOAD_XOR_32:
127 case ISD::ATOMIC_LOAD_NAND_32:
128 case ISD::ATOMIC_LOAD_MIN_32:
129 case ISD::ATOMIC_LOAD_MAX_32:
130 case ISD::ATOMIC_LOAD_UMIN_32:
131 case ISD::ATOMIC_LOAD_UMAX_32:
132 case ISD::ATOMIC_SWAP_32:
133 case ISD::ATOMIC_LOAD_ADD_64:
134 case ISD::ATOMIC_LOAD_SUB_64:
135 case ISD::ATOMIC_LOAD_AND_64:
136 case ISD::ATOMIC_LOAD_OR_64:
137 case ISD::ATOMIC_LOAD_XOR_64:
138 case ISD::ATOMIC_LOAD_NAND_64:
139 case ISD::ATOMIC_LOAD_MIN_64:
140 case ISD::ATOMIC_LOAD_MAX_64:
141 case ISD::ATOMIC_LOAD_UMIN_64:
142 case ISD::ATOMIC_LOAD_UMAX_64:
143 case ISD::ATOMIC_SWAP_64:
144 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
146 case ISD::ATOMIC_CMP_SWAP_8:
147 case ISD::ATOMIC_CMP_SWAP_16:
148 case ISD::ATOMIC_CMP_SWAP_32:
149 case ISD::ATOMIC_CMP_SWAP_64:
150 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
153 // If Result is null, the sub-method took care of registering the result.
154 if (Result.getNode())
155 SetPromotedInteger(SDValue(N, ResNo), Result);
158 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
159 // Sign-extend the new bits, and continue the assertion.
160 MVT OldVT = N->getValueType(0);
161 SDValue Op = GetPromotedInteger(N->getOperand(0));
162 return DAG.getNode(ISD::AssertSext, Op.getValueType(),
163 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
164 DAG.getValueType(OldVT)), N->getOperand(1));
167 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
168 // Zero the new bits, and continue the assertion.
169 MVT OldVT = N->getValueType(0);
170 SDValue Op = GetPromotedInteger(N->getOperand(0));
171 return DAG.getNode(ISD::AssertZext, Op.getValueType(),
172 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1));
175 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
176 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
177 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
178 Op2, N->getSrcValue(), N->getAlignment());
179 // Legalized the chain result - switch anything that used the old chain to
181 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
185 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
186 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
187 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
188 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
189 Op2, Op3, N->getSrcValue(), N->getAlignment());
190 // Legalized the chain result - switch anything that used the old chain to
192 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
196 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
197 SDValue InOp = N->getOperand(0);
198 MVT InVT = InOp.getValueType();
199 MVT NInVT = TLI.getTypeToTransformTo(InVT);
200 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
202 switch (getTypeAction(InVT)) {
204 assert(false && "Unknown type action!");
209 if (OutVT.bitsEq(NInVT))
210 // The input promotes to the same size. Convert the promoted value.
211 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
214 // Promote the integer operand by hand.
215 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
219 case ScalarizeVector:
220 // Convert the element to an integer and promote it by hand.
221 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
222 BitConvertToInteger(GetScalarizedVector(InOp)));
224 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
225 // pieces of the input into integers and reassemble in the final type.
227 GetSplitVector(N->getOperand(0), Lo, Hi);
228 Lo = BitConvertToInteger(Lo);
229 Hi = BitConvertToInteger(Hi);
231 if (TLI.isBigEndian())
234 InOp = DAG.getNode(ISD::ANY_EXTEND,
235 MVT::getIntegerVT(OutVT.getSizeInBits()),
236 JoinIntegers(Lo, Hi));
237 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
240 // Otherwise, lower the bit-convert to a store/load from the stack, then
242 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
243 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode()));
246 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
247 SDValue Op = GetPromotedInteger(N->getOperand(0));
248 MVT OVT = N->getValueType(0);
249 MVT NVT = Op.getValueType();
251 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
252 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
253 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
256 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
257 // The pair element type may be legal, or may not promote to the same type as
258 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
259 return DAG.getNode(ISD::ANY_EXTEND,
260 TLI.getTypeToTransformTo(N->getValueType(0)),
261 JoinIntegers(N->getOperand(0), N->getOperand(1)));
264 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
265 MVT VT = N->getValueType(0);
266 // Zero extend things like i1, sign extend everything else. It shouldn't
267 // matter in theory which one we pick, but this tends to give better code?
268 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
269 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
271 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
275 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
276 SDValue Op = GetPromotedInteger(N->getOperand(0));
277 MVT OVT = N->getValueType(0);
278 MVT NVT = Op.getValueType();
279 // Zero extend to the promoted type and do the count there.
280 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
281 // Subtract off the extra leading bits in the bigger type.
282 return DAG.getNode(ISD::SUB, NVT, Op,
283 DAG.getConstant(NVT.getSizeInBits() -
284 OVT.getSizeInBits(), NVT));
287 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
288 SDValue Op = GetPromotedInteger(N->getOperand(0));
289 MVT OVT = N->getValueType(0);
290 MVT NVT = Op.getValueType();
291 // Zero extend to the promoted type and do the count there.
292 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
295 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
296 SDValue Op = GetPromotedInteger(N->getOperand(0));
297 MVT OVT = N->getValueType(0);
298 MVT NVT = Op.getValueType();
299 // The count is the same in the promoted type except if the original
300 // value was zero. This can be handled by setting the bit just off
301 // the top of the original type.
302 APInt TopBit(NVT.getSizeInBits(), 0);
303 TopBit.set(OVT.getSizeInBits());
304 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
305 return DAG.getNode(ISD::CTTZ, NVT, Op);
308 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
309 MVT OldVT = N->getValueType(0);
310 SDValue OldVec = N->getOperand(0);
311 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
314 assert(!isTypeLegal(OldVec.getValueType()) &&
315 "Legal one-element vector of a type needing promotion!");
316 // It is tempting to follow GetScalarizedVector by a call to
317 // GetPromotedInteger, but this would be wrong because the
318 // scalarized value may not yet have been processed.
319 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
320 GetScalarizedVector(OldVec));
323 // Convert to a vector half as long with an element type of twice the width,
324 // for example <4 x i16> -> <2 x i32>.
325 assert(!(OldElts & 1) && "Odd length vectors not supported!");
326 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
327 assert(OldVT.isSimple() && NewVT.isSimple());
329 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
330 MVT::getVectorVT(NewVT, OldElts / 2),
333 // Extract the element at OldIdx / 2 from the new vector.
334 SDValue OldIdx = N->getOperand(1);
335 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
336 DAG.getConstant(1, TLI.getShiftAmountTy()));
337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
339 // Select the appropriate half of the element: Lo if OldIdx was even,
342 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
343 DAG.getConstant(OldVT.getSizeInBits(),
344 TLI.getShiftAmountTy()));
345 if (TLI.isBigEndian())
348 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx);
349 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
352 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
353 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
354 unsigned NewOpc = N->getOpcode();
356 // If we're promoting a UINT to a larger size, check to see if the new node
357 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
358 // we can use that instead. This allows us to generate better code for
359 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
360 // legal, such as PowerPC.
361 if (N->getOpcode() == ISD::FP_TO_UINT &&
362 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
363 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT))
364 NewOpc = ISD::FP_TO_SINT;
366 SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0));
368 // Assert that the converted value fits in the original type. If it doesn't
369 // (eg: because the value being converted is too big), then the result of the
370 // original operation was undefined anyway, so the assert is still correct.
371 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
372 ISD::AssertZext : ISD::AssertSext,
373 NVT, Res, DAG.getValueType(N->getValueType(0)));
376 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
377 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
379 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
380 SDValue Res = GetPromotedInteger(N->getOperand(0));
381 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
383 // If the result and operand types are the same after promotion, simplify
384 // to an in-register extension.
385 if (NVT == Res.getValueType()) {
386 // The high bits are not guaranteed to be anything. Insert an extend.
387 if (N->getOpcode() == ISD::SIGN_EXTEND)
388 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
389 DAG.getValueType(N->getOperand(0).getValueType()));
390 if (N->getOpcode() == ISD::ZERO_EXTEND)
391 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
392 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
397 // Otherwise, just extend the original operand all the way to the larger type.
398 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
401 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
402 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
403 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
404 ISD::LoadExtType ExtType =
405 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
406 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
407 N->getSrcValue(), N->getSrcValueOffset(),
408 N->getMemoryVT(), N->isVolatile(),
411 // Legalized the chain result - switch anything that used the old chain to
413 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
417 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
418 // Sign extend the input.
419 SDValue LHS = GetPromotedInteger(N->getOperand(0));
420 SDValue RHS = GetPromotedInteger(N->getOperand(1));
421 MVT VT = N->getValueType(0);
422 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
423 DAG.getValueType(VT));
424 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
425 DAG.getValueType(VT));
427 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
430 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
431 SDValue LHS = GetPromotedInteger(N->getOperand(1));
432 SDValue RHS = GetPromotedInteger(N->getOperand(2));
433 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
436 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
437 SDValue LHS = GetPromotedInteger(N->getOperand(2));
438 SDValue RHS = GetPromotedInteger(N->getOperand(3));
439 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
440 N->getOperand(1), LHS, RHS, N->getOperand(4));
443 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
444 MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
445 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
447 // Get the SETCC result using the canonical SETCC type.
448 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
449 N->getOperand(1), N->getOperand(2));
451 // Convert to the expected type.
452 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
453 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
454 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC);
457 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
458 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
459 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
462 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
463 SDValue Op = GetPromotedInteger(N->getOperand(0));
464 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
468 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
469 // The input may have strange things in the top bits of the registers, but
470 // these operations don't care. They may have weird bits going out, but
471 // that too is okay if they are integer operations.
472 SDValue LHS = GetPromotedInteger(N->getOperand(0));
473 SDValue RHS = GetPromotedInteger(N->getOperand(1));
474 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
477 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
478 // The input value must be properly sign extended.
479 MVT VT = N->getValueType(0);
480 MVT NVT = TLI.getTypeToTransformTo(VT);
481 SDValue Res = GetPromotedInteger(N->getOperand(0));
482 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
483 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
486 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
487 // The input value must be properly zero extended.
488 MVT VT = N->getValueType(0);
489 MVT NVT = TLI.getTypeToTransformTo(VT);
490 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
491 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
494 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
495 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
498 switch (getTypeAction(N->getOperand(0).getValueType())) {
499 default: assert(0 && "Unknown type action!");
502 Res = N->getOperand(0);
505 Res = GetPromotedInteger(N->getOperand(0));
509 // Truncate to NVT instead of VT
510 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
513 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
514 // Zero extend the input.
515 SDValue LHS = GetPromotedInteger(N->getOperand(0));
516 SDValue RHS = GetPromotedInteger(N->getOperand(1));
517 MVT VT = N->getValueType(0);
518 LHS = DAG.getZeroExtendInReg(LHS, VT);
519 RHS = DAG.getZeroExtendInReg(RHS, VT);
521 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
524 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
525 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
528 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
529 SDValue Chain = N->getOperand(0); // Get the chain.
530 SDValue Ptr = N->getOperand(1); // Get the pointer.
531 MVT VT = N->getValueType(0);
533 MVT RegVT = TLI.getRegisterType(VT);
534 unsigned NumRegs = TLI.getNumRegisters(VT);
535 // The argument is passed as NumRegs registers of type RegVT.
537 SmallVector<SDValue, 8> Parts(NumRegs);
538 for (unsigned i = 0; i < NumRegs; ++i) {
539 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2));
540 Chain = Parts[i].getValue(1);
543 // Handle endianness of the load.
544 if (TLI.isBigEndian())
545 std::reverse(Parts.begin(), Parts.end());
547 // Assemble the parts in the promoted type.
548 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
549 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]);
550 for (unsigned i = 1; i < NumRegs; ++i) {
551 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]);
552 // Shift it to the right position and "or" it in.
553 Part = DAG.getNode(ISD::SHL, NVT, Part,
554 DAG.getConstant(i * RegVT.getSizeInBits(),
555 TLI.getShiftAmountTy()));
556 Res = DAG.getNode(ISD::OR, NVT, Res, Part);
559 // Modified the chain result - switch anything that used the old chain to
561 ReplaceValueWith(SDValue(N, 1), Chain);
567 //===----------------------------------------------------------------------===//
568 // Integer Operand Promotion
569 //===----------------------------------------------------------------------===//
571 /// PromoteIntegerOperand - This method is called when the specified operand of
572 /// the specified node is found to need promotion. At this point, all of the
573 /// result types of the node are known to be legal, but other operands of the
574 /// node may need promotion or expansion as well as the specified one.
575 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
576 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
577 SDValue Res = SDValue();
579 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
580 == TargetLowering::Custom)
581 Res = TLI.LowerOperation(SDValue(N, 0), DAG);
583 if (Res.getNode() == 0) {
584 switch (N->getOpcode()) {
587 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
588 N->dump(&DAG); cerr << "\n";
590 assert(0 && "Do not know how to promote this operator's operand!");
593 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
594 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
595 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
596 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
597 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
598 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
599 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
600 case ISD::INSERT_VECTOR_ELT:
601 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
602 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
603 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
604 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
605 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
606 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
607 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
609 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
610 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
612 case ISD::SINT_TO_FP:
613 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
614 case ISD::CONVERT_RNDSAT: Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
618 // If the result is null, the sub-method took care of registering results etc.
619 if (!Res.getNode()) return false;
620 // If the result is N, the sub-method updated N in place.
621 if (Res.getNode() == N) {
622 // Mark N as new and remark N and its operands. This allows us to correctly
623 // revisit N if it needs another step of promotion and allows us to visit
624 // any new operands to N.
629 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
630 "Invalid operand expansion");
632 ReplaceValueWith(SDValue(N, 0), Res);
636 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
637 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
638 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
639 ISD::CondCode CCCode) {
640 MVT VT = NewLHS.getValueType();
642 // Get the promoted values.
643 NewLHS = GetPromotedInteger(NewLHS);
644 NewRHS = GetPromotedInteger(NewRHS);
646 // We have to insert explicit sign or zero extends. Note that we could
647 // insert sign extends for ALL conditions, but zero extend is cheaper on
648 // many machines (an AND instead of two shifts), so prefer it.
650 default: assert(0 && "Unknown integer comparison!");
657 // ALL of these operations will work if we either sign or zero extend
658 // the operands (including the unsigned comparisons!). Zero extend is
659 // usually a simpler/cheaper operation, so prefer it.
660 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
661 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
667 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
668 DAG.getValueType(VT));
669 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
670 DAG.getValueType(VT));
675 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
676 SDValue Op = GetPromotedInteger(N->getOperand(0));
677 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
680 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
681 assert(OpNo == 2 && "Don't know how to promote this operand!");
683 SDValue LHS = N->getOperand(2);
684 SDValue RHS = N->getOperand(3);
685 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
687 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
689 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
690 N->getOperand(1), LHS, RHS, N->getOperand(4));
693 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
694 assert(OpNo == 1 && "only know how to promote condition");
695 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
697 // Make sure the extra bits coming from type promotion conform to
698 // getSetCCResultContents.
699 unsigned CondBits = Cond.getValueSizeInBits();
700 switch (TLI.getSetCCResultContents()) {
702 assert(false && "Unknown SetCCResultValue!");
703 case TargetLowering::UndefinedSetCCResult:
704 // The promoted value, which may contain rubbish in the upper bits, is fine.
706 case TargetLowering::ZeroOrOneSetCCResult:
707 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
708 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
710 case TargetLowering::ZeroOrNegativeOneSetCCResult:
711 if (DAG.ComputeNumSignBits(Cond) != CondBits)
712 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond,
713 DAG.getValueType(MVT::i1));
717 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
718 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
722 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
723 // Since the result type is legal, the operands must promote to it.
724 MVT OVT = N->getOperand(0).getValueType();
725 SDValue Lo = GetPromotedInteger(N->getOperand(0));
726 SDValue Hi = GetPromotedInteger(N->getOperand(1));
727 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
729 Lo = DAG.getZeroExtendInReg(Lo, OVT);
730 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
731 DAG.getConstant(OVT.getSizeInBits(),
732 TLI.getShiftAmountTy()));
733 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
736 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
737 // The vector type is legal but the element type is not. This implies
738 // that the vector is a power-of-two in length and that the element
739 // type does not have a strange size (eg: it is not i1).
740 MVT VecVT = N->getValueType(0);
741 unsigned NumElts = VecVT.getVectorNumElements();
742 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
744 // Build a vector of half the length out of elements of twice the bitwidth.
745 // For example <4 x i16> -> <2 x i32>.
746 MVT OldVT = N->getOperand(0).getValueType();
747 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
748 assert(OldVT.isSimple() && NewVT.isSimple());
750 std::vector<SDValue> NewElts;
751 NewElts.reserve(NumElts/2);
753 for (unsigned i = 0; i < NumElts; i += 2) {
754 // Combine two successive elements into one promoted element.
755 SDValue Lo = N->getOperand(i);
756 SDValue Hi = N->getOperand(i+1);
757 if (TLI.isBigEndian())
759 NewElts.push_back(JoinIntegers(Lo, Hi));
762 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
763 MVT::getVectorVT(NewVT, NewElts.size()),
764 &NewElts[0], NewElts.size());
766 // Convert the new vector to the old vector type.
767 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
770 SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
771 SDValue Op = GetPromotedInteger(N->getOperand(0));
772 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
775 SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
776 SDValue Op = GetPromotedInteger(N->getOperand(0));
777 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
778 DAG.getIntPtrConstant(0));
781 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
784 // Promote the inserted value. This is valid because the type does not
785 // have to match the vector element type.
787 // Check that any extra bits introduced will be truncated away.
788 assert(N->getOperand(1).getValueType().getSizeInBits() >=
789 N->getValueType(0).getVectorElementType().getSizeInBits() &&
790 "Type of inserted value narrower than vector element type!");
791 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
792 GetPromotedInteger(N->getOperand(1)),
796 assert(OpNo == 2 && "Different operand and result vector types?");
798 // Promote the index.
799 SDValue Idx = N->getOperand(2);
800 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
801 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
802 N->getOperand(1), Idx);
805 SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
806 SDValue In = GetPromotedInteger(N->getOperand(0));
807 MVT OpVT = N->getOperand(0).getValueType();
808 if (N->getOpcode() == ISD::UINT_TO_FP)
809 In = DAG.getZeroExtendInReg(In, OpVT);
811 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
812 In, DAG.getValueType(OpVT));
814 return DAG.UpdateNodeOperands(SDValue(N, 0), In);
817 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
818 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
819 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
820 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
821 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
822 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
823 "can only promote integers");
824 SDValue In = DAG.getConvertRndSat(OutVT,N->getOperand(0),
825 N->getOperand(1), N->getOperand(2),
826 N->getOperand(3), N->getOperand(4), CvtCode);
827 return DAG.UpdateNodeOperands(SDValue(N, 0), In);
832 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
834 NewOps[0] = N->getOperand(0);
835 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
836 SDValue Flag = GetPromotedInteger(N->getOperand(i));
837 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
839 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
840 array_lengthof(NewOps));
843 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
844 assert(OpNo == 0 && "Only know how to promote condition");
845 SDValue Cond = GetPromotedInteger(N->getOperand(0));
847 // Promote all the way up to SVT, the canonical SetCC type.
848 // FIXME: Not clear what value to pass to getSetCCResultType.
849 // [This only matters for CellSPU since all other targets
850 // ignore the argument.] We used to pass Cond, resulting in
851 // SVT = MVT::i8, but CellSPU has no select patterns for i8,
852 // causing an abort later. Passing the result type works
853 // around the problem.
854 MVT SVT = TLI.getSetCCResultType(N->getOperand(1));
855 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
856 assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
858 // Make sure the extra bits conform to getSetCCResultContents. There are
859 // two sets of extra bits: those in Cond, which come from type promotion,
860 // and those we need to add to have the final type be SVT (for most targets
861 // this last set of bits is empty).
862 unsigned CondBits = Cond.getValueSizeInBits();
863 ISD::NodeType ExtendCode;
864 switch (TLI.getSetCCResultContents()) {
866 assert(false && "Unknown SetCCResultValue!");
867 case TargetLowering::UndefinedSetCCResult:
868 // Extend to SVT by adding rubbish.
869 ExtendCode = ISD::ANY_EXTEND;
871 case TargetLowering::ZeroOrOneSetCCResult:
872 ExtendCode = ISD::ZERO_EXTEND;
873 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
874 // All extra bits need to be cleared. Do this by zero extending the
875 // original condition value all the way to SVT.
876 Cond = N->getOperand(0);
878 case TargetLowering::ZeroOrNegativeOneSetCCResult: {
879 ExtendCode = ISD::SIGN_EXTEND;
880 unsigned SignBits = DAG.ComputeNumSignBits(Cond);
881 if (SignBits != CondBits)
882 // All extra bits need to be sign extended. Do this by sign extending the
883 // original condition value all the way to SVT.
884 Cond = N->getOperand(0);
888 Cond = DAG.getNode(ExtendCode, SVT, Cond);
890 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
891 N->getOperand(1), N->getOperand(2));
894 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
895 assert(OpNo == 0 && "Don't know how to promote this operand!");
897 SDValue LHS = N->getOperand(0);
898 SDValue RHS = N->getOperand(1);
899 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
901 // The CC (#4) and the possible return values (#2 and #3) have legal types.
902 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
903 N->getOperand(3), N->getOperand(4));
906 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
907 assert(OpNo == 0 && "Don't know how to promote this operand!");
909 SDValue LHS = N->getOperand(0);
910 SDValue RHS = N->getOperand(1);
911 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
913 // The CC (#2) is always legal.
914 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
917 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
918 SDValue Op = GetPromotedInteger(N->getOperand(0));
919 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
920 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
921 Op, DAG.getValueType(N->getOperand(0).getValueType()));
924 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
925 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
926 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
927 int SVOffset = N->getSrcValueOffset();
928 unsigned Alignment = N->getAlignment();
929 bool isVolatile = N->isVolatile();
931 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
933 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
935 // Truncate the value and store the result.
936 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
937 SVOffset, N->getMemoryVT(),
938 isVolatile, Alignment);
941 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
942 SDValue Op = GetPromotedInteger(N->getOperand(0));
943 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
946 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
947 SDValue Op = GetPromotedInteger(N->getOperand(0));
948 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
949 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
953 //===----------------------------------------------------------------------===//
954 // Integer Result Expansion
955 //===----------------------------------------------------------------------===//
957 /// ExpandIntegerResult - This method is called when the specified result of the
958 /// specified node is found to need expansion. At this point, the node may also
959 /// have invalid operands or may have other results that need promotion, we just
960 /// know that (at least) one result needs expansion.
961 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
962 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
966 // See if the target wants to custom expand this node.
967 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
968 TargetLowering::Custom) {
969 // If the target wants to, allow it to lower this itself.
970 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
971 // Everything that once used N now uses P. We are guaranteed that the
972 // result value types of N and the result value types of P match.
973 ReplaceNodeWith(N, P);
978 switch (N->getOpcode()) {
981 cerr << "ExpandIntegerResult #" << ResNo << ": ";
982 N->dump(&DAG); cerr << "\n";
984 assert(0 && "Do not know how to expand the result of this operator!");
987 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
988 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
989 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
990 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
992 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
993 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
994 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
995 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
996 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
998 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
999 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1000 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1001 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1002 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1003 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1004 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1005 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1006 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1007 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1008 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1009 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1010 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1011 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1012 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1013 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1014 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1015 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1016 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1017 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1021 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1024 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1027 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1030 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1034 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1037 // If Lo/Hi is null, the sub-method took care of registering results etc.
1039 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1042 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1043 /// and the shift amount is a constant 'Amt'. Expand the operation.
1044 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1045 SDValue &Lo, SDValue &Hi) {
1046 // Expand the incoming operand to be shifted, so that we have its parts
1048 GetExpandedInteger(N->getOperand(0), InL, InH);
1050 MVT NVT = InL.getValueType();
1051 unsigned VTBits = N->getValueType(0).getSizeInBits();
1052 unsigned NVTBits = NVT.getSizeInBits();
1053 MVT ShTy = N->getOperand(1).getValueType();
1055 if (N->getOpcode() == ISD::SHL) {
1057 Lo = Hi = DAG.getConstant(0, NVT);
1058 } else if (Amt > NVTBits) {
1059 Lo = DAG.getConstant(0, NVT);
1060 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1061 } else if (Amt == NVTBits) {
1062 Lo = DAG.getConstant(0, NVT);
1064 } else if (Amt == 1) {
1065 // Emit this X << 1 as X+X.
1066 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1067 SDValue LoOps[2] = { InL, InL };
1068 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1069 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1070 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1072 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1073 Hi = DAG.getNode(ISD::OR, NVT,
1074 DAG.getNode(ISD::SHL, NVT, InH,
1075 DAG.getConstant(Amt, ShTy)),
1076 DAG.getNode(ISD::SRL, NVT, InL,
1077 DAG.getConstant(NVTBits-Amt, ShTy)));
1082 if (N->getOpcode() == ISD::SRL) {
1084 Lo = DAG.getConstant(0, NVT);
1085 Hi = DAG.getConstant(0, NVT);
1086 } else if (Amt > NVTBits) {
1087 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1088 Hi = DAG.getConstant(0, NVT);
1089 } else if (Amt == NVTBits) {
1091 Hi = DAG.getConstant(0, NVT);
1093 Lo = DAG.getNode(ISD::OR, NVT,
1094 DAG.getNode(ISD::SRL, NVT, InL,
1095 DAG.getConstant(Amt, ShTy)),
1096 DAG.getNode(ISD::SHL, NVT, InH,
1097 DAG.getConstant(NVTBits-Amt, ShTy)));
1098 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1103 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1105 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1106 DAG.getConstant(NVTBits-1, ShTy));
1107 } else if (Amt > NVTBits) {
1108 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1109 DAG.getConstant(Amt-NVTBits, ShTy));
1110 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1111 DAG.getConstant(NVTBits-1, ShTy));
1112 } else if (Amt == NVTBits) {
1114 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1115 DAG.getConstant(NVTBits-1, ShTy));
1117 Lo = DAG.getNode(ISD::OR, NVT,
1118 DAG.getNode(ISD::SRL, NVT, InL,
1119 DAG.getConstant(Amt, ShTy)),
1120 DAG.getNode(ISD::SHL, NVT, InH,
1121 DAG.getConstant(NVTBits-Amt, ShTy)));
1122 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1126 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1127 /// this shift based on knowledge of the high bit of the shift amount. If we
1128 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1130 bool DAGTypeLegalizer::
1131 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1132 SDValue Amt = N->getOperand(1);
1133 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1134 MVT ShTy = Amt.getValueType();
1135 unsigned ShBits = ShTy.getSizeInBits();
1136 unsigned NVTBits = NVT.getSizeInBits();
1137 assert(isPowerOf2_32(NVTBits) &&
1138 "Expanded integer type size not a power of two!");
1140 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1141 APInt KnownZero, KnownOne;
1142 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1144 // If we don't know anything about the high bits, exit.
1145 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1148 // Get the incoming operand to be shifted.
1150 GetExpandedInteger(N->getOperand(0), InL, InH);
1152 // If we know that any of the high bits of the shift amount are one, then we
1153 // can do this as a couple of simple shifts.
1154 if (KnownOne.intersects(HighBitMask)) {
1155 // Mask out the high bit, which we know is set.
1156 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1157 DAG.getConstant(~HighBitMask, ShTy));
1159 switch (N->getOpcode()) {
1160 default: assert(0 && "Unknown shift");
1162 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1163 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1166 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1167 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1170 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1171 DAG.getConstant(NVTBits-1, ShTy));
1172 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1177 // If we know that all of the high bits of the shift amount are zero, then we
1178 // can do this as a couple of simple shifts.
1179 if ((KnownZero & HighBitMask) == HighBitMask) {
1181 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1182 DAG.getConstant(NVTBits, ShTy),
1185 switch (N->getOpcode()) {
1186 default: assert(0 && "Unknown shift");
1187 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1189 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1192 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1193 Hi = DAG.getNode(ISD::OR, NVT,
1194 DAG.getNode(Op1, NVT, InH, Amt),
1195 DAG.getNode(Op2, NVT, InL, Amt2));
1202 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1203 SDValue &Lo, SDValue &Hi) {
1204 // Expand the subcomponents.
1205 SDValue LHSL, LHSH, RHSL, RHSH;
1206 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1207 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1209 MVT NVT = LHSL.getValueType();
1210 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1211 SDValue LoOps[2] = { LHSL, RHSL };
1212 SDValue HiOps[3] = { LHSH, RHSH };
1214 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1215 // them. TODO: Teach operation legalization how to expand unsupported
1216 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1217 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1218 // generate a value of this type in the expanded code sequence.
1220 TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC,
1221 TLI.getTypeToExpandTo(NVT));
1224 if (N->getOpcode() == ISD::ADD) {
1225 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1226 HiOps[2] = Lo.getValue(1);
1227 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1229 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1230 HiOps[2] = Lo.getValue(1);
1231 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1234 if (N->getOpcode() == ISD::ADD) {
1235 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
1236 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
1237 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0],
1239 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
1240 DAG.getConstant(1, NVT),
1241 DAG.getConstant(0, NVT));
1242 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1],
1244 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
1245 DAG.getConstant(1, NVT), Carry1);
1246 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
1248 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
1249 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
1250 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
1251 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
1252 DAG.getConstant(1, NVT),
1253 DAG.getConstant(0, NVT));
1254 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
1259 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1260 SDValue &Lo, SDValue &Hi) {
1261 // Expand the subcomponents.
1262 SDValue LHSL, LHSH, RHSL, RHSH;
1263 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1264 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1265 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1266 SDValue LoOps[2] = { LHSL, RHSL };
1267 SDValue HiOps[3] = { LHSH, RHSH };
1269 if (N->getOpcode() == ISD::ADDC) {
1270 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1271 HiOps[2] = Lo.getValue(1);
1272 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1274 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1275 HiOps[2] = Lo.getValue(1);
1276 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1279 // Legalized the flag result - switch anything that used the old flag to
1281 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1284 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1285 SDValue &Lo, SDValue &Hi) {
1286 // Expand the subcomponents.
1287 SDValue LHSL, LHSH, RHSL, RHSH;
1288 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1289 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1290 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1291 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1292 SDValue HiOps[3] = { LHSH, RHSH };
1294 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1295 HiOps[2] = Lo.getValue(1);
1296 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1298 // Legalized the flag result - switch anything that used the old flag to
1300 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1303 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1304 SDValue &Lo, SDValue &Hi) {
1305 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1306 SDValue Op = N->getOperand(0);
1307 if (Op.getValueType().bitsLE(NVT)) {
1308 // The low part is any extension of the input (which degenerates to a copy).
1309 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
1310 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
1312 // For example, extension of an i48 to an i64. The operand type necessarily
1313 // promotes to the result type, so will end up being expanded too.
1314 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1315 "Only know how to promote this result!");
1316 SDValue Res = GetPromotedInteger(Op);
1317 assert(Res.getValueType() == N->getValueType(0) &&
1318 "Operand over promoted?");
1319 // Split the promoted operand. This will simplify when it is expanded.
1320 SplitInteger(Res, Lo, Hi);
1324 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1325 SDValue &Lo, SDValue &Hi) {
1326 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1327 MVT NVT = Lo.getValueType();
1328 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1329 unsigned NVTBits = NVT.getSizeInBits();
1330 unsigned EVTBits = EVT.getSizeInBits();
1332 if (NVTBits < EVTBits) {
1333 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi,
1334 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1336 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT));
1337 // The high part replicates the sign bit of Lo, make it explicit.
1338 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1339 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy()));
1343 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1344 SDValue &Lo, SDValue &Hi) {
1345 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1346 MVT NVT = Lo.getValueType();
1347 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1348 unsigned NVTBits = NVT.getSizeInBits();
1349 unsigned EVTBits = EVT.getSizeInBits();
1351 if (NVTBits < EVTBits) {
1352 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
1353 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1355 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
1356 // The high part must be zero, make it explicit.
1357 Hi = DAG.getConstant(0, NVT);
1361 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1362 SDValue &Lo, SDValue &Hi) {
1363 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1364 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1365 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1368 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1369 SDValue &Lo, SDValue &Hi) {
1370 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1371 unsigned NBitWidth = NVT.getSizeInBits();
1372 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1373 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1374 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1377 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1378 SDValue &Lo, SDValue &Hi) {
1379 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1380 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1381 MVT NVT = Lo.getValueType();
1383 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1384 DAG.getConstant(0, NVT), ISD::SETNE);
1386 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1387 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1389 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1390 DAG.getNode(ISD::ADD, NVT, LoLZ,
1391 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1392 Hi = DAG.getConstant(0, NVT);
1395 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1396 SDValue &Lo, SDValue &Hi) {
1397 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1398 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1399 MVT NVT = Lo.getValueType();
1400 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1401 DAG.getNode(ISD::CTPOP, NVT, Hi));
1402 Hi = DAG.getConstant(0, NVT);
1405 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1406 SDValue &Lo, SDValue &Hi) {
1407 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1408 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1409 MVT NVT = Lo.getValueType();
1411 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1412 DAG.getConstant(0, NVT), ISD::SETNE);
1414 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1415 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1417 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1418 DAG.getNode(ISD::ADD, NVT, HiLZ,
1419 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1420 Hi = DAG.getConstant(0, NVT);
1423 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1425 MVT VT = N->getValueType(0);
1426 SDValue Op = N->getOperand(0);
1427 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1428 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1429 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1432 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1434 MVT VT = N->getValueType(0);
1435 SDValue Op = N->getOperand(0);
1436 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1437 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1438 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1441 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1442 SDValue &Lo, SDValue &Hi) {
1443 if (ISD::isNormalLoad(N)) {
1444 ExpandRes_NormalLoad(N, Lo, Hi);
1448 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1450 MVT VT = N->getValueType(0);
1451 MVT NVT = TLI.getTypeToTransformTo(VT);
1452 SDValue Ch = N->getChain();
1453 SDValue Ptr = N->getBasePtr();
1454 ISD::LoadExtType ExtType = N->getExtensionType();
1455 int SVOffset = N->getSrcValueOffset();
1456 unsigned Alignment = N->getAlignment();
1457 bool isVolatile = N->isVolatile();
1459 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1461 if (N->getMemoryVT().bitsLE(NVT)) {
1462 MVT EVT = N->getMemoryVT();
1464 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1465 isVolatile, Alignment);
1467 // Remember the chain.
1468 Ch = Lo.getValue(1);
1470 if (ExtType == ISD::SEXTLOAD) {
1471 // The high part is obtained by SRA'ing all but one of the bits of the
1473 unsigned LoSize = Lo.getValueType().getSizeInBits();
1474 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1475 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1476 } else if (ExtType == ISD::ZEXTLOAD) {
1477 // The high part is just a zero.
1478 Hi = DAG.getConstant(0, NVT);
1480 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1481 // The high part is undefined.
1482 Hi = DAG.getNode(ISD::UNDEF, NVT);
1484 } else if (TLI.isLittleEndian()) {
1485 // Little-endian - low bits are at low addresses.
1486 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1487 isVolatile, Alignment);
1489 unsigned ExcessBits =
1490 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1491 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1493 // Increment the pointer to the other half.
1494 unsigned IncrementSize = NVT.getSizeInBits()/8;
1495 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1496 DAG.getIntPtrConstant(IncrementSize));
1497 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1498 SVOffset+IncrementSize, NEVT,
1499 isVolatile, MinAlign(Alignment, IncrementSize));
1501 // Build a factor node to remember that this load is independent of the
1503 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1506 // Big-endian - high bits are at low addresses. Favor aligned loads at
1507 // the cost of some bit-fiddling.
1508 MVT EVT = N->getMemoryVT();
1509 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1510 unsigned IncrementSize = NVT.getSizeInBits()/8;
1511 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1513 // Load both the high bits and maybe some of the low bits.
1514 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1515 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1516 isVolatile, Alignment);
1518 // Increment the pointer to the other half.
1519 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1520 DAG.getIntPtrConstant(IncrementSize));
1521 // Load the rest of the low bits.
1522 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1523 SVOffset+IncrementSize,
1524 MVT::getIntegerVT(ExcessBits),
1525 isVolatile, MinAlign(Alignment, IncrementSize));
1527 // Build a factor node to remember that this load is independent of the
1529 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1532 if (ExcessBits < NVT.getSizeInBits()) {
1533 // Transfer low bits from the bottom of Hi to the top of Lo.
1534 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1535 DAG.getNode(ISD::SHL, NVT, Hi,
1536 DAG.getConstant(ExcessBits,
1537 TLI.getShiftAmountTy())));
1538 // Move high bits to the right position in Hi.
1539 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1540 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1541 TLI.getShiftAmountTy()));
1545 // Legalized the chain result - switch anything that used the old chain to
1547 ReplaceValueWith(SDValue(N, 1), Ch);
1550 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1551 SDValue &Lo, SDValue &Hi) {
1552 SDValue LL, LH, RL, RH;
1553 GetExpandedInteger(N->getOperand(0), LL, LH);
1554 GetExpandedInteger(N->getOperand(1), RL, RH);
1555 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1556 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1559 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1560 SDValue &Lo, SDValue &Hi) {
1561 MVT VT = N->getValueType(0);
1562 MVT NVT = TLI.getTypeToTransformTo(VT);
1564 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1565 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1566 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1567 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1568 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1569 SDValue LL, LH, RL, RH;
1570 GetExpandedInteger(N->getOperand(0), LL, LH);
1571 GetExpandedInteger(N->getOperand(1), RL, RH);
1572 unsigned OuterBitSize = VT.getSizeInBits();
1573 unsigned InnerBitSize = NVT.getSizeInBits();
1574 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1575 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1577 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1578 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1579 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1580 // The inputs are both zero-extended.
1582 // We can emit a umul_lohi.
1583 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1584 Hi = SDValue(Lo.getNode(), 1);
1588 // We can emit a mulhu+mul.
1589 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1590 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1594 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1595 // The input values are both sign-extended.
1597 // We can emit a smul_lohi.
1598 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1599 Hi = SDValue(Lo.getNode(), 1);
1603 // We can emit a mulhs+mul.
1604 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1605 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1610 // Lo,Hi = umul LHS, RHS.
1611 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1612 DAG.getVTList(NVT, NVT), LL, RL);
1614 Hi = UMulLOHI.getValue(1);
1615 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1616 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1617 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1618 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1622 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1623 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1624 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1625 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1626 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1627 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1632 // If nothing else, we can make a libcall.
1633 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1635 LC = RTLIB::MUL_I32;
1636 else if (VT == MVT::i64)
1637 LC = RTLIB::MUL_I64;
1638 else if (VT == MVT::i128)
1639 LC = RTLIB::MUL_I128;
1640 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1642 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1643 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1646 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1647 SDValue &Lo, SDValue &Hi) {
1648 MVT VT = N->getValueType(0);
1650 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1652 LC = RTLIB::SDIV_I32;
1653 else if (VT == MVT::i64)
1654 LC = RTLIB::SDIV_I64;
1655 else if (VT == MVT::i128)
1656 LC = RTLIB::SDIV_I128;
1657 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1659 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1660 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1663 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1664 SDValue &Lo, SDValue &Hi) {
1665 MVT VT = N->getValueType(0);
1667 // If we can emit an efficient shift operation, do so now. Check to see if
1668 // the RHS is a constant.
1669 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1670 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1672 // If we can determine that the high bit of the shift is zero or one, even if
1673 // the low bits are variable, emit this shift in an optimized form.
1674 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1677 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1679 if (N->getOpcode() == ISD::SHL) {
1680 PartsOpc = ISD::SHL_PARTS;
1681 } else if (N->getOpcode() == ISD::SRL) {
1682 PartsOpc = ISD::SRL_PARTS;
1684 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1685 PartsOpc = ISD::SRA_PARTS;
1688 // Next check to see if the target supports this SHL_PARTS operation or if it
1689 // will custom expand it.
1690 MVT NVT = TLI.getTypeToTransformTo(VT);
1691 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1692 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1693 Action == TargetLowering::Custom) {
1694 // Expand the subcomponents.
1696 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1698 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1699 MVT VT = LHSL.getValueType();
1700 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1701 Hi = Lo.getValue(1);
1705 // Otherwise, emit a libcall.
1706 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1708 if (N->getOpcode() == ISD::SHL) {
1709 isSigned = false; /*sign irrelevant*/
1711 LC = RTLIB::SHL_I32;
1712 else if (VT == MVT::i64)
1713 LC = RTLIB::SHL_I64;
1714 else if (VT == MVT::i128)
1715 LC = RTLIB::SHL_I128;
1716 } else if (N->getOpcode() == ISD::SRL) {
1719 LC = RTLIB::SRL_I32;
1720 else if (VT == MVT::i64)
1721 LC = RTLIB::SRL_I64;
1722 else if (VT == MVT::i128)
1723 LC = RTLIB::SRL_I128;
1725 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1728 LC = RTLIB::SRA_I32;
1729 else if (VT == MVT::i64)
1730 LC = RTLIB::SRA_I64;
1731 else if (VT == MVT::i128)
1732 LC = RTLIB::SRA_I128;
1734 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1736 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1737 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1740 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1741 SDValue &Lo, SDValue &Hi) {
1742 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1743 SDValue Op = N->getOperand(0);
1744 if (Op.getValueType().bitsLE(NVT)) {
1745 // The low part is sign extension of the input (degenerates to a copy).
1746 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
1747 // The high part is obtained by SRA'ing all but one of the bits of low part.
1748 unsigned LoSize = NVT.getSizeInBits();
1749 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1750 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1752 // For example, extension of an i48 to an i64. The operand type necessarily
1753 // promotes to the result type, so will end up being expanded too.
1754 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1755 "Only know how to promote this result!");
1756 SDValue Res = GetPromotedInteger(Op);
1757 assert(Res.getValueType() == N->getValueType(0) &&
1758 "Operand over promoted?");
1759 // Split the promoted operand. This will simplify when it is expanded.
1760 SplitInteger(Res, Lo, Hi);
1761 unsigned ExcessBits =
1762 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1763 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1764 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1768 void DAGTypeLegalizer::
1769 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1770 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1771 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1773 if (EVT.bitsLE(Lo.getValueType())) {
1774 // sext_inreg the low part if needed.
1775 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1778 // The high part gets the sign extension from the lo-part. This handles
1779 // things like sextinreg V:i64 from i8.
1780 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1781 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1782 TLI.getShiftAmountTy()));
1784 // For example, extension of an i48 to an i64. Leave the low part alone,
1785 // sext_inreg the high part.
1786 unsigned ExcessBits =
1787 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1788 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1789 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1793 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1794 SDValue &Lo, SDValue &Hi) {
1795 MVT VT = N->getValueType(0);
1797 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1799 LC = RTLIB::SREM_I32;
1800 else if (VT == MVT::i64)
1801 LC = RTLIB::SREM_I64;
1802 else if (VT == MVT::i128)
1803 LC = RTLIB::SREM_I128;
1804 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1806 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1807 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1810 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1811 SDValue &Lo, SDValue &Hi) {
1812 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1813 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
1814 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
1815 DAG.getConstant(NVT.getSizeInBits(),
1816 TLI.getShiftAmountTy()));
1817 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
1820 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1821 SDValue &Lo, SDValue &Hi) {
1822 MVT VT = N->getValueType(0);
1824 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1826 LC = RTLIB::UDIV_I32;
1827 else if (VT == MVT::i64)
1828 LC = RTLIB::UDIV_I64;
1829 else if (VT == MVT::i128)
1830 LC = RTLIB::UDIV_I128;
1831 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1833 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1834 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1837 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1838 SDValue &Lo, SDValue &Hi) {
1839 MVT VT = N->getValueType(0);
1841 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1843 LC = RTLIB::UREM_I32;
1844 else if (VT == MVT::i64)
1845 LC = RTLIB::UREM_I64;
1846 else if (VT == MVT::i128)
1847 LC = RTLIB::UREM_I128;
1848 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1850 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1851 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1854 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1855 SDValue &Lo, SDValue &Hi) {
1856 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1857 SDValue Op = N->getOperand(0);
1858 if (Op.getValueType().bitsLE(NVT)) {
1859 // The low part is zero extension of the input (degenerates to a copy).
1860 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
1861 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1863 // For example, extension of an i48 to an i64. The operand type necessarily
1864 // promotes to the result type, so will end up being expanded too.
1865 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1866 "Only know how to promote this result!");
1867 SDValue Res = GetPromotedInteger(Op);
1868 assert(Res.getValueType() == N->getValueType(0) &&
1869 "Operand over promoted?");
1870 // Split the promoted operand. This will simplify when it is expanded.
1871 SplitInteger(Res, Lo, Hi);
1872 unsigned ExcessBits =
1873 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1874 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
1879 //===----------------------------------------------------------------------===//
1880 // Integer Operand Expansion
1881 //===----------------------------------------------------------------------===//
1883 /// ExpandIntegerOperand - This method is called when the specified operand of
1884 /// the specified node is found to need expansion. At this point, all of the
1885 /// result types of the node are known to be legal, but other operands of the
1886 /// node may need promotion or expansion as well as the specified one.
1887 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1888 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1889 SDValue Res = SDValue();
1891 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1892 == TargetLowering::Custom)
1893 Res = TLI.LowerOperation(SDValue(N, 0), DAG);
1895 if (Res.getNode() == 0) {
1896 switch (N->getOpcode()) {
1899 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1900 N->dump(&DAG); cerr << "\n";
1902 assert(0 && "Do not know how to expand this operator's operand!");
1905 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1906 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1907 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1909 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1910 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1911 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1912 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1913 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1915 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1916 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1920 // If the result is null, the sub-method took care of registering results etc.
1921 if (!Res.getNode()) return false;
1922 // If the result is N, the sub-method updated N in place. Check to see if any
1923 // operands are new, and if so, mark them.
1924 if (Res.getNode() == N) {
1925 // Mark N as new and remark N and its operands. This allows us to correctly
1926 // revisit N if it needs another step of expansion and allows us to visit
1927 // any new operands to N.
1932 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1933 "Invalid operand expansion");
1935 ReplaceValueWith(SDValue(N, 0), Res);
1939 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1940 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1941 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1943 ISD::CondCode &CCCode) {
1944 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1945 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1946 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1948 MVT VT = NewLHS.getValueType();
1950 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1951 if (RHSLo == RHSHi) {
1952 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1953 if (RHSCST->isAllOnesValue()) {
1954 // Equality comparison to -1.
1955 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1962 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1963 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1964 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1965 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1969 // If this is a comparison of the sign bit, just look at the top part.
1971 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1972 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1973 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1979 // FIXME: This generated code sucks.
1980 ISD::CondCode LowCC;
1982 default: assert(0 && "Unknown integer setcc!");
1984 case ISD::SETULT: LowCC = ISD::SETULT; break;
1986 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1988 case ISD::SETULE: LowCC = ISD::SETULE; break;
1990 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1993 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1994 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1995 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1997 // NOTE: on targets without efficient SELECT of bools, we can always use
1998 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1999 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2001 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
2002 false, DagCombineInfo);
2003 if (!Tmp1.getNode())
2004 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
2005 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2006 CCCode, false, DagCombineInfo);
2007 if (!Tmp2.getNode())
2008 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2009 DAG.getCondCode(CCCode));
2011 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2012 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2013 if ((Tmp1C && Tmp1C->isNullValue()) ||
2014 (Tmp2C && Tmp2C->isNullValue() &&
2015 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2016 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2017 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2018 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2019 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2020 // low part is known false, returns high part.
2021 // For LE / GE, if high part is known false, ignore the low part.
2022 // For LT / GT, if high part is known true, ignore the low part.
2028 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2029 ISD::SETEQ, false, DagCombineInfo);
2030 if (!NewLHS.getNode())
2031 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2033 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
2034 NewLHS, Tmp1, Tmp2);
2038 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2039 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2040 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2041 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2043 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2044 // against zero to select between true and false values.
2045 if (NewRHS.getNode() == 0) {
2046 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2047 CCCode = ISD::SETNE;
2050 // Update N to have the operands specified.
2051 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2052 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2056 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2057 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2058 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2059 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2061 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2062 // against zero to select between true and false values.
2063 if (NewRHS.getNode() == 0) {
2064 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2065 CCCode = ISD::SETNE;
2068 // Update N to have the operands specified.
2069 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2070 N->getOperand(2), N->getOperand(3),
2071 DAG.getCondCode(CCCode));
2074 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2075 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2076 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2077 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2079 // If ExpandSetCCOperands returned a scalar, use it.
2080 if (NewRHS.getNode() == 0) {
2081 assert(NewLHS.getValueType() == N->getValueType(0) &&
2082 "Unexpected setcc expansion!");
2086 // Otherwise, update N to have the operands specified.
2087 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2088 DAG.getCondCode(CCCode));
2091 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2092 SDValue Op = N->getOperand(0);
2093 MVT DstVT = N->getValueType(0);
2094 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2095 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2096 "Don't know how to expand this SINT_TO_FP!");
2097 return MakeLibCall(LC, DstVT, &Op, 1, true);
2100 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2101 if (ISD::isNormalStore(N))
2102 return ExpandOp_NormalStore(N, OpNo);
2104 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2105 assert(OpNo == 1 && "Can only expand the stored value so far");
2107 MVT VT = N->getOperand(1).getValueType();
2108 MVT NVT = TLI.getTypeToTransformTo(VT);
2109 SDValue Ch = N->getChain();
2110 SDValue Ptr = N->getBasePtr();
2111 int SVOffset = N->getSrcValueOffset();
2112 unsigned Alignment = N->getAlignment();
2113 bool isVolatile = N->isVolatile();
2116 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2118 if (N->getMemoryVT().bitsLE(NVT)) {
2119 GetExpandedInteger(N->getValue(), Lo, Hi);
2120 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2121 N->getMemoryVT(), isVolatile, Alignment);
2122 } else if (TLI.isLittleEndian()) {
2123 // Little-endian - low bits are at low addresses.
2124 GetExpandedInteger(N->getValue(), Lo, Hi);
2126 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2127 isVolatile, Alignment);
2129 unsigned ExcessBits =
2130 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2131 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2133 // Increment the pointer to the other half.
2134 unsigned IncrementSize = NVT.getSizeInBits()/8;
2135 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2136 DAG.getIntPtrConstant(IncrementSize));
2137 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2138 SVOffset+IncrementSize, NEVT,
2139 isVolatile, MinAlign(Alignment, IncrementSize));
2140 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2142 // Big-endian - high bits are at low addresses. Favor aligned stores at
2143 // the cost of some bit-fiddling.
2144 GetExpandedInteger(N->getValue(), Lo, Hi);
2146 MVT EVT = N->getMemoryVT();
2147 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2148 unsigned IncrementSize = NVT.getSizeInBits()/8;
2149 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2150 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2152 if (ExcessBits < NVT.getSizeInBits()) {
2153 // Transfer high bits from the top of Lo to the bottom of Hi.
2154 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
2155 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2156 TLI.getShiftAmountTy()));
2157 Hi = DAG.getNode(ISD::OR, NVT, Hi,
2158 DAG.getNode(ISD::SRL, NVT, Lo,
2159 DAG.getConstant(ExcessBits,
2160 TLI.getShiftAmountTy())));
2163 // Store both the high bits and maybe some of the low bits.
2164 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2165 SVOffset, HiVT, isVolatile, Alignment);
2167 // Increment the pointer to the other half.
2168 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2169 DAG.getIntPtrConstant(IncrementSize));
2170 // Store the lowest ExcessBits bits in the second half.
2171 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2172 SVOffset+IncrementSize,
2173 MVT::getIntegerVT(ExcessBits),
2174 isVolatile, MinAlign(Alignment, IncrementSize));
2175 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2179 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2181 GetExpandedInteger(N->getOperand(0), InL, InH);
2182 // Just truncate the low part of the source.
2183 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
2186 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2187 SDValue Op = N->getOperand(0);
2188 MVT SrcVT = Op.getValueType();
2189 MVT DstVT = N->getValueType(0);
2191 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2192 // Do a signed conversion then adjust the result.
2193 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
2194 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2196 // The result of the signed conversion needs adjusting if the 'sign bit' of
2197 // the incoming integer was set. To handle this, we dynamically test to see
2198 // if it is set, and, if so, add a fudge factor.
2200 const uint64_t F32TwoE32 = 0x4F800000ULL;
2201 const uint64_t F32TwoE64 = 0x5F800000ULL;
2202 const uint64_t F32TwoE128 = 0x7F800000ULL;
2205 if (SrcVT == MVT::i32)
2206 FF = APInt(32, F32TwoE32);
2207 else if (SrcVT == MVT::i64)
2208 FF = APInt(32, F32TwoE64);
2209 else if (SrcVT == MVT::i128)
2210 FF = APInt(32, F32TwoE128);
2212 assert(false && "Unsupported UINT_TO_FP!");
2214 // Check whether the sign bit is set.
2216 GetExpandedInteger(Op, Lo, Hi);
2217 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
2218 DAG.getConstant(0, Hi.getValueType()),
2221 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2222 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2223 TLI.getPointerTy());
2225 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2226 SDValue Zero = DAG.getIntPtrConstant(0);
2227 SDValue Four = DAG.getIntPtrConstant(4);
2228 if (TLI.isBigEndian()) std::swap(Zero, Four);
2229 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
2231 unsigned Alignment =
2232 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2233 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
2234 Alignment = std::min(Alignment, 4u);
2236 // Load the value out, extending it from f32 to the destination float type.
2237 // FIXME: Avoid the extend by constructing the right constant pool?
2238 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
2239 FudgePtr, NULL, 0, MVT::f32,
2241 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
2244 // Otherwise, use a libcall.
2245 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2246 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2247 "Don't know how to expand this UINT_TO_FP!");
2248 return MakeLibCall(LC, DstVT, &Op, 1, true);