1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
60 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ_ZERO_UNDEF:
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
66 case ISD::EXTRACT_VECTOR_ELT:
67 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
69 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));break;
70 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
71 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
72 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
73 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
74 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
75 case ISD::SIGN_EXTEND_INREG:
76 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
77 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
78 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
79 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
80 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
81 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
83 case ISD::EXTRACT_SUBVECTOR:
84 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
85 case ISD::VECTOR_SHUFFLE:
86 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
87 case ISD::INSERT_VECTOR_ELT:
88 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
89 case ISD::BUILD_VECTOR:
90 Res = PromoteIntRes_BUILD_VECTOR(N); break;
91 case ISD::SCALAR_TO_VECTOR:
92 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
93 case ISD::CONCAT_VECTORS:
94 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
96 case ISD::SIGN_EXTEND:
97 case ISD::ZERO_EXTEND:
98 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
100 case ISD::FP_TO_SINT:
101 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
103 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
110 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
113 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
116 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
119 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
121 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
123 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
125 case ISD::ATOMIC_LOAD:
126 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
128 case ISD::ATOMIC_LOAD_ADD:
129 case ISD::ATOMIC_LOAD_SUB:
130 case ISD::ATOMIC_LOAD_AND:
131 case ISD::ATOMIC_LOAD_OR:
132 case ISD::ATOMIC_LOAD_XOR:
133 case ISD::ATOMIC_LOAD_NAND:
134 case ISD::ATOMIC_LOAD_MIN:
135 case ISD::ATOMIC_LOAD_MAX:
136 case ISD::ATOMIC_LOAD_UMIN:
137 case ISD::ATOMIC_LOAD_UMAX:
138 case ISD::ATOMIC_SWAP:
139 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
141 case ISD::ATOMIC_CMP_SWAP:
142 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
143 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
147 // If the result is null then the sub-method took care of registering it.
149 SetPromotedInteger(SDValue(N, ResNo), Res);
152 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
154 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
155 return GetPromotedInteger(Op);
158 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
159 // Sign-extend the new bits, and continue the assertion.
160 SDValue Op = SExtPromotedInteger(N->getOperand(0));
161 return DAG.getNode(ISD::AssertSext, SDLoc(N),
162 Op.getValueType(), Op, N->getOperand(1));
165 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
166 // Zero the new bits, and continue the assertion.
167 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
168 return DAG.getNode(ISD::AssertZext, SDLoc(N),
169 Op.getValueType(), Op, N->getOperand(1));
172 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
173 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
174 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
175 N->getMemoryVT(), ResVT,
176 N->getChain(), N->getBasePtr(),
177 N->getMemOperand(), N->getOrdering(),
179 // Legalized the chain result - switch anything that used the old chain to
181 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
185 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
186 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
187 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
189 N->getChain(), N->getBasePtr(),
190 Op2, N->getMemOperand(), N->getOrdering(),
192 // Legalized the chain result - switch anything that used the old chain to
194 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
198 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
201 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
202 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
203 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
205 // Only use the result of getSetCCResultType if it is legal,
206 // otherwise just use the promoted result type (NVT).
207 if (!TLI.isTypeLegal(SVT))
210 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
211 SDValue Res = DAG.getAtomicCmpSwap(
212 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
213 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
214 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
216 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
217 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
218 return Res.getValue(1);
221 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
222 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
224 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
225 SDValue Res = DAG.getAtomicCmpSwap(
226 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
227 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
228 N->getFailureOrdering(), N->getSynchScope());
229 // Update the use to N with the newly created Res.
230 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
231 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
235 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
236 SDValue InOp = N->getOperand(0);
237 EVT InVT = InOp.getValueType();
238 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
239 EVT OutVT = N->getValueType(0);
240 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
243 switch (getTypeAction(InVT)) {
244 case TargetLowering::TypeLegal:
246 case TargetLowering::TypePromoteInteger:
247 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
248 // The input promotes to the same size. Convert the promoted value.
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
251 case TargetLowering::TypeSoftenFloat:
252 // Promote the integer operand by hand.
253 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
254 case TargetLowering::TypePromoteFloat: {
255 // Convert the promoted float by hand.
256 if (NOutVT.bitsEq(NInVT)) {
257 SDValue PromotedOp = GetPromotedFloat(InOp);
258 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
259 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
260 DAG.getValueType(OutVT));
264 case TargetLowering::TypeExpandInteger:
265 case TargetLowering::TypeExpandFloat:
267 case TargetLowering::TypeScalarizeVector:
268 // Convert the element to an integer and promote it by hand.
269 if (!NOutVT.isVector())
270 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
271 BitConvertToInteger(GetScalarizedVector(InOp)));
273 case TargetLowering::TypeSplitVector: {
274 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
275 // pieces of the input into integers and reassemble in the final type.
277 GetSplitVector(N->getOperand(0), Lo, Hi);
278 Lo = BitConvertToInteger(Lo);
279 Hi = BitConvertToInteger(Hi);
281 if (TLI.isBigEndian())
284 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
285 EVT::getIntegerVT(*DAG.getContext(),
286 NOutVT.getSizeInBits()),
287 JoinIntegers(Lo, Hi));
288 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
290 case TargetLowering::TypeWidenVector:
291 // The input is widened to the same size. Convert to the widened value.
292 // Make sure that the outgoing value is not a vector, because this would
293 // make us bitcast between two vectors which are legalized in different ways.
294 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
295 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
298 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
299 CreateStackStoreLoad(InOp, OutVT));
302 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
303 SDValue Op = GetPromotedInteger(N->getOperand(0));
304 EVT OVT = N->getValueType(0);
305 EVT NVT = Op.getValueType();
308 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
309 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
310 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
313 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
314 // The pair element type may be legal, or may not promote to the same type as
315 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
316 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
317 TLI.getTypeToTransformTo(*DAG.getContext(),
318 N->getValueType(0)), JoinIntegers(N->getOperand(0),
322 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
323 EVT VT = N->getValueType(0);
324 // FIXME there is no actual debug info here
326 // Zero extend things like i1, sign extend everything else. It shouldn't
327 // matter in theory which one we pick, but this tends to give better code?
328 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
329 SDValue Result = DAG.getNode(Opc, dl,
330 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
332 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
336 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
337 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
338 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
339 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
340 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
341 "can only promote integers");
342 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
343 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
344 N->getOperand(1), N->getOperand(2),
345 N->getOperand(3), N->getOperand(4), CvtCode);
348 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
349 // Zero extend to the promoted type and do the count there.
350 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
352 EVT OVT = N->getValueType(0);
353 EVT NVT = Op.getValueType();
354 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
355 // Subtract off the extra leading bits in the bigger type.
357 ISD::SUB, dl, NVT, Op,
358 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(),
362 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
363 // Zero extend to the promoted type and do the count there.
364 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
365 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
368 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
369 SDValue Op = GetPromotedInteger(N->getOperand(0));
370 EVT OVT = N->getValueType(0);
371 EVT NVT = Op.getValueType();
373 if (N->getOpcode() == ISD::CTTZ) {
374 // The count is the same in the promoted type except if the original
375 // value was zero. This can be handled by setting the bit just off
376 // the top of the original type.
377 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
378 OVT.getScalarSizeInBits());
379 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
381 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
384 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
387 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
391 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
392 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
393 unsigned NewOpc = N->getOpcode();
396 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
397 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
398 // and SINT conversions are Custom, there is no way to tell which is
399 // preferable. We choose SINT because that's the right thing on PPC.)
400 if (N->getOpcode() == ISD::FP_TO_UINT &&
401 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
402 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
403 NewOpc = ISD::FP_TO_SINT;
405 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
407 // Assert that the converted value fits in the original type. If it doesn't
408 // (eg: because the value being converted is too big), then the result of the
409 // original operation was undefined anyway, so the assert is still correct.
410 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
411 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
412 DAG.getValueType(N->getValueType(0).getScalarType()));
415 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
416 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
419 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
421 return DAG.getNode(ISD::AssertZext, dl,
422 NVT, Res, DAG.getValueType(N->getValueType(0)));
425 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
426 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
429 if (getTypeAction(N->getOperand(0).getValueType())
430 == TargetLowering::TypePromoteInteger) {
431 SDValue Res = GetPromotedInteger(N->getOperand(0));
432 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
434 // If the result and operand types are the same after promotion, simplify
435 // to an in-register extension.
436 if (NVT == Res.getValueType()) {
437 // The high bits are not guaranteed to be anything. Insert an extend.
438 if (N->getOpcode() == ISD::SIGN_EXTEND)
439 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
440 DAG.getValueType(N->getOperand(0).getValueType()));
441 if (N->getOpcode() == ISD::ZERO_EXTEND)
442 return DAG.getZeroExtendInReg(Res, dl,
443 N->getOperand(0).getValueType().getScalarType());
444 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
449 // Otherwise, just extend the original operand all the way to the larger type.
450 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
453 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
454 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
455 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
456 ISD::LoadExtType ExtType =
457 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
459 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
460 N->getMemoryVT(), N->getMemOperand());
462 // Legalized the chain result - switch anything that used the old chain to
464 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
468 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
469 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
470 SDValue ExtSrc0 = GetPromotedInteger(N->getSrc0());
472 SDValue Mask = N->getMask();
473 EVT NewMaskVT = getSetCCResultType(NVT);
474 if (NewMaskVT != N->getMask().getValueType())
475 Mask = PromoteTargetBoolean(Mask, NewMaskVT);
478 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
479 Mask, ExtSrc0, N->getMemoryVT(),
480 N->getMemOperand(), ISD::SEXTLOAD);
481 // Legalized the chain result - switch anything that used the old chain to
483 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
486 /// Promote the overflow flag of an overflowing arithmetic node.
487 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
488 // Simply change the return type of the boolean result.
489 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
490 EVT ValueVTs[] = { N->getValueType(0), NVT };
491 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
492 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
493 DAG.getVTList(ValueVTs), Ops);
495 // Modified the sum result - switch anything that used the old sum to use
497 ReplaceValueWith(SDValue(N, 0), Res);
499 return SDValue(Res.getNode(), 1);
502 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
504 return PromoteIntRes_Overflow(N);
506 // The operation overflowed iff the result in the larger type is not the
507 // sign extension of its truncation to the original type.
508 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
509 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
510 EVT OVT = N->getOperand(0).getValueType();
511 EVT NVT = LHS.getValueType();
514 // Do the arithmetic in the larger type.
515 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
516 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
518 // Calculate the overflow flag: sign extend the arithmetic result from
519 // the original type.
520 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
521 DAG.getValueType(OVT));
522 // Overflowed if and only if this is not equal to Res.
523 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
525 // Use the calculated overflow everywhere.
526 ReplaceValueWith(SDValue(N, 1), Ofl);
531 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
532 // Sign extend the input.
533 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
534 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
535 return DAG.getNode(N->getOpcode(), SDLoc(N),
536 LHS.getValueType(), LHS, RHS);
539 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
540 SDValue LHS = GetPromotedInteger(N->getOperand(1));
541 SDValue RHS = GetPromotedInteger(N->getOperand(2));
542 return DAG.getSelect(SDLoc(N),
543 LHS.getValueType(), N->getOperand(0), LHS, RHS);
546 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
547 SDValue Mask = N->getOperand(0);
548 EVT OpTy = N->getOperand(1).getValueType();
550 // Promote all the way up to the canonical SetCC type.
551 Mask = PromoteTargetBoolean(Mask, OpTy);
552 SDValue LHS = GetPromotedInteger(N->getOperand(1));
553 SDValue RHS = GetPromotedInteger(N->getOperand(2));
554 return DAG.getNode(ISD::VSELECT, SDLoc(N),
555 LHS.getValueType(), Mask, LHS, RHS);
558 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
559 SDValue LHS = GetPromotedInteger(N->getOperand(2));
560 SDValue RHS = GetPromotedInteger(N->getOperand(3));
561 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
562 LHS.getValueType(), N->getOperand(0),
563 N->getOperand(1), LHS, RHS, N->getOperand(4));
566 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
567 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
569 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
571 // Only use the result of getSetCCResultType if it is legal,
572 // otherwise just use the promoted result type (NVT).
573 if (!TLI.isTypeLegal(SVT))
577 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
578 "Vector compare must return a vector result!");
580 SDValue LHS = N->getOperand(0);
581 SDValue RHS = N->getOperand(1);
582 if (LHS.getValueType() != RHS.getValueType()) {
583 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
584 !LHS.getValueType().isVector())
585 LHS = GetPromotedInteger(LHS);
586 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
587 !RHS.getValueType().isVector())
588 RHS = GetPromotedInteger(RHS);
591 // Get the SETCC result using the canonical SETCC type.
592 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
595 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
596 // Convert to the expected type.
597 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
600 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
601 SDValue Res = GetPromotedInteger(N->getOperand(0));
602 SDValue Amt = N->getOperand(1);
603 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
604 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
607 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
608 SDValue Op = GetPromotedInteger(N->getOperand(0));
609 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
610 Op.getValueType(), Op, N->getOperand(1));
613 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
614 // The input may have strange things in the top bits of the registers, but
615 // these operations don't care. They may have weird bits going out, but
616 // that too is okay if they are integer operations.
617 SDValue LHS = GetPromotedInteger(N->getOperand(0));
618 SDValue RHS = GetPromotedInteger(N->getOperand(1));
619 return DAG.getNode(N->getOpcode(), SDLoc(N),
620 LHS.getValueType(), LHS, RHS);
623 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
624 // The input value must be properly sign extended.
625 SDValue Res = SExtPromotedInteger(N->getOperand(0));
626 SDValue Amt = N->getOperand(1);
627 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
628 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
631 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
632 // The input value must be properly zero extended.
633 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
634 SDValue Amt = N->getOperand(1);
635 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
636 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
639 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
640 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
642 SDValue InOp = N->getOperand(0);
645 switch (getTypeAction(InOp.getValueType())) {
646 default: llvm_unreachable("Unknown type action!");
647 case TargetLowering::TypeLegal:
648 case TargetLowering::TypeExpandInteger:
651 case TargetLowering::TypePromoteInteger:
652 Res = GetPromotedInteger(InOp);
654 case TargetLowering::TypeSplitVector:
655 EVT InVT = InOp.getValueType();
656 assert(InVT.isVector() && "Cannot split scalar types");
657 unsigned NumElts = InVT.getVectorNumElements();
658 assert(NumElts == NVT.getVectorNumElements() &&
659 "Dst and Src must have the same number of elements");
660 assert(isPowerOf2_32(NumElts) &&
661 "Promoted vector type must be a power of two");
664 GetSplitVector(InOp, EOp1, EOp2);
666 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
668 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
669 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
671 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
674 // Truncate to NVT instead of VT
675 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
678 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
680 return PromoteIntRes_Overflow(N);
682 // The operation overflowed iff the result in the larger type is not the
683 // zero extension of its truncation to the original type.
684 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
685 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
686 EVT OVT = N->getOperand(0).getValueType();
687 EVT NVT = LHS.getValueType();
690 // Do the arithmetic in the larger type.
691 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
692 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
694 // Calculate the overflow flag: zero extend the arithmetic result from
695 // the original type.
696 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
697 // Overflowed if and only if this is not equal to Res.
698 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
700 // Use the calculated overflow everywhere.
701 ReplaceValueWith(SDValue(N, 1), Ofl);
706 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
707 // Promote the overflow bit trivially.
709 return PromoteIntRes_Overflow(N);
711 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
713 EVT SmallVT = LHS.getValueType();
715 // To determine if the result overflowed in a larger type, we extend the
716 // input to the larger type, do the multiply (checking if it overflows),
717 // then also check the high bits of the result to see if overflow happened
719 if (N->getOpcode() == ISD::SMULO) {
720 LHS = SExtPromotedInteger(LHS);
721 RHS = SExtPromotedInteger(RHS);
723 LHS = ZExtPromotedInteger(LHS);
724 RHS = ZExtPromotedInteger(RHS);
726 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
727 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
729 // Overflow occurred if it occurred in the larger type, or if the high part
730 // of the result does not zero/sign-extend the low part. Check this second
731 // possibility first.
733 if (N->getOpcode() == ISD::UMULO) {
734 // Unsigned overflow occurred if the high part is non-zero.
735 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
736 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
737 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
738 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
740 // Signed overflow occurred if the high part does not sign extend the low.
741 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
742 Mul, DAG.getValueType(SmallVT));
743 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
746 // The only other way for overflow to occur is if the multiplication in the
747 // larger type itself overflowed.
748 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
749 SDValue(Mul.getNode(), 1));
751 // Use the calculated overflow everywhere.
752 ReplaceValueWith(SDValue(N, 1), Overflow);
756 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
757 // Zero extend the input.
758 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
759 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
760 return DAG.getNode(N->getOpcode(), SDLoc(N),
761 LHS.getValueType(), LHS, RHS);
764 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
765 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
766 N->getValueType(0)));
769 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
770 SDValue Chain = N->getOperand(0); // Get the chain.
771 SDValue Ptr = N->getOperand(1); // Get the pointer.
772 EVT VT = N->getValueType(0);
775 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
776 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
777 // The argument is passed as NumRegs registers of type RegVT.
779 SmallVector<SDValue, 8> Parts(NumRegs);
780 for (unsigned i = 0; i < NumRegs; ++i) {
781 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
782 N->getConstantOperandVal(3));
783 Chain = Parts[i].getValue(1);
786 // Handle endianness of the load.
787 if (TLI.isBigEndian())
788 std::reverse(Parts.begin(), Parts.end());
790 // Assemble the parts in the promoted type.
791 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
792 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
793 for (unsigned i = 1; i < NumRegs; ++i) {
794 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
795 // Shift it to the right position and "or" it in.
796 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
797 DAG.getConstant(i * RegVT.getSizeInBits(),
798 TLI.getPointerTy()));
799 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
802 // Modified the chain result - switch anything that used the old chain to
804 ReplaceValueWith(SDValue(N, 1), Chain);
809 //===----------------------------------------------------------------------===//
810 // Integer Operand Promotion
811 //===----------------------------------------------------------------------===//
813 /// PromoteIntegerOperand - This method is called when the specified operand of
814 /// the specified node is found to need promotion. At this point, all of the
815 /// result types of the node are known to be legal, but other operands of the
816 /// node may need promotion or expansion as well as the specified one.
817 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
818 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
819 SDValue Res = SDValue();
821 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
824 switch (N->getOpcode()) {
827 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
828 N->dump(&DAG); dbgs() << "\n";
830 llvm_unreachable("Do not know how to promote this operator's operand!");
832 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
833 case ISD::ATOMIC_STORE:
834 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
836 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
837 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
838 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
839 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
840 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
841 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
842 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
843 case ISD::CONVERT_RNDSAT:
844 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
845 case ISD::INSERT_VECTOR_ELT:
846 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
847 case ISD::SCALAR_TO_VECTOR:
848 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
850 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
851 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
852 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
853 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
854 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
855 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
857 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
859 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
861 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
862 case ISD::FP16_TO_FP:
863 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
864 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
870 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
873 // If the result is null, the sub-method took care of registering results etc.
874 if (!Res.getNode()) return false;
876 // If the result is N, the sub-method updated N in place. Tell the legalizer
878 if (Res.getNode() == N)
881 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
882 "Invalid operand expansion");
884 ReplaceValueWith(SDValue(N, 0), Res);
888 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
889 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
890 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
891 ISD::CondCode CCCode) {
892 // We have to insert explicit sign or zero extends. Note that we could
893 // insert sign extends for ALL conditions, but zero extend is cheaper on
894 // many machines (an AND instead of two shifts), so prefer it.
896 default: llvm_unreachable("Unknown integer comparison!");
899 SDValue OpL = GetPromotedInteger(NewLHS);
900 SDValue OpR = GetPromotedInteger(NewRHS);
902 // We would prefer to promote the comparison operand with sign extension,
903 // if we find the operand is actually to truncate an AssertSext. With this
904 // optimization, we can avoid inserting real truncate instruction, which
905 // is redudant eventually.
906 if (OpL->getOpcode() == ISD::AssertSext &&
907 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
908 OpR->getOpcode() == ISD::AssertSext &&
909 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
913 NewLHS = ZExtPromotedInteger(NewLHS);
914 NewRHS = ZExtPromotedInteger(NewRHS);
922 // ALL of these operations will work if we either sign or zero extend
923 // the operands (including the unsigned comparisons!). Zero extend is
924 // usually a simpler/cheaper operation, so prefer it.
925 NewLHS = ZExtPromotedInteger(NewLHS);
926 NewRHS = ZExtPromotedInteger(NewRHS);
932 NewLHS = SExtPromotedInteger(NewLHS);
933 NewRHS = SExtPromotedInteger(NewRHS);
938 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
939 SDValue Op = GetPromotedInteger(N->getOperand(0));
940 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
943 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
944 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
945 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
946 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
947 N->getOrdering(), N->getSynchScope());
950 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
951 // This should only occur in unusual situations like bitcasting to an
952 // x86_fp80, so just turn it into a store+load
953 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
956 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
957 assert(OpNo == 2 && "Don't know how to promote this operand!");
959 SDValue LHS = N->getOperand(2);
960 SDValue RHS = N->getOperand(3);
961 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
963 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
965 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
966 N->getOperand(1), LHS, RHS, N->getOperand(4)),
970 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
971 assert(OpNo == 1 && "only know how to promote condition");
973 // Promote all the way up to the canonical SetCC type.
974 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
976 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
977 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
978 N->getOperand(2)), 0);
981 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
982 // Since the result type is legal, the operands must promote to it.
983 EVT OVT = N->getOperand(0).getValueType();
984 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
985 SDValue Hi = GetPromotedInteger(N->getOperand(1));
986 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
989 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
990 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
991 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
994 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
995 // The vector type is legal but the element type is not. This implies
996 // that the vector is a power-of-two in length and that the element
997 // type does not have a strange size (eg: it is not i1).
998 EVT VecVT = N->getValueType(0);
999 unsigned NumElts = VecVT.getVectorNumElements();
1000 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1001 "Legal vector of one illegal element?");
1003 // Promote the inserted value. The type does not need to match the
1004 // vector element type. Check that any extra bits introduced will be
1006 assert(N->getOperand(0).getValueType().getSizeInBits() >=
1007 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1008 "Type of inserted value narrower than vector element type!");
1010 SmallVector<SDValue, 16> NewOps;
1011 for (unsigned i = 0; i < NumElts; ++i)
1012 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1014 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1017 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
1018 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1019 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1020 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1021 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1022 "can only promote integer arguments");
1023 SDValue InOp = GetPromotedInteger(N->getOperand(0));
1024 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
1025 N->getOperand(1), N->getOperand(2),
1026 N->getOperand(3), N->getOperand(4), CvtCode);
1029 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1032 // Promote the inserted value. This is valid because the type does not
1033 // have to match the vector element type.
1035 // Check that any extra bits introduced will be truncated away.
1036 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1037 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1038 "Type of inserted value narrower than vector element type!");
1039 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1040 GetPromotedInteger(N->getOperand(1)),
1045 assert(OpNo == 2 && "Different operand and result vector types?");
1047 // Promote the index.
1048 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1049 TLI.getVectorIdxTy());
1050 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1051 N->getOperand(1), Idx), 0);
1054 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1055 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1056 // the operand in place.
1057 return SDValue(DAG.UpdateNodeOperands(N,
1058 GetPromotedInteger(N->getOperand(0))), 0);
1061 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1062 assert(OpNo == 0 && "Only know how to promote the condition!");
1063 SDValue Cond = N->getOperand(0);
1064 EVT OpTy = N->getOperand(1).getValueType();
1066 // Promote all the way up to the canonical SetCC type.
1067 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1068 Cond = PromoteTargetBoolean(Cond, OpVT);
1070 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1071 N->getOperand(2)), 0);
1074 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1075 assert(OpNo == 0 && "Don't know how to promote this operand!");
1077 SDValue LHS = N->getOperand(0);
1078 SDValue RHS = N->getOperand(1);
1079 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1081 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1082 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1083 N->getOperand(3), N->getOperand(4)), 0);
1086 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1087 assert(OpNo == 0 && "Don't know how to promote this operand!");
1089 SDValue LHS = N->getOperand(0);
1090 SDValue RHS = N->getOperand(1);
1091 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1093 // The CC (#2) is always legal.
1094 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1097 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1098 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1099 ZExtPromotedInteger(N->getOperand(1))), 0);
1102 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1103 SDValue Op = GetPromotedInteger(N->getOperand(0));
1105 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1106 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1107 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1110 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1111 return SDValue(DAG.UpdateNodeOperands(N,
1112 SExtPromotedInteger(N->getOperand(0))), 0);
1115 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1116 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1117 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1120 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1122 // Truncate the value and store the result.
1123 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1124 N->getMemoryVT(), N->getMemOperand());
1127 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo){
1129 SDValue DataOp = N->getValue();
1130 EVT DataVT = DataOp.getValueType();
1131 SDValue Mask = N->getMask();
1132 EVT MaskVT = Mask.getValueType();
1135 bool TruncateStore = false;
1136 if (!TLI.isTypeLegal(DataVT)) {
1137 if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger) {
1138 DataOp = GetPromotedInteger(DataOp);
1139 if (!TLI.isTypeLegal(MaskVT))
1140 Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
1141 TruncateStore = true;
1144 assert(getTypeAction(DataVT) == TargetLowering::TypeWidenVector &&
1145 "Unexpected data legalization in MSTORE");
1146 DataOp = GetWidenedVector(DataOp);
1148 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
1149 Mask = GetWidenedVector(Mask);
1151 EVT BoolVT = getSetCCResultType(DataOp.getValueType());
1153 // We can't use ModifyToType() because we should fill the mask with
1155 unsigned WidenNumElts = BoolVT.getVectorNumElements();
1156 unsigned MaskNumElts = MaskVT.getVectorNumElements();
1158 unsigned NumConcat = WidenNumElts / MaskNumElts;
1159 SmallVector<SDValue, 16> Ops(NumConcat);
1160 SDValue ZeroVal = DAG.getConstant(0, MaskVT);
1162 for (unsigned i = 1; i != NumConcat; ++i)
1165 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
1170 Mask = PromoteTargetBoolean(N->getMask(), DataOp.getValueType());
1171 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1172 N->getMemoryVT(), N->getMemOperand(),
1176 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo){
1177 assert(OpNo == 2 && "Only know how to promote the mask!");
1178 EVT DataVT = N->getValueType(0);
1179 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1180 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1181 NewOps[OpNo] = Mask;
1182 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1185 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1186 SDValue Op = GetPromotedInteger(N->getOperand(0));
1187 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1190 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1191 return SDValue(DAG.UpdateNodeOperands(N,
1192 ZExtPromotedInteger(N->getOperand(0))), 0);
1195 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1197 SDValue Op = GetPromotedInteger(N->getOperand(0));
1198 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1199 return DAG.getZeroExtendInReg(Op, dl,
1200 N->getOperand(0).getValueType().getScalarType());
1204 //===----------------------------------------------------------------------===//
1205 // Integer Result Expansion
1206 //===----------------------------------------------------------------------===//
1208 /// ExpandIntegerResult - This method is called when the specified result of the
1209 /// specified node is found to need expansion. At this point, the node may also
1210 /// have invalid operands or may have other results that need promotion, we just
1211 /// know that (at least) one result needs expansion.
1212 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1213 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1215 Lo = Hi = SDValue();
1217 // See if the target wants to custom expand this node.
1218 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1221 switch (N->getOpcode()) {
1224 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1225 N->dump(&DAG); dbgs() << "\n";
1227 llvm_unreachable("Do not know how to expand the result of this operator!");
1229 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1230 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1231 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1232 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1234 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1235 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1236 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1237 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1238 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1240 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1241 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1242 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1243 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1244 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1245 case ISD::CTLZ_ZERO_UNDEF:
1246 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1247 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1248 case ISD::CTTZ_ZERO_UNDEF:
1249 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1250 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1251 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1252 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1253 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1254 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1255 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1256 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1257 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1258 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1259 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1260 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1261 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1262 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1264 case ISD::ATOMIC_LOAD_ADD:
1265 case ISD::ATOMIC_LOAD_SUB:
1266 case ISD::ATOMIC_LOAD_AND:
1267 case ISD::ATOMIC_LOAD_OR:
1268 case ISD::ATOMIC_LOAD_XOR:
1269 case ISD::ATOMIC_LOAD_NAND:
1270 case ISD::ATOMIC_LOAD_MIN:
1271 case ISD::ATOMIC_LOAD_MAX:
1272 case ISD::ATOMIC_LOAD_UMIN:
1273 case ISD::ATOMIC_LOAD_UMAX:
1274 case ISD::ATOMIC_SWAP:
1275 case ISD::ATOMIC_CMP_SWAP: {
1276 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1277 SplitInteger(Tmp.first, Lo, Hi);
1278 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1281 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1282 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1283 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1284 SDValue Tmp = DAG.getAtomicCmpSwap(
1285 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1286 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1287 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1288 AN->getSynchScope());
1290 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1291 // success simply by comparing the loaded value against the ingoing
1293 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1294 N->getOperand(2), ISD::SETEQ);
1296 SplitInteger(Tmp, Lo, Hi);
1297 ReplaceValueWith(SDValue(N, 1), Success);
1298 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1304 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1307 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1310 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1313 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1317 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1320 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1322 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1324 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1327 // If Lo/Hi is null, the sub-method took care of registering results etc.
1329 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1332 /// Lower an atomic node to the appropriate builtin call.
1333 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1334 unsigned Opc = Node->getOpcode();
1335 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1336 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
1337 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
1339 return ExpandChainLibCall(LC, Node, false);
1342 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1343 /// and the shift amount is a constant 'Amt'. Expand the operation.
1344 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1345 SDValue &Lo, SDValue &Hi) {
1347 // Expand the incoming operand to be shifted, so that we have its parts
1349 GetExpandedInteger(N->getOperand(0), InL, InH);
1351 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1352 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1359 EVT NVT = InL.getValueType();
1360 unsigned VTBits = N->getValueType(0).getSizeInBits();
1361 unsigned NVTBits = NVT.getSizeInBits();
1362 EVT ShTy = N->getOperand(1).getValueType();
1364 if (N->getOpcode() == ISD::SHL) {
1366 Lo = Hi = DAG.getConstant(0, NVT);
1367 } else if (Amt > NVTBits) {
1368 Lo = DAG.getConstant(0, NVT);
1369 Hi = DAG.getNode(ISD::SHL, DL,
1370 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1371 } else if (Amt == NVTBits) {
1372 Lo = DAG.getConstant(0, NVT);
1374 } else if (Amt == 1 &&
1375 TLI.isOperationLegalOrCustom(ISD::ADDC,
1376 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1377 // Emit this X << 1 as X+X.
1378 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1379 SDValue LoOps[2] = { InL, InL };
1380 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1381 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1382 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1384 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1385 Hi = DAG.getNode(ISD::OR, DL, NVT,
1386 DAG.getNode(ISD::SHL, DL, NVT, InH,
1387 DAG.getConstant(Amt, ShTy)),
1388 DAG.getNode(ISD::SRL, DL, NVT, InL,
1389 DAG.getConstant(NVTBits-Amt, ShTy)));
1394 if (N->getOpcode() == ISD::SRL) {
1396 Lo = DAG.getConstant(0, NVT);
1397 Hi = DAG.getConstant(0, NVT);
1398 } else if (Amt > NVTBits) {
1399 Lo = DAG.getNode(ISD::SRL, DL,
1400 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1401 Hi = DAG.getConstant(0, NVT);
1402 } else if (Amt == NVTBits) {
1404 Hi = DAG.getConstant(0, NVT);
1406 Lo = DAG.getNode(ISD::OR, DL, NVT,
1407 DAG.getNode(ISD::SRL, DL, NVT, InL,
1408 DAG.getConstant(Amt, ShTy)),
1409 DAG.getNode(ISD::SHL, DL, NVT, InH,
1410 DAG.getConstant(NVTBits-Amt, ShTy)));
1411 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1416 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1418 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1419 DAG.getConstant(NVTBits-1, ShTy));
1420 } else if (Amt > NVTBits) {
1421 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1422 DAG.getConstant(Amt-NVTBits, ShTy));
1423 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1424 DAG.getConstant(NVTBits-1, ShTy));
1425 } else if (Amt == NVTBits) {
1427 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1428 DAG.getConstant(NVTBits-1, ShTy));
1430 Lo = DAG.getNode(ISD::OR, DL, NVT,
1431 DAG.getNode(ISD::SRL, DL, NVT, InL,
1432 DAG.getConstant(Amt, ShTy)),
1433 DAG.getNode(ISD::SHL, DL, NVT, InH,
1434 DAG.getConstant(NVTBits-Amt, ShTy)));
1435 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1439 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1440 /// this shift based on knowledge of the high bit of the shift amount. If we
1441 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1443 bool DAGTypeLegalizer::
1444 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1445 SDValue Amt = N->getOperand(1);
1446 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1447 EVT ShTy = Amt.getValueType();
1448 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1449 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1450 assert(isPowerOf2_32(NVTBits) &&
1451 "Expanded integer type size not a power of two!");
1454 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1455 APInt KnownZero, KnownOne;
1456 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1458 // If we don't know anything about the high bits, exit.
1459 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1462 // Get the incoming operand to be shifted.
1464 GetExpandedInteger(N->getOperand(0), InL, InH);
1466 // If we know that any of the high bits of the shift amount are one, then we
1467 // can do this as a couple of simple shifts.
1468 if (KnownOne.intersects(HighBitMask)) {
1469 // Mask out the high bit, which we know is set.
1470 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1471 DAG.getConstant(~HighBitMask, ShTy));
1473 switch (N->getOpcode()) {
1474 default: llvm_unreachable("Unknown shift");
1476 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1477 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1480 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1481 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1484 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1485 DAG.getConstant(NVTBits-1, ShTy));
1486 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1491 // If we know that all of the high bits of the shift amount are zero, then we
1492 // can do this as a couple of simple shifts.
1493 if ((KnownZero & HighBitMask) == HighBitMask) {
1494 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1495 // shift if x is zero. We can use XOR here because x is known to be smaller
1497 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1498 DAG.getConstant(NVTBits-1, ShTy));
1501 switch (N->getOpcode()) {
1502 default: llvm_unreachable("Unknown shift");
1503 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1505 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1508 // When shifting right the arithmetic for Lo and Hi is swapped.
1509 if (N->getOpcode() != ISD::SHL)
1510 std::swap(InL, InH);
1512 // Use a little trick to get the bits that move from Lo to Hi. First
1513 // shift by one bit.
1514 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
1515 // Then compute the remaining shift with amount-1.
1516 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1518 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1519 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1521 if (N->getOpcode() != ISD::SHL)
1529 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1531 bool DAGTypeLegalizer::
1532 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1533 SDValue Amt = N->getOperand(1);
1534 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1535 EVT ShTy = Amt.getValueType();
1536 unsigned NVTBits = NVT.getSizeInBits();
1537 assert(isPowerOf2_32(NVTBits) &&
1538 "Expanded integer type size not a power of two!");
1541 // Get the incoming operand to be shifted.
1543 GetExpandedInteger(N->getOperand(0), InL, InH);
1545 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1546 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1547 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1548 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1549 Amt, NVBitsNode, ISD::SETULT);
1550 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1551 Amt, DAG.getConstant(0, ShTy),
1554 SDValue LoS, HiS, LoL, HiL;
1555 switch (N->getOpcode()) {
1556 default: llvm_unreachable("Unknown shift");
1558 // Short: ShAmt < NVTBits
1559 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1560 HiS = DAG.getNode(ISD::OR, dl, NVT,
1561 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1562 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1564 // Long: ShAmt >= NVTBits
1565 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1566 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1568 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1569 Hi = DAG.getSelect(dl, NVT, isZero, InH,
1570 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
1573 // Short: ShAmt < NVTBits
1574 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1575 LoS = DAG.getNode(ISD::OR, dl, NVT,
1576 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1577 // FIXME: If Amt is zero, the following shift generates an undefined result
1578 // on some architectures.
1579 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1581 // Long: ShAmt >= NVTBits
1582 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1583 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1585 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1586 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1587 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1590 // Short: ShAmt < NVTBits
1591 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1592 LoS = DAG.getNode(ISD::OR, dl, NVT,
1593 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1594 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1596 // Long: ShAmt >= NVTBits
1597 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1598 DAG.getConstant(NVTBits-1, ShTy));
1599 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1601 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1602 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1603 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1608 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1609 SDValue &Lo, SDValue &Hi) {
1611 // Expand the subcomponents.
1612 SDValue LHSL, LHSH, RHSL, RHSH;
1613 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1614 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1616 EVT NVT = LHSL.getValueType();
1617 SDValue LoOps[2] = { LHSL, RHSL };
1618 SDValue HiOps[3] = { LHSH, RHSH };
1620 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1621 // them. TODO: Teach operation legalization how to expand unsupported
1622 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1623 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1624 // generate a value of this type in the expanded code sequence.
1626 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1627 ISD::ADDC : ISD::SUBC,
1628 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1631 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1632 if (N->getOpcode() == ISD::ADD) {
1633 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1634 HiOps[2] = Lo.getValue(1);
1635 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1637 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1638 HiOps[2] = Lo.getValue(1);
1639 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1644 if (N->getOpcode() == ISD::ADD) {
1645 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1646 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1647 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1649 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1650 DAG.getConstant(1, NVT),
1651 DAG.getConstant(0, NVT));
1652 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1654 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1655 DAG.getConstant(1, NVT), Carry1);
1656 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1658 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1659 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1661 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1662 LoOps[0], LoOps[1], ISD::SETULT);
1663 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1664 DAG.getConstant(1, NVT),
1665 DAG.getConstant(0, NVT));
1666 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1670 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1671 SDValue &Lo, SDValue &Hi) {
1672 // Expand the subcomponents.
1673 SDValue LHSL, LHSH, RHSL, RHSH;
1675 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1676 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1677 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1678 SDValue LoOps[2] = { LHSL, RHSL };
1679 SDValue HiOps[3] = { LHSH, RHSH };
1681 if (N->getOpcode() == ISD::ADDC) {
1682 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1683 HiOps[2] = Lo.getValue(1);
1684 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1686 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1687 HiOps[2] = Lo.getValue(1);
1688 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1691 // Legalized the flag result - switch anything that used the old flag to
1693 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1696 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1697 SDValue &Lo, SDValue &Hi) {
1698 // Expand the subcomponents.
1699 SDValue LHSL, LHSH, RHSL, RHSH;
1701 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1702 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1703 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1704 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1705 SDValue HiOps[3] = { LHSH, RHSH };
1707 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1708 HiOps[2] = Lo.getValue(1);
1709 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1711 // Legalized the flag result - switch anything that used the old flag to
1713 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1716 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1717 SDValue &Lo, SDValue &Hi) {
1718 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1719 SplitInteger(Res, Lo, Hi);
1722 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1723 SDValue &Lo, SDValue &Hi) {
1724 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1726 SDValue Op = N->getOperand(0);
1727 if (Op.getValueType().bitsLE(NVT)) {
1728 // The low part is any extension of the input (which degenerates to a copy).
1729 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1730 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1732 // For example, extension of an i48 to an i64. The operand type necessarily
1733 // promotes to the result type, so will end up being expanded too.
1734 assert(getTypeAction(Op.getValueType()) ==
1735 TargetLowering::TypePromoteInteger &&
1736 "Only know how to promote this result!");
1737 SDValue Res = GetPromotedInteger(Op);
1738 assert(Res.getValueType() == N->getValueType(0) &&
1739 "Operand over promoted?");
1740 // Split the promoted operand. This will simplify when it is expanded.
1741 SplitInteger(Res, Lo, Hi);
1745 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1746 SDValue &Lo, SDValue &Hi) {
1748 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1749 EVT NVT = Lo.getValueType();
1750 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1751 unsigned NVTBits = NVT.getSizeInBits();
1752 unsigned EVTBits = EVT.getSizeInBits();
1754 if (NVTBits < EVTBits) {
1755 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1756 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1757 EVTBits - NVTBits)));
1759 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1760 // The high part replicates the sign bit of Lo, make it explicit.
1761 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1762 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1766 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1767 SDValue &Lo, SDValue &Hi) {
1769 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1770 EVT NVT = Lo.getValueType();
1771 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1772 unsigned NVTBits = NVT.getSizeInBits();
1773 unsigned EVTBits = EVT.getSizeInBits();
1775 if (NVTBits < EVTBits) {
1776 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1777 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1778 EVTBits - NVTBits)));
1780 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1781 // The high part must be zero, make it explicit.
1782 Hi = DAG.getConstant(0, NVT);
1786 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1787 SDValue &Lo, SDValue &Hi) {
1789 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1790 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1791 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1794 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1795 SDValue &Lo, SDValue &Hi) {
1796 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1797 unsigned NBitWidth = NVT.getSizeInBits();
1798 auto Constant = cast<ConstantSDNode>(N);
1799 const APInt &Cst = Constant->getAPIntValue();
1800 bool IsTarget = Constant->isTargetOpcode();
1801 bool IsOpaque = Constant->isOpaque();
1802 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT, IsTarget, IsOpaque);
1803 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT, IsTarget,
1807 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1808 SDValue &Lo, SDValue &Hi) {
1810 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1811 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1812 EVT NVT = Lo.getValueType();
1814 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1815 DAG.getConstant(0, NVT), ISD::SETNE);
1817 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1818 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1820 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1821 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1822 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1823 Hi = DAG.getConstant(0, NVT);
1826 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1827 SDValue &Lo, SDValue &Hi) {
1829 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1830 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1831 EVT NVT = Lo.getValueType();
1832 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1833 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1834 Hi = DAG.getConstant(0, NVT);
1837 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1838 SDValue &Lo, SDValue &Hi) {
1840 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1841 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1842 EVT NVT = Lo.getValueType();
1844 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1845 DAG.getConstant(0, NVT), ISD::SETNE);
1847 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1848 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1850 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1851 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1852 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1853 Hi = DAG.getConstant(0, NVT);
1856 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1859 EVT VT = N->getValueType(0);
1861 SDValue Op = N->getOperand(0);
1862 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1863 Op = GetPromotedFloat(Op);
1865 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1866 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1867 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1872 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1875 EVT VT = N->getValueType(0);
1877 SDValue Op = N->getOperand(0);
1878 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1879 Op = GetPromotedFloat(Op);
1881 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1882 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1883 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1888 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1889 SDValue &Lo, SDValue &Hi) {
1890 if (ISD::isNormalLoad(N)) {
1891 ExpandRes_NormalLoad(N, Lo, Hi);
1895 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1897 EVT VT = N->getValueType(0);
1898 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1899 SDValue Ch = N->getChain();
1900 SDValue Ptr = N->getBasePtr();
1901 ISD::LoadExtType ExtType = N->getExtensionType();
1902 unsigned Alignment = N->getAlignment();
1903 bool isVolatile = N->isVolatile();
1904 bool isNonTemporal = N->isNonTemporal();
1905 bool isInvariant = N->isInvariant();
1906 AAMDNodes AAInfo = N->getAAInfo();
1909 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1911 if (N->getMemoryVT().bitsLE(NVT)) {
1912 EVT MemVT = N->getMemoryVT();
1914 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1915 MemVT, isVolatile, isNonTemporal, isInvariant,
1918 // Remember the chain.
1919 Ch = Lo.getValue(1);
1921 if (ExtType == ISD::SEXTLOAD) {
1922 // The high part is obtained by SRA'ing all but one of the bits of the
1924 unsigned LoSize = Lo.getValueType().getSizeInBits();
1925 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1926 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1927 } else if (ExtType == ISD::ZEXTLOAD) {
1928 // The high part is just a zero.
1929 Hi = DAG.getConstant(0, NVT);
1931 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1932 // The high part is undefined.
1933 Hi = DAG.getUNDEF(NVT);
1935 } else if (TLI.isLittleEndian()) {
1936 // Little-endian - low bits are at low addresses.
1937 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1938 isVolatile, isNonTemporal, isInvariant, Alignment,
1941 unsigned ExcessBits =
1942 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1943 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1945 // Increment the pointer to the other half.
1946 unsigned IncrementSize = NVT.getSizeInBits()/8;
1947 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1948 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1949 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1950 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1951 isVolatile, isNonTemporal, isInvariant,
1952 MinAlign(Alignment, IncrementSize), AAInfo);
1954 // Build a factor node to remember that this load is independent of the
1956 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1959 // Big-endian - high bits are at low addresses. Favor aligned loads at
1960 // the cost of some bit-fiddling.
1961 EVT MemVT = N->getMemoryVT();
1962 unsigned EBytes = MemVT.getStoreSize();
1963 unsigned IncrementSize = NVT.getSizeInBits()/8;
1964 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1966 // Load both the high bits and maybe some of the low bits.
1967 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1968 EVT::getIntegerVT(*DAG.getContext(),
1969 MemVT.getSizeInBits() - ExcessBits),
1970 isVolatile, isNonTemporal, isInvariant, Alignment,
1973 // Increment the pointer to the other half.
1974 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1975 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1976 // Load the rest of the low bits.
1977 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1978 N->getPointerInfo().getWithOffset(IncrementSize),
1979 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1980 isVolatile, isNonTemporal, isInvariant,
1981 MinAlign(Alignment, IncrementSize), AAInfo);
1983 // Build a factor node to remember that this load is independent of the
1985 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1988 if (ExcessBits < NVT.getSizeInBits()) {
1989 // Transfer low bits from the bottom of Hi to the top of Lo.
1990 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1991 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1992 DAG.getConstant(ExcessBits,
1993 TLI.getPointerTy())));
1994 // Move high bits to the right position in Hi.
1995 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1997 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1998 TLI.getPointerTy()));
2002 // Legalized the chain result - switch anything that used the old chain to
2004 ReplaceValueWith(SDValue(N, 1), Ch);
2007 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2008 SDValue &Lo, SDValue &Hi) {
2010 SDValue LL, LH, RL, RH;
2011 GetExpandedInteger(N->getOperand(0), LL, LH);
2012 GetExpandedInteger(N->getOperand(1), RL, RH);
2013 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2014 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2017 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2018 SDValue &Lo, SDValue &Hi) {
2019 EVT VT = N->getValueType(0);
2020 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2023 SDValue LL, LH, RL, RH;
2024 GetExpandedInteger(N->getOperand(0), LL, LH);
2025 GetExpandedInteger(N->getOperand(1), RL, RH);
2027 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2030 // If nothing else, we can make a libcall.
2031 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2033 LC = RTLIB::MUL_I16;
2034 else if (VT == MVT::i32)
2035 LC = RTLIB::MUL_I32;
2036 else if (VT == MVT::i64)
2037 LC = RTLIB::MUL_I64;
2038 else if (VT == MVT::i128)
2039 LC = RTLIB::MUL_I128;
2040 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2042 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2043 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2048 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2049 SDValue &Lo, SDValue &Hi) {
2050 SDValue LHS = Node->getOperand(0);
2051 SDValue RHS = Node->getOperand(1);
2054 // Expand the result by simply replacing it with the equivalent
2055 // non-overflow-checking operation.
2056 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2057 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2059 SplitInteger(Sum, Lo, Hi);
2061 // Compute the overflow.
2063 // LHSSign -> LHS >= 0
2064 // RHSSign -> RHS >= 0
2065 // SumSign -> Sum >= 0
2068 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2070 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2072 EVT OType = Node->getValueType(1);
2073 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2075 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2076 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2077 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2078 Node->getOpcode() == ISD::SADDO ?
2079 ISD::SETEQ : ISD::SETNE);
2081 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2082 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2084 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2086 // Use the calculated overflow everywhere.
2087 ReplaceValueWith(SDValue(Node, 1), Cmp);
2090 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2091 SDValue &Lo, SDValue &Hi) {
2092 EVT VT = N->getValueType(0);
2095 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2097 LC = RTLIB::SDIV_I16;
2098 else if (VT == MVT::i32)
2099 LC = RTLIB::SDIV_I32;
2100 else if (VT == MVT::i64)
2101 LC = RTLIB::SDIV_I64;
2102 else if (VT == MVT::i128)
2103 LC = RTLIB::SDIV_I128;
2104 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2106 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2107 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2110 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2111 SDValue &Lo, SDValue &Hi) {
2112 EVT VT = N->getValueType(0);
2115 // If we can emit an efficient shift operation, do so now. Check to see if
2116 // the RHS is a constant.
2117 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2118 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2120 // If we can determine that the high bit of the shift is zero or one, even if
2121 // the low bits are variable, emit this shift in an optimized form.
2122 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2125 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2127 if (N->getOpcode() == ISD::SHL) {
2128 PartsOpc = ISD::SHL_PARTS;
2129 } else if (N->getOpcode() == ISD::SRL) {
2130 PartsOpc = ISD::SRL_PARTS;
2132 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2133 PartsOpc = ISD::SRA_PARTS;
2136 // Next check to see if the target supports this SHL_PARTS operation or if it
2137 // will custom expand it.
2138 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2139 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2140 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2141 Action == TargetLowering::Custom) {
2142 // Expand the subcomponents.
2144 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2145 EVT VT = LHSL.getValueType();
2147 // If the shift amount operand is coming from a vector legalization it may
2148 // have an illegal type. Fix that first by casting the operand, otherwise
2149 // the new SHL_PARTS operation would need further legalization.
2150 SDValue ShiftOp = N->getOperand(1);
2151 EVT ShiftTy = TLI.getShiftAmountTy(VT);
2152 assert(ShiftTy.getScalarType().getSizeInBits() >=
2153 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2154 "ShiftAmountTy is too small to cover the range of this type!");
2155 if (ShiftOp.getValueType() != ShiftTy)
2156 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2158 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2159 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2160 Hi = Lo.getValue(1);
2164 // Otherwise, emit a libcall.
2165 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2167 if (N->getOpcode() == ISD::SHL) {
2168 isSigned = false; /*sign irrelevant*/
2170 LC = RTLIB::SHL_I16;
2171 else if (VT == MVT::i32)
2172 LC = RTLIB::SHL_I32;
2173 else if (VT == MVT::i64)
2174 LC = RTLIB::SHL_I64;
2175 else if (VT == MVT::i128)
2176 LC = RTLIB::SHL_I128;
2177 } else if (N->getOpcode() == ISD::SRL) {
2180 LC = RTLIB::SRL_I16;
2181 else if (VT == MVT::i32)
2182 LC = RTLIB::SRL_I32;
2183 else if (VT == MVT::i64)
2184 LC = RTLIB::SRL_I64;
2185 else if (VT == MVT::i128)
2186 LC = RTLIB::SRL_I128;
2188 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2191 LC = RTLIB::SRA_I16;
2192 else if (VT == MVT::i32)
2193 LC = RTLIB::SRA_I32;
2194 else if (VT == MVT::i64)
2195 LC = RTLIB::SRA_I64;
2196 else if (VT == MVT::i128)
2197 LC = RTLIB::SRA_I128;
2200 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2201 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2202 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2207 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2208 llvm_unreachable("Unsupported shift!");
2211 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2212 SDValue &Lo, SDValue &Hi) {
2213 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2215 SDValue Op = N->getOperand(0);
2216 if (Op.getValueType().bitsLE(NVT)) {
2217 // The low part is sign extension of the input (degenerates to a copy).
2218 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2219 // The high part is obtained by SRA'ing all but one of the bits of low part.
2220 unsigned LoSize = NVT.getSizeInBits();
2221 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2222 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2224 // For example, extension of an i48 to an i64. The operand type necessarily
2225 // promotes to the result type, so will end up being expanded too.
2226 assert(getTypeAction(Op.getValueType()) ==
2227 TargetLowering::TypePromoteInteger &&
2228 "Only know how to promote this result!");
2229 SDValue Res = GetPromotedInteger(Op);
2230 assert(Res.getValueType() == N->getValueType(0) &&
2231 "Operand over promoted?");
2232 // Split the promoted operand. This will simplify when it is expanded.
2233 SplitInteger(Res, Lo, Hi);
2234 unsigned ExcessBits =
2235 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2236 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2237 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2242 void DAGTypeLegalizer::
2243 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2245 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2246 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2248 if (EVT.bitsLE(Lo.getValueType())) {
2249 // sext_inreg the low part if needed.
2250 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2253 // The high part gets the sign extension from the lo-part. This handles
2254 // things like sextinreg V:i64 from i8.
2255 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2256 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2257 TLI.getPointerTy()));
2259 // For example, extension of an i48 to an i64. Leave the low part alone,
2260 // sext_inreg the high part.
2261 unsigned ExcessBits =
2262 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2263 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2264 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2269 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2270 SDValue &Lo, SDValue &Hi) {
2271 EVT VT = N->getValueType(0);
2274 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2276 LC = RTLIB::SREM_I16;
2277 else if (VT == MVT::i32)
2278 LC = RTLIB::SREM_I32;
2279 else if (VT == MVT::i64)
2280 LC = RTLIB::SREM_I64;
2281 else if (VT == MVT::i128)
2282 LC = RTLIB::SREM_I128;
2283 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2285 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2286 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2289 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2290 SDValue &Lo, SDValue &Hi) {
2291 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2293 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2294 Hi = DAG.getNode(ISD::SRL, dl,
2295 N->getOperand(0).getValueType(), N->getOperand(0),
2296 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2297 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2300 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2301 SDValue &Lo, SDValue &Hi) {
2302 SDValue LHS = N->getOperand(0);
2303 SDValue RHS = N->getOperand(1);
2306 // Expand the result by simply replacing it with the equivalent
2307 // non-overflow-checking operation.
2308 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2309 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2311 SplitInteger(Sum, Lo, Hi);
2313 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2314 // overflows iff a - b > a.
2315 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2316 N->getOpcode () == ISD::UADDO ?
2317 ISD::SETULT : ISD::SETUGT);
2319 // Use the calculated overflow everywhere.
2320 ReplaceValueWith(SDValue(N, 1), Ofl);
2323 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2324 SDValue &Lo, SDValue &Hi) {
2325 EVT VT = N->getValueType(0);
2328 // A divide for UMULO should be faster than a function call.
2329 if (N->getOpcode() == ISD::UMULO) {
2330 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2332 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2333 SplitInteger(MUL, Lo, Hi);
2335 // A divide for UMULO will be faster than a function call. Select to
2336 // make sure we aren't using 0.
2337 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2338 RHS, DAG.getConstant(0, VT), ISD::SETEQ);
2339 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2340 DAG.getConstant(1, VT), RHS);
2341 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2342 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2344 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2345 DAG.getConstant(0, N->getValueType(1)),
2347 ReplaceValueWith(SDValue(N, 1), Overflow);
2351 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2352 EVT PtrVT = TLI.getPointerTy();
2353 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2355 // Replace this with a libcall that will check overflow.
2356 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2358 LC = RTLIB::MULO_I32;
2359 else if (VT == MVT::i64)
2360 LC = RTLIB::MULO_I64;
2361 else if (VT == MVT::i128)
2362 LC = RTLIB::MULO_I128;
2363 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2365 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2366 // Temporary for the overflow value, default it to zero.
2367 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2368 DAG.getConstant(0, PtrVT), Temp,
2369 MachinePointerInfo(), false, false, 0);
2371 TargetLowering::ArgListTy Args;
2372 TargetLowering::ArgListEntry Entry;
2373 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2374 EVT ArgVT = N->getOperand(i).getValueType();
2375 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2376 Entry.Node = N->getOperand(i);
2378 Entry.isSExt = true;
2379 Entry.isZExt = false;
2380 Args.push_back(Entry);
2383 // Also pass the address of the overflow check.
2385 Entry.Ty = PtrTy->getPointerTo();
2386 Entry.isSExt = true;
2387 Entry.isZExt = false;
2388 Args.push_back(Entry);
2390 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2392 TargetLowering::CallLoweringInfo CLI(DAG);
2393 CLI.setDebugLoc(dl).setChain(Chain)
2394 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2397 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2399 SplitInteger(CallInfo.first, Lo, Hi);
2400 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2401 MachinePointerInfo(), false, false, false, 0);
2402 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2403 DAG.getConstant(0, PtrVT),
2405 // Use the overflow from the libcall everywhere.
2406 ReplaceValueWith(SDValue(N, 1), Ofl);
2409 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2410 SDValue &Lo, SDValue &Hi) {
2411 EVT VT = N->getValueType(0);
2414 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2416 LC = RTLIB::UDIV_I16;
2417 else if (VT == MVT::i32)
2418 LC = RTLIB::UDIV_I32;
2419 else if (VT == MVT::i64)
2420 LC = RTLIB::UDIV_I64;
2421 else if (VT == MVT::i128)
2422 LC = RTLIB::UDIV_I128;
2423 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2425 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2426 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2429 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2430 SDValue &Lo, SDValue &Hi) {
2431 EVT VT = N->getValueType(0);
2434 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2436 LC = RTLIB::UREM_I16;
2437 else if (VT == MVT::i32)
2438 LC = RTLIB::UREM_I32;
2439 else if (VT == MVT::i64)
2440 LC = RTLIB::UREM_I64;
2441 else if (VT == MVT::i128)
2442 LC = RTLIB::UREM_I128;
2443 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2445 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2446 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2449 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2450 SDValue &Lo, SDValue &Hi) {
2451 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2453 SDValue Op = N->getOperand(0);
2454 if (Op.getValueType().bitsLE(NVT)) {
2455 // The low part is zero extension of the input (degenerates to a copy).
2456 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2457 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2459 // For example, extension of an i48 to an i64. The operand type necessarily
2460 // promotes to the result type, so will end up being expanded too.
2461 assert(getTypeAction(Op.getValueType()) ==
2462 TargetLowering::TypePromoteInteger &&
2463 "Only know how to promote this result!");
2464 SDValue Res = GetPromotedInteger(Op);
2465 assert(Res.getValueType() == N->getValueType(0) &&
2466 "Operand over promoted?");
2467 // Split the promoted operand. This will simplify when it is expanded.
2468 SplitInteger(Res, Lo, Hi);
2469 unsigned ExcessBits =
2470 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2471 Hi = DAG.getZeroExtendInReg(Hi, dl,
2472 EVT::getIntegerVT(*DAG.getContext(),
2477 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2478 SDValue &Lo, SDValue &Hi) {
2480 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2481 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2482 SDValue Zero = DAG.getConstant(0, VT);
2483 SDValue Swap = DAG.getAtomicCmpSwap(
2484 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2485 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2486 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2487 cast<AtomicSDNode>(N)->getOrdering(),
2488 cast<AtomicSDNode>(N)->getOrdering(),
2489 cast<AtomicSDNode>(N)->getSynchScope());
2491 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2492 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2495 //===----------------------------------------------------------------------===//
2496 // Integer Operand Expansion
2497 //===----------------------------------------------------------------------===//
2499 /// ExpandIntegerOperand - This method is called when the specified operand of
2500 /// the specified node is found to need expansion. At this point, all of the
2501 /// result types of the node are known to be legal, but other operands of the
2502 /// node may need promotion or expansion as well as the specified one.
2503 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2504 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2505 SDValue Res = SDValue();
2507 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2510 switch (N->getOpcode()) {
2513 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2514 N->dump(&DAG); dbgs() << "\n";
2516 llvm_unreachable("Do not know how to expand this operator's operand!");
2518 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2519 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2520 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2521 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2522 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2523 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2524 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2525 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2526 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2527 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2528 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2529 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2535 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2536 case ISD::RETURNADDR:
2537 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2539 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2542 // If the result is null, the sub-method took care of registering results etc.
2543 if (!Res.getNode()) return false;
2545 // If the result is N, the sub-method updated N in place. Tell the legalizer
2547 if (Res.getNode() == N)
2550 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2551 "Invalid operand expansion");
2553 ReplaceValueWith(SDValue(N, 0), Res);
2557 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2558 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2559 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2561 ISD::CondCode &CCCode,
2563 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2564 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2565 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2567 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2568 if (RHSLo == RHSHi) {
2569 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2570 if (RHSCST->isAllOnesValue()) {
2571 // Equality comparison to -1.
2572 NewLHS = DAG.getNode(ISD::AND, dl,
2573 LHSLo.getValueType(), LHSLo, LHSHi);
2580 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2581 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2582 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2583 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2587 // If this is a comparison of the sign bit, just look at the top part.
2589 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2590 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2591 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2597 // FIXME: This generated code sucks.
2598 ISD::CondCode LowCC;
2600 default: llvm_unreachable("Unknown integer setcc!");
2602 case ISD::SETULT: LowCC = ISD::SETULT; break;
2604 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2606 case ISD::SETULE: LowCC = ISD::SETULE; break;
2608 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2611 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2612 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2613 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2615 // NOTE: on targets without efficient SELECT of bools, we can always use
2616 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2617 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2620 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2621 TLI.isTypeLegal(RHSLo.getValueType()))
2622 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2623 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2624 if (!Tmp1.getNode())
2625 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2626 LHSLo, RHSLo, LowCC);
2627 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2628 TLI.isTypeLegal(RHSHi.getValueType()))
2629 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2630 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2631 if (!Tmp2.getNode())
2632 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2633 getSetCCResultType(LHSHi.getValueType()),
2634 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2636 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2637 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2638 if ((Tmp1C && Tmp1C->isNullValue()) ||
2639 (Tmp2C && Tmp2C->isNullValue() &&
2640 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2641 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2642 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2643 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2644 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2645 // low part is known false, returns high part.
2646 // For LE / GE, if high part is known false, ignore the low part.
2647 // For LT / GT, if high part is known true, ignore the low part.
2653 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2654 LHSHi, RHSHi, ISD::SETEQ, false,
2655 DagCombineInfo, dl);
2656 if (!NewLHS.getNode())
2657 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2658 LHSHi, RHSHi, ISD::SETEQ);
2659 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2660 NewLHS, Tmp1, Tmp2);
2664 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2665 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2666 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2667 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2669 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2670 // against zero to select between true and false values.
2671 if (!NewRHS.getNode()) {
2672 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2673 CCCode = ISD::SETNE;
2676 // Update N to have the operands specified.
2677 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2678 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2679 N->getOperand(4)), 0);
2682 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2683 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2684 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2685 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2687 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2688 // against zero to select between true and false values.
2689 if (!NewRHS.getNode()) {
2690 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2691 CCCode = ISD::SETNE;
2694 // Update N to have the operands specified.
2695 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2696 N->getOperand(2), N->getOperand(3),
2697 DAG.getCondCode(CCCode)), 0);
2700 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2701 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2702 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2703 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2705 // If ExpandSetCCOperands returned a scalar, use it.
2706 if (!NewRHS.getNode()) {
2707 assert(NewLHS.getValueType() == N->getValueType(0) &&
2708 "Unexpected setcc expansion!");
2712 // Otherwise, update N to have the operands specified.
2713 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2714 DAG.getCondCode(CCCode)), 0);
2717 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2718 // The value being shifted is legal, but the shift amount is too big.
2719 // It follows that either the result of the shift is undefined, or the
2720 // upper half of the shift amount is zero. Just use the lower half.
2722 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2723 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2726 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2727 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2728 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2729 // constant to valid type.
2731 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2732 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2735 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2736 SDValue Op = N->getOperand(0);
2737 EVT DstVT = N->getValueType(0);
2738 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2739 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2740 "Don't know how to expand this SINT_TO_FP!");
2741 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2744 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2745 if (ISD::isNormalStore(N))
2746 return ExpandOp_NormalStore(N, OpNo);
2748 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2749 assert(OpNo == 1 && "Can only expand the stored value so far");
2751 EVT VT = N->getOperand(1).getValueType();
2752 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2753 SDValue Ch = N->getChain();
2754 SDValue Ptr = N->getBasePtr();
2755 unsigned Alignment = N->getAlignment();
2756 bool isVolatile = N->isVolatile();
2757 bool isNonTemporal = N->isNonTemporal();
2758 AAMDNodes AAInfo = N->getAAInfo();
2762 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2764 if (N->getMemoryVT().bitsLE(NVT)) {
2765 GetExpandedInteger(N->getValue(), Lo, Hi);
2766 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2767 N->getMemoryVT(), isVolatile, isNonTemporal,
2771 if (TLI.isLittleEndian()) {
2772 // Little-endian - low bits are at low addresses.
2773 GetExpandedInteger(N->getValue(), Lo, Hi);
2775 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2776 isVolatile, isNonTemporal, Alignment, AAInfo);
2778 unsigned ExcessBits =
2779 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2780 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2782 // Increment the pointer to the other half.
2783 unsigned IncrementSize = NVT.getSizeInBits()/8;
2784 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2785 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2786 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2787 N->getPointerInfo().getWithOffset(IncrementSize),
2788 NEVT, isVolatile, isNonTemporal,
2789 MinAlign(Alignment, IncrementSize), AAInfo);
2790 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2793 // Big-endian - high bits are at low addresses. Favor aligned stores at
2794 // the cost of some bit-fiddling.
2795 GetExpandedInteger(N->getValue(), Lo, Hi);
2797 EVT ExtVT = N->getMemoryVT();
2798 unsigned EBytes = ExtVT.getStoreSize();
2799 unsigned IncrementSize = NVT.getSizeInBits()/8;
2800 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2801 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2802 ExtVT.getSizeInBits() - ExcessBits);
2804 if (ExcessBits < NVT.getSizeInBits()) {
2805 // Transfer high bits from the top of Lo to the bottom of Hi.
2806 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2807 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2808 TLI.getPointerTy()));
2809 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2810 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2811 DAG.getConstant(ExcessBits,
2812 TLI.getPointerTy())));
2815 // Store both the high bits and maybe some of the low bits.
2816 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2817 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
2819 // Increment the pointer to the other half.
2820 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2821 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2822 // Store the lowest ExcessBits bits in the second half.
2823 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2824 N->getPointerInfo().getWithOffset(IncrementSize),
2825 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2826 isVolatile, isNonTemporal,
2827 MinAlign(Alignment, IncrementSize), AAInfo);
2828 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2831 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2833 GetExpandedInteger(N->getOperand(0), InL, InH);
2834 // Just truncate the low part of the source.
2835 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2838 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2839 SDValue Op = N->getOperand(0);
2840 EVT SrcVT = Op.getValueType();
2841 EVT DstVT = N->getValueType(0);
2844 // The following optimization is valid only if every value in SrcVT (when
2845 // treated as signed) is representable in DstVT. Check that the mantissa
2846 // size of DstVT is >= than the number of bits in SrcVT -1.
2847 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2848 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2849 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2850 // Do a signed conversion then adjust the result.
2851 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2852 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2854 // The result of the signed conversion needs adjusting if the 'sign bit' of
2855 // the incoming integer was set. To handle this, we dynamically test to see
2856 // if it is set, and, if so, add a fudge factor.
2858 const uint64_t F32TwoE32 = 0x4F800000ULL;
2859 const uint64_t F32TwoE64 = 0x5F800000ULL;
2860 const uint64_t F32TwoE128 = 0x7F800000ULL;
2863 if (SrcVT == MVT::i32)
2864 FF = APInt(32, F32TwoE32);
2865 else if (SrcVT == MVT::i64)
2866 FF = APInt(32, F32TwoE64);
2867 else if (SrcVT == MVT::i128)
2868 FF = APInt(32, F32TwoE128);
2870 llvm_unreachable("Unsupported UINT_TO_FP!");
2872 // Check whether the sign bit is set.
2874 GetExpandedInteger(Op, Lo, Hi);
2875 SDValue SignSet = DAG.getSetCC(dl,
2876 getSetCCResultType(Hi.getValueType()),
2877 Hi, DAG.getConstant(0, Hi.getValueType()),
2880 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2881 SDValue FudgePtr = DAG.getConstantPool(
2882 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2883 TLI.getPointerTy());
2885 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2886 SDValue Zero = DAG.getIntPtrConstant(0);
2887 SDValue Four = DAG.getIntPtrConstant(4);
2888 if (TLI.isBigEndian()) std::swap(Zero, Four);
2889 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2891 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2892 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2894 Alignment = std::min(Alignment, 4u);
2896 // Load the value out, extending it from f32 to the destination float type.
2897 // FIXME: Avoid the extend by constructing the right constant pool?
2898 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2900 MachinePointerInfo::getConstantPool(),
2902 false, false, false, Alignment);
2903 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2906 // Otherwise, use a libcall.
2907 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2908 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2909 "Don't know how to expand this UINT_TO_FP!");
2910 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
2913 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2915 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2916 cast<AtomicSDNode>(N)->getMemoryVT(),
2918 N->getOperand(1), N->getOperand(2),
2919 cast<AtomicSDNode>(N)->getMemOperand(),
2920 cast<AtomicSDNode>(N)->getOrdering(),
2921 cast<AtomicSDNode>(N)->getSynchScope());
2922 return Swap.getValue(1);
2926 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2927 SDValue InOp0 = N->getOperand(0);
2928 EVT InVT = InOp0.getValueType();
2930 EVT OutVT = N->getValueType(0);
2931 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2932 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2933 unsigned OutNumElems = OutVT.getVectorNumElements();
2934 EVT NOutVTElem = NOutVT.getVectorElementType();
2937 SDValue BaseIdx = N->getOperand(1);
2939 SmallVector<SDValue, 8> Ops;
2940 Ops.reserve(OutNumElems);
2941 for (unsigned i = 0; i != OutNumElems; ++i) {
2943 // Extract the element from the original vector.
2944 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2945 BaseIdx, DAG.getConstant(i, BaseIdx.getValueType()));
2946 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2947 InVT.getVectorElementType(), N->getOperand(0), Index);
2949 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2950 // Insert the converted element to the new vector.
2954 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
2958 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2959 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2960 EVT VT = N->getValueType(0);
2963 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
2965 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2966 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2967 EVT OutVT = V0.getValueType();
2969 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
2973 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2974 EVT OutVT = N->getValueType(0);
2975 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2976 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2977 unsigned NumElems = N->getNumOperands();
2978 EVT NOutVTElem = NOutVT.getVectorElementType();
2982 SmallVector<SDValue, 8> Ops;
2983 Ops.reserve(NumElems);
2984 for (unsigned i = 0; i != NumElems; ++i) {
2986 // BUILD_VECTOR integer operand types are allowed to be larger than the
2987 // result's element type. This may still be true after the promotion. For
2988 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
2989 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
2990 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
2991 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2993 Op = N->getOperand(i);
2997 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3000 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3004 assert(!N->getOperand(0).getValueType().isVector() &&
3005 "Input must be a scalar");
3007 EVT OutVT = N->getValueType(0);
3008 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3009 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3010 EVT NOutVTElem = NOutVT.getVectorElementType();
3012 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3014 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3017 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3020 EVT OutVT = N->getValueType(0);
3021 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3022 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3024 EVT InElemTy = OutVT.getVectorElementType();
3025 EVT OutElemTy = NOutVT.getVectorElementType();
3027 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3028 unsigned NumOutElem = NOutVT.getVectorNumElements();
3029 unsigned NumOperands = N->getNumOperands();
3030 assert(NumElem * NumOperands == NumOutElem &&
3031 "Unexpected number of elements");
3033 // Take the elements from the first vector.
3034 SmallVector<SDValue, 8> Ops(NumOutElem);
3035 for (unsigned i = 0; i < NumOperands; ++i) {
3036 SDValue Op = N->getOperand(i);
3037 for (unsigned j = 0; j < NumElem; ++j) {
3038 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3039 InElemTy, Op, DAG.getConstant(j,
3040 TLI.getVectorIdxTy()));
3041 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3045 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3048 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3049 EVT OutVT = N->getValueType(0);
3050 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3051 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3053 EVT NOutVTElem = NOutVT.getVectorElementType();
3056 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3058 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3059 NOutVTElem, N->getOperand(1));
3060 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3061 V0, ConvElem, N->getOperand(2));
3064 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3066 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3067 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, TLI.getVectorIdxTy());
3068 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3069 V0->getValueType(0).getScalarType(), V0, V1);
3071 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3072 // element types. If this is the case then we need to expand the outgoing
3073 // value and not truncate it.
3074 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3077 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3079 unsigned NumElems = N->getNumOperands();
3081 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3083 SmallVector<SDValue, 8> NewOps;
3084 NewOps.reserve(NumElems);
3086 // For each incoming vector
3087 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3088 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3089 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3090 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3092 for (unsigned i=0; i<NumElem; ++i) {
3093 // Extract element from incoming vector
3094 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3095 Incoming, DAG.getConstant(i, TLI.getVectorIdxTy()));
3096 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3097 NewOps.push_back(Tr);
3101 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);