1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
28 //===----------------------------------------------------------------------===//
29 // Integer Result Promotion
30 //===----------------------------------------------------------------------===//
32 /// PromoteIntegerResult - This method is called when a result of a node is
33 /// found to be in need of promotion to a larger type. At this point, the node
34 /// may also have invalid operands or may have other results that need
35 /// expansion, we just know that (at least) one result needs promotion.
36 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
37 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
38 SDValue Res = SDValue();
40 // See if the target wants to custom expand this node.
41 if (CustomLowerNode(N, N->getValueType(ResNo), true))
44 switch (N->getOpcode()) {
47 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
48 N->dump(&DAG); dbgs() << "\n";
50 llvm_unreachable("Do not know how to promote this operator!");
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
57 case ISD::CONVERT_RNDSAT:
58 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
59 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
60 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
61 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
62 case ISD::EXTRACT_VECTOR_ELT:
63 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
64 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
65 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
66 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
67 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
68 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
69 case ISD::SIGN_EXTEND_INREG:
70 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
71 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
72 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
73 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
74 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
75 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
77 case ISD::EXTRACT_SUBVECTOR:
78 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
79 case ISD::VECTOR_SHUFFLE:
80 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
81 case ISD::INSERT_VECTOR_ELT:
82 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
83 case ISD::BUILD_VECTOR:
84 Res = PromoteIntRes_BUILD_VECTOR(N); break;
85 case ISD::SCALAR_TO_VECTOR:
86 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
88 case ISD::SIGN_EXTEND:
89 case ISD::ZERO_EXTEND:
90 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
93 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
95 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
102 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
105 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
108 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
111 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
113 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
115 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
117 case ISD::ATOMIC_LOAD_ADD:
118 case ISD::ATOMIC_LOAD_SUB:
119 case ISD::ATOMIC_LOAD_AND:
120 case ISD::ATOMIC_LOAD_OR:
121 case ISD::ATOMIC_LOAD_XOR:
122 case ISD::ATOMIC_LOAD_NAND:
123 case ISD::ATOMIC_LOAD_MIN:
124 case ISD::ATOMIC_LOAD_MAX:
125 case ISD::ATOMIC_LOAD_UMIN:
126 case ISD::ATOMIC_LOAD_UMAX:
127 case ISD::ATOMIC_SWAP:
128 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
130 case ISD::ATOMIC_CMP_SWAP:
131 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
134 // If the result is null then the sub-method took care of registering it.
136 SetPromotedInteger(SDValue(N, ResNo), Res);
139 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
140 // Sign-extend the new bits, and continue the assertion.
141 SDValue Op = SExtPromotedInteger(N->getOperand(0));
142 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
143 Op.getValueType(), Op, N->getOperand(1));
146 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
147 // Zero the new bits, and continue the assertion.
148 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
149 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
150 Op.getValueType(), Op, N->getOperand(1));
153 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
154 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
155 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
157 N->getChain(), N->getBasePtr(),
158 Op2, N->getMemOperand(), N->getOrdering(),
160 // Legalized the chain result - switch anything that used the old chain to
162 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
166 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
167 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
168 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
169 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
170 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
171 Op2, Op3, N->getMemOperand(), N->getOrdering(),
173 // Legalized the chain result - switch anything that used the old chain to
175 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
179 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
180 SDValue InOp = N->getOperand(0);
181 EVT InVT = InOp.getValueType();
182 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
183 EVT OutVT = N->getValueType(0);
184 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
185 DebugLoc dl = N->getDebugLoc();
187 switch (getTypeAction(InVT)) {
189 assert(false && "Unknown type action!");
191 case TargetLowering::TypeLegal:
193 case TargetLowering::TypePromoteInteger:
194 if (NOutVT.bitsEq(NInVT))
195 // The input promotes to the same size. Convert the promoted value.
196 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
198 case TargetLowering::TypeSoftenFloat:
199 // Promote the integer operand by hand.
200 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
201 case TargetLowering::TypeExpandInteger:
202 case TargetLowering::TypeExpandFloat:
204 case TargetLowering::TypeScalarizeVector:
205 // Convert the element to an integer and promote it by hand.
206 if (!NOutVT.isVector())
207 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
208 BitConvertToInteger(GetScalarizedVector(InOp)));
210 case TargetLowering::TypeSplitVector: {
211 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
212 // pieces of the input into integers and reassemble in the final type.
214 GetSplitVector(N->getOperand(0), Lo, Hi);
215 Lo = BitConvertToInteger(Lo);
216 Hi = BitConvertToInteger(Hi);
218 if (TLI.isBigEndian())
221 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
222 EVT::getIntegerVT(*DAG.getContext(),
223 NOutVT.getSizeInBits()),
224 JoinIntegers(Lo, Hi));
225 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
227 case TargetLowering::TypeWidenVector:
228 if (OutVT.bitsEq(NInVT))
229 // The input is widened to the same size. Convert to the widened value.
230 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp));
233 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
234 CreateStackStoreLoad(InOp, OutVT));
237 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
238 SDValue Op = GetPromotedInteger(N->getOperand(0));
239 EVT OVT = N->getValueType(0);
240 EVT NVT = Op.getValueType();
241 DebugLoc dl = N->getDebugLoc();
243 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
244 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
245 DAG.getConstant(DiffBits, TLI.getPointerTy()));
248 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
249 // The pair element type may be legal, or may not promote to the same type as
250 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
251 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
252 TLI.getTypeToTransformTo(*DAG.getContext(),
253 N->getValueType(0)), JoinIntegers(N->getOperand(0),
257 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
258 EVT VT = N->getValueType(0);
259 // FIXME there is no actual debug info here
260 DebugLoc dl = N->getDebugLoc();
261 // Zero extend things like i1, sign extend everything else. It shouldn't
262 // matter in theory which one we pick, but this tends to give better code?
263 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
264 SDValue Result = DAG.getNode(Opc, dl,
265 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
267 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
271 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
272 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
273 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
274 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
275 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
276 "can only promote integers");
277 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
278 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
279 N->getOperand(1), N->getOperand(2),
280 N->getOperand(3), N->getOperand(4), CvtCode);
283 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
284 // Zero extend to the promoted type and do the count there.
285 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
286 DebugLoc dl = N->getDebugLoc();
287 EVT OVT = N->getValueType(0);
288 EVT NVT = Op.getValueType();
289 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
290 // Subtract off the extra leading bits in the bigger type.
291 return DAG.getNode(ISD::SUB, dl, NVT, Op,
292 DAG.getConstant(NVT.getSizeInBits() -
293 OVT.getSizeInBits(), NVT));
296 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
297 // Zero extend to the promoted type and do the count there.
298 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
299 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
302 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
303 SDValue Op = GetPromotedInteger(N->getOperand(0));
304 EVT OVT = N->getValueType(0);
305 EVT NVT = Op.getValueType();
306 DebugLoc dl = N->getDebugLoc();
307 // The count is the same in the promoted type except if the original
308 // value was zero. This can be handled by setting the bit just off
309 // the top of the original type.
310 APInt TopBit(NVT.getSizeInBits(), 0);
311 TopBit.setBit(OVT.getSizeInBits());
312 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
313 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
316 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
317 DebugLoc dl = N->getDebugLoc();
318 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
319 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
323 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
324 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
325 unsigned NewOpc = N->getOpcode();
326 DebugLoc dl = N->getDebugLoc();
328 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
329 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
330 // and SINT conversions are Custom, there is no way to tell which is
331 // preferable. We choose SINT because that's the right thing on PPC.)
332 if (N->getOpcode() == ISD::FP_TO_UINT &&
333 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
334 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
335 NewOpc = ISD::FP_TO_SINT;
337 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
339 // Assert that the converted value fits in the original type. If it doesn't
340 // (eg: because the value being converted is too big), then the result of the
341 // original operation was undefined anyway, so the assert is still correct.
342 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
343 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
344 DAG.getValueType(N->getValueType(0).getScalarType()));
347 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
348 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
349 DebugLoc dl = N->getDebugLoc();
351 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
353 return DAG.getNode(ISD::AssertZext, dl,
354 NVT, Res, DAG.getValueType(N->getValueType(0)));
357 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
358 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
359 DebugLoc dl = N->getDebugLoc();
361 if (getTypeAction(N->getOperand(0).getValueType())
362 == TargetLowering::TypePromoteInteger) {
363 SDValue Res = GetPromotedInteger(N->getOperand(0));
364 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
366 // If the result and operand types are the same after promotion, simplify
367 // to an in-register extension.
368 if (NVT == Res.getValueType()) {
369 // The high bits are not guaranteed to be anything. Insert an extend.
370 if (N->getOpcode() == ISD::SIGN_EXTEND)
371 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
372 DAG.getValueType(N->getOperand(0).getValueType()));
373 if (N->getOpcode() == ISD::ZERO_EXTEND)
374 return DAG.getZeroExtendInReg(Res, dl,
375 N->getOperand(0).getValueType().getScalarType());
376 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
381 // Otherwise, just extend the original operand all the way to the larger type.
382 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
385 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
386 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
387 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
388 ISD::LoadExtType ExtType =
389 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
390 DebugLoc dl = N->getDebugLoc();
391 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
393 N->getMemoryVT(), N->isVolatile(),
394 N->isNonTemporal(), N->getAlignment());
396 // Legalized the chain result - switch anything that used the old chain to
398 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
402 /// Promote the overflow flag of an overflowing arithmetic node.
403 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
404 // Simply change the return type of the boolean result.
405 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
406 EVT ValueVTs[] = { N->getValueType(0), NVT };
407 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
408 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
409 DAG.getVTList(ValueVTs, 2), Ops, 2);
411 // Modified the sum result - switch anything that used the old sum to use
413 ReplaceValueWith(SDValue(N, 0), Res);
415 return SDValue(Res.getNode(), 1);
418 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
420 return PromoteIntRes_Overflow(N);
422 // The operation overflowed iff the result in the larger type is not the
423 // sign extension of its truncation to the original type.
424 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
425 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
426 EVT OVT = N->getOperand(0).getValueType();
427 EVT NVT = LHS.getValueType();
428 DebugLoc dl = N->getDebugLoc();
430 // Do the arithmetic in the larger type.
431 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
432 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
434 // Calculate the overflow flag: sign extend the arithmetic result from
435 // the original type.
436 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
437 DAG.getValueType(OVT));
438 // Overflowed if and only if this is not equal to Res.
439 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
441 // Use the calculated overflow everywhere.
442 ReplaceValueWith(SDValue(N, 1), Ofl);
447 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
448 // Sign extend the input.
449 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
450 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
451 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
452 LHS.getValueType(), LHS, RHS);
455 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
456 SDValue LHS = GetPromotedInteger(N->getOperand(1));
457 SDValue RHS = GetPromotedInteger(N->getOperand(2));
458 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
459 LHS.getValueType(), N->getOperand(0),LHS,RHS);
462 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
463 SDValue LHS = GetPromotedInteger(N->getOperand(2));
464 SDValue RHS = GetPromotedInteger(N->getOperand(3));
465 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
466 LHS.getValueType(), N->getOperand(0),
467 N->getOperand(1), LHS, RHS, N->getOperand(4));
470 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
471 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
472 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
473 DebugLoc dl = N->getDebugLoc();
475 // Get the SETCC result using the canonical SETCC type.
476 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
477 N->getOperand(1), N->getOperand(2));
479 // Convert to the expected type.
480 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
481 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
482 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
485 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
486 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
487 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
488 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
491 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
492 SDValue Op = GetPromotedInteger(N->getOperand(0));
493 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
494 Op.getValueType(), Op, N->getOperand(1));
497 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
498 // The input may have strange things in the top bits of the registers, but
499 // these operations don't care. They may have weird bits going out, but
500 // that too is okay if they are integer operations.
501 SDValue LHS = GetPromotedInteger(N->getOperand(0));
502 SDValue RHS = GetPromotedInteger(N->getOperand(1));
503 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
504 LHS.getValueType(), LHS, RHS);
507 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
508 // The input value must be properly sign extended.
509 SDValue Res = SExtPromotedInteger(N->getOperand(0));
510 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
511 Res.getValueType(), Res, N->getOperand(1));
514 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
515 // The input value must be properly zero extended.
516 EVT VT = N->getValueType(0);
517 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
518 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
519 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
522 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
523 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
525 SDValue InOp = N->getOperand(0);
526 DebugLoc dl = N->getDebugLoc();
528 switch (getTypeAction(InOp.getValueType())) {
529 default: llvm_unreachable("Unknown type action!");
530 case TargetLowering::TypeLegal:
531 case TargetLowering::TypeExpandInteger:
534 case TargetLowering::TypePromoteInteger:
535 Res = GetPromotedInteger(InOp);
537 case TargetLowering::TypeSplitVector:
538 EVT InVT = InOp.getValueType();
539 assert(InVT.isVector() && "Cannot split scalar types");
540 unsigned NumElts = InVT.getVectorNumElements();
541 assert(NumElts == NVT.getVectorNumElements() &&
542 "Dst and Src must have the same number of elements");
543 EVT EltVT = InVT.getScalarType();
544 assert(isPowerOf2_32(NumElts) &&
545 "Promoted vector type must be a power of two");
547 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts/2);
548 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
551 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
552 DAG.getIntPtrConstant(0));
553 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
554 DAG.getIntPtrConstant(NumElts/2));
555 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
556 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
558 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
561 // Truncate to NVT instead of VT
562 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
565 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
567 return PromoteIntRes_Overflow(N);
569 // The operation overflowed iff the result in the larger type is not the
570 // zero extension of its truncation to the original type.
571 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
572 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
573 EVT OVT = N->getOperand(0).getValueType();
574 EVT NVT = LHS.getValueType();
575 DebugLoc dl = N->getDebugLoc();
577 // Do the arithmetic in the larger type.
578 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
579 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
581 // Calculate the overflow flag: zero extend the arithmetic result from
582 // the original type.
583 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
584 // Overflowed if and only if this is not equal to Res.
585 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
587 // Use the calculated overflow everywhere.
588 ReplaceValueWith(SDValue(N, 1), Ofl);
593 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
594 // Promote the overflow bit trivially.
596 return PromoteIntRes_Overflow(N);
598 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
599 DebugLoc DL = N->getDebugLoc();
600 EVT SmallVT = LHS.getValueType();
602 // To determine if the result overflowed in a larger type, we extend the
603 // input to the larger type, do the multiply, then check the high bits of
604 // the result to see if the overflow happened.
605 if (N->getOpcode() == ISD::SMULO) {
606 LHS = SExtPromotedInteger(LHS);
607 RHS = SExtPromotedInteger(RHS);
609 LHS = ZExtPromotedInteger(LHS);
610 RHS = ZExtPromotedInteger(RHS);
612 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
614 // Overflow occurred iff the high part of the result does not
615 // zero/sign-extend the low part.
617 if (N->getOpcode() == ISD::UMULO) {
618 // Unsigned overflow occurred iff the high part is non-zero.
619 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
620 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
621 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
622 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
624 // Signed overflow occurred iff the high part does not sign extend the low.
625 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
626 Mul, DAG.getValueType(SmallVT));
627 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
630 // Use the calculated overflow everywhere.
631 ReplaceValueWith(SDValue(N, 1), Overflow);
635 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
636 // Zero extend the input.
637 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
638 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
639 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
640 LHS.getValueType(), LHS, RHS);
643 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
644 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
645 N->getValueType(0)));
648 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
649 SDValue Chain = N->getOperand(0); // Get the chain.
650 SDValue Ptr = N->getOperand(1); // Get the pointer.
651 EVT VT = N->getValueType(0);
652 DebugLoc dl = N->getDebugLoc();
654 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
655 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
656 // The argument is passed as NumRegs registers of type RegVT.
658 SmallVector<SDValue, 8> Parts(NumRegs);
659 for (unsigned i = 0; i < NumRegs; ++i) {
660 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
661 N->getConstantOperandVal(3));
662 Chain = Parts[i].getValue(1);
665 // Handle endianness of the load.
666 if (TLI.isBigEndian())
667 std::reverse(Parts.begin(), Parts.end());
669 // Assemble the parts in the promoted type.
670 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
671 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
672 for (unsigned i = 1; i < NumRegs; ++i) {
673 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
674 // Shift it to the right position and "or" it in.
675 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
676 DAG.getConstant(i * RegVT.getSizeInBits(),
677 TLI.getPointerTy()));
678 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
681 // Modified the chain result - switch anything that used the old chain to
683 ReplaceValueWith(SDValue(N, 1), Chain);
688 //===----------------------------------------------------------------------===//
689 // Integer Operand Promotion
690 //===----------------------------------------------------------------------===//
692 /// PromoteIntegerOperand - This method is called when the specified operand of
693 /// the specified node is found to need promotion. At this point, all of the
694 /// result types of the node are known to be legal, but other operands of the
695 /// node may need promotion or expansion as well as the specified one.
696 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
697 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
698 SDValue Res = SDValue();
700 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
703 switch (N->getOpcode()) {
706 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
707 N->dump(&DAG); dbgs() << "\n";
709 llvm_unreachable("Do not know how to promote this operator's operand!");
711 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
712 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
713 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
714 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
715 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
716 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
717 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
718 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
719 case ISD::CONVERT_RNDSAT:
720 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
721 case ISD::INSERT_VECTOR_ELT:
722 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
723 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
724 case ISD::SCALAR_TO_VECTOR:
725 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
726 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
727 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
728 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
729 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
730 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
731 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
733 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
734 case ISD::FP16_TO_FP32:
735 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
736 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
742 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
745 // If the result is null, the sub-method took care of registering results etc.
746 if (!Res.getNode()) return false;
748 // If the result is N, the sub-method updated N in place. Tell the legalizer
750 if (Res.getNode() == N)
753 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
754 "Invalid operand expansion");
756 ReplaceValueWith(SDValue(N, 0), Res);
760 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
761 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
762 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
763 ISD::CondCode CCCode) {
764 // We have to insert explicit sign or zero extends. Note that we could
765 // insert sign extends for ALL conditions, but zero extend is cheaper on
766 // many machines (an AND instead of two shifts), so prefer it.
768 default: llvm_unreachable("Unknown integer comparison!");
775 // ALL of these operations will work if we either sign or zero extend
776 // the operands (including the unsigned comparisons!). Zero extend is
777 // usually a simpler/cheaper operation, so prefer it.
778 NewLHS = ZExtPromotedInteger(NewLHS);
779 NewRHS = ZExtPromotedInteger(NewRHS);
785 NewLHS = SExtPromotedInteger(NewLHS);
786 NewRHS = SExtPromotedInteger(NewRHS);
791 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
792 SDValue Op = GetPromotedInteger(N->getOperand(0));
793 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
796 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
797 // This should only occur in unusual situations like bitcasting to an
798 // x86_fp80, so just turn it into a store+load
799 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
802 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
803 assert(OpNo == 2 && "Don't know how to promote this operand!");
805 SDValue LHS = N->getOperand(2);
806 SDValue RHS = N->getOperand(3);
807 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
809 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
811 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
812 N->getOperand(1), LHS, RHS, N->getOperand(4)),
816 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
817 assert(OpNo == 1 && "only know how to promote condition");
819 // Promote all the way up to the canonical SetCC type.
820 EVT SVT = TLI.getSetCCResultType(MVT::Other);
821 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
823 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
824 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
825 N->getOperand(2)), 0);
828 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
829 // Since the result type is legal, the operands must promote to it.
830 EVT OVT = N->getOperand(0).getValueType();
831 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
832 SDValue Hi = GetPromotedInteger(N->getOperand(1));
833 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
834 DebugLoc dl = N->getDebugLoc();
836 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
837 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
838 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
841 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
842 // The vector type is legal but the element type is not. This implies
843 // that the vector is a power-of-two in length and that the element
844 // type does not have a strange size (eg: it is not i1).
845 EVT VecVT = N->getValueType(0);
846 unsigned NumElts = VecVT.getVectorNumElements();
847 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
849 // Promote the inserted value. The type does not need to match the
850 // vector element type. Check that any extra bits introduced will be
852 assert(N->getOperand(0).getValueType().getSizeInBits() >=
853 N->getValueType(0).getVectorElementType().getSizeInBits() &&
854 "Type of inserted value narrower than vector element type!");
856 SmallVector<SDValue, 16> NewOps;
857 for (unsigned i = 0; i < NumElts; ++i)
858 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
860 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
863 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
864 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
865 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
866 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
867 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
868 "can only promote integer arguments");
869 SDValue InOp = GetPromotedInteger(N->getOperand(0));
870 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
871 N->getOperand(1), N->getOperand(2),
872 N->getOperand(3), N->getOperand(4), CvtCode);
875 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
878 // Promote the inserted value. This is valid because the type does not
879 // have to match the vector element type.
881 // Check that any extra bits introduced will be truncated away.
882 assert(N->getOperand(1).getValueType().getSizeInBits() >=
883 N->getValueType(0).getVectorElementType().getSizeInBits() &&
884 "Type of inserted value narrower than vector element type!");
885 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
886 GetPromotedInteger(N->getOperand(1)),
891 assert(OpNo == 2 && "Different operand and result vector types?");
893 // Promote the index.
894 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
895 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
896 N->getOperand(1), Idx), 0);
899 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
901 DebugLoc dl = N->getDebugLoc();
902 NewOps[0] = N->getOperand(0);
903 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
904 SDValue Flag = GetPromotedInteger(N->getOperand(i));
905 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
907 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
910 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
911 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
912 // the operand in place.
913 return SDValue(DAG.UpdateNodeOperands(N,
914 GetPromotedInteger(N->getOperand(0))), 0);
917 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
918 assert(OpNo == 0 && "Only know how to promote condition");
920 // Promote all the way up to the canonical SetCC type.
921 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
922 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
924 return SDValue(DAG.UpdateNodeOperands(N, Cond,
925 N->getOperand(1), N->getOperand(2)), 0);
928 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
929 assert(OpNo == 0 && "Don't know how to promote this operand!");
931 SDValue LHS = N->getOperand(0);
932 SDValue RHS = N->getOperand(1);
933 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
935 // The CC (#4) and the possible return values (#2 and #3) have legal types.
936 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
937 N->getOperand(3), N->getOperand(4)), 0);
940 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
941 assert(OpNo == 0 && "Don't know how to promote this operand!");
943 SDValue LHS = N->getOperand(0);
944 SDValue RHS = N->getOperand(1);
945 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
947 // The CC (#2) is always legal.
948 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
951 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
952 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
953 ZExtPromotedInteger(N->getOperand(1))), 0);
956 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
957 SDValue Op = GetPromotedInteger(N->getOperand(0));
958 DebugLoc dl = N->getDebugLoc();
959 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
960 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
961 Op, DAG.getValueType(N->getOperand(0).getValueType()));
964 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
965 return SDValue(DAG.UpdateNodeOperands(N,
966 SExtPromotedInteger(N->getOperand(0))), 0);
969 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
970 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
971 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
972 unsigned Alignment = N->getAlignment();
973 bool isVolatile = N->isVolatile();
974 bool isNonTemporal = N->isNonTemporal();
975 DebugLoc dl = N->getDebugLoc();
977 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
979 // Truncate the value and store the result.
980 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
982 isVolatile, isNonTemporal, Alignment);
985 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
986 SDValue Op = GetPromotedInteger(N->getOperand(0));
987 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
990 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
991 return SDValue(DAG.UpdateNodeOperands(N,
992 ZExtPromotedInteger(N->getOperand(0))), 0);
995 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
996 DebugLoc dl = N->getDebugLoc();
997 SDValue Op = GetPromotedInteger(N->getOperand(0));
998 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
999 return DAG.getZeroExtendInReg(Op, dl,
1000 N->getOperand(0).getValueType().getScalarType());
1004 //===----------------------------------------------------------------------===//
1005 // Integer Result Expansion
1006 //===----------------------------------------------------------------------===//
1008 /// ExpandIntegerResult - This method is called when the specified result of the
1009 /// specified node is found to need expansion. At this point, the node may also
1010 /// have invalid operands or may have other results that need promotion, we just
1011 /// know that (at least) one result needs expansion.
1012 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1013 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1015 Lo = Hi = SDValue();
1017 // See if the target wants to custom expand this node.
1018 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1021 switch (N->getOpcode()) {
1024 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1025 N->dump(&DAG); dbgs() << "\n";
1027 llvm_unreachable("Do not know how to expand the result of this operator!");
1029 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
1030 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1031 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1032 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1034 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1035 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1036 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1037 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1038 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1040 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1041 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1042 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1043 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1044 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1045 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1046 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1047 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1048 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1049 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1050 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1051 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1052 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1053 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1054 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1055 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1056 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1057 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1058 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1059 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1061 case ISD::ATOMIC_LOAD_ADD:
1062 case ISD::ATOMIC_LOAD_SUB:
1063 case ISD::ATOMIC_LOAD_AND:
1064 case ISD::ATOMIC_LOAD_OR:
1065 case ISD::ATOMIC_LOAD_XOR:
1066 case ISD::ATOMIC_LOAD_NAND:
1067 case ISD::ATOMIC_LOAD_MIN:
1068 case ISD::ATOMIC_LOAD_MAX:
1069 case ISD::ATOMIC_LOAD_UMIN:
1070 case ISD::ATOMIC_LOAD_UMAX:
1071 case ISD::ATOMIC_SWAP: {
1072 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1073 SplitInteger(Tmp.first, Lo, Hi);
1074 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1080 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1083 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1086 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1089 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1093 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1096 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1098 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1100 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1103 // If Lo/Hi is null, the sub-method took care of registering results etc.
1105 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1108 /// Lower an atomic node to the appropriate builtin call.
1109 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1110 unsigned Opc = Node->getOpcode();
1111 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1116 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1118 case ISD::ATOMIC_SWAP:
1119 switch (VT.SimpleTy) {
1120 default: llvm_unreachable("Unexpected value type for atomic!");
1121 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1122 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1123 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1124 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1127 case ISD::ATOMIC_CMP_SWAP:
1128 switch (VT.SimpleTy) {
1129 default: llvm_unreachable("Unexpected value type for atomic!");
1130 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1131 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1132 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1133 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1136 case ISD::ATOMIC_LOAD_ADD:
1137 switch (VT.SimpleTy) {
1138 default: llvm_unreachable("Unexpected value type for atomic!");
1139 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1140 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1141 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1142 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1145 case ISD::ATOMIC_LOAD_SUB:
1146 switch (VT.SimpleTy) {
1147 default: llvm_unreachable("Unexpected value type for atomic!");
1148 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1149 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1150 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1151 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1154 case ISD::ATOMIC_LOAD_AND:
1155 switch (VT.SimpleTy) {
1156 default: llvm_unreachable("Unexpected value type for atomic!");
1157 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1158 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1159 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1160 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1163 case ISD::ATOMIC_LOAD_OR:
1164 switch (VT.SimpleTy) {
1165 default: llvm_unreachable("Unexpected value type for atomic!");
1166 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1167 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1168 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1169 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1172 case ISD::ATOMIC_LOAD_XOR:
1173 switch (VT.SimpleTy) {
1174 default: llvm_unreachable("Unexpected value type for atomic!");
1175 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1176 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1177 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1178 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1181 case ISD::ATOMIC_LOAD_NAND:
1182 switch (VT.SimpleTy) {
1183 default: llvm_unreachable("Unexpected value type for atomic!");
1184 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1185 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1186 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1187 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1192 return ExpandChainLibCall(LC, Node, false);
1195 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1196 /// and the shift amount is a constant 'Amt'. Expand the operation.
1197 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1198 SDValue &Lo, SDValue &Hi) {
1199 DebugLoc DL = N->getDebugLoc();
1200 // Expand the incoming operand to be shifted, so that we have its parts
1202 GetExpandedInteger(N->getOperand(0), InL, InH);
1204 EVT NVT = InL.getValueType();
1205 unsigned VTBits = N->getValueType(0).getSizeInBits();
1206 unsigned NVTBits = NVT.getSizeInBits();
1207 EVT ShTy = N->getOperand(1).getValueType();
1209 if (N->getOpcode() == ISD::SHL) {
1211 Lo = Hi = DAG.getConstant(0, NVT);
1212 } else if (Amt > NVTBits) {
1213 Lo = DAG.getConstant(0, NVT);
1214 Hi = DAG.getNode(ISD::SHL, DL,
1215 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1216 } else if (Amt == NVTBits) {
1217 Lo = DAG.getConstant(0, NVT);
1219 } else if (Amt == 1 &&
1220 TLI.isOperationLegalOrCustom(ISD::ADDC,
1221 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1222 // Emit this X << 1 as X+X.
1223 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1224 SDValue LoOps[2] = { InL, InL };
1225 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1226 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1227 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1229 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1230 Hi = DAG.getNode(ISD::OR, DL, NVT,
1231 DAG.getNode(ISD::SHL, DL, NVT, InH,
1232 DAG.getConstant(Amt, ShTy)),
1233 DAG.getNode(ISD::SRL, DL, NVT, InL,
1234 DAG.getConstant(NVTBits-Amt, ShTy)));
1239 if (N->getOpcode() == ISD::SRL) {
1241 Lo = DAG.getConstant(0, NVT);
1242 Hi = DAG.getConstant(0, NVT);
1243 } else if (Amt > NVTBits) {
1244 Lo = DAG.getNode(ISD::SRL, DL,
1245 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1246 Hi = DAG.getConstant(0, NVT);
1247 } else if (Amt == NVTBits) {
1249 Hi = DAG.getConstant(0, NVT);
1251 Lo = DAG.getNode(ISD::OR, DL, NVT,
1252 DAG.getNode(ISD::SRL, DL, NVT, InL,
1253 DAG.getConstant(Amt, ShTy)),
1254 DAG.getNode(ISD::SHL, DL, NVT, InH,
1255 DAG.getConstant(NVTBits-Amt, ShTy)));
1256 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1261 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1263 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1264 DAG.getConstant(NVTBits-1, ShTy));
1265 } else if (Amt > NVTBits) {
1266 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1267 DAG.getConstant(Amt-NVTBits, ShTy));
1268 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1269 DAG.getConstant(NVTBits-1, ShTy));
1270 } else if (Amt == NVTBits) {
1272 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1273 DAG.getConstant(NVTBits-1, ShTy));
1275 Lo = DAG.getNode(ISD::OR, DL, NVT,
1276 DAG.getNode(ISD::SRL, DL, NVT, InL,
1277 DAG.getConstant(Amt, ShTy)),
1278 DAG.getNode(ISD::SHL, DL, NVT, InH,
1279 DAG.getConstant(NVTBits-Amt, ShTy)));
1280 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1284 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1285 /// this shift based on knowledge of the high bit of the shift amount. If we
1286 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1288 bool DAGTypeLegalizer::
1289 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1290 SDValue Amt = N->getOperand(1);
1291 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1292 EVT ShTy = Amt.getValueType();
1293 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1294 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1295 assert(isPowerOf2_32(NVTBits) &&
1296 "Expanded integer type size not a power of two!");
1297 DebugLoc dl = N->getDebugLoc();
1299 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1300 APInt KnownZero, KnownOne;
1301 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1303 // If we don't know anything about the high bits, exit.
1304 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1307 // Get the incoming operand to be shifted.
1309 GetExpandedInteger(N->getOperand(0), InL, InH);
1311 // If we know that any of the high bits of the shift amount are one, then we
1312 // can do this as a couple of simple shifts.
1313 if (KnownOne.intersects(HighBitMask)) {
1314 // Mask out the high bit, which we know is set.
1315 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1316 DAG.getConstant(~HighBitMask, ShTy));
1318 switch (N->getOpcode()) {
1319 default: llvm_unreachable("Unknown shift");
1321 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1322 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1325 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1326 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1329 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1330 DAG.getConstant(NVTBits-1, ShTy));
1331 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1337 // FIXME: This code is broken for shifts with a zero amount!
1338 // If we know that all of the high bits of the shift amount are zero, then we
1339 // can do this as a couple of simple shifts.
1340 if ((KnownZero & HighBitMask) == HighBitMask) {
1342 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1343 DAG.getConstant(NVTBits, ShTy),
1346 switch (N->getOpcode()) {
1347 default: llvm_unreachable("Unknown shift");
1348 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1350 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1353 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1354 Hi = DAG.getNode(ISD::OR, NVT,
1355 DAG.getNode(Op1, NVT, InH, Amt),
1356 DAG.getNode(Op2, NVT, InL, Amt2));
1364 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1366 bool DAGTypeLegalizer::
1367 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1368 SDValue Amt = N->getOperand(1);
1369 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1370 EVT ShTy = Amt.getValueType();
1371 unsigned NVTBits = NVT.getSizeInBits();
1372 assert(isPowerOf2_32(NVTBits) &&
1373 "Expanded integer type size not a power of two!");
1374 DebugLoc dl = N->getDebugLoc();
1376 // Get the incoming operand to be shifted.
1378 GetExpandedInteger(N->getOperand(0), InL, InH);
1380 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1381 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1382 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1383 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1384 Amt, NVBitsNode, ISD::SETULT);
1386 SDValue LoS, HiS, LoL, HiL;
1387 switch (N->getOpcode()) {
1388 default: llvm_unreachable("Unknown shift");
1390 // Short: ShAmt < NVTBits
1391 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1392 HiS = DAG.getNode(ISD::OR, dl, NVT,
1393 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1394 // FIXME: If Amt is zero, the following shift generates an undefined result
1395 // on some architectures.
1396 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1398 // Long: ShAmt >= NVTBits
1399 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1400 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1402 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1403 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1406 // Short: ShAmt < NVTBits
1407 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1408 LoS = DAG.getNode(ISD::OR, dl, NVT,
1409 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1410 // FIXME: If Amt is zero, the following shift generates an undefined result
1411 // on some architectures.
1412 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1414 // Long: ShAmt >= NVTBits
1415 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1416 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1418 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1419 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1422 // Short: ShAmt < NVTBits
1423 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1424 LoS = DAG.getNode(ISD::OR, dl, NVT,
1425 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1426 // FIXME: If Amt is zero, the following shift generates an undefined result
1427 // on some architectures.
1428 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1430 // Long: ShAmt >= NVTBits
1431 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1432 DAG.getConstant(NVTBits-1, ShTy));
1433 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1435 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1436 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1443 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1444 SDValue &Lo, SDValue &Hi) {
1445 DebugLoc dl = N->getDebugLoc();
1446 // Expand the subcomponents.
1447 SDValue LHSL, LHSH, RHSL, RHSH;
1448 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1449 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1451 EVT NVT = LHSL.getValueType();
1452 SDValue LoOps[2] = { LHSL, RHSL };
1453 SDValue HiOps[3] = { LHSH, RHSH };
1455 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1456 // them. TODO: Teach operation legalization how to expand unsupported
1457 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1458 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1459 // generate a value of this type in the expanded code sequence.
1461 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1462 ISD::ADDC : ISD::SUBC,
1463 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1466 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1467 if (N->getOpcode() == ISD::ADD) {
1468 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1469 HiOps[2] = Lo.getValue(1);
1470 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1472 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1473 HiOps[2] = Lo.getValue(1);
1474 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1479 if (N->getOpcode() == ISD::ADD) {
1480 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1481 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1482 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1484 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1485 DAG.getConstant(1, NVT),
1486 DAG.getConstant(0, NVT));
1487 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1489 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1490 DAG.getConstant(1, NVT), Carry1);
1491 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1493 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1494 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1496 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1497 LoOps[0], LoOps[1], ISD::SETULT);
1498 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1499 DAG.getConstant(1, NVT),
1500 DAG.getConstant(0, NVT));
1501 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1505 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1506 SDValue &Lo, SDValue &Hi) {
1507 // Expand the subcomponents.
1508 SDValue LHSL, LHSH, RHSL, RHSH;
1509 DebugLoc dl = N->getDebugLoc();
1510 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1511 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1512 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1513 SDValue LoOps[2] = { LHSL, RHSL };
1514 SDValue HiOps[3] = { LHSH, RHSH };
1516 if (N->getOpcode() == ISD::ADDC) {
1517 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1518 HiOps[2] = Lo.getValue(1);
1519 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1521 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1522 HiOps[2] = Lo.getValue(1);
1523 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1526 // Legalized the flag result - switch anything that used the old flag to
1528 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1531 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1532 SDValue &Lo, SDValue &Hi) {
1533 // Expand the subcomponents.
1534 SDValue LHSL, LHSH, RHSL, RHSH;
1535 DebugLoc dl = N->getDebugLoc();
1536 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1537 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1538 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1539 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1540 SDValue HiOps[3] = { LHSH, RHSH };
1542 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1543 HiOps[2] = Lo.getValue(1);
1544 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1546 // Legalized the flag result - switch anything that used the old flag to
1548 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1551 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1552 SDValue &Lo, SDValue &Hi) {
1553 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1554 DebugLoc dl = N->getDebugLoc();
1555 SDValue Op = N->getOperand(0);
1556 if (Op.getValueType().bitsLE(NVT)) {
1557 // The low part is any extension of the input (which degenerates to a copy).
1558 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1559 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1561 // For example, extension of an i48 to an i64. The operand type necessarily
1562 // promotes to the result type, so will end up being expanded too.
1563 assert(getTypeAction(Op.getValueType()) ==
1564 TargetLowering::TypePromoteInteger &&
1565 "Only know how to promote this result!");
1566 SDValue Res = GetPromotedInteger(Op);
1567 assert(Res.getValueType() == N->getValueType(0) &&
1568 "Operand over promoted?");
1569 // Split the promoted operand. This will simplify when it is expanded.
1570 SplitInteger(Res, Lo, Hi);
1574 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1575 SDValue &Lo, SDValue &Hi) {
1576 DebugLoc dl = N->getDebugLoc();
1577 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1578 EVT NVT = Lo.getValueType();
1579 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1580 unsigned NVTBits = NVT.getSizeInBits();
1581 unsigned EVTBits = EVT.getSizeInBits();
1583 if (NVTBits < EVTBits) {
1584 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1585 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1586 EVTBits - NVTBits)));
1588 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1589 // The high part replicates the sign bit of Lo, make it explicit.
1590 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1591 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1595 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1596 SDValue &Lo, SDValue &Hi) {
1597 DebugLoc dl = N->getDebugLoc();
1598 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1599 EVT NVT = Lo.getValueType();
1600 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1601 unsigned NVTBits = NVT.getSizeInBits();
1602 unsigned EVTBits = EVT.getSizeInBits();
1604 if (NVTBits < EVTBits) {
1605 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1606 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1607 EVTBits - NVTBits)));
1609 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1610 // The high part must be zero, make it explicit.
1611 Hi = DAG.getConstant(0, NVT);
1615 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1616 SDValue &Lo, SDValue &Hi) {
1617 DebugLoc dl = N->getDebugLoc();
1618 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1619 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1620 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1623 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1624 SDValue &Lo, SDValue &Hi) {
1625 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1626 unsigned NBitWidth = NVT.getSizeInBits();
1627 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1628 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1629 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1632 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1633 SDValue &Lo, SDValue &Hi) {
1634 DebugLoc dl = N->getDebugLoc();
1635 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1636 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1637 EVT NVT = Lo.getValueType();
1639 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1640 DAG.getConstant(0, NVT), ISD::SETNE);
1642 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1643 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1645 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1646 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1647 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1648 Hi = DAG.getConstant(0, NVT);
1651 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1652 SDValue &Lo, SDValue &Hi) {
1653 DebugLoc dl = N->getDebugLoc();
1654 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1655 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1656 EVT NVT = Lo.getValueType();
1657 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1658 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1659 Hi = DAG.getConstant(0, NVT);
1662 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1663 SDValue &Lo, SDValue &Hi) {
1664 DebugLoc dl = N->getDebugLoc();
1665 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1666 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1667 EVT NVT = Lo.getValueType();
1669 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1670 DAG.getConstant(0, NVT), ISD::SETNE);
1672 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1673 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1675 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1676 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1677 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1678 Hi = DAG.getConstant(0, NVT);
1681 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1683 DebugLoc dl = N->getDebugLoc();
1684 EVT VT = N->getValueType(0);
1685 SDValue Op = N->getOperand(0);
1686 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1687 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1688 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1691 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1693 DebugLoc dl = N->getDebugLoc();
1694 EVT VT = N->getValueType(0);
1695 SDValue Op = N->getOperand(0);
1696 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1697 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1698 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1701 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1702 SDValue &Lo, SDValue &Hi) {
1703 if (ISD::isNormalLoad(N)) {
1704 ExpandRes_NormalLoad(N, Lo, Hi);
1708 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1710 EVT VT = N->getValueType(0);
1711 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1712 SDValue Ch = N->getChain();
1713 SDValue Ptr = N->getBasePtr();
1714 ISD::LoadExtType ExtType = N->getExtensionType();
1715 unsigned Alignment = N->getAlignment();
1716 bool isVolatile = N->isVolatile();
1717 bool isNonTemporal = N->isNonTemporal();
1718 DebugLoc dl = N->getDebugLoc();
1720 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1722 if (N->getMemoryVT().bitsLE(NVT)) {
1723 EVT MemVT = N->getMemoryVT();
1725 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1726 MemVT, isVolatile, isNonTemporal, Alignment);
1728 // Remember the chain.
1729 Ch = Lo.getValue(1);
1731 if (ExtType == ISD::SEXTLOAD) {
1732 // The high part is obtained by SRA'ing all but one of the bits of the
1734 unsigned LoSize = Lo.getValueType().getSizeInBits();
1735 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1736 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1737 } else if (ExtType == ISD::ZEXTLOAD) {
1738 // The high part is just a zero.
1739 Hi = DAG.getConstant(0, NVT);
1741 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1742 // The high part is undefined.
1743 Hi = DAG.getUNDEF(NVT);
1745 } else if (TLI.isLittleEndian()) {
1746 // Little-endian - low bits are at low addresses.
1747 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1748 isVolatile, isNonTemporal, Alignment);
1750 unsigned ExcessBits =
1751 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1752 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1754 // Increment the pointer to the other half.
1755 unsigned IncrementSize = NVT.getSizeInBits()/8;
1756 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1757 DAG.getIntPtrConstant(IncrementSize));
1758 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1759 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1760 isVolatile, isNonTemporal,
1761 MinAlign(Alignment, IncrementSize));
1763 // Build a factor node to remember that this load is independent of the
1765 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1768 // Big-endian - high bits are at low addresses. Favor aligned loads at
1769 // the cost of some bit-fiddling.
1770 EVT MemVT = N->getMemoryVT();
1771 unsigned EBytes = MemVT.getStoreSize();
1772 unsigned IncrementSize = NVT.getSizeInBits()/8;
1773 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1775 // Load both the high bits and maybe some of the low bits.
1776 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1777 EVT::getIntegerVT(*DAG.getContext(),
1778 MemVT.getSizeInBits() - ExcessBits),
1779 isVolatile, isNonTemporal, Alignment);
1781 // Increment the pointer to the other half.
1782 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1783 DAG.getIntPtrConstant(IncrementSize));
1784 // Load the rest of the low bits.
1785 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1786 N->getPointerInfo().getWithOffset(IncrementSize),
1787 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1788 isVolatile, isNonTemporal,
1789 MinAlign(Alignment, IncrementSize));
1791 // Build a factor node to remember that this load is independent of the
1793 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1796 if (ExcessBits < NVT.getSizeInBits()) {
1797 // Transfer low bits from the bottom of Hi to the top of Lo.
1798 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1799 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1800 DAG.getConstant(ExcessBits,
1801 TLI.getPointerTy())));
1802 // Move high bits to the right position in Hi.
1803 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1805 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1806 TLI.getPointerTy()));
1810 // Legalized the chain result - switch anything that used the old chain to
1812 ReplaceValueWith(SDValue(N, 1), Ch);
1815 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1816 SDValue &Lo, SDValue &Hi) {
1817 DebugLoc dl = N->getDebugLoc();
1818 SDValue LL, LH, RL, RH;
1819 GetExpandedInteger(N->getOperand(0), LL, LH);
1820 GetExpandedInteger(N->getOperand(1), RL, RH);
1821 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1822 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1825 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1826 SDValue &Lo, SDValue &Hi) {
1827 EVT VT = N->getValueType(0);
1828 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1829 DebugLoc dl = N->getDebugLoc();
1831 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1832 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1833 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1834 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1835 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1836 SDValue LL, LH, RL, RH;
1837 GetExpandedInteger(N->getOperand(0), LL, LH);
1838 GetExpandedInteger(N->getOperand(1), RL, RH);
1839 unsigned OuterBitSize = VT.getSizeInBits();
1840 unsigned InnerBitSize = NVT.getSizeInBits();
1841 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1842 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1844 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1845 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1846 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1847 // The inputs are both zero-extended.
1849 // We can emit a umul_lohi.
1850 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1851 Hi = SDValue(Lo.getNode(), 1);
1855 // We can emit a mulhu+mul.
1856 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1857 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1861 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1862 // The input values are both sign-extended.
1864 // We can emit a smul_lohi.
1865 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1866 Hi = SDValue(Lo.getNode(), 1);
1870 // We can emit a mulhs+mul.
1871 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1872 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1877 // Lo,Hi = umul LHS, RHS.
1878 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1879 DAG.getVTList(NVT, NVT), LL, RL);
1881 Hi = UMulLOHI.getValue(1);
1882 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1883 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1884 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1885 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1889 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1890 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1891 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1892 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1893 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1894 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1899 // If nothing else, we can make a libcall.
1900 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1902 LC = RTLIB::MUL_I16;
1903 else if (VT == MVT::i32)
1904 LC = RTLIB::MUL_I32;
1905 else if (VT == MVT::i64)
1906 LC = RTLIB::MUL_I64;
1907 else if (VT == MVT::i128)
1908 LC = RTLIB::MUL_I128;
1909 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1911 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1912 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1915 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1916 SDValue &Lo, SDValue &Hi) {
1917 SDValue LHS = Node->getOperand(0);
1918 SDValue RHS = Node->getOperand(1);
1919 DebugLoc dl = Node->getDebugLoc();
1921 // Expand the result by simply replacing it with the equivalent
1922 // non-overflow-checking operation.
1923 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1924 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1926 SplitInteger(Sum, Lo, Hi);
1928 // Compute the overflow.
1930 // LHSSign -> LHS >= 0
1931 // RHSSign -> RHS >= 0
1932 // SumSign -> Sum >= 0
1935 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
1937 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
1939 EVT OType = Node->getValueType(1);
1940 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
1942 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
1943 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
1944 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
1945 Node->getOpcode() == ISD::SADDO ?
1946 ISD::SETEQ : ISD::SETNE);
1948 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
1949 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
1951 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
1953 // Use the calculated overflow everywhere.
1954 ReplaceValueWith(SDValue(Node, 1), Cmp);
1957 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1958 SDValue &Lo, SDValue &Hi) {
1959 EVT VT = N->getValueType(0);
1960 DebugLoc dl = N->getDebugLoc();
1962 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1964 LC = RTLIB::SDIV_I16;
1965 else if (VT == MVT::i32)
1966 LC = RTLIB::SDIV_I32;
1967 else if (VT == MVT::i64)
1968 LC = RTLIB::SDIV_I64;
1969 else if (VT == MVT::i128)
1970 LC = RTLIB::SDIV_I128;
1971 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1973 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1974 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1977 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1978 SDValue &Lo, SDValue &Hi) {
1979 EVT VT = N->getValueType(0);
1980 DebugLoc dl = N->getDebugLoc();
1982 // If we can emit an efficient shift operation, do so now. Check to see if
1983 // the RHS is a constant.
1984 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1985 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1987 // If we can determine that the high bit of the shift is zero or one, even if
1988 // the low bits are variable, emit this shift in an optimized form.
1989 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1992 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1994 if (N->getOpcode() == ISD::SHL) {
1995 PartsOpc = ISD::SHL_PARTS;
1996 } else if (N->getOpcode() == ISD::SRL) {
1997 PartsOpc = ISD::SRL_PARTS;
1999 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2000 PartsOpc = ISD::SRA_PARTS;
2003 // Next check to see if the target supports this SHL_PARTS operation or if it
2004 // will custom expand it.
2005 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2006 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2007 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2008 Action == TargetLowering::Custom) {
2009 // Expand the subcomponents.
2011 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2013 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
2014 EVT VT = LHSL.getValueType();
2015 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
2016 Hi = Lo.getValue(1);
2020 // Otherwise, emit a libcall.
2021 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2023 if (N->getOpcode() == ISD::SHL) {
2024 isSigned = false; /*sign irrelevant*/
2026 LC = RTLIB::SHL_I16;
2027 else if (VT == MVT::i32)
2028 LC = RTLIB::SHL_I32;
2029 else if (VT == MVT::i64)
2030 LC = RTLIB::SHL_I64;
2031 else if (VT == MVT::i128)
2032 LC = RTLIB::SHL_I128;
2033 } else if (N->getOpcode() == ISD::SRL) {
2036 LC = RTLIB::SRL_I16;
2037 else if (VT == MVT::i32)
2038 LC = RTLIB::SRL_I32;
2039 else if (VT == MVT::i64)
2040 LC = RTLIB::SRL_I64;
2041 else if (VT == MVT::i128)
2042 LC = RTLIB::SRL_I128;
2044 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2047 LC = RTLIB::SRA_I16;
2048 else if (VT == MVT::i32)
2049 LC = RTLIB::SRA_I32;
2050 else if (VT == MVT::i64)
2051 LC = RTLIB::SRA_I64;
2052 else if (VT == MVT::i128)
2053 LC = RTLIB::SRA_I128;
2056 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2057 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2058 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
2062 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2063 llvm_unreachable("Unsupported shift!");
2066 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2067 SDValue &Lo, SDValue &Hi) {
2068 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2069 DebugLoc dl = N->getDebugLoc();
2070 SDValue Op = N->getOperand(0);
2071 if (Op.getValueType().bitsLE(NVT)) {
2072 // The low part is sign extension of the input (degenerates to a copy).
2073 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2074 // The high part is obtained by SRA'ing all but one of the bits of low part.
2075 unsigned LoSize = NVT.getSizeInBits();
2076 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2077 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2079 // For example, extension of an i48 to an i64. The operand type necessarily
2080 // promotes to the result type, so will end up being expanded too.
2081 assert(getTypeAction(Op.getValueType()) ==
2082 TargetLowering::TypePromoteInteger &&
2083 "Only know how to promote this result!");
2084 SDValue Res = GetPromotedInteger(Op);
2085 assert(Res.getValueType() == N->getValueType(0) &&
2086 "Operand over promoted?");
2087 // Split the promoted operand. This will simplify when it is expanded.
2088 SplitInteger(Res, Lo, Hi);
2089 unsigned ExcessBits =
2090 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2091 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2092 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2097 void DAGTypeLegalizer::
2098 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2099 DebugLoc dl = N->getDebugLoc();
2100 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2101 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2103 if (EVT.bitsLE(Lo.getValueType())) {
2104 // sext_inreg the low part if needed.
2105 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2108 // The high part gets the sign extension from the lo-part. This handles
2109 // things like sextinreg V:i64 from i8.
2110 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2111 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2112 TLI.getPointerTy()));
2114 // For example, extension of an i48 to an i64. Leave the low part alone,
2115 // sext_inreg the high part.
2116 unsigned ExcessBits =
2117 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2118 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2119 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2124 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2125 SDValue &Lo, SDValue &Hi) {
2126 EVT VT = N->getValueType(0);
2127 DebugLoc dl = N->getDebugLoc();
2129 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2131 LC = RTLIB::SREM_I16;
2132 else if (VT == MVT::i32)
2133 LC = RTLIB::SREM_I32;
2134 else if (VT == MVT::i64)
2135 LC = RTLIB::SREM_I64;
2136 else if (VT == MVT::i128)
2137 LC = RTLIB::SREM_I128;
2138 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2140 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2141 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2144 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2145 SDValue &Lo, SDValue &Hi) {
2146 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2147 DebugLoc dl = N->getDebugLoc();
2148 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2149 Hi = DAG.getNode(ISD::SRL, dl,
2150 N->getOperand(0).getValueType(), N->getOperand(0),
2151 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2152 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2155 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2156 SDValue &Lo, SDValue &Hi) {
2157 SDValue LHS = N->getOperand(0);
2158 SDValue RHS = N->getOperand(1);
2159 DebugLoc dl = N->getDebugLoc();
2161 // Expand the result by simply replacing it with the equivalent
2162 // non-overflow-checking operation.
2163 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2164 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2166 SplitInteger(Sum, Lo, Hi);
2168 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2169 // overflows iff a - b > a.
2170 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2171 N->getOpcode () == ISD::UADDO ?
2172 ISD::SETULT : ISD::SETUGT);
2174 // Use the calculated overflow everywhere.
2175 ReplaceValueWith(SDValue(N, 1), Ofl);
2178 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2179 SDValue &Lo, SDValue &Hi) {
2180 EVT VT = N->getValueType(0);
2181 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2182 EVT PtrVT = TLI.getPointerTy();
2183 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2184 DebugLoc dl = N->getDebugLoc();
2186 // A divide for UMULO should be faster than a function call.
2187 if (N->getOpcode() == ISD::UMULO) {
2188 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2189 DebugLoc DL = N->getDebugLoc();
2191 SDValue MUL = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
2192 SplitInteger(MUL, Lo, Hi);
2194 // A divide for UMULO will be faster than a function call. Select to
2195 // make sure we aren't using 0.
2196 SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2197 RHS, DAG.getConstant(0, VT), ISD::SETNE);
2198 SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
2199 DAG.getConstant(1, VT), RHS);
2200 SDValue DIV = DAG.getNode(ISD::UDIV, DL, LHS.getValueType(), MUL, NotZero);
2202 Overflow = DAG.getSetCC(DL, N->getValueType(1), DIV, LHS, ISD::SETNE);
2203 ReplaceValueWith(SDValue(N, 1), Overflow);
2207 // Replace this with a libcall that will check overflow.
2208 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2210 LC = RTLIB::MULO_I32;
2211 else if (VT == MVT::i64)
2212 LC = RTLIB::MULO_I64;
2213 else if (VT == MVT::i128)
2214 LC = RTLIB::MULO_I128;
2215 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2217 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2218 // Temporary for the overflow value, default it to zero.
2219 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2220 DAG.getConstant(0, PtrVT), Temp,
2221 MachinePointerInfo(), false, false, 0);
2223 TargetLowering::ArgListTy Args;
2224 TargetLowering::ArgListEntry Entry;
2225 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2226 EVT ArgVT = N->getOperand(i).getValueType();
2227 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2228 Entry.Node = N->getOperand(i);
2230 Entry.isSExt = true;
2231 Entry.isZExt = false;
2232 Args.push_back(Entry);
2235 // Also pass the address of the overflow check.
2237 Entry.Ty = PtrTy->getPointerTo();
2238 Entry.isSExt = true;
2239 Entry.isZExt = false;
2240 Args.push_back(Entry);
2242 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2243 std::pair<SDValue, SDValue> CallInfo =
2244 TLI.LowerCallTo(Chain, RetTy, true, false, false, false,
2245 0, TLI.getLibcallCallingConv(LC), false,
2246 true, Func, Args, DAG, dl);
2248 SplitInteger(CallInfo.first, Lo, Hi);
2249 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2250 MachinePointerInfo(), false, false, 0);
2251 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2252 DAG.getConstant(0, PtrVT),
2254 // Use the overflow from the libcall everywhere.
2255 ReplaceValueWith(SDValue(N, 1), Ofl);
2258 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2259 SDValue &Lo, SDValue &Hi) {
2260 EVT VT = N->getValueType(0);
2261 DebugLoc dl = N->getDebugLoc();
2263 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2265 LC = RTLIB::UDIV_I16;
2266 else if (VT == MVT::i32)
2267 LC = RTLIB::UDIV_I32;
2268 else if (VT == MVT::i64)
2269 LC = RTLIB::UDIV_I64;
2270 else if (VT == MVT::i128)
2271 LC = RTLIB::UDIV_I128;
2272 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2274 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2275 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2278 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2279 SDValue &Lo, SDValue &Hi) {
2280 EVT VT = N->getValueType(0);
2281 DebugLoc dl = N->getDebugLoc();
2283 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2285 LC = RTLIB::UREM_I16;
2286 else if (VT == MVT::i32)
2287 LC = RTLIB::UREM_I32;
2288 else if (VT == MVT::i64)
2289 LC = RTLIB::UREM_I64;
2290 else if (VT == MVT::i128)
2291 LC = RTLIB::UREM_I128;
2292 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2294 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2295 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2298 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2299 SDValue &Lo, SDValue &Hi) {
2300 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2301 DebugLoc dl = N->getDebugLoc();
2302 SDValue Op = N->getOperand(0);
2303 if (Op.getValueType().bitsLE(NVT)) {
2304 // The low part is zero extension of the input (degenerates to a copy).
2305 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2306 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2308 // For example, extension of an i48 to an i64. The operand type necessarily
2309 // promotes to the result type, so will end up being expanded too.
2310 assert(getTypeAction(Op.getValueType()) ==
2311 TargetLowering::TypePromoteInteger &&
2312 "Only know how to promote this result!");
2313 SDValue Res = GetPromotedInteger(Op);
2314 assert(Res.getValueType() == N->getValueType(0) &&
2315 "Operand over promoted?");
2316 // Split the promoted operand. This will simplify when it is expanded.
2317 SplitInteger(Res, Lo, Hi);
2318 unsigned ExcessBits =
2319 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2320 Hi = DAG.getZeroExtendInReg(Hi, dl,
2321 EVT::getIntegerVT(*DAG.getContext(),
2327 //===----------------------------------------------------------------------===//
2328 // Integer Operand Expansion
2329 //===----------------------------------------------------------------------===//
2331 /// ExpandIntegerOperand - This method is called when the specified operand of
2332 /// the specified node is found to need expansion. At this point, all of the
2333 /// result types of the node are known to be legal, but other operands of the
2334 /// node may need promotion or expansion as well as the specified one.
2335 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2336 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2337 SDValue Res = SDValue();
2339 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2342 switch (N->getOpcode()) {
2345 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2346 N->dump(&DAG); dbgs() << "\n";
2348 llvm_unreachable("Do not know how to expand this operator's operand!");
2350 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2351 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2352 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2353 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2354 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2355 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2356 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2357 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2358 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2359 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2360 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2361 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2367 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2368 case ISD::RETURNADDR:
2369 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2372 // If the result is null, the sub-method took care of registering results etc.
2373 if (!Res.getNode()) return false;
2375 // If the result is N, the sub-method updated N in place. Tell the legalizer
2377 if (Res.getNode() == N)
2380 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2381 "Invalid operand expansion");
2383 ReplaceValueWith(SDValue(N, 0), Res);
2387 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2388 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2389 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2391 ISD::CondCode &CCCode,
2393 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2394 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2395 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2397 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2398 if (RHSLo == RHSHi) {
2399 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2400 if (RHSCST->isAllOnesValue()) {
2401 // Equality comparison to -1.
2402 NewLHS = DAG.getNode(ISD::AND, dl,
2403 LHSLo.getValueType(), LHSLo, LHSHi);
2410 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2411 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2412 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2413 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2417 // If this is a comparison of the sign bit, just look at the top part.
2419 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2420 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2421 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2427 // FIXME: This generated code sucks.
2428 ISD::CondCode LowCC;
2430 default: llvm_unreachable("Unknown integer setcc!");
2432 case ISD::SETULT: LowCC = ISD::SETULT; break;
2434 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2436 case ISD::SETULE: LowCC = ISD::SETULE; break;
2438 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2441 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2442 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2443 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2445 // NOTE: on targets without efficient SELECT of bools, we can always use
2446 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2447 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2449 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2450 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2451 if (!Tmp1.getNode())
2452 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2453 LHSLo, RHSLo, LowCC);
2454 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2455 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2456 if (!Tmp2.getNode())
2457 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2458 TLI.getSetCCResultType(LHSHi.getValueType()),
2459 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2461 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2462 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2463 if ((Tmp1C && Tmp1C->isNullValue()) ||
2464 (Tmp2C && Tmp2C->isNullValue() &&
2465 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2466 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2467 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2468 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2469 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2470 // low part is known false, returns high part.
2471 // For LE / GE, if high part is known false, ignore the low part.
2472 // For LT / GT, if high part is known true, ignore the low part.
2478 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2479 LHSHi, RHSHi, ISD::SETEQ, false,
2480 DagCombineInfo, dl);
2481 if (!NewLHS.getNode())
2482 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2483 LHSHi, RHSHi, ISD::SETEQ);
2484 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2485 NewLHS, Tmp1, Tmp2);
2489 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2490 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2491 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2492 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2494 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2495 // against zero to select between true and false values.
2496 if (NewRHS.getNode() == 0) {
2497 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2498 CCCode = ISD::SETNE;
2501 // Update N to have the operands specified.
2502 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2503 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2504 N->getOperand(4)), 0);
2507 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2508 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2509 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2510 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2512 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2513 // against zero to select between true and false values.
2514 if (NewRHS.getNode() == 0) {
2515 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2516 CCCode = ISD::SETNE;
2519 // Update N to have the operands specified.
2520 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2521 N->getOperand(2), N->getOperand(3),
2522 DAG.getCondCode(CCCode)), 0);
2525 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2526 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2527 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2528 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2530 // If ExpandSetCCOperands returned a scalar, use it.
2531 if (NewRHS.getNode() == 0) {
2532 assert(NewLHS.getValueType() == N->getValueType(0) &&
2533 "Unexpected setcc expansion!");
2537 // Otherwise, update N to have the operands specified.
2538 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2539 DAG.getCondCode(CCCode)), 0);
2542 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2543 // The value being shifted is legal, but the shift amount is too big.
2544 // It follows that either the result of the shift is undefined, or the
2545 // upper half of the shift amount is zero. Just use the lower half.
2547 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2548 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2551 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2552 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2553 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2554 // constant to valid type.
2556 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2557 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2560 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2561 SDValue Op = N->getOperand(0);
2562 EVT DstVT = N->getValueType(0);
2563 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2564 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2565 "Don't know how to expand this SINT_TO_FP!");
2566 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2569 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2570 if (ISD::isNormalStore(N))
2571 return ExpandOp_NormalStore(N, OpNo);
2573 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2574 assert(OpNo == 1 && "Can only expand the stored value so far");
2576 EVT VT = N->getOperand(1).getValueType();
2577 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2578 SDValue Ch = N->getChain();
2579 SDValue Ptr = N->getBasePtr();
2580 unsigned Alignment = N->getAlignment();
2581 bool isVolatile = N->isVolatile();
2582 bool isNonTemporal = N->isNonTemporal();
2583 DebugLoc dl = N->getDebugLoc();
2586 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2588 if (N->getMemoryVT().bitsLE(NVT)) {
2589 GetExpandedInteger(N->getValue(), Lo, Hi);
2590 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2591 N->getMemoryVT(), isVolatile, isNonTemporal,
2595 if (TLI.isLittleEndian()) {
2596 // Little-endian - low bits are at low addresses.
2597 GetExpandedInteger(N->getValue(), Lo, Hi);
2599 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2600 isVolatile, isNonTemporal, Alignment);
2602 unsigned ExcessBits =
2603 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2604 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2606 // Increment the pointer to the other half.
2607 unsigned IncrementSize = NVT.getSizeInBits()/8;
2608 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2609 DAG.getIntPtrConstant(IncrementSize));
2610 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2611 N->getPointerInfo().getWithOffset(IncrementSize),
2612 NEVT, isVolatile, isNonTemporal,
2613 MinAlign(Alignment, IncrementSize));
2614 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2617 // Big-endian - high bits are at low addresses. Favor aligned stores at
2618 // the cost of some bit-fiddling.
2619 GetExpandedInteger(N->getValue(), Lo, Hi);
2621 EVT ExtVT = N->getMemoryVT();
2622 unsigned EBytes = ExtVT.getStoreSize();
2623 unsigned IncrementSize = NVT.getSizeInBits()/8;
2624 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2625 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2626 ExtVT.getSizeInBits() - ExcessBits);
2628 if (ExcessBits < NVT.getSizeInBits()) {
2629 // Transfer high bits from the top of Lo to the bottom of Hi.
2630 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2631 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2632 TLI.getPointerTy()));
2633 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2634 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2635 DAG.getConstant(ExcessBits,
2636 TLI.getPointerTy())));
2639 // Store both the high bits and maybe some of the low bits.
2640 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2641 HiVT, isVolatile, isNonTemporal, Alignment);
2643 // Increment the pointer to the other half.
2644 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2645 DAG.getIntPtrConstant(IncrementSize));
2646 // Store the lowest ExcessBits bits in the second half.
2647 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2648 N->getPointerInfo().getWithOffset(IncrementSize),
2649 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2650 isVolatile, isNonTemporal,
2651 MinAlign(Alignment, IncrementSize));
2652 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2655 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2657 GetExpandedInteger(N->getOperand(0), InL, InH);
2658 // Just truncate the low part of the source.
2659 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2662 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2663 switch (VT.getSimpleVT().SimpleTy) {
2664 default: llvm_unreachable("Unknown FP format");
2665 case MVT::f32: return &APFloat::IEEEsingle;
2666 case MVT::f64: return &APFloat::IEEEdouble;
2667 case MVT::f80: return &APFloat::x87DoubleExtended;
2668 case MVT::f128: return &APFloat::IEEEquad;
2669 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2673 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2674 SDValue Op = N->getOperand(0);
2675 EVT SrcVT = Op.getValueType();
2676 EVT DstVT = N->getValueType(0);
2677 DebugLoc dl = N->getDebugLoc();
2679 // The following optimization is valid only if every value in SrcVT (when
2680 // treated as signed) is representable in DstVT. Check that the mantissa
2681 // size of DstVT is >= than the number of bits in SrcVT -1.
2682 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2683 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2684 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2685 // Do a signed conversion then adjust the result.
2686 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2687 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2689 // The result of the signed conversion needs adjusting if the 'sign bit' of
2690 // the incoming integer was set. To handle this, we dynamically test to see
2691 // if it is set, and, if so, add a fudge factor.
2693 const uint64_t F32TwoE32 = 0x4F800000ULL;
2694 const uint64_t F32TwoE64 = 0x5F800000ULL;
2695 const uint64_t F32TwoE128 = 0x7F800000ULL;
2698 if (SrcVT == MVT::i32)
2699 FF = APInt(32, F32TwoE32);
2700 else if (SrcVT == MVT::i64)
2701 FF = APInt(32, F32TwoE64);
2702 else if (SrcVT == MVT::i128)
2703 FF = APInt(32, F32TwoE128);
2705 assert(false && "Unsupported UINT_TO_FP!");
2707 // Check whether the sign bit is set.
2709 GetExpandedInteger(Op, Lo, Hi);
2710 SDValue SignSet = DAG.getSetCC(dl,
2711 TLI.getSetCCResultType(Hi.getValueType()),
2712 Hi, DAG.getConstant(0, Hi.getValueType()),
2715 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2716 SDValue FudgePtr = DAG.getConstantPool(
2717 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2718 TLI.getPointerTy());
2720 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2721 SDValue Zero = DAG.getIntPtrConstant(0);
2722 SDValue Four = DAG.getIntPtrConstant(4);
2723 if (TLI.isBigEndian()) std::swap(Zero, Four);
2724 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2726 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2727 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2728 Alignment = std::min(Alignment, 4u);
2730 // Load the value out, extending it from f32 to the destination float type.
2731 // FIXME: Avoid the extend by constructing the right constant pool?
2732 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2734 MachinePointerInfo::getConstantPool(),
2736 false, false, Alignment);
2737 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2740 // Otherwise, use a libcall.
2741 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2742 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2743 "Don't know how to expand this UINT_TO_FP!");
2744 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);
2747 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2748 SDValue InOp0 = N->getOperand(0);
2749 EVT InVT = InOp0.getValueType();
2751 EVT OutVT = N->getValueType(0);
2752 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2753 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2754 unsigned OutNumElems = OutVT.getVectorNumElements();
2755 EVT NOutVTElem = NOutVT.getVectorElementType();
2757 DebugLoc dl = N->getDebugLoc();
2758 SDValue BaseIdx = N->getOperand(1);
2760 SmallVector<SDValue, 8> Ops;
2761 Ops.reserve(OutNumElems);
2762 for (unsigned i = 0; i != OutNumElems; ++i) {
2764 // Extract the element from the original vector.
2765 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2766 BaseIdx, DAG.getIntPtrConstant(i));
2767 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2768 InVT.getVectorElementType(), N->getOperand(0), Index);
2770 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2771 // Insert the converted element to the new vector.
2775 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2779 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2780 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2781 EVT VT = N->getValueType(0);
2782 DebugLoc dl = N->getDebugLoc();
2784 unsigned NumElts = VT.getVectorNumElements();
2785 SmallVector<int, 8> NewMask;
2786 for (unsigned i = 0; i != NumElts; ++i) {
2787 NewMask.push_back(SV->getMaskElt(i));
2790 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2791 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2792 EVT OutVT = V0.getValueType();
2794 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2798 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2799 EVT OutVT = N->getValueType(0);
2800 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2801 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2802 unsigned NumElems = N->getNumOperands();
2803 EVT NOutVTElem = NOutVT.getVectorElementType();
2805 DebugLoc dl = N->getDebugLoc();
2807 SmallVector<SDValue, 8> Ops;
2808 Ops.reserve(NumElems);
2809 for (unsigned i = 0; i != NumElems; ++i) {
2810 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2814 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2817 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2819 DebugLoc dl = N->getDebugLoc();
2821 assert(!N->getOperand(0).getValueType().isVector() &&
2822 "Input must be a scalar");
2824 EVT OutVT = N->getValueType(0);
2825 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2826 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2827 EVT NOutVTElem = NOutVT.getVectorElementType();
2829 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2831 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2834 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
2835 EVT OutVT = N->getValueType(0);
2836 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2837 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2839 EVT NOutVTElem = NOutVT.getVectorElementType();
2841 DebugLoc dl = N->getDebugLoc();
2842 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2844 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
2845 NOutVTElem, N->getOperand(1));
2846 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
2847 V0, ConvElem, N->getOperand(2));
2850 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2851 DebugLoc dl = N->getDebugLoc();
2852 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2853 SDValue V1 = N->getOperand(1);
2854 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2855 V0->getValueType(0).getScalarType(), V0, V1);
2857 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
2861 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
2862 DebugLoc dl = N->getDebugLoc();
2863 unsigned NumElems = N->getNumOperands();
2865 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
2867 SmallVector<SDValue, 8> NewOps;
2868 NewOps.reserve(NumElems);
2870 // For each incoming vector
2871 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
2872 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
2873 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
2874 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
2876 for (unsigned i=0; i<NumElem; ++i) {
2877 // Extract element from incoming vector
2878 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
2879 Incoming, DAG.getIntPtrConstant(i));
2880 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
2881 NewOps.push_back(Tr);
2885 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
2886 &NewOps[0], NewOps.size());