1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDValue Res = SDValue();
37 // See if the target wants to custom expand this node.
38 if (CustomLowerNode(N, N->getValueType(ResNo), true))
41 switch (N->getOpcode()) {
44 cerr << "PromoteIntegerResult #" << ResNo << ": ";
45 N->dump(&DAG); cerr << "\n";
47 assert(0 && "Do not know how to promote this operator!");
49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
55 case ISD::CONVERT_RNDSAT:
56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
60 case ISD::EXTRACT_VECTOR_ELT:
61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
67 case ISD::SIGN_EXTEND_INREG:
68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
75 case ISD::SIGN_EXTEND:
76 case ISD::ZERO_EXTEND:
77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
102 case ISD::SUBC: Res = PromoteIntRes_ADDSUBC(N, ResNo); break;
104 case ISD::SUBE: Res = PromoteIntRes_ADDSUBE(N, ResNo); break;
106 case ISD::ATOMIC_LOAD_ADD:
107 case ISD::ATOMIC_LOAD_SUB:
108 case ISD::ATOMIC_LOAD_AND:
109 case ISD::ATOMIC_LOAD_OR:
110 case ISD::ATOMIC_LOAD_XOR:
111 case ISD::ATOMIC_LOAD_NAND:
112 case ISD::ATOMIC_LOAD_MIN:
113 case ISD::ATOMIC_LOAD_MAX:
114 case ISD::ATOMIC_LOAD_UMIN:
115 case ISD::ATOMIC_LOAD_UMAX:
116 case ISD::ATOMIC_SWAP:
117 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
119 case ISD::ATOMIC_CMP_SWAP:
120 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
123 // If the result is null then the sub-method took care of registering it.
125 SetPromotedInteger(SDValue(N, ResNo), Res);
128 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBC(SDNode *N, unsigned ResNo) {
129 // Only the carry bit result is expected to be promoted.
130 assert(ResNo == 1 && "Only carry bit result promotion currently supported!");
131 return PromoteIntRes_Overflow(N);
134 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBE(SDNode *N, unsigned ResNo) {
135 // Only the carry bit result is expected to be promoted.
136 assert(ResNo == 1 && "Only carry bit result promotion currently supported!");
137 // This is a ternary operator, so clone a slightly modified
138 // PromoteIntRes_Overflow here (this is the only client).
140 // Simply change the return type of the boolean result.
141 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
142 MVT ValueVTs[] = { N->getValueType(0), NVT };
143 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
144 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
145 DAG.getVTList(ValueVTs, 2), Ops, 3);
147 // Modified the sum result - switch anything that used the old sum to use
149 ReplaceValueWith(SDValue(N, 0), Res);
151 return SDValue(Res.getNode(), 1);
153 assert(0 && "Do not know how to promote this operator!");
157 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
158 // Sign-extend the new bits, and continue the assertion.
159 SDValue Op = SExtPromotedInteger(N->getOperand(0));
160 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
161 Op.getValueType(), Op, N->getOperand(1));
164 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
165 // Zero the new bits, and continue the assertion.
166 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
167 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
168 Op.getValueType(), Op, N->getOperand(1));
171 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
172 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
173 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
175 N->getChain(), N->getBasePtr(),
176 Op2, N->getSrcValue(), N->getAlignment());
177 // Legalized the chain result - switch anything that used the old chain to
179 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
183 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
184 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
185 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
186 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
187 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
188 Op2, Op3, N->getSrcValue(), N->getAlignment());
189 // Legalized the chain result - switch anything that used the old chain to
191 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
195 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
196 SDValue InOp = N->getOperand(0);
197 MVT InVT = InOp.getValueType();
198 MVT NInVT = TLI.getTypeToTransformTo(InVT);
199 MVT OutVT = N->getValueType(0);
200 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
201 DebugLoc dl = N->getDebugLoc();
203 switch (getTypeAction(InVT)) {
205 assert(false && "Unknown type action!");
210 if (NOutVT.bitsEq(NInVT))
211 // The input promotes to the same size. Convert the promoted value.
212 return DAG.getNode(ISD::BIT_CONVERT, dl,
213 NOutVT, GetPromotedInteger(InOp));
216 // Promote the integer operand by hand.
217 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
221 case ScalarizeVector:
222 // Convert the element to an integer and promote it by hand.
223 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
224 BitConvertToInteger(GetScalarizedVector(InOp)));
226 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
227 // pieces of the input into integers and reassemble in the final type.
229 GetSplitVector(N->getOperand(0), Lo, Hi);
230 Lo = BitConvertToInteger(Lo);
231 Hi = BitConvertToInteger(Hi);
233 if (TLI.isBigEndian())
236 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
237 MVT::getIntegerVT(NOutVT.getSizeInBits()),
238 JoinIntegers(Lo, Hi));
239 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
242 if (OutVT.bitsEq(NInVT))
243 // The input is widened to the same size. Convert to the widened value.
244 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
247 // Otherwise, lower the bit-convert to a store/load from the stack.
248 // Create the stack frame object. Make sure it is aligned for both
249 // the source and destination types.
250 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT);
251 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
252 const Value *SV = PseudoSourceValue::getFixedStack(FI);
254 // Emit a store to the stack slot.
255 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
257 // Result is an extending load from the stack slot.
258 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT);
261 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
262 SDValue Op = GetPromotedInteger(N->getOperand(0));
263 MVT OVT = N->getValueType(0);
264 MVT NVT = Op.getValueType();
265 DebugLoc dl = N->getDebugLoc();
267 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
268 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
269 DAG.getConstant(DiffBits, TLI.getPointerTy()));
272 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
273 // The pair element type may be legal, or may not promote to the same type as
274 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
275 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
276 TLI.getTypeToTransformTo(N->getValueType(0)),
277 JoinIntegers(N->getOperand(0), N->getOperand(1)));
280 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
281 MVT VT = N->getValueType(0);
282 // FIXME there is no actual debug info here
283 DebugLoc dl = N->getDebugLoc();
284 // Zero extend things like i1, sign extend everything else. It shouldn't
285 // matter in theory which one we pick, but this tends to give better code?
286 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
287 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
289 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
293 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
294 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
295 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
296 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
297 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
298 "can only promote integers");
299 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
300 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
301 N->getOperand(1), N->getOperand(2),
302 N->getOperand(3), N->getOperand(4), CvtCode);
305 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
306 // Zero extend to the promoted type and do the count there.
307 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
308 DebugLoc dl = N->getDebugLoc();
309 MVT OVT = N->getValueType(0);
310 MVT NVT = Op.getValueType();
311 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
312 // Subtract off the extra leading bits in the bigger type.
313 return DAG.getNode(ISD::SUB, dl, NVT, Op,
314 DAG.getConstant(NVT.getSizeInBits() -
315 OVT.getSizeInBits(), NVT));
318 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
319 // Zero extend to the promoted type and do the count there.
320 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
321 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
324 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
325 SDValue Op = GetPromotedInteger(N->getOperand(0));
326 MVT OVT = N->getValueType(0);
327 MVT NVT = Op.getValueType();
328 DebugLoc dl = N->getDebugLoc();
329 // The count is the same in the promoted type except if the original
330 // value was zero. This can be handled by setting the bit just off
331 // the top of the original type.
332 APInt TopBit(NVT.getSizeInBits(), 0);
333 TopBit.set(OVT.getSizeInBits());
334 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
335 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
338 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
339 MVT OldVT = N->getValueType(0);
340 SDValue OldVec = N->getOperand(0);
341 if (getTypeAction(OldVec.getValueType()) == WidenVector)
342 OldVec = GetWidenedVector(N->getOperand(0));
343 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
344 DebugLoc dl = N->getDebugLoc();
347 assert(!isTypeLegal(OldVec.getValueType()) &&
348 "Legal one-element vector of a type needing promotion!");
349 // It is tempting to follow GetScalarizedVector by a call to
350 // GetPromotedInteger, but this would be wrong because the
351 // scalarized value may not yet have been processed.
352 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT),
353 GetScalarizedVector(OldVec));
356 // Convert to a vector half as long with an element type of twice the width,
357 // for example <4 x i16> -> <2 x i32>.
358 assert(!(OldElts & 1) && "Odd length vectors not supported!");
359 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
360 assert(OldVT.isSimple() && NewVT.isSimple());
362 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
363 MVT::getVectorVT(NewVT, OldElts / 2),
366 // Extract the element at OldIdx / 2 from the new vector.
367 SDValue OldIdx = N->getOperand(1);
368 SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx,
369 DAG.getConstant(1, TLI.getPointerTy()));
370 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx);
372 // Select the appropriate half of the element: Lo if OldIdx was even,
375 SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt,
376 DAG.getConstant(OldVT.getSizeInBits(),
377 TLI.getPointerTy()));
378 if (TLI.isBigEndian())
381 // Extend to the promoted type.
382 SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx);
383 SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo);
384 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res);
387 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
388 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
389 unsigned NewOpc = N->getOpcode();
390 DebugLoc dl = N->getDebugLoc();
392 // If we're promoting a UINT to a larger size, check to see if the new node
393 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
394 // we can use that instead. This allows us to generate better code for
395 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
396 // legal, such as PowerPC.
397 if (N->getOpcode() == ISD::FP_TO_UINT &&
398 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
399 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
400 NewOpc = ISD::FP_TO_SINT;
402 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
404 // Assert that the converted value fits in the original type. If it doesn't
405 // (eg: because the value being converted is too big), then the result of the
406 // original operation was undefined anyway, so the assert is still correct.
407 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
408 ISD::AssertZext : ISD::AssertSext, dl,
409 NVT, Res, DAG.getValueType(N->getValueType(0)));
412 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
413 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
414 DebugLoc dl = N->getDebugLoc();
416 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
417 SDValue Res = GetPromotedInteger(N->getOperand(0));
418 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
420 // If the result and operand types are the same after promotion, simplify
421 // to an in-register extension.
422 if (NVT == Res.getValueType()) {
423 // The high bits are not guaranteed to be anything. Insert an extend.
424 if (N->getOpcode() == ISD::SIGN_EXTEND)
425 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
426 DAG.getValueType(N->getOperand(0).getValueType()));
427 if (N->getOpcode() == ISD::ZERO_EXTEND)
428 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
429 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
434 // Otherwise, just extend the original operand all the way to the larger type.
435 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
438 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
439 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
440 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
441 ISD::LoadExtType ExtType =
442 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
443 DebugLoc dl = N->getDebugLoc();
444 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
445 N->getSrcValue(), N->getSrcValueOffset(),
446 N->getMemoryVT(), N->isVolatile(),
449 // Legalized the chain result - switch anything that used the old chain to
451 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
455 /// Promote the overflow or carry result of an overflowing arithmetic node.
456 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
457 // Simply change the return type of the boolean result.
458 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
459 MVT ValueVTs[] = { N->getValueType(0), NVT };
460 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
461 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
462 DAG.getVTList(ValueVTs, 2), Ops, 2);
464 // Modified the sum result - switch anything that used the old sum to use
466 ReplaceValueWith(SDValue(N, 0), Res);
468 return SDValue(Res.getNode(), 1);
471 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
473 return PromoteIntRes_Overflow(N);
475 // The operation overflowed iff the result in the larger type is not the
476 // sign extension of its truncation to the original type.
477 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
478 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
479 MVT OVT = N->getOperand(0).getValueType();
480 MVT NVT = LHS.getValueType();
481 DebugLoc dl = N->getDebugLoc();
483 // Do the arithmetic in the larger type.
484 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
485 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
487 // Calculate the overflow flag: sign extend the arithmetic result from
488 // the original type.
489 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
490 DAG.getValueType(OVT));
491 // Overflowed if and only if this is not equal to Res.
492 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
494 // Use the calculated overflow everywhere.
495 ReplaceValueWith(SDValue(N, 1), Ofl);
500 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
501 // Sign extend the input.
502 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
503 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
504 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
505 LHS.getValueType(), LHS, RHS);
508 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
509 SDValue LHS = GetPromotedInteger(N->getOperand(1));
510 SDValue RHS = GetPromotedInteger(N->getOperand(2));
511 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
512 LHS.getValueType(), N->getOperand(0),LHS,RHS);
515 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
516 SDValue LHS = GetPromotedInteger(N->getOperand(2));
517 SDValue RHS = GetPromotedInteger(N->getOperand(3));
518 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
519 LHS.getValueType(), N->getOperand(0),
520 N->getOperand(1), LHS, RHS, N->getOperand(4));
523 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
524 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
525 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
526 DebugLoc dl = N->getDebugLoc();
528 // Get the SETCC result using the canonical SETCC type.
529 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
530 N->getOperand(1), N->getOperand(2));
532 // Convert to the expected type.
533 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
534 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
535 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
538 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
539 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
540 TLI.getTypeToTransformTo(N->getValueType(0)),
541 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
544 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
545 SDValue Op = GetPromotedInteger(N->getOperand(0));
546 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
547 Op.getValueType(), Op, N->getOperand(1));
550 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
551 // The input may have strange things in the top bits of the registers, but
552 // these operations don't care. They may have weird bits going out, but
553 // that too is okay if they are integer operations.
554 SDValue LHS = GetPromotedInteger(N->getOperand(0));
555 SDValue RHS = GetPromotedInteger(N->getOperand(1));
556 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
557 LHS.getValueType(), LHS, RHS);
560 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
561 // The input value must be properly sign extended.
562 SDValue Res = SExtPromotedInteger(N->getOperand(0));
563 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
564 Res.getValueType(), Res, N->getOperand(1));
567 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
568 // The input value must be properly zero extended.
569 MVT VT = N->getValueType(0);
570 MVT NVT = TLI.getTypeToTransformTo(VT);
571 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
572 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
575 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
576 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
579 switch (getTypeAction(N->getOperand(0).getValueType())) {
580 default: assert(0 && "Unknown type action!");
583 Res = N->getOperand(0);
586 Res = GetPromotedInteger(N->getOperand(0));
590 // Truncate to NVT instead of VT
591 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
594 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
596 return PromoteIntRes_Overflow(N);
598 // The operation overflowed iff the result in the larger type is not the
599 // zero extension of its truncation to the original type.
600 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
601 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
602 MVT OVT = N->getOperand(0).getValueType();
603 MVT NVT = LHS.getValueType();
604 DebugLoc dl = N->getDebugLoc();
606 // Do the arithmetic in the larger type.
607 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
608 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
610 // Calculate the overflow flag: zero extend the arithmetic result from
611 // the original type.
612 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
613 // Overflowed if and only if this is not equal to Res.
614 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
616 // Use the calculated overflow everywhere.
617 ReplaceValueWith(SDValue(N, 1), Ofl);
622 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
623 // Zero extend the input.
624 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
625 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
626 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
627 LHS.getValueType(), LHS, RHS);
630 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
631 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
634 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
635 SDValue Chain = N->getOperand(0); // Get the chain.
636 SDValue Ptr = N->getOperand(1); // Get the pointer.
637 MVT VT = N->getValueType(0);
638 DebugLoc dl = N->getDebugLoc();
640 MVT RegVT = TLI.getRegisterType(VT);
641 unsigned NumRegs = TLI.getNumRegisters(VT);
642 // The argument is passed as NumRegs registers of type RegVT.
644 SmallVector<SDValue, 8> Parts(NumRegs);
645 for (unsigned i = 0; i < NumRegs; ++i) {
646 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
647 Chain = Parts[i].getValue(1);
650 // Handle endianness of the load.
651 if (TLI.isBigEndian())
652 std::reverse(Parts.begin(), Parts.end());
654 // Assemble the parts in the promoted type.
655 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
656 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
657 for (unsigned i = 1; i < NumRegs; ++i) {
658 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
659 // Shift it to the right position and "or" it in.
660 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
661 DAG.getConstant(i * RegVT.getSizeInBits(),
662 TLI.getPointerTy()));
663 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
666 // Modified the chain result - switch anything that used the old chain to
668 ReplaceValueWith(SDValue(N, 1), Chain);
673 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
674 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
675 return PromoteIntRes_Overflow(N);
678 //===----------------------------------------------------------------------===//
679 // Integer Operand Promotion
680 //===----------------------------------------------------------------------===//
682 /// PromoteIntegerOperand - This method is called when the specified operand of
683 /// the specified node is found to need promotion. At this point, all of the
684 /// result types of the node are known to be legal, but other operands of the
685 /// node may need promotion or expansion as well as the specified one.
686 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
687 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
688 SDValue Res = SDValue();
690 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
693 switch (N->getOpcode()) {
696 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
697 N->dump(&DAG); cerr << "\n";
699 assert(0 && "Do not know how to promote this operator's operand!");
703 case ISD::SUBE: Res = PromoteIntOp_ADDSUBE(N, OpNo); break;
704 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
705 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
706 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
707 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
708 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
709 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
710 case ISD::CONVERT_RNDSAT:
711 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
712 case ISD::INSERT_VECTOR_ELT:
713 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
714 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
715 case ISD::SCALAR_TO_VECTOR:
716 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
717 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
718 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
719 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
720 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
721 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
722 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
724 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
725 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
726 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
732 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
735 // If the result is null, the sub-method took care of registering results etc.
736 if (!Res.getNode()) return false;
738 // If the result is N, the sub-method updated N in place. Tell the legalizer
740 if (Res.getNode() == N)
743 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
744 "Invalid operand expansion");
746 ReplaceValueWith(SDValue(N, 0), Res);
750 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
751 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
752 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
753 ISD::CondCode CCCode) {
754 // We have to insert explicit sign or zero extends. Note that we could
755 // insert sign extends for ALL conditions, but zero extend is cheaper on
756 // many machines (an AND instead of two shifts), so prefer it.
758 default: assert(0 && "Unknown integer comparison!");
765 // ALL of these operations will work if we either sign or zero extend
766 // the operands (including the unsigned comparisons!). Zero extend is
767 // usually a simpler/cheaper operation, so prefer it.
768 NewLHS = ZExtPromotedInteger(NewLHS);
769 NewRHS = ZExtPromotedInteger(NewRHS);
775 NewLHS = SExtPromotedInteger(NewLHS);
776 NewRHS = SExtPromotedInteger(NewRHS);
781 SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBE(SDNode *N, unsigned OpNo) {
782 assert(OpNo == 2 && "Don't know how to promote this operand!");
783 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
785 GetPromotedInteger(N->getOperand(2)));
788 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
789 SDValue Op = GetPromotedInteger(N->getOperand(0));
790 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
793 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
794 // This should only occur in unusual situations like bitcasting to an
795 // x86_fp80, so just turn it into a store+load
796 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
799 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
800 assert(OpNo == 2 && "Don't know how to promote this operand!");
802 SDValue LHS = N->getOperand(2);
803 SDValue RHS = N->getOperand(3);
804 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
806 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
808 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
809 N->getOperand(1), LHS, RHS, N->getOperand(4));
812 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
813 assert(OpNo == 1 && "only know how to promote condition");
815 // Promote all the way up to the canonical SetCC type.
816 MVT SVT = TLI.getSetCCResultType(MVT::Other);
817 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
819 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
820 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
824 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
825 // Since the result type is legal, the operands must promote to it.
826 MVT OVT = N->getOperand(0).getValueType();
827 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
828 SDValue Hi = GetPromotedInteger(N->getOperand(1));
829 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
830 DebugLoc dl = N->getDebugLoc();
832 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
833 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
834 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
837 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
838 // The vector type is legal but the element type is not. This implies
839 // that the vector is a power-of-two in length and that the element
840 // type does not have a strange size (eg: it is not i1).
841 MVT VecVT = N->getValueType(0);
842 unsigned NumElts = VecVT.getVectorNumElements();
843 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
845 // Promote the inserted value. The type does not need to match the
846 // vector element type. Check that any extra bits introduced will be
848 assert(N->getOperand(0).getValueType().getSizeInBits() >=
849 N->getValueType(0).getVectorElementType().getSizeInBits() &&
850 "Type of inserted value narrower than vector element type!");
852 SmallVector<SDValue, 16> NewOps;
853 for (unsigned i = 0; i < NumElts; ++i)
854 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
856 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts);
859 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
860 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
861 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
862 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
863 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
864 "can only promote integer arguments");
865 SDValue InOp = GetPromotedInteger(N->getOperand(0));
866 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
867 N->getOperand(1), N->getOperand(2),
868 N->getOperand(3), N->getOperand(4), CvtCode);
871 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
874 // Promote the inserted value. This is valid because the type does not
875 // have to match the vector element type.
877 // Check that any extra bits introduced will be truncated away.
878 assert(N->getOperand(1).getValueType().getSizeInBits() >=
879 N->getValueType(0).getVectorElementType().getSizeInBits() &&
880 "Type of inserted value narrower than vector element type!");
881 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
882 GetPromotedInteger(N->getOperand(1)),
886 assert(OpNo == 2 && "Different operand and result vector types?");
888 // Promote the index.
889 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
890 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
891 N->getOperand(1), Idx);
894 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
896 DebugLoc dl = N->getDebugLoc();
897 NewOps[0] = N->getOperand(0);
898 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
899 SDValue Flag = GetPromotedInteger(N->getOperand(i));
900 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
902 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
903 array_lengthof(NewOps));
906 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
907 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
908 // the operand in place.
909 return DAG.UpdateNodeOperands(SDValue(N, 0),
910 GetPromotedInteger(N->getOperand(0)));
913 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
914 assert(OpNo == 0 && "Only know how to promote condition");
916 // Promote all the way up to the canonical SetCC type.
917 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
918 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
920 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
921 N->getOperand(1), N->getOperand(2));
924 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
925 assert(OpNo == 0 && "Don't know how to promote this operand!");
927 SDValue LHS = N->getOperand(0);
928 SDValue RHS = N->getOperand(1);
929 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
931 // The CC (#4) and the possible return values (#2 and #3) have legal types.
932 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
933 N->getOperand(3), N->getOperand(4));
936 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
937 assert(OpNo == 0 && "Don't know how to promote this operand!");
939 SDValue LHS = N->getOperand(0);
940 SDValue RHS = N->getOperand(1);
941 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
943 // The CC (#2) is always legal.
944 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
947 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
948 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
949 ZExtPromotedInteger(N->getOperand(1)));
952 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
953 SDValue Op = GetPromotedInteger(N->getOperand(0));
954 DebugLoc dl = N->getDebugLoc();
955 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
956 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
957 Op, DAG.getValueType(N->getOperand(0).getValueType()));
960 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
961 return DAG.UpdateNodeOperands(SDValue(N, 0),
962 SExtPromotedInteger(N->getOperand(0)));
965 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
966 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
967 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
968 int SVOffset = N->getSrcValueOffset();
969 unsigned Alignment = N->getAlignment();
970 bool isVolatile = N->isVolatile();
971 DebugLoc dl = N->getDebugLoc();
973 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
975 // Truncate the value and store the result.
976 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
977 SVOffset, N->getMemoryVT(),
978 isVolatile, Alignment);
981 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
982 SDValue Op = GetPromotedInteger(N->getOperand(0));
983 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
986 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
987 return DAG.UpdateNodeOperands(SDValue(N, 0),
988 ZExtPromotedInteger(N->getOperand(0)));
991 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
992 DebugLoc dl = N->getDebugLoc();
993 SDValue Op = GetPromotedInteger(N->getOperand(0));
994 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
995 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
999 //===----------------------------------------------------------------------===//
1000 // Integer Result Expansion
1001 //===----------------------------------------------------------------------===//
1003 /// ExpandIntegerResult - This method is called when the specified result of the
1004 /// specified node is found to need expansion. At this point, the node may also
1005 /// have invalid operands or may have other results that need promotion, we just
1006 /// know that (at least) one result needs expansion.
1007 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1008 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
1010 Lo = Hi = SDValue();
1012 // See if the target wants to custom expand this node.
1013 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1016 switch (N->getOpcode()) {
1019 cerr << "ExpandIntegerResult #" << ResNo << ": ";
1020 N->dump(&DAG); cerr << "\n";
1022 assert(0 && "Do not know how to expand the result of this operator!");
1025 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
1026 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1027 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1028 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1030 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
1031 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1032 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1033 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1034 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1036 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1037 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1038 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1039 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1040 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1041 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1042 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1043 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1044 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1045 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1046 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1047 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1048 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1049 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1050 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1051 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1052 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1053 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1054 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1055 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1059 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1062 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1065 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1068 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1072 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1075 // If Lo/Hi is null, the sub-method took care of registering results etc.
1077 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1080 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1081 /// and the shift amount is a constant 'Amt'. Expand the operation.
1082 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1083 SDValue &Lo, SDValue &Hi) {
1084 DebugLoc dl = N->getDebugLoc();
1085 // Expand the incoming operand to be shifted, so that we have its parts
1087 GetExpandedInteger(N->getOperand(0), InL, InH);
1089 MVT NVT = InL.getValueType();
1090 unsigned VTBits = N->getValueType(0).getSizeInBits();
1091 unsigned NVTBits = NVT.getSizeInBits();
1092 MVT ShTy = N->getOperand(1).getValueType();
1094 if (N->getOpcode() == ISD::SHL) {
1096 Lo = Hi = DAG.getConstant(0, NVT);
1097 } else if (Amt > NVTBits) {
1098 Lo = DAG.getConstant(0, NVT);
1099 Hi = DAG.getNode(ISD::SHL, dl,
1100 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1101 } else if (Amt == NVTBits) {
1102 Lo = DAG.getConstant(0, NVT);
1104 } else if (Amt == 1 &&
1105 TLI.isOperationLegalOrCustom(ISD::ADDC,
1106 TLI.getTypeToExpandTo(NVT))) {
1107 // Emit this X << 1 as X+X.
1108 SDVTList VTList = DAG.getVTList(NVT, MVT::i1);
1109 SDValue LoOps[2] = { InL, InL };
1110 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1111 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1112 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1114 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1115 Hi = DAG.getNode(ISD::OR, dl, NVT,
1116 DAG.getNode(ISD::SHL, dl, NVT, InH,
1117 DAG.getConstant(Amt, ShTy)),
1118 DAG.getNode(ISD::SRL, dl, NVT, InL,
1119 DAG.getConstant(NVTBits-Amt, ShTy)));
1124 if (N->getOpcode() == ISD::SRL) {
1126 Lo = DAG.getConstant(0, NVT);
1127 Hi = DAG.getConstant(0, NVT);
1128 } else if (Amt > NVTBits) {
1129 Lo = DAG.getNode(ISD::SRL, dl,
1130 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1131 Hi = DAG.getConstant(0, NVT);
1132 } else if (Amt == NVTBits) {
1134 Hi = DAG.getConstant(0, NVT);
1136 Lo = DAG.getNode(ISD::OR, dl, NVT,
1137 DAG.getNode(ISD::SRL, dl, NVT, InL,
1138 DAG.getConstant(Amt, ShTy)),
1139 DAG.getNode(ISD::SHL, dl, NVT, InH,
1140 DAG.getConstant(NVTBits-Amt, ShTy)));
1141 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1146 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1148 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1149 DAG.getConstant(NVTBits-1, ShTy));
1150 } else if (Amt > NVTBits) {
1151 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1152 DAG.getConstant(Amt-NVTBits, ShTy));
1153 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1154 DAG.getConstant(NVTBits-1, ShTy));
1155 } else if (Amt == NVTBits) {
1157 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1158 DAG.getConstant(NVTBits-1, ShTy));
1160 Lo = DAG.getNode(ISD::OR, dl, NVT,
1161 DAG.getNode(ISD::SRL, dl, NVT, InL,
1162 DAG.getConstant(Amt, ShTy)),
1163 DAG.getNode(ISD::SHL, dl, NVT, InH,
1164 DAG.getConstant(NVTBits-Amt, ShTy)));
1165 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1169 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1170 /// this shift based on knowledge of the high bit of the shift amount. If we
1171 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1173 bool DAGTypeLegalizer::
1174 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1175 SDValue Amt = N->getOperand(1);
1176 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1177 MVT ShTy = Amt.getValueType();
1178 unsigned ShBits = ShTy.getSizeInBits();
1179 unsigned NVTBits = NVT.getSizeInBits();
1180 assert(isPowerOf2_32(NVTBits) &&
1181 "Expanded integer type size not a power of two!");
1182 DebugLoc dl = N->getDebugLoc();
1184 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1185 APInt KnownZero, KnownOne;
1186 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1188 // If we don't know anything about the high bits, exit.
1189 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1192 // Get the incoming operand to be shifted.
1194 GetExpandedInteger(N->getOperand(0), InL, InH);
1196 // If we know that any of the high bits of the shift amount are one, then we
1197 // can do this as a couple of simple shifts.
1198 if (KnownOne.intersects(HighBitMask)) {
1199 // Mask out the high bit, which we know is set.
1200 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1201 DAG.getConstant(~HighBitMask, ShTy));
1203 switch (N->getOpcode()) {
1204 default: assert(0 && "Unknown shift");
1206 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1207 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1210 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1211 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1214 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1215 DAG.getConstant(NVTBits-1, ShTy));
1216 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1222 // FIXME: This code is broken for shifts with a zero amount!
1223 // If we know that all of the high bits of the shift amount are zero, then we
1224 // can do this as a couple of simple shifts.
1225 if ((KnownZero & HighBitMask) == HighBitMask) {
1227 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1228 DAG.getConstant(NVTBits, ShTy),
1231 switch (N->getOpcode()) {
1232 default: assert(0 && "Unknown shift");
1233 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1235 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1238 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1239 Hi = DAG.getNode(ISD::OR, NVT,
1240 DAG.getNode(Op1, NVT, InH, Amt),
1241 DAG.getNode(Op2, NVT, InL, Amt2));
1249 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1251 bool DAGTypeLegalizer::
1252 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1253 SDValue Amt = N->getOperand(1);
1254 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1255 MVT ShTy = Amt.getValueType();
1256 unsigned NVTBits = NVT.getSizeInBits();
1257 assert(isPowerOf2_32(NVTBits) &&
1258 "Expanded integer type size not a power of two!");
1259 DebugLoc dl = N->getDebugLoc();
1261 // Get the incoming operand to be shifted.
1263 GetExpandedInteger(N->getOperand(0), InL, InH);
1265 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1266 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1267 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1268 Amt, NVBitsNode, ISD::SETULT);
1270 SDValue Lo1, Hi1, Lo2, Hi2;
1271 switch (N->getOpcode()) {
1272 default: assert(0 && "Unknown shift");
1275 Lo1 = DAG.getConstant(0, NVT); // Low part is zero.
1276 Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1279 Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1280 Hi2 = DAG.getNode(ISD::OR, dl, NVT,
1281 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1282 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
1284 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1285 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1289 Hi1 = DAG.getConstant(0, NVT); // Hi part is zero.
1290 Lo1 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1293 Hi2 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1294 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1295 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1296 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1298 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1299 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1303 Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1304 DAG.getConstant(NVTBits-1, ShTy));
1305 Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1308 Hi2 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1309 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1310 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1311 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1313 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1314 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1321 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1322 SDValue &Lo, SDValue &Hi) {
1323 DebugLoc dl = N->getDebugLoc();
1324 // Expand the subcomponents.
1325 SDValue LHSL, LHSH, RHSL, RHSH;
1326 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1327 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1329 MVT NVT = LHSL.getValueType();
1330 SDValue LoOps[2] = { LHSL, RHSL };
1331 SDValue HiOps[3] = { LHSH, RHSH };
1333 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1334 // them. TODO: Teach operation legalization how to expand unsupported
1335 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1336 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1337 // generate a value of this type in the expanded code sequence.
1339 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1340 ISD::ADDC : ISD::SUBC,
1341 TLI.getTypeToExpandTo(NVT));
1344 SDVTList VTList = DAG.getVTList(NVT, MVT::i1);
1345 if (N->getOpcode() == ISD::ADD) {
1346 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1347 HiOps[2] = Lo.getValue(1);
1348 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1350 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1351 HiOps[2] = Lo.getValue(1);
1352 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1355 if (N->getOpcode() == ISD::ADD) {
1356 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1357 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1358 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1360 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1361 DAG.getConstant(1, NVT),
1362 DAG.getConstant(0, NVT));
1363 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1365 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1366 DAG.getConstant(1, NVT), Carry1);
1367 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1369 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1370 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1372 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1373 LoOps[0], LoOps[1], ISD::SETULT);
1374 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1375 DAG.getConstant(1, NVT),
1376 DAG.getConstant(0, NVT));
1377 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1382 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1383 SDValue &Lo, SDValue &Hi) {
1384 // Expand the subcomponents.
1385 SDValue LHSL, LHSH, RHSL, RHSH;
1386 DebugLoc dl = N->getDebugLoc();
1387 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1388 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1389 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1);
1390 SDValue LoOps[2] = { LHSL, RHSL };
1391 SDValue HiOps[3] = { LHSH, RHSH };
1393 if (N->getOpcode() == ISD::ADDC) {
1394 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1395 HiOps[2] = Lo.getValue(1);
1396 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1398 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1399 HiOps[2] = Lo.getValue(1);
1400 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1403 // Legalized the second result (carry bit) - switch anything that used the
1404 // result to use the new one.
1405 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1408 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1409 SDValue &Lo, SDValue &Hi) {
1410 // Expand the subcomponents.
1411 SDValue LHSL, LHSH, RHSL, RHSH;
1412 DebugLoc dl = N->getDebugLoc();
1413 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1414 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1415 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::i1);
1416 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1417 SDValue HiOps[3] = { LHSH, RHSH };
1419 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1420 HiOps[2] = Lo.getValue(1);
1421 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1423 // Legalized the second result (carry bit) - switch anything that used the
1424 // result to use the new one.
1425 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1428 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1429 SDValue &Lo, SDValue &Hi) {
1430 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1431 DebugLoc dl = N->getDebugLoc();
1432 SDValue Op = N->getOperand(0);
1433 if (Op.getValueType().bitsLE(NVT)) {
1434 // The low part is any extension of the input (which degenerates to a copy).
1435 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1436 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1438 // For example, extension of an i48 to an i64. The operand type necessarily
1439 // promotes to the result type, so will end up being expanded too.
1440 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1441 "Only know how to promote this result!");
1442 SDValue Res = GetPromotedInteger(Op);
1443 assert(Res.getValueType() == N->getValueType(0) &&
1444 "Operand over promoted?");
1445 // Split the promoted operand. This will simplify when it is expanded.
1446 SplitInteger(Res, Lo, Hi);
1450 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1451 SDValue &Lo, SDValue &Hi) {
1452 DebugLoc dl = N->getDebugLoc();
1453 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1454 MVT NVT = Lo.getValueType();
1455 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1456 unsigned NVTBits = NVT.getSizeInBits();
1457 unsigned EVTBits = EVT.getSizeInBits();
1459 if (NVTBits < EVTBits) {
1460 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1461 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1463 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1464 // The high part replicates the sign bit of Lo, make it explicit.
1465 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1466 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1470 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1471 SDValue &Lo, SDValue &Hi) {
1472 DebugLoc dl = N->getDebugLoc();
1473 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1474 MVT NVT = Lo.getValueType();
1475 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1476 unsigned NVTBits = NVT.getSizeInBits();
1477 unsigned EVTBits = EVT.getSizeInBits();
1479 if (NVTBits < EVTBits) {
1480 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1481 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1483 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1484 // The high part must be zero, make it explicit.
1485 Hi = DAG.getConstant(0, NVT);
1489 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1490 SDValue &Lo, SDValue &Hi) {
1491 DebugLoc dl = N->getDebugLoc();
1492 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1493 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1494 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1497 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1498 SDValue &Lo, SDValue &Hi) {
1499 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1500 unsigned NBitWidth = NVT.getSizeInBits();
1501 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1502 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1503 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1506 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1507 SDValue &Lo, SDValue &Hi) {
1508 DebugLoc dl = N->getDebugLoc();
1509 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1510 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1511 MVT NVT = Lo.getValueType();
1513 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1514 DAG.getConstant(0, NVT), ISD::SETNE);
1516 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1517 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1519 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1520 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1521 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1522 Hi = DAG.getConstant(0, NVT);
1525 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1526 SDValue &Lo, SDValue &Hi) {
1527 DebugLoc dl = N->getDebugLoc();
1528 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1529 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1530 MVT NVT = Lo.getValueType();
1531 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1532 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1533 Hi = DAG.getConstant(0, NVT);
1536 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1537 SDValue &Lo, SDValue &Hi) {
1538 DebugLoc dl = N->getDebugLoc();
1539 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1540 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1541 MVT NVT = Lo.getValueType();
1543 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1544 DAG.getConstant(0, NVT), ISD::SETNE);
1546 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1547 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1549 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1550 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1551 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1552 Hi = DAG.getConstant(0, NVT);
1555 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1557 DebugLoc dl = N->getDebugLoc();
1558 MVT VT = N->getValueType(0);
1559 SDValue Op = N->getOperand(0);
1560 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1561 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1562 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1565 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1567 DebugLoc dl = N->getDebugLoc();
1568 MVT VT = N->getValueType(0);
1569 SDValue Op = N->getOperand(0);
1570 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1571 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1572 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1575 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1576 SDValue &Lo, SDValue &Hi) {
1577 if (ISD::isNormalLoad(N)) {
1578 ExpandRes_NormalLoad(N, Lo, Hi);
1582 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1584 MVT VT = N->getValueType(0);
1585 MVT NVT = TLI.getTypeToTransformTo(VT);
1586 SDValue Ch = N->getChain();
1587 SDValue Ptr = N->getBasePtr();
1588 ISD::LoadExtType ExtType = N->getExtensionType();
1589 int SVOffset = N->getSrcValueOffset();
1590 unsigned Alignment = N->getAlignment();
1591 bool isVolatile = N->isVolatile();
1592 DebugLoc dl = N->getDebugLoc();
1594 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1596 if (N->getMemoryVT().bitsLE(NVT)) {
1597 MVT EVT = N->getMemoryVT();
1599 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1600 EVT, isVolatile, Alignment);
1602 // Remember the chain.
1603 Ch = Lo.getValue(1);
1605 if (ExtType == ISD::SEXTLOAD) {
1606 // The high part is obtained by SRA'ing all but one of the bits of the
1608 unsigned LoSize = Lo.getValueType().getSizeInBits();
1609 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1610 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1611 } else if (ExtType == ISD::ZEXTLOAD) {
1612 // The high part is just a zero.
1613 Hi = DAG.getConstant(0, NVT);
1615 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1616 // The high part is undefined.
1617 Hi = DAG.getUNDEF(NVT);
1619 } else if (TLI.isLittleEndian()) {
1620 // Little-endian - low bits are at low addresses.
1621 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1622 isVolatile, Alignment);
1624 unsigned ExcessBits =
1625 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1626 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1628 // Increment the pointer to the other half.
1629 unsigned IncrementSize = NVT.getSizeInBits()/8;
1630 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1631 DAG.getIntPtrConstant(IncrementSize));
1632 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1633 SVOffset+IncrementSize, NEVT,
1634 isVolatile, MinAlign(Alignment, IncrementSize));
1636 // Build a factor node to remember that this load is independent of the
1638 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1641 // Big-endian - high bits are at low addresses. Favor aligned loads at
1642 // the cost of some bit-fiddling.
1643 MVT EVT = N->getMemoryVT();
1644 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1645 unsigned IncrementSize = NVT.getSizeInBits()/8;
1646 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1648 // Load both the high bits and maybe some of the low bits.
1649 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1650 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1651 isVolatile, Alignment);
1653 // Increment the pointer to the other half.
1654 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1655 DAG.getIntPtrConstant(IncrementSize));
1656 // Load the rest of the low bits.
1657 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1658 SVOffset+IncrementSize,
1659 MVT::getIntegerVT(ExcessBits),
1660 isVolatile, MinAlign(Alignment, IncrementSize));
1662 // Build a factor node to remember that this load is independent of the
1664 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1667 if (ExcessBits < NVT.getSizeInBits()) {
1668 // Transfer low bits from the bottom of Hi to the top of Lo.
1669 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1670 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1671 DAG.getConstant(ExcessBits,
1672 TLI.getPointerTy())));
1673 // Move high bits to the right position in Hi.
1674 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1676 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1677 TLI.getPointerTy()));
1681 // Legalized the chain result - switch anything that used the old chain to
1683 ReplaceValueWith(SDValue(N, 1), Ch);
1686 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1687 SDValue &Lo, SDValue &Hi) {
1688 DebugLoc dl = N->getDebugLoc();
1689 SDValue LL, LH, RL, RH;
1690 GetExpandedInteger(N->getOperand(0), LL, LH);
1691 GetExpandedInteger(N->getOperand(1), RL, RH);
1692 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1693 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1696 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1697 SDValue &Lo, SDValue &Hi) {
1698 MVT VT = N->getValueType(0);
1699 MVT NVT = TLI.getTypeToTransformTo(VT);
1700 DebugLoc dl = N->getDebugLoc();
1702 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1703 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1704 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1705 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1706 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1707 SDValue LL, LH, RL, RH;
1708 GetExpandedInteger(N->getOperand(0), LL, LH);
1709 GetExpandedInteger(N->getOperand(1), RL, RH);
1710 unsigned OuterBitSize = VT.getSizeInBits();
1711 unsigned InnerBitSize = NVT.getSizeInBits();
1712 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1713 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1715 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1716 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1717 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1718 // The inputs are both zero-extended.
1720 // We can emit a umul_lohi.
1721 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1722 Hi = SDValue(Lo.getNode(), 1);
1726 // We can emit a mulhu+mul.
1727 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1728 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1732 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1733 // The input values are both sign-extended.
1735 // We can emit a smul_lohi.
1736 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1737 Hi = SDValue(Lo.getNode(), 1);
1741 // We can emit a mulhs+mul.
1742 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1743 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1748 // Lo,Hi = umul LHS, RHS.
1749 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1750 DAG.getVTList(NVT, NVT), LL, RL);
1752 Hi = UMulLOHI.getValue(1);
1753 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1754 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1755 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1756 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1760 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1761 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1762 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1763 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1764 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1765 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1770 // If nothing else, we can make a libcall.
1771 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1773 LC = RTLIB::MUL_I16;
1774 else if (VT == MVT::i32)
1775 LC = RTLIB::MUL_I32;
1776 else if (VT == MVT::i64)
1777 LC = RTLIB::MUL_I64;
1778 else if (VT == MVT::i128)
1779 LC = RTLIB::MUL_I128;
1780 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1782 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1783 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1786 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1787 SDValue &Lo, SDValue &Hi) {
1788 MVT VT = N->getValueType(0);
1789 DebugLoc dl = N->getDebugLoc();
1791 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1793 LC = RTLIB::SDIV_I32;
1794 else if (VT == MVT::i64)
1795 LC = RTLIB::SDIV_I64;
1796 else if (VT == MVT::i128)
1797 LC = RTLIB::SDIV_I128;
1798 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1800 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1801 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1804 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1805 SDValue &Lo, SDValue &Hi) {
1806 MVT VT = N->getValueType(0);
1807 DebugLoc dl = N->getDebugLoc();
1809 // If we can emit an efficient shift operation, do so now. Check to see if
1810 // the RHS is a constant.
1811 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1812 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1814 // If we can determine that the high bit of the shift is zero or one, even if
1815 // the low bits are variable, emit this shift in an optimized form.
1816 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1819 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1821 if (N->getOpcode() == ISD::SHL) {
1822 PartsOpc = ISD::SHL_PARTS;
1823 } else if (N->getOpcode() == ISD::SRL) {
1824 PartsOpc = ISD::SRL_PARTS;
1826 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1827 PartsOpc = ISD::SRA_PARTS;
1830 // Next check to see if the target supports this SHL_PARTS operation or if it
1831 // will custom expand it.
1832 MVT NVT = TLI.getTypeToTransformTo(VT);
1833 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1834 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1835 Action == TargetLowering::Custom) {
1836 // Expand the subcomponents.
1838 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1840 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1841 MVT VT = LHSL.getValueType();
1842 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1843 Hi = Lo.getValue(1);
1847 // Otherwise, emit a libcall.
1848 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1850 if (N->getOpcode() == ISD::SHL) {
1851 isSigned = false; /*sign irrelevant*/
1853 LC = RTLIB::SHL_I16;
1854 else if (VT == MVT::i32)
1855 LC = RTLIB::SHL_I32;
1856 else if (VT == MVT::i64)
1857 LC = RTLIB::SHL_I64;
1858 else if (VT == MVT::i128)
1859 LC = RTLIB::SHL_I128;
1860 } else if (N->getOpcode() == ISD::SRL) {
1863 LC = RTLIB::SRL_I16;
1864 else if (VT == MVT::i32)
1865 LC = RTLIB::SRL_I32;
1866 else if (VT == MVT::i64)
1867 LC = RTLIB::SRL_I64;
1868 else if (VT == MVT::i128)
1869 LC = RTLIB::SRL_I128;
1871 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1874 LC = RTLIB::SRA_I16;
1875 else if (VT == MVT::i32)
1876 LC = RTLIB::SRA_I32;
1877 else if (VT == MVT::i64)
1878 LC = RTLIB::SRA_I64;
1879 else if (VT == MVT::i128)
1880 LC = RTLIB::SRA_I128;
1883 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1884 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1885 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1889 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1890 assert(0 && "Unsupported shift!");
1893 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1894 SDValue &Lo, SDValue &Hi) {
1895 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1896 DebugLoc dl = N->getDebugLoc();
1897 SDValue Op = N->getOperand(0);
1898 if (Op.getValueType().bitsLE(NVT)) {
1899 // The low part is sign extension of the input (degenerates to a copy).
1900 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1901 // The high part is obtained by SRA'ing all but one of the bits of low part.
1902 unsigned LoSize = NVT.getSizeInBits();
1903 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1904 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1906 // For example, extension of an i48 to an i64. The operand type necessarily
1907 // promotes to the result type, so will end up being expanded too.
1908 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1909 "Only know how to promote this result!");
1910 SDValue Res = GetPromotedInteger(Op);
1911 assert(Res.getValueType() == N->getValueType(0) &&
1912 "Operand over promoted?");
1913 // Split the promoted operand. This will simplify when it is expanded.
1914 SplitInteger(Res, Lo, Hi);
1915 unsigned ExcessBits =
1916 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1917 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1918 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1922 void DAGTypeLegalizer::
1923 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1924 DebugLoc dl = N->getDebugLoc();
1925 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1926 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1928 if (EVT.bitsLE(Lo.getValueType())) {
1929 // sext_inreg the low part if needed.
1930 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1933 // The high part gets the sign extension from the lo-part. This handles
1934 // things like sextinreg V:i64 from i8.
1935 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1936 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1937 TLI.getPointerTy()));
1939 // For example, extension of an i48 to an i64. Leave the low part alone,
1940 // sext_inreg the high part.
1941 unsigned ExcessBits =
1942 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1943 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1944 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1948 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1949 SDValue &Lo, SDValue &Hi) {
1950 MVT VT = N->getValueType(0);
1951 DebugLoc dl = N->getDebugLoc();
1953 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1955 LC = RTLIB::SREM_I32;
1956 else if (VT == MVT::i64)
1957 LC = RTLIB::SREM_I64;
1958 else if (VT == MVT::i128)
1959 LC = RTLIB::SREM_I128;
1960 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1962 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1963 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1966 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1967 SDValue &Lo, SDValue &Hi) {
1968 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1969 DebugLoc dl = N->getDebugLoc();
1970 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1971 Hi = DAG.getNode(ISD::SRL, dl,
1972 N->getOperand(0).getValueType(), N->getOperand(0),
1973 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1974 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1977 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1978 SDValue &Lo, SDValue &Hi) {
1979 MVT VT = N->getValueType(0);
1980 DebugLoc dl = N->getDebugLoc();
1982 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1984 LC = RTLIB::UDIV_I32;
1985 else if (VT == MVT::i64)
1986 LC = RTLIB::UDIV_I64;
1987 else if (VT == MVT::i128)
1988 LC = RTLIB::UDIV_I128;
1989 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1991 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1992 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1995 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1996 SDValue &Lo, SDValue &Hi) {
1997 MVT VT = N->getValueType(0);
1998 DebugLoc dl = N->getDebugLoc();
2000 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2002 LC = RTLIB::UREM_I32;
2003 else if (VT == MVT::i64)
2004 LC = RTLIB::UREM_I64;
2005 else if (VT == MVT::i128)
2006 LC = RTLIB::UREM_I128;
2007 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2009 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2010 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2013 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2014 SDValue &Lo, SDValue &Hi) {
2015 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
2016 DebugLoc dl = N->getDebugLoc();
2017 SDValue Op = N->getOperand(0);
2018 if (Op.getValueType().bitsLE(NVT)) {
2019 // The low part is zero extension of the input (degenerates to a copy).
2020 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2021 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2023 // For example, extension of an i48 to an i64. The operand type necessarily
2024 // promotes to the result type, so will end up being expanded too.
2025 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
2026 "Only know how to promote this result!");
2027 SDValue Res = GetPromotedInteger(Op);
2028 assert(Res.getValueType() == N->getValueType(0) &&
2029 "Operand over promoted?");
2030 // Split the promoted operand. This will simplify when it is expanded.
2031 SplitInteger(Res, Lo, Hi);
2032 unsigned ExcessBits =
2033 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2034 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
2039 //===----------------------------------------------------------------------===//
2040 // Integer Operand Expansion
2041 //===----------------------------------------------------------------------===//
2043 /// ExpandIntegerOperand - This method is called when the specified operand of
2044 /// the specified node is found to need expansion. At this point, all of the
2045 /// result types of the node are known to be legal, but other operands of the
2046 /// node may need promotion or expansion as well as the specified one.
2047 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2048 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
2049 SDValue Res = SDValue();
2051 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2054 switch (N->getOpcode()) {
2057 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
2058 N->dump(&DAG); cerr << "\n";
2060 assert(0 && "Do not know how to expand this operator's operand!");
2063 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
2064 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2065 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2066 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2067 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2068 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2069 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2070 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2071 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2072 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2073 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2074 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2080 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2083 // If the result is null, the sub-method took care of registering results etc.
2084 if (!Res.getNode()) return false;
2086 // If the result is N, the sub-method updated N in place. Tell the legalizer
2088 if (Res.getNode() == N)
2091 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2092 "Invalid operand expansion");
2094 ReplaceValueWith(SDValue(N, 0), Res);
2098 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2099 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2100 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2102 ISD::CondCode &CCCode,
2104 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2105 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2106 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2108 MVT VT = NewLHS.getValueType();
2110 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2111 if (RHSLo == RHSHi) {
2112 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2113 if (RHSCST->isAllOnesValue()) {
2114 // Equality comparison to -1.
2115 NewLHS = DAG.getNode(ISD::AND, dl,
2116 LHSLo.getValueType(), LHSLo, LHSHi);
2123 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2124 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2125 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2126 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2130 // If this is a comparison of the sign bit, just look at the top part.
2132 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2133 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2134 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2140 // FIXME: This generated code sucks.
2141 ISD::CondCode LowCC;
2143 default: assert(0 && "Unknown integer setcc!");
2145 case ISD::SETULT: LowCC = ISD::SETULT; break;
2147 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2149 case ISD::SETULE: LowCC = ISD::SETULE; break;
2151 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2154 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2155 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2156 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2158 // NOTE: on targets without efficient SELECT of bools, we can always use
2159 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2160 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2162 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2163 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2164 if (!Tmp1.getNode())
2165 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2166 LHSLo, RHSLo, LowCC);
2167 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2168 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2169 if (!Tmp2.getNode())
2170 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2171 TLI.getSetCCResultType(LHSHi.getValueType()),
2172 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2174 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2175 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2176 if ((Tmp1C && Tmp1C->isNullValue()) ||
2177 (Tmp2C && Tmp2C->isNullValue() &&
2178 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2179 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2180 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2181 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2182 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2183 // low part is known false, returns high part.
2184 // For LE / GE, if high part is known false, ignore the low part.
2185 // For LT / GT, if high part is known true, ignore the low part.
2191 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2192 LHSHi, RHSHi, ISD::SETEQ, false,
2193 DagCombineInfo, dl);
2194 if (!NewLHS.getNode())
2195 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2196 LHSHi, RHSHi, ISD::SETEQ);
2197 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2198 NewLHS, Tmp1, Tmp2);
2202 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2203 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2204 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2205 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2207 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2208 // against zero to select between true and false values.
2209 if (NewRHS.getNode() == 0) {
2210 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2211 CCCode = ISD::SETNE;
2214 // Update N to have the operands specified.
2215 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2216 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2220 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2221 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2222 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2223 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2225 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2226 // against zero to select between true and false values.
2227 if (NewRHS.getNode() == 0) {
2228 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2229 CCCode = ISD::SETNE;
2232 // Update N to have the operands specified.
2233 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2234 N->getOperand(2), N->getOperand(3),
2235 DAG.getCondCode(CCCode));
2238 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2239 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2240 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2241 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2243 // If ExpandSetCCOperands returned a scalar, use it.
2244 if (NewRHS.getNode() == 0) {
2245 assert(NewLHS.getValueType() == N->getValueType(0) &&
2246 "Unexpected setcc expansion!");
2250 // Otherwise, update N to have the operands specified.
2251 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2252 DAG.getCondCode(CCCode));
2255 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2256 // The value being shifted is legal, but the shift amount is too big.
2257 // It follows that either the result of the shift is undefined, or the
2258 // upper half of the shift amount is zero. Just use the lower half.
2260 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2261 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2264 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2265 SDValue Op = N->getOperand(0);
2266 MVT DstVT = N->getValueType(0);
2267 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2268 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2269 "Don't know how to expand this SINT_TO_FP!");
2270 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2273 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2274 if (ISD::isNormalStore(N))
2275 return ExpandOp_NormalStore(N, OpNo);
2277 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2278 assert(OpNo == 1 && "Can only expand the stored value so far");
2280 MVT VT = N->getOperand(1).getValueType();
2281 MVT NVT = TLI.getTypeToTransformTo(VT);
2282 SDValue Ch = N->getChain();
2283 SDValue Ptr = N->getBasePtr();
2284 int SVOffset = N->getSrcValueOffset();
2285 unsigned Alignment = N->getAlignment();
2286 bool isVolatile = N->isVolatile();
2287 DebugLoc dl = N->getDebugLoc();
2290 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2292 if (N->getMemoryVT().bitsLE(NVT)) {
2293 GetExpandedInteger(N->getValue(), Lo, Hi);
2294 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2295 N->getMemoryVT(), isVolatile, Alignment);
2296 } else if (TLI.isLittleEndian()) {
2297 // Little-endian - low bits are at low addresses.
2298 GetExpandedInteger(N->getValue(), Lo, Hi);
2300 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2301 isVolatile, Alignment);
2303 unsigned ExcessBits =
2304 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2305 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2307 // Increment the pointer to the other half.
2308 unsigned IncrementSize = NVT.getSizeInBits()/8;
2309 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2310 DAG.getIntPtrConstant(IncrementSize));
2311 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2312 SVOffset+IncrementSize, NEVT,
2313 isVolatile, MinAlign(Alignment, IncrementSize));
2314 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2316 // Big-endian - high bits are at low addresses. Favor aligned stores at
2317 // the cost of some bit-fiddling.
2318 GetExpandedInteger(N->getValue(), Lo, Hi);
2320 MVT EVT = N->getMemoryVT();
2321 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2322 unsigned IncrementSize = NVT.getSizeInBits()/8;
2323 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2324 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2326 if (ExcessBits < NVT.getSizeInBits()) {
2327 // Transfer high bits from the top of Lo to the bottom of Hi.
2328 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2329 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2330 TLI.getPointerTy()));
2331 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2332 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2333 DAG.getConstant(ExcessBits,
2334 TLI.getPointerTy())));
2337 // Store both the high bits and maybe some of the low bits.
2338 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2339 SVOffset, HiVT, isVolatile, Alignment);
2341 // Increment the pointer to the other half.
2342 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2343 DAG.getIntPtrConstant(IncrementSize));
2344 // Store the lowest ExcessBits bits in the second half.
2345 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2346 SVOffset+IncrementSize,
2347 MVT::getIntegerVT(ExcessBits),
2348 isVolatile, MinAlign(Alignment, IncrementSize));
2349 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2353 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2355 GetExpandedInteger(N->getOperand(0), InL, InH);
2356 // Just truncate the low part of the source.
2357 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2360 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2361 SDValue Op = N->getOperand(0);
2362 MVT SrcVT = Op.getValueType();
2363 MVT DstVT = N->getValueType(0);
2364 DebugLoc dl = N->getDebugLoc();
2366 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2367 // Do a signed conversion then adjust the result.
2368 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2369 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2371 // The result of the signed conversion needs adjusting if the 'sign bit' of
2372 // the incoming integer was set. To handle this, we dynamically test to see
2373 // if it is set, and, if so, add a fudge factor.
2375 const uint64_t F32TwoE32 = 0x4F800000ULL;
2376 const uint64_t F32TwoE64 = 0x5F800000ULL;
2377 const uint64_t F32TwoE128 = 0x7F800000ULL;
2380 if (SrcVT == MVT::i32)
2381 FF = APInt(32, F32TwoE32);
2382 else if (SrcVT == MVT::i64)
2383 FF = APInt(32, F32TwoE64);
2384 else if (SrcVT == MVT::i128)
2385 FF = APInt(32, F32TwoE128);
2387 assert(false && "Unsupported UINT_TO_FP!");
2389 // Check whether the sign bit is set.
2391 GetExpandedInteger(Op, Lo, Hi);
2392 SDValue SignSet = DAG.getSetCC(dl,
2393 TLI.getSetCCResultType(Hi.getValueType()),
2394 Hi, DAG.getConstant(0, Hi.getValueType()),
2397 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2398 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2399 TLI.getPointerTy());
2401 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2402 SDValue Zero = DAG.getIntPtrConstant(0);
2403 SDValue Four = DAG.getIntPtrConstant(4);
2404 if (TLI.isBigEndian()) std::swap(Zero, Four);
2405 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2407 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2408 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2409 Alignment = std::min(Alignment, 4u);
2411 // Load the value out, extending it from f32 to the destination float type.
2412 // FIXME: Avoid the extend by constructing the right constant pool?
2413 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2414 FudgePtr, NULL, 0, MVT::f32,
2416 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2419 // Otherwise, use a libcall.
2420 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2421 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2422 "Don't know how to expand this UINT_TO_FP!");
2423 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);