1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDValue Res = SDValue();
37 // See if the target wants to custom expand this node.
38 if (CustomLowerResults(N, N->getValueType(ResNo), true))
41 switch (N->getOpcode()) {
44 cerr << "PromoteIntegerResult #" << ResNo << ": ";
45 N->dump(&DAG); cerr << "\n";
47 assert(0 && "Do not know how to promote this operator!");
49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
55 case ISD::CONVERT_RNDSAT:
56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
60 case ISD::EXTRACT_VECTOR_ELT:
61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
67 case ISD::SIGN_EXTEND_INREG:
68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
75 case ISD::SIGN_EXTEND:
76 case ISD::ZERO_EXTEND:
77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
102 case ISD::ATOMIC_LOAD_ADD:
103 case ISD::ATOMIC_LOAD_SUB:
104 case ISD::ATOMIC_LOAD_AND:
105 case ISD::ATOMIC_LOAD_OR:
106 case ISD::ATOMIC_LOAD_XOR:
107 case ISD::ATOMIC_LOAD_NAND:
108 case ISD::ATOMIC_LOAD_MIN:
109 case ISD::ATOMIC_LOAD_MAX:
110 case ISD::ATOMIC_LOAD_UMIN:
111 case ISD::ATOMIC_LOAD_UMAX:
112 case ISD::ATOMIC_SWAP:
113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
115 case ISD::ATOMIC_CMP_SWAP:
116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
119 // If the result is null then the sub-method took care of registering it.
121 SetPromotedInteger(SDValue(N, ResNo), Res);
124 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
125 // Sign-extend the new bits, and continue the assertion.
126 SDValue Op = SExtPromotedInteger(N->getOperand(0));
127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
128 Op.getValueType(), Op, N->getOperand(1));
131 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
132 // Zero the new bits, and continue the assertion.
133 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
135 Op.getValueType(), Op, N->getOperand(1));
138 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
139 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
142 N->getChain(), N->getBasePtr(),
143 Op2, N->getSrcValue(), N->getAlignment());
144 // Legalized the chain result - switch anything that used the old chain to
146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
150 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
151 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
152 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
154 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
155 Op2, Op3, N->getSrcValue(), N->getAlignment());
156 // Legalized the chain result - switch anything that used the old chain to
158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
162 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
163 SDValue InOp = N->getOperand(0);
164 MVT InVT = InOp.getValueType();
165 MVT NInVT = TLI.getTypeToTransformTo(InVT);
166 MVT OutVT = N->getValueType(0);
167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
168 DebugLoc dl = N->getDebugLoc();
170 switch (getTypeAction(InVT)) {
172 assert(false && "Unknown type action!");
177 if (NOutVT.bitsEq(NInVT))
178 // The input promotes to the same size. Convert the promoted value.
179 return DAG.getNode(ISD::BIT_CONVERT, dl,
180 NOutVT, GetPromotedInteger(InOp));
183 // Promote the integer operand by hand.
184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
188 case ScalarizeVector:
189 // Convert the element to an integer and promote it by hand.
190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
191 BitConvertToInteger(GetScalarizedVector(InOp)));
193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
194 // pieces of the input into integers and reassemble in the final type.
196 GetSplitVector(N->getOperand(0), Lo, Hi);
197 Lo = BitConvertToInteger(Lo);
198 Hi = BitConvertToInteger(Hi);
200 if (TLI.isBigEndian())
203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
204 MVT::getIntegerVT(NOutVT.getSizeInBits()),
205 JoinIntegers(Lo, Hi));
206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
209 if (OutVT.bitsEq(NInVT))
210 // The input is widened to the same size. Convert to the widened value.
211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
214 // Otherwise, lower the bit-convert to a store/load from the stack.
215 // Create the stack frame object. Make sure it is aligned for both
216 // the source and destination types.
217 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT);
218 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
219 const Value *SV = PseudoSourceValue::getFixedStack(FI);
221 // Emit a store to the stack slot.
222 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
224 // Result is an extending load from the stack slot.
225 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT);
228 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
229 SDValue Op = GetPromotedInteger(N->getOperand(0));
230 MVT OVT = N->getValueType(0);
231 MVT NVT = Op.getValueType();
232 DebugLoc dl = N->getDebugLoc();
234 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
235 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
236 DAG.getConstant(DiffBits, TLI.getPointerTy()));
239 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
240 // The pair element type may be legal, or may not promote to the same type as
241 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
242 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
243 TLI.getTypeToTransformTo(N->getValueType(0)),
244 JoinIntegers(N->getOperand(0), N->getOperand(1)));
247 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
248 MVT VT = N->getValueType(0);
249 // FIXME there is no actual debug info here
250 DebugLoc dl = N->getDebugLoc();
251 // Zero extend things like i1, sign extend everything else. It shouldn't
252 // matter in theory which one we pick, but this tends to give better code?
253 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
254 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
256 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
260 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
261 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
262 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
263 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
264 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
265 "can only promote integers");
266 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
267 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
268 N->getOperand(1), N->getOperand(2),
269 N->getOperand(3), N->getOperand(4), CvtCode);
272 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
273 // Zero extend to the promoted type and do the count there.
274 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
275 DebugLoc dl = N->getDebugLoc();
276 MVT OVT = N->getValueType(0);
277 MVT NVT = Op.getValueType();
278 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
279 // Subtract off the extra leading bits in the bigger type.
280 return DAG.getNode(ISD::SUB, dl, NVT, Op,
281 DAG.getConstant(NVT.getSizeInBits() -
282 OVT.getSizeInBits(), NVT));
285 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
286 // Zero extend to the promoted type and do the count there.
287 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
288 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
291 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
292 SDValue Op = GetPromotedInteger(N->getOperand(0));
293 MVT OVT = N->getValueType(0);
294 MVT NVT = Op.getValueType();
295 DebugLoc dl = N->getDebugLoc();
296 // The count is the same in the promoted type except if the original
297 // value was zero. This can be handled by setting the bit just off
298 // the top of the original type.
299 APInt TopBit(NVT.getSizeInBits(), 0);
300 TopBit.set(OVT.getSizeInBits());
301 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
302 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
305 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
306 MVT OldVT = N->getValueType(0);
307 SDValue OldVec = N->getOperand(0);
308 if (getTypeAction(OldVec.getValueType()) == WidenVector)
309 OldVec = GetWidenedVector(N->getOperand(0));
310 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
311 DebugLoc dl = N->getDebugLoc();
314 assert(!isTypeLegal(OldVec.getValueType()) &&
315 "Legal one-element vector of a type needing promotion!");
316 // It is tempting to follow GetScalarizedVector by a call to
317 // GetPromotedInteger, but this would be wrong because the
318 // scalarized value may not yet have been processed.
319 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT),
320 GetScalarizedVector(OldVec));
323 // Convert to a vector half as long with an element type of twice the width,
324 // for example <4 x i16> -> <2 x i32>.
325 assert(!(OldElts & 1) && "Odd length vectors not supported!");
326 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
327 assert(OldVT.isSimple() && NewVT.isSimple());
329 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
330 MVT::getVectorVT(NewVT, OldElts / 2),
333 // Extract the element at OldIdx / 2 from the new vector.
334 SDValue OldIdx = N->getOperand(1);
335 SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx,
336 DAG.getConstant(1, TLI.getPointerTy()));
337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx);
339 // Select the appropriate half of the element: Lo if OldIdx was even,
342 SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt,
343 DAG.getConstant(OldVT.getSizeInBits(),
344 TLI.getPointerTy()));
345 if (TLI.isBigEndian())
348 // Extend to the promoted type.
349 SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx);
350 SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo);
351 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res);
354 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
355 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
356 unsigned NewOpc = N->getOpcode();
357 DebugLoc dl = N->getDebugLoc();
359 // If we're promoting a UINT to a larger size, check to see if the new node
360 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
361 // we can use that instead. This allows us to generate better code for
362 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
363 // legal, such as PowerPC.
364 if (N->getOpcode() == ISD::FP_TO_UINT &&
365 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
366 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
367 NewOpc = ISD::FP_TO_SINT;
369 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
371 // Assert that the converted value fits in the original type. If it doesn't
372 // (eg: because the value being converted is too big), then the result of the
373 // original operation was undefined anyway, so the assert is still correct.
374 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
375 ISD::AssertZext : ISD::AssertSext, dl,
376 NVT, Res, DAG.getValueType(N->getValueType(0)));
379 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
380 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
381 DebugLoc dl = N->getDebugLoc();
383 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
384 SDValue Res = GetPromotedInteger(N->getOperand(0));
385 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
387 // If the result and operand types are the same after promotion, simplify
388 // to an in-register extension.
389 if (NVT == Res.getValueType()) {
390 // The high bits are not guaranteed to be anything. Insert an extend.
391 if (N->getOpcode() == ISD::SIGN_EXTEND)
392 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
393 DAG.getValueType(N->getOperand(0).getValueType()));
394 if (N->getOpcode() == ISD::ZERO_EXTEND)
395 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
396 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
401 // Otherwise, just extend the original operand all the way to the larger type.
402 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
405 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
406 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
407 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
408 ISD::LoadExtType ExtType =
409 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
410 DebugLoc dl = N->getDebugLoc();
411 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
412 N->getSrcValue(), N->getSrcValueOffset(),
413 N->getMemoryVT(), N->isVolatile(),
416 // Legalized the chain result - switch anything that used the old chain to
418 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
422 /// Promote the overflow flag of an overflowing arithmetic node.
423 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
424 // Simply change the return type of the boolean result.
425 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
426 MVT ValueVTs[] = { N->getValueType(0), NVT };
427 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
428 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
429 DAG.getVTList(ValueVTs, 2), Ops, 2);
431 // Modified the sum result - switch anything that used the old sum to use
433 ReplaceValueWith(SDValue(N, 0), Res);
435 return SDValue(Res.getNode(), 1);
438 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
440 return PromoteIntRes_Overflow(N);
442 // The operation overflowed iff the result in the larger type is not the
443 // sign extension of its truncation to the original type.
444 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
445 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
446 MVT OVT = N->getOperand(0).getValueType();
447 MVT NVT = LHS.getValueType();
448 DebugLoc dl = N->getDebugLoc();
450 // Do the arithmetic in the larger type.
451 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
452 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
454 // Calculate the overflow flag: sign extend the arithmetic result from
455 // the original type.
456 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
457 DAG.getValueType(OVT));
458 // Overflowed if and only if this is not equal to Res.
459 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
461 // Use the calculated overflow everywhere.
462 ReplaceValueWith(SDValue(N, 1), Ofl);
467 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
468 // Sign extend the input.
469 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
470 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
471 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
472 LHS.getValueType(), LHS, RHS);
475 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
476 SDValue LHS = GetPromotedInteger(N->getOperand(1));
477 SDValue RHS = GetPromotedInteger(N->getOperand(2));
478 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
479 LHS.getValueType(), N->getOperand(0),LHS,RHS);
482 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
483 SDValue LHS = GetPromotedInteger(N->getOperand(2));
484 SDValue RHS = GetPromotedInteger(N->getOperand(3));
485 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
486 LHS.getValueType(), N->getOperand(0),
487 N->getOperand(1), LHS, RHS, N->getOperand(4));
490 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
491 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
492 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
493 DebugLoc dl = N->getDebugLoc();
495 // Get the SETCC result using the canonical SETCC type.
496 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
497 N->getOperand(1), N->getOperand(2));
499 // Convert to the expected type.
500 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
501 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
502 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
505 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
506 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
507 TLI.getTypeToTransformTo(N->getValueType(0)),
508 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
511 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
512 SDValue Op = GetPromotedInteger(N->getOperand(0));
513 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
514 Op.getValueType(), Op, N->getOperand(1));
517 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
518 // The input may have strange things in the top bits of the registers, but
519 // these operations don't care. They may have weird bits going out, but
520 // that too is okay if they are integer operations.
521 SDValue LHS = GetPromotedInteger(N->getOperand(0));
522 SDValue RHS = GetPromotedInteger(N->getOperand(1));
523 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
524 LHS.getValueType(), LHS, RHS);
527 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
528 // The input value must be properly sign extended.
529 SDValue Res = SExtPromotedInteger(N->getOperand(0));
530 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
531 Res.getValueType(), Res, N->getOperand(1));
534 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
535 // The input value must be properly zero extended.
536 MVT VT = N->getValueType(0);
537 MVT NVT = TLI.getTypeToTransformTo(VT);
538 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
539 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
542 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
543 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
546 switch (getTypeAction(N->getOperand(0).getValueType())) {
547 default: assert(0 && "Unknown type action!");
550 Res = N->getOperand(0);
553 Res = GetPromotedInteger(N->getOperand(0));
557 // Truncate to NVT instead of VT
558 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
561 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
563 return PromoteIntRes_Overflow(N);
565 // The operation overflowed iff the result in the larger type is not the
566 // zero extension of its truncation to the original type.
567 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
568 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
569 MVT OVT = N->getOperand(0).getValueType();
570 MVT NVT = LHS.getValueType();
571 DebugLoc dl = N->getDebugLoc();
573 // Do the arithmetic in the larger type.
574 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
575 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
577 // Calculate the overflow flag: zero extend the arithmetic result from
578 // the original type.
579 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
580 // Overflowed if and only if this is not equal to Res.
581 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
583 // Use the calculated overflow everywhere.
584 ReplaceValueWith(SDValue(N, 1), Ofl);
589 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
590 // Zero extend the input.
591 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
592 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
593 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
594 LHS.getValueType(), LHS, RHS);
597 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
598 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
601 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
602 SDValue Chain = N->getOperand(0); // Get the chain.
603 SDValue Ptr = N->getOperand(1); // Get the pointer.
604 MVT VT = N->getValueType(0);
605 DebugLoc dl = N->getDebugLoc();
607 MVT RegVT = TLI.getRegisterType(VT);
608 unsigned NumRegs = TLI.getNumRegisters(VT);
609 // The argument is passed as NumRegs registers of type RegVT.
611 SmallVector<SDValue, 8> Parts(NumRegs);
612 for (unsigned i = 0; i < NumRegs; ++i) {
613 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
614 Chain = Parts[i].getValue(1);
617 // Handle endianness of the load.
618 if (TLI.isBigEndian())
619 std::reverse(Parts.begin(), Parts.end());
621 // Assemble the parts in the promoted type.
622 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
623 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
624 for (unsigned i = 1; i < NumRegs; ++i) {
625 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
626 // Shift it to the right position and "or" it in.
627 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
628 DAG.getConstant(i * RegVT.getSizeInBits(),
629 TLI.getPointerTy()));
630 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
633 // Modified the chain result - switch anything that used the old chain to
635 ReplaceValueWith(SDValue(N, 1), Chain);
640 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
641 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
642 return PromoteIntRes_Overflow(N);
645 //===----------------------------------------------------------------------===//
646 // Integer Operand Promotion
647 //===----------------------------------------------------------------------===//
649 /// PromoteIntegerOperand - This method is called when the specified operand of
650 /// the specified node is found to need promotion. At this point, all of the
651 /// result types of the node are known to be legal, but other operands of the
652 /// node may need promotion or expansion as well as the specified one.
653 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
654 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
655 SDValue Res = SDValue();
657 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
660 switch (N->getOpcode()) {
663 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
664 N->dump(&DAG); cerr << "\n";
666 assert(0 && "Do not know how to promote this operator's operand!");
669 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
670 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
671 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
672 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
673 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
674 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
675 case ISD::CONVERT_RNDSAT:
676 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
677 case ISD::INSERT_VECTOR_ELT:
678 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
679 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
680 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
681 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
682 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
683 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
684 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
685 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
687 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
688 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
689 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
695 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
698 // If the result is null, the sub-method took care of registering results etc.
699 if (!Res.getNode()) return false;
701 // If the result is N, the sub-method updated N in place. Tell the legalizer
703 if (Res.getNode() == N)
706 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
707 "Invalid operand expansion");
709 ReplaceValueWith(SDValue(N, 0), Res);
713 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
714 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
715 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
716 ISD::CondCode CCCode) {
717 // We have to insert explicit sign or zero extends. Note that we could
718 // insert sign extends for ALL conditions, but zero extend is cheaper on
719 // many machines (an AND instead of two shifts), so prefer it.
721 default: assert(0 && "Unknown integer comparison!");
728 // ALL of these operations will work if we either sign or zero extend
729 // the operands (including the unsigned comparisons!). Zero extend is
730 // usually a simpler/cheaper operation, so prefer it.
731 NewLHS = ZExtPromotedInteger(NewLHS);
732 NewRHS = ZExtPromotedInteger(NewRHS);
738 NewLHS = SExtPromotedInteger(NewLHS);
739 NewRHS = SExtPromotedInteger(NewRHS);
744 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
745 SDValue Op = GetPromotedInteger(N->getOperand(0));
746 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
749 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
750 // This should only occur in unusual situations like bitcasting to an
751 // x86_fp80, so just turn it into a store+load
752 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
755 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
756 assert(OpNo == 2 && "Don't know how to promote this operand!");
758 SDValue LHS = N->getOperand(2);
759 SDValue RHS = N->getOperand(3);
760 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
762 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
764 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
765 N->getOperand(1), LHS, RHS, N->getOperand(4));
768 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
769 assert(OpNo == 1 && "only know how to promote condition");
771 // Promote all the way up to the canonical SetCC type.
772 MVT SVT = TLI.getSetCCResultType(MVT::Other);
773 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
775 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
776 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
780 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
781 // Since the result type is legal, the operands must promote to it.
782 MVT OVT = N->getOperand(0).getValueType();
783 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
784 SDValue Hi = GetPromotedInteger(N->getOperand(1));
785 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
786 DebugLoc dl = N->getDebugLoc();
788 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
789 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
790 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
793 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
794 // The vector type is legal but the element type is not. This implies
795 // that the vector is a power-of-two in length and that the element
796 // type does not have a strange size (eg: it is not i1).
797 MVT VecVT = N->getValueType(0);
798 unsigned NumElts = VecVT.getVectorNumElements();
799 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
800 DebugLoc dl = N->getDebugLoc();
802 // Build a vector of half the length out of elements of twice the bitwidth.
803 // For example <4 x i16> -> <2 x i32>.
804 MVT OldVT = N->getOperand(0).getValueType();
805 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
806 assert(OldVT.isSimple() && NewVT.isSimple());
808 std::vector<SDValue> NewElts;
809 NewElts.reserve(NumElts/2);
811 for (unsigned i = 0; i < NumElts; i += 2) {
812 // Combine two successive elements into one promoted element.
813 SDValue Lo = N->getOperand(i);
814 SDValue Hi = N->getOperand(i+1);
815 if (TLI.isBigEndian())
817 NewElts.push_back(JoinIntegers(Lo, Hi));
820 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
821 MVT::getVectorVT(NewVT, NewElts.size()),
822 &NewElts[0], NewElts.size());
824 // Convert the new vector to the old vector type.
825 return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec);
828 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
829 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
830 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
831 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
832 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
833 "can only promote integer arguments");
834 SDValue InOp = GetPromotedInteger(N->getOperand(0));
835 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
836 N->getOperand(1), N->getOperand(2),
837 N->getOperand(3), N->getOperand(4), CvtCode);
840 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
843 // Promote the inserted value. This is valid because the type does not
844 // have to match the vector element type.
846 // Check that any extra bits introduced will be truncated away.
847 assert(N->getOperand(1).getValueType().getSizeInBits() >=
848 N->getValueType(0).getVectorElementType().getSizeInBits() &&
849 "Type of inserted value narrower than vector element type!");
850 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
851 GetPromotedInteger(N->getOperand(1)),
855 assert(OpNo == 2 && "Different operand and result vector types?");
857 // Promote the index.
858 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
859 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
860 N->getOperand(1), Idx);
863 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
865 DebugLoc dl = N->getDebugLoc();
866 NewOps[0] = N->getOperand(0);
867 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
868 SDValue Flag = GetPromotedInteger(N->getOperand(i));
869 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
871 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
872 array_lengthof(NewOps));
875 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
876 assert(OpNo == 0 && "Only know how to promote condition");
878 // Promote all the way up to the canonical SetCC type.
879 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
880 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
882 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
883 N->getOperand(1), N->getOperand(2));
886 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
887 assert(OpNo == 0 && "Don't know how to promote this operand!");
889 SDValue LHS = N->getOperand(0);
890 SDValue RHS = N->getOperand(1);
891 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
893 // The CC (#4) and the possible return values (#2 and #3) have legal types.
894 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
895 N->getOperand(3), N->getOperand(4));
898 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
899 assert(OpNo == 0 && "Don't know how to promote this operand!");
901 SDValue LHS = N->getOperand(0);
902 SDValue RHS = N->getOperand(1);
903 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
905 // The CC (#2) is always legal.
906 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
909 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
910 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
911 ZExtPromotedInteger(N->getOperand(1)));
914 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
915 SDValue Op = GetPromotedInteger(N->getOperand(0));
916 DebugLoc dl = N->getDebugLoc();
917 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
918 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
919 Op, DAG.getValueType(N->getOperand(0).getValueType()));
922 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
923 return DAG.UpdateNodeOperands(SDValue(N, 0),
924 SExtPromotedInteger(N->getOperand(0)));
927 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
928 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
929 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
930 int SVOffset = N->getSrcValueOffset();
931 unsigned Alignment = N->getAlignment();
932 bool isVolatile = N->isVolatile();
933 DebugLoc dl = N->getDebugLoc();
935 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
937 // Truncate the value and store the result.
938 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
939 SVOffset, N->getMemoryVT(),
940 isVolatile, Alignment);
943 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
944 SDValue Op = GetPromotedInteger(N->getOperand(0));
945 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
948 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
949 return DAG.UpdateNodeOperands(SDValue(N, 0),
950 ZExtPromotedInteger(N->getOperand(0)));
953 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
954 DebugLoc dl = N->getDebugLoc();
955 SDValue Op = GetPromotedInteger(N->getOperand(0));
956 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
957 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
961 //===----------------------------------------------------------------------===//
962 // Integer Result Expansion
963 //===----------------------------------------------------------------------===//
965 /// ExpandIntegerResult - This method is called when the specified result of the
966 /// specified node is found to need expansion. At this point, the node may also
967 /// have invalid operands or may have other results that need promotion, we just
968 /// know that (at least) one result needs expansion.
969 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
970 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
974 // See if the target wants to custom expand this node.
975 if (CustomLowerResults(N, N->getValueType(ResNo), true))
978 switch (N->getOpcode()) {
981 cerr << "ExpandIntegerResult #" << ResNo << ": ";
982 N->dump(&DAG); cerr << "\n";
984 assert(0 && "Do not know how to expand the result of this operator!");
987 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
988 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
989 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
990 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
992 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
993 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
994 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
995 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
996 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
998 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
999 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1000 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1001 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1002 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1003 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1004 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1005 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1006 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1007 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1008 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1009 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1010 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1011 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1012 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1013 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1014 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1015 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1016 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1017 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1021 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1024 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1027 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1030 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1034 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1037 // If Lo/Hi is null, the sub-method took care of registering results etc.
1039 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1042 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1043 /// and the shift amount is a constant 'Amt'. Expand the operation.
1044 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1045 SDValue &Lo, SDValue &Hi) {
1046 DebugLoc dl = N->getDebugLoc();
1047 // Expand the incoming operand to be shifted, so that we have its parts
1049 GetExpandedInteger(N->getOperand(0), InL, InH);
1051 MVT NVT = InL.getValueType();
1052 unsigned VTBits = N->getValueType(0).getSizeInBits();
1053 unsigned NVTBits = NVT.getSizeInBits();
1054 MVT ShTy = N->getOperand(1).getValueType();
1056 if (N->getOpcode() == ISD::SHL) {
1058 Lo = Hi = DAG.getConstant(0, NVT);
1059 } else if (Amt > NVTBits) {
1060 Lo = DAG.getConstant(0, NVT);
1061 Hi = DAG.getNode(ISD::SHL, dl,
1062 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1063 } else if (Amt == NVTBits) {
1064 Lo = DAG.getConstant(0, NVT);
1066 } else if (Amt == 1 &&
1067 TLI.isOperationLegalOrCustom(ISD::ADDC,
1068 TLI.getTypeToExpandTo(NVT))) {
1069 // Emit this X << 1 as X+X.
1070 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1071 SDValue LoOps[2] = { InL, InL };
1072 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1073 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1074 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1076 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1077 Hi = DAG.getNode(ISD::OR, dl, NVT,
1078 DAG.getNode(ISD::SHL, dl, NVT, InH,
1079 DAG.getConstant(Amt, ShTy)),
1080 DAG.getNode(ISD::SRL, dl, NVT, InL,
1081 DAG.getConstant(NVTBits-Amt, ShTy)));
1086 if (N->getOpcode() == ISD::SRL) {
1088 Lo = DAG.getConstant(0, NVT);
1089 Hi = DAG.getConstant(0, NVT);
1090 } else if (Amt > NVTBits) {
1091 Lo = DAG.getNode(ISD::SRL, dl,
1092 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1093 Hi = DAG.getConstant(0, NVT);
1094 } else if (Amt == NVTBits) {
1096 Hi = DAG.getConstant(0, NVT);
1098 Lo = DAG.getNode(ISD::OR, dl, NVT,
1099 DAG.getNode(ISD::SRL, dl, NVT, InL,
1100 DAG.getConstant(Amt, ShTy)),
1101 DAG.getNode(ISD::SHL, dl, NVT, InH,
1102 DAG.getConstant(NVTBits-Amt, ShTy)));
1103 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1108 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1110 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1111 DAG.getConstant(NVTBits-1, ShTy));
1112 } else if (Amt > NVTBits) {
1113 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1114 DAG.getConstant(Amt-NVTBits, ShTy));
1115 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1116 DAG.getConstant(NVTBits-1, ShTy));
1117 } else if (Amt == NVTBits) {
1119 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1120 DAG.getConstant(NVTBits-1, ShTy));
1122 Lo = DAG.getNode(ISD::OR, dl, NVT,
1123 DAG.getNode(ISD::SRL, dl, NVT, InL,
1124 DAG.getConstant(Amt, ShTy)),
1125 DAG.getNode(ISD::SHL, dl, NVT, InH,
1126 DAG.getConstant(NVTBits-Amt, ShTy)));
1127 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1131 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1132 /// this shift based on knowledge of the high bit of the shift amount. If we
1133 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1135 bool DAGTypeLegalizer::
1136 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1137 SDValue Amt = N->getOperand(1);
1138 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1139 MVT ShTy = Amt.getValueType();
1140 unsigned ShBits = ShTy.getSizeInBits();
1141 unsigned NVTBits = NVT.getSizeInBits();
1142 assert(isPowerOf2_32(NVTBits) &&
1143 "Expanded integer type size not a power of two!");
1144 DebugLoc dl = N->getDebugLoc();
1146 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1147 APInt KnownZero, KnownOne;
1148 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1150 // If we don't know anything about the high bits, exit.
1151 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1154 // Get the incoming operand to be shifted.
1156 GetExpandedInteger(N->getOperand(0), InL, InH);
1158 // If we know that any of the high bits of the shift amount are one, then we
1159 // can do this as a couple of simple shifts.
1160 if (KnownOne.intersects(HighBitMask)) {
1161 // Mask out the high bit, which we know is set.
1162 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1163 DAG.getConstant(~HighBitMask, ShTy));
1165 switch (N->getOpcode()) {
1166 default: assert(0 && "Unknown shift");
1168 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1169 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1172 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1173 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1176 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1177 DAG.getConstant(NVTBits-1, ShTy));
1178 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1184 // FIXME: This code is broken for shifts with a zero amount!
1185 // If we know that all of the high bits of the shift amount are zero, then we
1186 // can do this as a couple of simple shifts.
1187 if ((KnownZero & HighBitMask) == HighBitMask) {
1189 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1190 DAG.getConstant(NVTBits, ShTy),
1193 switch (N->getOpcode()) {
1194 default: assert(0 && "Unknown shift");
1195 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1197 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1200 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1201 Hi = DAG.getNode(ISD::OR, NVT,
1202 DAG.getNode(Op1, NVT, InH, Amt),
1203 DAG.getNode(Op2, NVT, InL, Amt2));
1211 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1212 SDValue &Lo, SDValue &Hi) {
1213 DebugLoc dl = N->getDebugLoc();
1214 // Expand the subcomponents.
1215 SDValue LHSL, LHSH, RHSL, RHSH;
1216 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1217 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1219 MVT NVT = LHSL.getValueType();
1220 SDValue LoOps[2] = { LHSL, RHSL };
1221 SDValue HiOps[3] = { LHSH, RHSH };
1223 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1224 // them. TODO: Teach operation legalization how to expand unsupported
1225 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1226 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1227 // generate a value of this type in the expanded code sequence.
1229 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1230 ISD::ADDC : ISD::SUBC,
1231 TLI.getTypeToExpandTo(NVT));
1234 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1235 if (N->getOpcode() == ISD::ADD) {
1236 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1237 HiOps[2] = Lo.getValue(1);
1238 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1240 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1241 HiOps[2] = Lo.getValue(1);
1242 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1245 if (N->getOpcode() == ISD::ADD) {
1246 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1247 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1248 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1250 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1251 DAG.getConstant(1, NVT),
1252 DAG.getConstant(0, NVT));
1253 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1255 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1256 DAG.getConstant(1, NVT), Carry1);
1257 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1259 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1260 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1262 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1263 LoOps[0], LoOps[1], ISD::SETULT);
1264 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1265 DAG.getConstant(1, NVT),
1266 DAG.getConstant(0, NVT));
1267 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1272 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1273 SDValue &Lo, SDValue &Hi) {
1274 // Expand the subcomponents.
1275 SDValue LHSL, LHSH, RHSL, RHSH;
1276 DebugLoc dl = N->getDebugLoc();
1277 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1278 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1279 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1280 SDValue LoOps[2] = { LHSL, RHSL };
1281 SDValue HiOps[3] = { LHSH, RHSH };
1283 if (N->getOpcode() == ISD::ADDC) {
1284 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1285 HiOps[2] = Lo.getValue(1);
1286 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1288 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1289 HiOps[2] = Lo.getValue(1);
1290 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1293 // Legalized the flag result - switch anything that used the old flag to
1295 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1298 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1299 SDValue &Lo, SDValue &Hi) {
1300 // Expand the subcomponents.
1301 SDValue LHSL, LHSH, RHSL, RHSH;
1302 DebugLoc dl = N->getDebugLoc();
1303 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1304 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1305 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1306 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1307 SDValue HiOps[3] = { LHSH, RHSH };
1309 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1310 HiOps[2] = Lo.getValue(1);
1311 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1313 // Legalized the flag result - switch anything that used the old flag to
1315 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1318 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1319 SDValue &Lo, SDValue &Hi) {
1320 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1321 DebugLoc dl = N->getDebugLoc();
1322 SDValue Op = N->getOperand(0);
1323 if (Op.getValueType().bitsLE(NVT)) {
1324 // The low part is any extension of the input (which degenerates to a copy).
1325 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1326 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1328 // For example, extension of an i48 to an i64. The operand type necessarily
1329 // promotes to the result type, so will end up being expanded too.
1330 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1331 "Only know how to promote this result!");
1332 SDValue Res = GetPromotedInteger(Op);
1333 assert(Res.getValueType() == N->getValueType(0) &&
1334 "Operand over promoted?");
1335 // Split the promoted operand. This will simplify when it is expanded.
1336 SplitInteger(Res, Lo, Hi);
1340 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1341 SDValue &Lo, SDValue &Hi) {
1342 DebugLoc dl = N->getDebugLoc();
1343 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1344 MVT NVT = Lo.getValueType();
1345 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1346 unsigned NVTBits = NVT.getSizeInBits();
1347 unsigned EVTBits = EVT.getSizeInBits();
1349 if (NVTBits < EVTBits) {
1350 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1351 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1353 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1354 // The high part replicates the sign bit of Lo, make it explicit.
1355 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1356 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1360 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1361 SDValue &Lo, SDValue &Hi) {
1362 DebugLoc dl = N->getDebugLoc();
1363 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1364 MVT NVT = Lo.getValueType();
1365 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1366 unsigned NVTBits = NVT.getSizeInBits();
1367 unsigned EVTBits = EVT.getSizeInBits();
1369 if (NVTBits < EVTBits) {
1370 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1371 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1373 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1374 // The high part must be zero, make it explicit.
1375 Hi = DAG.getConstant(0, NVT);
1379 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1380 SDValue &Lo, SDValue &Hi) {
1381 DebugLoc dl = N->getDebugLoc();
1382 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1383 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1384 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1387 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1388 SDValue &Lo, SDValue &Hi) {
1389 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1390 unsigned NBitWidth = NVT.getSizeInBits();
1391 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1392 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1393 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1396 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1397 SDValue &Lo, SDValue &Hi) {
1398 DebugLoc dl = N->getDebugLoc();
1399 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1400 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1401 MVT NVT = Lo.getValueType();
1403 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1404 DAG.getConstant(0, NVT), ISD::SETNE);
1406 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1407 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1409 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1410 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1411 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1412 Hi = DAG.getConstant(0, NVT);
1415 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1416 SDValue &Lo, SDValue &Hi) {
1417 DebugLoc dl = N->getDebugLoc();
1418 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1419 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1420 MVT NVT = Lo.getValueType();
1421 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1422 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1423 Hi = DAG.getConstant(0, NVT);
1426 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1427 SDValue &Lo, SDValue &Hi) {
1428 DebugLoc dl = N->getDebugLoc();
1429 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1430 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1431 MVT NVT = Lo.getValueType();
1433 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1434 DAG.getConstant(0, NVT), ISD::SETNE);
1436 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1437 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1439 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1440 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1441 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1442 Hi = DAG.getConstant(0, NVT);
1445 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1447 DebugLoc dl = N->getDebugLoc();
1448 MVT VT = N->getValueType(0);
1449 SDValue Op = N->getOperand(0);
1450 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1451 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1452 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1455 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1457 DebugLoc dl = N->getDebugLoc();
1458 MVT VT = N->getValueType(0);
1459 SDValue Op = N->getOperand(0);
1460 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1461 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1462 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1465 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1466 SDValue &Lo, SDValue &Hi) {
1467 if (ISD::isNormalLoad(N)) {
1468 ExpandRes_NormalLoad(N, Lo, Hi);
1472 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1474 MVT VT = N->getValueType(0);
1475 MVT NVT = TLI.getTypeToTransformTo(VT);
1476 SDValue Ch = N->getChain();
1477 SDValue Ptr = N->getBasePtr();
1478 ISD::LoadExtType ExtType = N->getExtensionType();
1479 int SVOffset = N->getSrcValueOffset();
1480 unsigned Alignment = N->getAlignment();
1481 bool isVolatile = N->isVolatile();
1482 DebugLoc dl = N->getDebugLoc();
1484 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1486 if (N->getMemoryVT().bitsLE(NVT)) {
1487 MVT EVT = N->getMemoryVT();
1489 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1490 EVT, isVolatile, Alignment);
1492 // Remember the chain.
1493 Ch = Lo.getValue(1);
1495 if (ExtType == ISD::SEXTLOAD) {
1496 // The high part is obtained by SRA'ing all but one of the bits of the
1498 unsigned LoSize = Lo.getValueType().getSizeInBits();
1499 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1500 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1501 } else if (ExtType == ISD::ZEXTLOAD) {
1502 // The high part is just a zero.
1503 Hi = DAG.getConstant(0, NVT);
1505 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1506 // The high part is undefined.
1507 Hi = DAG.getUNDEF(NVT);
1509 } else if (TLI.isLittleEndian()) {
1510 // Little-endian - low bits are at low addresses.
1511 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1512 isVolatile, Alignment);
1514 unsigned ExcessBits =
1515 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1516 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1518 // Increment the pointer to the other half.
1519 unsigned IncrementSize = NVT.getSizeInBits()/8;
1520 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1521 DAG.getIntPtrConstant(IncrementSize));
1522 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1523 SVOffset+IncrementSize, NEVT,
1524 isVolatile, MinAlign(Alignment, IncrementSize));
1526 // Build a factor node to remember that this load is independent of the
1528 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1531 // Big-endian - high bits are at low addresses. Favor aligned loads at
1532 // the cost of some bit-fiddling.
1533 MVT EVT = N->getMemoryVT();
1534 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1535 unsigned IncrementSize = NVT.getSizeInBits()/8;
1536 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1538 // Load both the high bits and maybe some of the low bits.
1539 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1540 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1541 isVolatile, Alignment);
1543 // Increment the pointer to the other half.
1544 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1545 DAG.getIntPtrConstant(IncrementSize));
1546 // Load the rest of the low bits.
1547 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1548 SVOffset+IncrementSize,
1549 MVT::getIntegerVT(ExcessBits),
1550 isVolatile, MinAlign(Alignment, IncrementSize));
1552 // Build a factor node to remember that this load is independent of the
1554 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1557 if (ExcessBits < NVT.getSizeInBits()) {
1558 // Transfer low bits from the bottom of Hi to the top of Lo.
1559 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1560 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1561 DAG.getConstant(ExcessBits,
1562 TLI.getPointerTy())));
1563 // Move high bits to the right position in Hi.
1564 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1566 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1567 TLI.getPointerTy()));
1571 // Legalized the chain result - switch anything that used the old chain to
1573 ReplaceValueWith(SDValue(N, 1), Ch);
1576 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1577 SDValue &Lo, SDValue &Hi) {
1578 DebugLoc dl = N->getDebugLoc();
1579 SDValue LL, LH, RL, RH;
1580 GetExpandedInteger(N->getOperand(0), LL, LH);
1581 GetExpandedInteger(N->getOperand(1), RL, RH);
1582 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1583 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1586 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1587 SDValue &Lo, SDValue &Hi) {
1588 MVT VT = N->getValueType(0);
1589 MVT NVT = TLI.getTypeToTransformTo(VT);
1590 DebugLoc dl = N->getDebugLoc();
1592 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1593 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1594 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1595 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1596 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1597 SDValue LL, LH, RL, RH;
1598 GetExpandedInteger(N->getOperand(0), LL, LH);
1599 GetExpandedInteger(N->getOperand(1), RL, RH);
1600 unsigned OuterBitSize = VT.getSizeInBits();
1601 unsigned InnerBitSize = NVT.getSizeInBits();
1602 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1603 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1605 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1606 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1607 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1608 // The inputs are both zero-extended.
1610 // We can emit a umul_lohi.
1611 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1612 Hi = SDValue(Lo.getNode(), 1);
1616 // We can emit a mulhu+mul.
1617 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1618 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1622 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1623 // The input values are both sign-extended.
1625 // We can emit a smul_lohi.
1626 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1627 Hi = SDValue(Lo.getNode(), 1);
1631 // We can emit a mulhs+mul.
1632 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1633 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1638 // Lo,Hi = umul LHS, RHS.
1639 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1640 DAG.getVTList(NVT, NVT), LL, RL);
1642 Hi = UMulLOHI.getValue(1);
1643 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1644 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1645 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1646 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1650 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1651 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1652 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1653 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1654 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1655 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1660 // If nothing else, we can make a libcall.
1661 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1663 LC = RTLIB::MUL_I16;
1664 else if (VT == MVT::i32)
1665 LC = RTLIB::MUL_I32;
1666 else if (VT == MVT::i64)
1667 LC = RTLIB::MUL_I64;
1668 else if (VT == MVT::i128)
1669 LC = RTLIB::MUL_I128;
1670 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1672 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1673 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1676 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1677 SDValue &Lo, SDValue &Hi) {
1678 MVT VT = N->getValueType(0);
1679 DebugLoc dl = N->getDebugLoc();
1681 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1683 LC = RTLIB::SDIV_I32;
1684 else if (VT == MVT::i64)
1685 LC = RTLIB::SDIV_I64;
1686 else if (VT == MVT::i128)
1687 LC = RTLIB::SDIV_I128;
1688 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1690 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1691 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1694 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1695 SDValue &Lo, SDValue &Hi) {
1696 MVT VT = N->getValueType(0);
1697 DebugLoc dl = N->getDebugLoc();
1699 // If we can emit an efficient shift operation, do so now. Check to see if
1700 // the RHS is a constant.
1701 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1702 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1704 // If we can determine that the high bit of the shift is zero or one, even if
1705 // the low bits are variable, emit this shift in an optimized form.
1706 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1709 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1711 if (N->getOpcode() == ISD::SHL) {
1712 PartsOpc = ISD::SHL_PARTS;
1713 } else if (N->getOpcode() == ISD::SRL) {
1714 PartsOpc = ISD::SRL_PARTS;
1716 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1717 PartsOpc = ISD::SRA_PARTS;
1720 // Next check to see if the target supports this SHL_PARTS operation or if it
1721 // will custom expand it.
1722 MVT NVT = TLI.getTypeToTransformTo(VT);
1723 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1724 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1725 Action == TargetLowering::Custom) {
1726 // Expand the subcomponents.
1728 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1730 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1731 MVT VT = LHSL.getValueType();
1732 Lo = DAG.getNode(PartsOpc, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1733 Hi = Lo.getValue(1);
1737 // Otherwise, emit a libcall.
1738 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1740 if (N->getOpcode() == ISD::SHL) {
1741 isSigned = false; /*sign irrelevant*/
1743 LC = RTLIB::SHL_I16;
1744 else if (VT == MVT::i32)
1745 LC = RTLIB::SHL_I32;
1746 else if (VT == MVT::i64)
1747 LC = RTLIB::SHL_I64;
1748 else if (VT == MVT::i128)
1749 LC = RTLIB::SHL_I128;
1750 } else if (N->getOpcode() == ISD::SRL) {
1753 LC = RTLIB::SRL_I16;
1754 else if (VT == MVT::i32)
1755 LC = RTLIB::SRL_I32;
1756 else if (VT == MVT::i64)
1757 LC = RTLIB::SRL_I64;
1758 else if (VT == MVT::i128)
1759 LC = RTLIB::SRL_I128;
1761 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1764 LC = RTLIB::SRA_I16;
1765 else if (VT == MVT::i32)
1766 LC = RTLIB::SRA_I32;
1767 else if (VT == MVT::i64)
1768 LC = RTLIB::SRA_I64;
1769 else if (VT == MVT::i128)
1770 LC = RTLIB::SRA_I128;
1772 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1774 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1775 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1778 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1779 SDValue &Lo, SDValue &Hi) {
1780 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1781 DebugLoc dl = N->getDebugLoc();
1782 SDValue Op = N->getOperand(0);
1783 if (Op.getValueType().bitsLE(NVT)) {
1784 // The low part is sign extension of the input (degenerates to a copy).
1785 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1786 // The high part is obtained by SRA'ing all but one of the bits of low part.
1787 unsigned LoSize = NVT.getSizeInBits();
1788 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1789 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1791 // For example, extension of an i48 to an i64. The operand type necessarily
1792 // promotes to the result type, so will end up being expanded too.
1793 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1794 "Only know how to promote this result!");
1795 SDValue Res = GetPromotedInteger(Op);
1796 assert(Res.getValueType() == N->getValueType(0) &&
1797 "Operand over promoted?");
1798 // Split the promoted operand. This will simplify when it is expanded.
1799 SplitInteger(Res, Lo, Hi);
1800 unsigned ExcessBits =
1801 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1802 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1803 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1807 void DAGTypeLegalizer::
1808 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1809 DebugLoc dl = N->getDebugLoc();
1810 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1811 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1813 if (EVT.bitsLE(Lo.getValueType())) {
1814 // sext_inreg the low part if needed.
1815 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1818 // The high part gets the sign extension from the lo-part. This handles
1819 // things like sextinreg V:i64 from i8.
1820 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1821 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1822 TLI.getPointerTy()));
1824 // For example, extension of an i48 to an i64. Leave the low part alone,
1825 // sext_inreg the high part.
1826 unsigned ExcessBits =
1827 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1828 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1829 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1833 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1834 SDValue &Lo, SDValue &Hi) {
1835 MVT VT = N->getValueType(0);
1836 DebugLoc dl = N->getDebugLoc();
1838 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1840 LC = RTLIB::SREM_I32;
1841 else if (VT == MVT::i64)
1842 LC = RTLIB::SREM_I64;
1843 else if (VT == MVT::i128)
1844 LC = RTLIB::SREM_I128;
1845 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1847 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1848 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1851 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1852 SDValue &Lo, SDValue &Hi) {
1853 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1854 DebugLoc dl = N->getDebugLoc();
1855 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1856 Hi = DAG.getNode(ISD::SRL, dl,
1857 N->getOperand(0).getValueType(), N->getOperand(0),
1858 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1859 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1862 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1863 SDValue &Lo, SDValue &Hi) {
1864 MVT VT = N->getValueType(0);
1865 DebugLoc dl = N->getDebugLoc();
1867 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1869 LC = RTLIB::UDIV_I32;
1870 else if (VT == MVT::i64)
1871 LC = RTLIB::UDIV_I64;
1872 else if (VT == MVT::i128)
1873 LC = RTLIB::UDIV_I128;
1874 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1876 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1877 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1880 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1881 SDValue &Lo, SDValue &Hi) {
1882 MVT VT = N->getValueType(0);
1883 DebugLoc dl = N->getDebugLoc();
1885 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1887 LC = RTLIB::UREM_I32;
1888 else if (VT == MVT::i64)
1889 LC = RTLIB::UREM_I64;
1890 else if (VT == MVT::i128)
1891 LC = RTLIB::UREM_I128;
1892 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1894 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1895 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1898 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1899 SDValue &Lo, SDValue &Hi) {
1900 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1901 DebugLoc dl = N->getDebugLoc();
1902 SDValue Op = N->getOperand(0);
1903 if (Op.getValueType().bitsLE(NVT)) {
1904 // The low part is zero extension of the input (degenerates to a copy).
1905 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1906 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1908 // For example, extension of an i48 to an i64. The operand type necessarily
1909 // promotes to the result type, so will end up being expanded too.
1910 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1911 "Only know how to promote this result!");
1912 SDValue Res = GetPromotedInteger(Op);
1913 assert(Res.getValueType() == N->getValueType(0) &&
1914 "Operand over promoted?");
1915 // Split the promoted operand. This will simplify when it is expanded.
1916 SplitInteger(Res, Lo, Hi);
1917 unsigned ExcessBits =
1918 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1919 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
1924 //===----------------------------------------------------------------------===//
1925 // Integer Operand Expansion
1926 //===----------------------------------------------------------------------===//
1928 /// ExpandIntegerOperand - This method is called when the specified operand of
1929 /// the specified node is found to need expansion. At this point, all of the
1930 /// result types of the node are known to be legal, but other operands of the
1931 /// node may need promotion or expansion as well as the specified one.
1932 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1933 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1934 SDValue Res = SDValue();
1936 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
1939 switch (N->getOpcode()) {
1942 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1943 N->dump(&DAG); cerr << "\n";
1945 assert(0 && "Do not know how to expand this operator's operand!");
1948 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1949 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1950 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1951 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1952 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
1953 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
1954 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1955 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1956 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1957 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
1958 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1959 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1965 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
1968 // If the result is null, the sub-method took care of registering results etc.
1969 if (!Res.getNode()) return false;
1971 // If the result is N, the sub-method updated N in place. Tell the legalizer
1973 if (Res.getNode() == N)
1976 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1977 "Invalid operand expansion");
1979 ReplaceValueWith(SDValue(N, 0), Res);
1983 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1984 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1985 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1987 ISD::CondCode &CCCode,
1989 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1990 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1991 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1993 MVT VT = NewLHS.getValueType();
1995 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1996 if (RHSLo == RHSHi) {
1997 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1998 if (RHSCST->isAllOnesValue()) {
1999 // Equality comparison to -1.
2000 NewLHS = DAG.getNode(ISD::AND, dl,
2001 LHSLo.getValueType(), LHSLo, LHSHi);
2008 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2009 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2010 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2011 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2015 // If this is a comparison of the sign bit, just look at the top part.
2017 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2018 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2019 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2025 // FIXME: This generated code sucks.
2026 ISD::CondCode LowCC;
2028 default: assert(0 && "Unknown integer setcc!");
2030 case ISD::SETULT: LowCC = ISD::SETULT; break;
2032 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2034 case ISD::SETULE: LowCC = ISD::SETULE; break;
2036 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2039 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2040 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2041 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2043 // NOTE: on targets without efficient SELECT of bools, we can always use
2044 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2045 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2047 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2048 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2049 if (!Tmp1.getNode())
2050 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2051 LHSLo, RHSLo, LowCC);
2052 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2053 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2054 if (!Tmp2.getNode())
2055 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2056 TLI.getSetCCResultType(LHSHi.getValueType()),
2057 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2059 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2060 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2061 if ((Tmp1C && Tmp1C->isNullValue()) ||
2062 (Tmp2C && Tmp2C->isNullValue() &&
2063 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2064 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2065 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2066 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2067 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2068 // low part is known false, returns high part.
2069 // For LE / GE, if high part is known false, ignore the low part.
2070 // For LT / GT, if high part is known true, ignore the low part.
2076 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2077 LHSHi, RHSHi, ISD::SETEQ, false,
2078 DagCombineInfo, dl);
2079 if (!NewLHS.getNode())
2080 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2081 LHSHi, RHSHi, ISD::SETEQ);
2082 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2083 NewLHS, Tmp1, Tmp2);
2087 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2088 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2089 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2090 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2092 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2093 // against zero to select between true and false values.
2094 if (NewRHS.getNode() == 0) {
2095 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2096 CCCode = ISD::SETNE;
2099 // Update N to have the operands specified.
2100 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2101 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2105 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2106 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2107 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2108 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2110 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2111 // against zero to select between true and false values.
2112 if (NewRHS.getNode() == 0) {
2113 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2114 CCCode = ISD::SETNE;
2117 // Update N to have the operands specified.
2118 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2119 N->getOperand(2), N->getOperand(3),
2120 DAG.getCondCode(CCCode));
2123 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2124 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2125 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2126 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2128 // If ExpandSetCCOperands returned a scalar, use it.
2129 if (NewRHS.getNode() == 0) {
2130 assert(NewLHS.getValueType() == N->getValueType(0) &&
2131 "Unexpected setcc expansion!");
2135 // Otherwise, update N to have the operands specified.
2136 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2137 DAG.getCondCode(CCCode));
2140 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2141 // The value being shifted is legal, but the shift amount is too big.
2142 // It follows that either the result of the shift is undefined, or the
2143 // upper half of the shift amount is zero. Just use the lower half.
2145 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2146 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2149 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2150 SDValue Op = N->getOperand(0);
2151 MVT DstVT = N->getValueType(0);
2152 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2153 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2154 "Don't know how to expand this SINT_TO_FP!");
2155 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2158 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2159 if (ISD::isNormalStore(N))
2160 return ExpandOp_NormalStore(N, OpNo);
2162 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2163 assert(OpNo == 1 && "Can only expand the stored value so far");
2165 MVT VT = N->getOperand(1).getValueType();
2166 MVT NVT = TLI.getTypeToTransformTo(VT);
2167 SDValue Ch = N->getChain();
2168 SDValue Ptr = N->getBasePtr();
2169 int SVOffset = N->getSrcValueOffset();
2170 unsigned Alignment = N->getAlignment();
2171 bool isVolatile = N->isVolatile();
2172 DebugLoc dl = N->getDebugLoc();
2175 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2177 if (N->getMemoryVT().bitsLE(NVT)) {
2178 GetExpandedInteger(N->getValue(), Lo, Hi);
2179 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2180 N->getMemoryVT(), isVolatile, Alignment);
2181 } else if (TLI.isLittleEndian()) {
2182 // Little-endian - low bits are at low addresses.
2183 GetExpandedInteger(N->getValue(), Lo, Hi);
2185 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2186 isVolatile, Alignment);
2188 unsigned ExcessBits =
2189 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2190 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2192 // Increment the pointer to the other half.
2193 unsigned IncrementSize = NVT.getSizeInBits()/8;
2194 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2195 DAG.getIntPtrConstant(IncrementSize));
2196 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2197 SVOffset+IncrementSize, NEVT,
2198 isVolatile, MinAlign(Alignment, IncrementSize));
2199 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2201 // Big-endian - high bits are at low addresses. Favor aligned stores at
2202 // the cost of some bit-fiddling.
2203 GetExpandedInteger(N->getValue(), Lo, Hi);
2205 MVT EVT = N->getMemoryVT();
2206 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2207 unsigned IncrementSize = NVT.getSizeInBits()/8;
2208 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2209 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2211 if (ExcessBits < NVT.getSizeInBits()) {
2212 // Transfer high bits from the top of Lo to the bottom of Hi.
2213 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2214 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2215 TLI.getPointerTy()));
2216 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2217 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2218 DAG.getConstant(ExcessBits,
2219 TLI.getPointerTy())));
2222 // Store both the high bits and maybe some of the low bits.
2223 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2224 SVOffset, HiVT, isVolatile, Alignment);
2226 // Increment the pointer to the other half.
2227 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2228 DAG.getIntPtrConstant(IncrementSize));
2229 // Store the lowest ExcessBits bits in the second half.
2230 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2231 SVOffset+IncrementSize,
2232 MVT::getIntegerVT(ExcessBits),
2233 isVolatile, MinAlign(Alignment, IncrementSize));
2234 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2238 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2240 GetExpandedInteger(N->getOperand(0), InL, InH);
2241 // Just truncate the low part of the source.
2242 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2245 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2246 SDValue Op = N->getOperand(0);
2247 MVT SrcVT = Op.getValueType();
2248 MVT DstVT = N->getValueType(0);
2249 DebugLoc dl = N->getDebugLoc();
2251 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2252 // Do a signed conversion then adjust the result.
2253 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2254 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2256 // The result of the signed conversion needs adjusting if the 'sign bit' of
2257 // the incoming integer was set. To handle this, we dynamically test to see
2258 // if it is set, and, if so, add a fudge factor.
2260 const uint64_t F32TwoE32 = 0x4F800000ULL;
2261 const uint64_t F32TwoE64 = 0x5F800000ULL;
2262 const uint64_t F32TwoE128 = 0x7F800000ULL;
2265 if (SrcVT == MVT::i32)
2266 FF = APInt(32, F32TwoE32);
2267 else if (SrcVT == MVT::i64)
2268 FF = APInt(32, F32TwoE64);
2269 else if (SrcVT == MVT::i128)
2270 FF = APInt(32, F32TwoE128);
2272 assert(false && "Unsupported UINT_TO_FP!");
2274 // Check whether the sign bit is set.
2276 GetExpandedInteger(Op, Lo, Hi);
2277 SDValue SignSet = DAG.getSetCC(dl,
2278 TLI.getSetCCResultType(Hi.getValueType()),
2279 Hi, DAG.getConstant(0, Hi.getValueType()),
2282 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2283 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2284 TLI.getPointerTy());
2286 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2287 SDValue Zero = DAG.getIntPtrConstant(0);
2288 SDValue Four = DAG.getIntPtrConstant(4);
2289 if (TLI.isBigEndian()) std::swap(Zero, Four);
2290 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2292 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2293 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2294 Alignment = std::min(Alignment, 4u);
2296 // Load the value out, extending it from f32 to the destination float type.
2297 // FIXME: Avoid the extend by constructing the right constant pool?
2298 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2299 FudgePtr, NULL, 0, MVT::f32,
2301 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2304 // Otherwise, use a libcall.
2305 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2306 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2307 "Don't know how to expand this UINT_TO_FP!");
2308 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);