1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
28 //===----------------------------------------------------------------------===//
29 // Integer Result Promotion
30 //===----------------------------------------------------------------------===//
32 /// PromoteIntegerResult - This method is called when a result of a node is
33 /// found to be in need of promotion to a larger type. At this point, the node
34 /// may also have invalid operands or may have other results that need
35 /// expansion, we just know that (at least) one result needs promotion.
36 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
37 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
38 SDValue Res = SDValue();
40 // See if the target wants to custom expand this node.
41 if (CustomLowerNode(N, N->getValueType(ResNo), true))
44 switch (N->getOpcode()) {
47 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
48 N->dump(&DAG); dbgs() << "\n";
50 llvm_unreachable("Do not know how to promote this operator!");
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
57 case ISD::CONVERT_RNDSAT:
58 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
59 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
60 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
61 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
62 case ISD::EXTRACT_VECTOR_ELT:
63 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
64 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
65 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
66 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
67 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
68 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
69 case ISD::SIGN_EXTEND_INREG:
70 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
71 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
72 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
73 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
74 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
75 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
77 case ISD::EXTRACT_SUBVECTOR:
78 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
79 case ISD::VECTOR_SHUFFLE:
80 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
81 case ISD::INSERT_VECTOR_ELT:
82 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
83 case ISD::BUILD_VECTOR:
84 Res = PromoteIntRes_BUILD_VECTOR(N); break;
85 case ISD::SCALAR_TO_VECTOR:
86 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
88 case ISD::SIGN_EXTEND:
89 case ISD::ZERO_EXTEND:
90 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
93 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
95 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
102 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
105 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
108 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
111 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
113 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
115 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
117 case ISD::ATOMIC_LOAD_ADD:
118 case ISD::ATOMIC_LOAD_SUB:
119 case ISD::ATOMIC_LOAD_AND:
120 case ISD::ATOMIC_LOAD_OR:
121 case ISD::ATOMIC_LOAD_XOR:
122 case ISD::ATOMIC_LOAD_NAND:
123 case ISD::ATOMIC_LOAD_MIN:
124 case ISD::ATOMIC_LOAD_MAX:
125 case ISD::ATOMIC_LOAD_UMIN:
126 case ISD::ATOMIC_LOAD_UMAX:
127 case ISD::ATOMIC_SWAP:
128 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
130 case ISD::ATOMIC_CMP_SWAP:
131 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
134 // If the result is null then the sub-method took care of registering it.
136 SetPromotedInteger(SDValue(N, ResNo), Res);
139 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
140 // Sign-extend the new bits, and continue the assertion.
141 SDValue Op = SExtPromotedInteger(N->getOperand(0));
142 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
143 Op.getValueType(), Op, N->getOperand(1));
146 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
147 // Zero the new bits, and continue the assertion.
148 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
149 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
150 Op.getValueType(), Op, N->getOperand(1));
153 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
154 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
155 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
157 N->getChain(), N->getBasePtr(),
158 Op2, N->getMemOperand());
159 // Legalized the chain result - switch anything that used the old chain to
161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
165 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
166 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
167 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
168 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
169 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
170 Op2, Op3, N->getMemOperand());
171 // Legalized the chain result - switch anything that used the old chain to
173 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
177 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
178 SDValue InOp = N->getOperand(0);
179 EVT InVT = InOp.getValueType();
180 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
181 EVT OutVT = N->getValueType(0);
182 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
183 DebugLoc dl = N->getDebugLoc();
185 switch (getTypeAction(InVT)) {
187 assert(false && "Unknown type action!");
189 case TargetLowering::TypeLegal:
191 case TargetLowering::TypePromoteInteger:
192 if (NOutVT.bitsEq(NInVT))
193 // The input promotes to the same size. Convert the promoted value.
194 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
195 if (NInVT.isVector())
196 // Promote vector element via memory load/store.
197 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
198 CreateStackStoreLoad(InOp, OutVT));
200 case TargetLowering::TypeSoftenFloat:
201 // Promote the integer operand by hand.
202 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
203 case TargetLowering::TypeExpandInteger:
204 case TargetLowering::TypeExpandFloat:
206 case TargetLowering::TypeScalarizeVector:
207 // Convert the element to an integer and promote it by hand.
208 if (!NOutVT.isVector())
209 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
210 BitConvertToInteger(GetScalarizedVector(InOp)));
212 case TargetLowering::TypeSplitVector: {
213 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
214 // pieces of the input into integers and reassemble in the final type.
216 GetSplitVector(N->getOperand(0), Lo, Hi);
217 Lo = BitConvertToInteger(Lo);
218 Hi = BitConvertToInteger(Hi);
220 if (TLI.isBigEndian())
223 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
224 EVT::getIntegerVT(*DAG.getContext(),
225 NOutVT.getSizeInBits()),
226 JoinIntegers(Lo, Hi));
227 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
229 case TargetLowering::TypeWidenVector:
230 if (OutVT.bitsEq(NInVT))
231 // The input is widened to the same size. Convert to the widened value.
232 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp));
235 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
236 CreateStackStoreLoad(InOp, OutVT));
239 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
240 SDValue Op = GetPromotedInteger(N->getOperand(0));
241 EVT OVT = N->getValueType(0);
242 EVT NVT = Op.getValueType();
243 DebugLoc dl = N->getDebugLoc();
245 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
246 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
247 DAG.getConstant(DiffBits, TLI.getPointerTy()));
250 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
251 // The pair element type may be legal, or may not promote to the same type as
252 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
253 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
254 TLI.getTypeToTransformTo(*DAG.getContext(),
255 N->getValueType(0)), JoinIntegers(N->getOperand(0),
259 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
260 EVT VT = N->getValueType(0);
261 // FIXME there is no actual debug info here
262 DebugLoc dl = N->getDebugLoc();
263 // Zero extend things like i1, sign extend everything else. It shouldn't
264 // matter in theory which one we pick, but this tends to give better code?
265 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
266 SDValue Result = DAG.getNode(Opc, dl,
267 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
269 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
273 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
274 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
275 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
276 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
277 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
278 "can only promote integers");
279 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
280 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
281 N->getOperand(1), N->getOperand(2),
282 N->getOperand(3), N->getOperand(4), CvtCode);
285 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
286 // Zero extend to the promoted type and do the count there.
287 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
288 DebugLoc dl = N->getDebugLoc();
289 EVT OVT = N->getValueType(0);
290 EVT NVT = Op.getValueType();
291 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
292 // Subtract off the extra leading bits in the bigger type.
293 return DAG.getNode(ISD::SUB, dl, NVT, Op,
294 DAG.getConstant(NVT.getSizeInBits() -
295 OVT.getSizeInBits(), NVT));
298 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
299 // Zero extend to the promoted type and do the count there.
300 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
301 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
304 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
305 SDValue Op = GetPromotedInteger(N->getOperand(0));
306 EVT OVT = N->getValueType(0);
307 EVT NVT = Op.getValueType();
308 DebugLoc dl = N->getDebugLoc();
309 // The count is the same in the promoted type except if the original
310 // value was zero. This can be handled by setting the bit just off
311 // the top of the original type.
312 APInt TopBit(NVT.getSizeInBits(), 0);
313 TopBit.setBit(OVT.getSizeInBits());
314 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
315 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
318 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
319 DebugLoc dl = N->getDebugLoc();
320 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
321 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
325 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
326 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
327 unsigned NewOpc = N->getOpcode();
328 DebugLoc dl = N->getDebugLoc();
330 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
331 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
332 // and SINT conversions are Custom, there is no way to tell which is
333 // preferable. We choose SINT because that's the right thing on PPC.)
334 if (N->getOpcode() == ISD::FP_TO_UINT &&
335 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
336 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
337 NewOpc = ISD::FP_TO_SINT;
339 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
341 // Assert that the converted value fits in the original type. If it doesn't
342 // (eg: because the value being converted is too big), then the result of the
343 // original operation was undefined anyway, so the assert is still correct.
344 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
345 ISD::AssertZext : ISD::AssertSext, dl,
346 NVT, Res, DAG.getValueType(N->getValueType(0)));
349 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
350 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
351 DebugLoc dl = N->getDebugLoc();
353 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
355 return DAG.getNode(ISD::AssertZext, dl,
356 NVT, Res, DAG.getValueType(N->getValueType(0)));
359 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
360 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
361 DebugLoc dl = N->getDebugLoc();
363 if (getTypeAction(N->getOperand(0).getValueType())
364 == TargetLowering::TypePromoteInteger) {
365 SDValue Res = GetPromotedInteger(N->getOperand(0));
366 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
368 // If the result and operand types are the same after promotion, simplify
369 // to an in-register extension.
370 if (NVT == Res.getValueType()) {
371 // The high bits are not guaranteed to be anything. Insert an extend.
372 if (N->getOpcode() == ISD::SIGN_EXTEND)
373 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
374 DAG.getValueType(N->getOperand(0).getValueType()));
375 if (N->getOpcode() == ISD::ZERO_EXTEND)
376 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
377 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
382 // Otherwise, just extend the original operand all the way to the larger type.
383 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
386 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
387 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
388 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
389 ISD::LoadExtType ExtType =
390 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
391 DebugLoc dl = N->getDebugLoc();
392 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
394 N->getMemoryVT(), N->isVolatile(),
395 N->isNonTemporal(), N->getAlignment());
397 // Legalized the chain result - switch anything that used the old chain to
399 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
403 /// Promote the overflow flag of an overflowing arithmetic node.
404 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
405 // Simply change the return type of the boolean result.
406 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
407 EVT ValueVTs[] = { N->getValueType(0), NVT };
408 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
409 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
410 DAG.getVTList(ValueVTs, 2), Ops, 2);
412 // Modified the sum result - switch anything that used the old sum to use
414 ReplaceValueWith(SDValue(N, 0), Res);
416 return SDValue(Res.getNode(), 1);
419 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
421 return PromoteIntRes_Overflow(N);
423 // The operation overflowed iff the result in the larger type is not the
424 // sign extension of its truncation to the original type.
425 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
426 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
427 EVT OVT = N->getOperand(0).getValueType();
428 EVT NVT = LHS.getValueType();
429 DebugLoc dl = N->getDebugLoc();
431 // Do the arithmetic in the larger type.
432 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
433 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
435 // Calculate the overflow flag: sign extend the arithmetic result from
436 // the original type.
437 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
438 DAG.getValueType(OVT));
439 // Overflowed if and only if this is not equal to Res.
440 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
442 // Use the calculated overflow everywhere.
443 ReplaceValueWith(SDValue(N, 1), Ofl);
448 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
449 // Sign extend the input.
450 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
451 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
452 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
453 LHS.getValueType(), LHS, RHS);
456 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
457 SDValue LHS = GetPromotedInteger(N->getOperand(1));
458 SDValue RHS = GetPromotedInteger(N->getOperand(2));
459 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
460 LHS.getValueType(), N->getOperand(0),LHS,RHS);
463 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
464 SDValue LHS = GetPromotedInteger(N->getOperand(2));
465 SDValue RHS = GetPromotedInteger(N->getOperand(3));
466 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
467 LHS.getValueType(), N->getOperand(0),
468 N->getOperand(1), LHS, RHS, N->getOperand(4));
471 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
472 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
473 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
474 DebugLoc dl = N->getDebugLoc();
476 // Get the SETCC result using the canonical SETCC type.
477 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
478 N->getOperand(1), N->getOperand(2));
480 // Convert to the expected type.
481 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
482 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
483 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
486 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
487 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
488 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
489 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
492 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
493 SDValue Op = GetPromotedInteger(N->getOperand(0));
494 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
495 Op.getValueType(), Op, N->getOperand(1));
498 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
499 // The input may have strange things in the top bits of the registers, but
500 // these operations don't care. They may have weird bits going out, but
501 // that too is okay if they are integer operations.
502 SDValue LHS = GetPromotedInteger(N->getOperand(0));
503 SDValue RHS = GetPromotedInteger(N->getOperand(1));
504 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
505 LHS.getValueType(), LHS, RHS);
508 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
509 // The input value must be properly sign extended.
510 SDValue Res = SExtPromotedInteger(N->getOperand(0));
511 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
512 Res.getValueType(), Res, N->getOperand(1));
515 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
516 // The input value must be properly zero extended.
517 EVT VT = N->getValueType(0);
518 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
519 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
520 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
523 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
524 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
527 switch (getTypeAction(N->getOperand(0).getValueType())) {
528 default: llvm_unreachable("Unknown type action!");
529 case TargetLowering::TypeLegal:
530 case TargetLowering::TypeExpandInteger:
531 Res = N->getOperand(0);
533 case TargetLowering::TypePromoteInteger:
534 Res = GetPromotedInteger(N->getOperand(0));
538 // Truncate to NVT instead of VT
539 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
542 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
544 return PromoteIntRes_Overflow(N);
546 // The operation overflowed iff the result in the larger type is not the
547 // zero extension of its truncation to the original type.
548 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
549 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
550 EVT OVT = N->getOperand(0).getValueType();
551 EVT NVT = LHS.getValueType();
552 DebugLoc dl = N->getDebugLoc();
554 // Do the arithmetic in the larger type.
555 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
556 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
558 // Calculate the overflow flag: zero extend the arithmetic result from
559 // the original type.
560 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
561 // Overflowed if and only if this is not equal to Res.
562 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
564 // Use the calculated overflow everywhere.
565 ReplaceValueWith(SDValue(N, 1), Ofl);
570 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
571 // Promote the overflow bit trivially.
573 return PromoteIntRes_Overflow(N);
575 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
576 DebugLoc DL = N->getDebugLoc();
577 EVT SmallVT = LHS.getValueType();
579 // To determine if the result overflowed in a larger type, we extend the
580 // input to the larger type, do the multiply, then check the high bits of
581 // the result to see if the overflow happened.
582 if (N->getOpcode() == ISD::SMULO) {
583 LHS = SExtPromotedInteger(LHS);
584 RHS = SExtPromotedInteger(RHS);
586 LHS = ZExtPromotedInteger(LHS);
587 RHS = ZExtPromotedInteger(RHS);
589 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
591 // Overflow occurred iff the high part of the result does not
592 // zero/sign-extend the low part.
594 if (N->getOpcode() == ISD::UMULO) {
595 // Unsigned overflow occurred iff the high part is non-zero.
596 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
597 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
598 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
599 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
601 // Signed overflow occurred iff the high part does not sign extend the low.
602 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
603 Mul, DAG.getValueType(SmallVT));
604 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
607 // Use the calculated overflow everywhere.
608 ReplaceValueWith(SDValue(N, 1), Overflow);
612 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
613 // Zero extend the input.
614 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
615 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
616 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
617 LHS.getValueType(), LHS, RHS);
620 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
621 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
622 N->getValueType(0)));
625 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
626 SDValue Chain = N->getOperand(0); // Get the chain.
627 SDValue Ptr = N->getOperand(1); // Get the pointer.
628 EVT VT = N->getValueType(0);
629 DebugLoc dl = N->getDebugLoc();
631 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
632 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
633 // The argument is passed as NumRegs registers of type RegVT.
635 SmallVector<SDValue, 8> Parts(NumRegs);
636 for (unsigned i = 0; i < NumRegs; ++i) {
637 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
638 N->getConstantOperandVal(3));
639 Chain = Parts[i].getValue(1);
642 // Handle endianness of the load.
643 if (TLI.isBigEndian())
644 std::reverse(Parts.begin(), Parts.end());
646 // Assemble the parts in the promoted type.
647 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
648 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
649 for (unsigned i = 1; i < NumRegs; ++i) {
650 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
651 // Shift it to the right position and "or" it in.
652 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
653 DAG.getConstant(i * RegVT.getSizeInBits(),
654 TLI.getPointerTy()));
655 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
658 // Modified the chain result - switch anything that used the old chain to
660 ReplaceValueWith(SDValue(N, 1), Chain);
665 //===----------------------------------------------------------------------===//
666 // Integer Operand Promotion
667 //===----------------------------------------------------------------------===//
669 /// PromoteIntegerOperand - This method is called when the specified operand of
670 /// the specified node is found to need promotion. At this point, all of the
671 /// result types of the node are known to be legal, but other operands of the
672 /// node may need promotion or expansion as well as the specified one.
673 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
674 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
675 SDValue Res = SDValue();
677 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
680 switch (N->getOpcode()) {
683 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
684 N->dump(&DAG); dbgs() << "\n";
686 llvm_unreachable("Do not know how to promote this operator's operand!");
688 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
689 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
690 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
691 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
692 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
693 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
694 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
695 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
696 case ISD::CONVERT_RNDSAT:
697 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
698 case ISD::INSERT_VECTOR_ELT:
699 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
700 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
701 case ISD::SCALAR_TO_VECTOR:
702 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
703 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
704 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
705 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
706 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
707 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
708 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
710 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
711 case ISD::FP16_TO_FP32:
712 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
713 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
719 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
722 // If the result is null, the sub-method took care of registering results etc.
723 if (!Res.getNode()) return false;
725 // If the result is N, the sub-method updated N in place. Tell the legalizer
727 if (Res.getNode() == N)
730 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
731 "Invalid operand expansion");
733 ReplaceValueWith(SDValue(N, 0), Res);
737 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
738 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
739 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
740 ISD::CondCode CCCode) {
741 // We have to insert explicit sign or zero extends. Note that we could
742 // insert sign extends for ALL conditions, but zero extend is cheaper on
743 // many machines (an AND instead of two shifts), so prefer it.
745 default: llvm_unreachable("Unknown integer comparison!");
752 // ALL of these operations will work if we either sign or zero extend
753 // the operands (including the unsigned comparisons!). Zero extend is
754 // usually a simpler/cheaper operation, so prefer it.
755 NewLHS = ZExtPromotedInteger(NewLHS);
756 NewRHS = ZExtPromotedInteger(NewRHS);
762 NewLHS = SExtPromotedInteger(NewLHS);
763 NewRHS = SExtPromotedInteger(NewRHS);
768 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
769 SDValue Op = GetPromotedInteger(N->getOperand(0));
770 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
773 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
774 // This should only occur in unusual situations like bitcasting to an
775 // x86_fp80, so just turn it into a store+load
776 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
779 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
780 assert(OpNo == 2 && "Don't know how to promote this operand!");
782 SDValue LHS = N->getOperand(2);
783 SDValue RHS = N->getOperand(3);
784 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
786 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
788 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
789 N->getOperand(1), LHS, RHS, N->getOperand(4)),
793 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
794 assert(OpNo == 1 && "only know how to promote condition");
796 // Promote all the way up to the canonical SetCC type.
797 EVT SVT = TLI.getSetCCResultType(MVT::Other);
798 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
800 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
801 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
802 N->getOperand(2)), 0);
805 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
806 // Since the result type is legal, the operands must promote to it.
807 EVT OVT = N->getOperand(0).getValueType();
808 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
809 SDValue Hi = GetPromotedInteger(N->getOperand(1));
810 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
811 DebugLoc dl = N->getDebugLoc();
813 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
814 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
815 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
818 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
819 // The vector type is legal but the element type is not. This implies
820 // that the vector is a power-of-two in length and that the element
821 // type does not have a strange size (eg: it is not i1).
822 EVT VecVT = N->getValueType(0);
823 unsigned NumElts = VecVT.getVectorNumElements();
824 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
826 // Promote the inserted value. The type does not need to match the
827 // vector element type. Check that any extra bits introduced will be
829 assert(N->getOperand(0).getValueType().getSizeInBits() >=
830 N->getValueType(0).getVectorElementType().getSizeInBits() &&
831 "Type of inserted value narrower than vector element type!");
833 SmallVector<SDValue, 16> NewOps;
834 for (unsigned i = 0; i < NumElts; ++i)
835 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
837 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
840 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
841 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
842 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
843 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
844 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
845 "can only promote integer arguments");
846 SDValue InOp = GetPromotedInteger(N->getOperand(0));
847 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
848 N->getOperand(1), N->getOperand(2),
849 N->getOperand(3), N->getOperand(4), CvtCode);
852 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
855 // Promote the inserted value. This is valid because the type does not
856 // have to match the vector element type.
858 // Check that any extra bits introduced will be truncated away.
859 assert(N->getOperand(1).getValueType().getSizeInBits() >=
860 N->getValueType(0).getVectorElementType().getSizeInBits() &&
861 "Type of inserted value narrower than vector element type!");
862 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
863 GetPromotedInteger(N->getOperand(1)),
868 assert(OpNo == 2 && "Different operand and result vector types?");
870 // Promote the index.
871 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
872 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
873 N->getOperand(1), Idx), 0);
876 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
878 DebugLoc dl = N->getDebugLoc();
879 NewOps[0] = N->getOperand(0);
880 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
881 SDValue Flag = GetPromotedInteger(N->getOperand(i));
882 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
884 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
887 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
888 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
889 // the operand in place.
890 return SDValue(DAG.UpdateNodeOperands(N,
891 GetPromotedInteger(N->getOperand(0))), 0);
894 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
895 assert(OpNo == 0 && "Only know how to promote condition");
897 // Promote all the way up to the canonical SetCC type.
898 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
899 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
901 return SDValue(DAG.UpdateNodeOperands(N, Cond,
902 N->getOperand(1), N->getOperand(2)), 0);
905 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
906 assert(OpNo == 0 && "Don't know how to promote this operand!");
908 SDValue LHS = N->getOperand(0);
909 SDValue RHS = N->getOperand(1);
910 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
912 // The CC (#4) and the possible return values (#2 and #3) have legal types.
913 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
914 N->getOperand(3), N->getOperand(4)), 0);
917 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
918 assert(OpNo == 0 && "Don't know how to promote this operand!");
920 SDValue LHS = N->getOperand(0);
921 SDValue RHS = N->getOperand(1);
922 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
924 // The CC (#2) is always legal.
925 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
928 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
929 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
930 ZExtPromotedInteger(N->getOperand(1))), 0);
933 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
934 SDValue Op = GetPromotedInteger(N->getOperand(0));
935 DebugLoc dl = N->getDebugLoc();
936 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
937 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
938 Op, DAG.getValueType(N->getOperand(0).getValueType()));
941 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
942 return SDValue(DAG.UpdateNodeOperands(N,
943 SExtPromotedInteger(N->getOperand(0))), 0);
946 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
947 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
948 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
949 unsigned Alignment = N->getAlignment();
950 bool isVolatile = N->isVolatile();
951 bool isNonTemporal = N->isNonTemporal();
952 DebugLoc dl = N->getDebugLoc();
954 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
956 // Truncate the value and store the result.
957 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
959 isVolatile, isNonTemporal, Alignment);
962 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
963 SDValue Op = GetPromotedInteger(N->getOperand(0));
964 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
967 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
968 return SDValue(DAG.UpdateNodeOperands(N,
969 ZExtPromotedInteger(N->getOperand(0))), 0);
972 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
973 DebugLoc dl = N->getDebugLoc();
974 SDValue Op = GetPromotedInteger(N->getOperand(0));
975 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
976 return DAG.getZeroExtendInReg(Op, dl,
977 N->getOperand(0).getValueType().getScalarType());
981 //===----------------------------------------------------------------------===//
982 // Integer Result Expansion
983 //===----------------------------------------------------------------------===//
985 /// ExpandIntegerResult - This method is called when the specified result of the
986 /// specified node is found to need expansion. At this point, the node may also
987 /// have invalid operands or may have other results that need promotion, we just
988 /// know that (at least) one result needs expansion.
989 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
990 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
994 // See if the target wants to custom expand this node.
995 if (CustomLowerNode(N, N->getValueType(ResNo), true))
998 switch (N->getOpcode()) {
1001 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1002 N->dump(&DAG); dbgs() << "\n";
1004 llvm_unreachable("Do not know how to expand the result of this operator!");
1006 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
1007 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1008 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1009 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1011 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1012 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1013 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1014 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1015 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1017 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1018 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1019 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1020 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1021 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1022 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1023 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1024 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1025 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1026 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1027 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1028 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1029 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1030 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1031 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1032 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1033 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1034 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1035 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1036 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1038 case ISD::ATOMIC_LOAD_ADD:
1039 case ISD::ATOMIC_LOAD_SUB:
1040 case ISD::ATOMIC_LOAD_AND:
1041 case ISD::ATOMIC_LOAD_OR:
1042 case ISD::ATOMIC_LOAD_XOR:
1043 case ISD::ATOMIC_LOAD_NAND:
1044 case ISD::ATOMIC_LOAD_MIN:
1045 case ISD::ATOMIC_LOAD_MAX:
1046 case ISD::ATOMIC_LOAD_UMIN:
1047 case ISD::ATOMIC_LOAD_UMAX:
1048 case ISD::ATOMIC_SWAP: {
1049 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1050 SplitInteger(Tmp.first, Lo, Hi);
1051 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1057 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1060 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1063 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1066 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1070 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1073 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1075 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1077 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1080 // If Lo/Hi is null, the sub-method took care of registering results etc.
1082 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1085 /// Lower an atomic node to the appropriate builtin call.
1086 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1087 unsigned Opc = Node->getOpcode();
1088 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1093 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1095 case ISD::ATOMIC_SWAP:
1096 switch (VT.SimpleTy) {
1097 default: llvm_unreachable("Unexpected value type for atomic!");
1098 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1099 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1100 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1101 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1104 case ISD::ATOMIC_CMP_SWAP:
1105 switch (VT.SimpleTy) {
1106 default: llvm_unreachable("Unexpected value type for atomic!");
1107 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1108 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1109 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1110 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1113 case ISD::ATOMIC_LOAD_ADD:
1114 switch (VT.SimpleTy) {
1115 default: llvm_unreachable("Unexpected value type for atomic!");
1116 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1117 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1118 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1119 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1122 case ISD::ATOMIC_LOAD_SUB:
1123 switch (VT.SimpleTy) {
1124 default: llvm_unreachable("Unexpected value type for atomic!");
1125 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1126 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1127 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1128 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1131 case ISD::ATOMIC_LOAD_AND:
1132 switch (VT.SimpleTy) {
1133 default: llvm_unreachable("Unexpected value type for atomic!");
1134 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1135 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1136 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1137 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1140 case ISD::ATOMIC_LOAD_OR:
1141 switch (VT.SimpleTy) {
1142 default: llvm_unreachable("Unexpected value type for atomic!");
1143 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1144 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1145 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1146 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1149 case ISD::ATOMIC_LOAD_XOR:
1150 switch (VT.SimpleTy) {
1151 default: llvm_unreachable("Unexpected value type for atomic!");
1152 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1153 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1154 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1155 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1158 case ISD::ATOMIC_LOAD_NAND:
1159 switch (VT.SimpleTy) {
1160 default: llvm_unreachable("Unexpected value type for atomic!");
1161 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1162 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1163 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1164 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1169 return ExpandChainLibCall(LC, Node, false);
1172 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1173 /// and the shift amount is a constant 'Amt'. Expand the operation.
1174 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1175 SDValue &Lo, SDValue &Hi) {
1176 DebugLoc DL = N->getDebugLoc();
1177 // Expand the incoming operand to be shifted, so that we have its parts
1179 GetExpandedInteger(N->getOperand(0), InL, InH);
1181 EVT NVT = InL.getValueType();
1182 unsigned VTBits = N->getValueType(0).getSizeInBits();
1183 unsigned NVTBits = NVT.getSizeInBits();
1184 EVT ShTy = N->getOperand(1).getValueType();
1186 if (N->getOpcode() == ISD::SHL) {
1188 Lo = Hi = DAG.getConstant(0, NVT);
1189 } else if (Amt > NVTBits) {
1190 Lo = DAG.getConstant(0, NVT);
1191 Hi = DAG.getNode(ISD::SHL, DL,
1192 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1193 } else if (Amt == NVTBits) {
1194 Lo = DAG.getConstant(0, NVT);
1196 } else if (Amt == 1 &&
1197 TLI.isOperationLegalOrCustom(ISD::ADDC,
1198 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1199 // Emit this X << 1 as X+X.
1200 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1201 SDValue LoOps[2] = { InL, InL };
1202 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1203 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1204 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1206 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1207 Hi = DAG.getNode(ISD::OR, DL, NVT,
1208 DAG.getNode(ISD::SHL, DL, NVT, InH,
1209 DAG.getConstant(Amt, ShTy)),
1210 DAG.getNode(ISD::SRL, DL, NVT, InL,
1211 DAG.getConstant(NVTBits-Amt, ShTy)));
1216 if (N->getOpcode() == ISD::SRL) {
1218 Lo = DAG.getConstant(0, NVT);
1219 Hi = DAG.getConstant(0, NVT);
1220 } else if (Amt > NVTBits) {
1221 Lo = DAG.getNode(ISD::SRL, DL,
1222 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1223 Hi = DAG.getConstant(0, NVT);
1224 } else if (Amt == NVTBits) {
1226 Hi = DAG.getConstant(0, NVT);
1228 Lo = DAG.getNode(ISD::OR, DL, NVT,
1229 DAG.getNode(ISD::SRL, DL, NVT, InL,
1230 DAG.getConstant(Amt, ShTy)),
1231 DAG.getNode(ISD::SHL, DL, NVT, InH,
1232 DAG.getConstant(NVTBits-Amt, ShTy)));
1233 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1238 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1240 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1241 DAG.getConstant(NVTBits-1, ShTy));
1242 } else if (Amt > NVTBits) {
1243 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1244 DAG.getConstant(Amt-NVTBits, ShTy));
1245 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1246 DAG.getConstant(NVTBits-1, ShTy));
1247 } else if (Amt == NVTBits) {
1249 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1250 DAG.getConstant(NVTBits-1, ShTy));
1252 Lo = DAG.getNode(ISD::OR, DL, NVT,
1253 DAG.getNode(ISD::SRL, DL, NVT, InL,
1254 DAG.getConstant(Amt, ShTy)),
1255 DAG.getNode(ISD::SHL, DL, NVT, InH,
1256 DAG.getConstant(NVTBits-Amt, ShTy)));
1257 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1261 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1262 /// this shift based on knowledge of the high bit of the shift amount. If we
1263 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1265 bool DAGTypeLegalizer::
1266 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1267 SDValue Amt = N->getOperand(1);
1268 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1269 EVT ShTy = Amt.getValueType();
1270 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1271 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1272 assert(isPowerOf2_32(NVTBits) &&
1273 "Expanded integer type size not a power of two!");
1274 DebugLoc dl = N->getDebugLoc();
1276 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1277 APInt KnownZero, KnownOne;
1278 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1280 // If we don't know anything about the high bits, exit.
1281 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1284 // Get the incoming operand to be shifted.
1286 GetExpandedInteger(N->getOperand(0), InL, InH);
1288 // If we know that any of the high bits of the shift amount are one, then we
1289 // can do this as a couple of simple shifts.
1290 if (KnownOne.intersects(HighBitMask)) {
1291 // Mask out the high bit, which we know is set.
1292 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1293 DAG.getConstant(~HighBitMask, ShTy));
1295 switch (N->getOpcode()) {
1296 default: llvm_unreachable("Unknown shift");
1298 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1299 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1302 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1303 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1306 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1307 DAG.getConstant(NVTBits-1, ShTy));
1308 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1314 // FIXME: This code is broken for shifts with a zero amount!
1315 // If we know that all of the high bits of the shift amount are zero, then we
1316 // can do this as a couple of simple shifts.
1317 if ((KnownZero & HighBitMask) == HighBitMask) {
1319 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1320 DAG.getConstant(NVTBits, ShTy),
1323 switch (N->getOpcode()) {
1324 default: llvm_unreachable("Unknown shift");
1325 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1327 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1330 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1331 Hi = DAG.getNode(ISD::OR, NVT,
1332 DAG.getNode(Op1, NVT, InH, Amt),
1333 DAG.getNode(Op2, NVT, InL, Amt2));
1341 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1343 bool DAGTypeLegalizer::
1344 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1345 SDValue Amt = N->getOperand(1);
1346 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1347 EVT ShTy = Amt.getValueType();
1348 unsigned NVTBits = NVT.getSizeInBits();
1349 assert(isPowerOf2_32(NVTBits) &&
1350 "Expanded integer type size not a power of two!");
1351 DebugLoc dl = N->getDebugLoc();
1353 // Get the incoming operand to be shifted.
1355 GetExpandedInteger(N->getOperand(0), InL, InH);
1357 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1358 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1359 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1360 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1361 Amt, NVBitsNode, ISD::SETULT);
1363 SDValue LoS, HiS, LoL, HiL;
1364 switch (N->getOpcode()) {
1365 default: llvm_unreachable("Unknown shift");
1367 // Short: ShAmt < NVTBits
1368 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1369 HiS = DAG.getNode(ISD::OR, dl, NVT,
1370 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1371 // FIXME: If Amt is zero, the following shift generates an undefined result
1372 // on some architectures.
1373 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1375 // Long: ShAmt >= NVTBits
1376 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1377 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1379 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1380 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1383 // Short: ShAmt < NVTBits
1384 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1385 LoS = DAG.getNode(ISD::OR, dl, NVT,
1386 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1387 // FIXME: If Amt is zero, the following shift generates an undefined result
1388 // on some architectures.
1389 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1391 // Long: ShAmt >= NVTBits
1392 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1393 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1395 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1396 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1399 // Short: ShAmt < NVTBits
1400 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1401 LoS = DAG.getNode(ISD::OR, dl, NVT,
1402 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1403 // FIXME: If Amt is zero, the following shift generates an undefined result
1404 // on some architectures.
1405 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1407 // Long: ShAmt >= NVTBits
1408 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1409 DAG.getConstant(NVTBits-1, ShTy));
1410 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1412 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1413 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1420 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1421 SDValue &Lo, SDValue &Hi) {
1422 DebugLoc dl = N->getDebugLoc();
1423 // Expand the subcomponents.
1424 SDValue LHSL, LHSH, RHSL, RHSH;
1425 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1426 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1428 EVT NVT = LHSL.getValueType();
1429 SDValue LoOps[2] = { LHSL, RHSL };
1430 SDValue HiOps[3] = { LHSH, RHSH };
1432 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1433 // them. TODO: Teach operation legalization how to expand unsupported
1434 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1435 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1436 // generate a value of this type in the expanded code sequence.
1438 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1439 ISD::ADDC : ISD::SUBC,
1440 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1443 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1444 if (N->getOpcode() == ISD::ADD) {
1445 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1446 HiOps[2] = Lo.getValue(1);
1447 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1449 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1450 HiOps[2] = Lo.getValue(1);
1451 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1456 if (N->getOpcode() == ISD::ADD) {
1457 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1458 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1459 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1461 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1462 DAG.getConstant(1, NVT),
1463 DAG.getConstant(0, NVT));
1464 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1466 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1467 DAG.getConstant(1, NVT), Carry1);
1468 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1470 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1471 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1473 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1474 LoOps[0], LoOps[1], ISD::SETULT);
1475 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1476 DAG.getConstant(1, NVT),
1477 DAG.getConstant(0, NVT));
1478 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1482 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1483 SDValue &Lo, SDValue &Hi) {
1484 // Expand the subcomponents.
1485 SDValue LHSL, LHSH, RHSL, RHSH;
1486 DebugLoc dl = N->getDebugLoc();
1487 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1488 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1489 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1490 SDValue LoOps[2] = { LHSL, RHSL };
1491 SDValue HiOps[3] = { LHSH, RHSH };
1493 if (N->getOpcode() == ISD::ADDC) {
1494 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1495 HiOps[2] = Lo.getValue(1);
1496 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1498 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1499 HiOps[2] = Lo.getValue(1);
1500 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1503 // Legalized the flag result - switch anything that used the old flag to
1505 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1508 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1509 SDValue &Lo, SDValue &Hi) {
1510 // Expand the subcomponents.
1511 SDValue LHSL, LHSH, RHSL, RHSH;
1512 DebugLoc dl = N->getDebugLoc();
1513 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1514 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1515 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1516 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1517 SDValue HiOps[3] = { LHSH, RHSH };
1519 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1520 HiOps[2] = Lo.getValue(1);
1521 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1523 // Legalized the flag result - switch anything that used the old flag to
1525 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1528 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1529 SDValue &Lo, SDValue &Hi) {
1530 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1531 DebugLoc dl = N->getDebugLoc();
1532 SDValue Op = N->getOperand(0);
1533 if (Op.getValueType().bitsLE(NVT)) {
1534 // The low part is any extension of the input (which degenerates to a copy).
1535 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1536 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1538 // For example, extension of an i48 to an i64. The operand type necessarily
1539 // promotes to the result type, so will end up being expanded too.
1540 assert(getTypeAction(Op.getValueType()) ==
1541 TargetLowering::TypePromoteInteger &&
1542 "Only know how to promote this result!");
1543 SDValue Res = GetPromotedInteger(Op);
1544 assert(Res.getValueType() == N->getValueType(0) &&
1545 "Operand over promoted?");
1546 // Split the promoted operand. This will simplify when it is expanded.
1547 SplitInteger(Res, Lo, Hi);
1551 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1552 SDValue &Lo, SDValue &Hi) {
1553 DebugLoc dl = N->getDebugLoc();
1554 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1555 EVT NVT = Lo.getValueType();
1556 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1557 unsigned NVTBits = NVT.getSizeInBits();
1558 unsigned EVTBits = EVT.getSizeInBits();
1560 if (NVTBits < EVTBits) {
1561 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1562 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1563 EVTBits - NVTBits)));
1565 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1566 // The high part replicates the sign bit of Lo, make it explicit.
1567 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1568 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1572 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1573 SDValue &Lo, SDValue &Hi) {
1574 DebugLoc dl = N->getDebugLoc();
1575 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1576 EVT NVT = Lo.getValueType();
1577 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1578 unsigned NVTBits = NVT.getSizeInBits();
1579 unsigned EVTBits = EVT.getSizeInBits();
1581 if (NVTBits < EVTBits) {
1582 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1583 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1584 EVTBits - NVTBits)));
1586 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1587 // The high part must be zero, make it explicit.
1588 Hi = DAG.getConstant(0, NVT);
1592 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1593 SDValue &Lo, SDValue &Hi) {
1594 DebugLoc dl = N->getDebugLoc();
1595 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1596 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1597 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1600 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1601 SDValue &Lo, SDValue &Hi) {
1602 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1603 unsigned NBitWidth = NVT.getSizeInBits();
1604 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1605 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1606 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1609 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1610 SDValue &Lo, SDValue &Hi) {
1611 DebugLoc dl = N->getDebugLoc();
1612 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1613 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1614 EVT NVT = Lo.getValueType();
1616 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1617 DAG.getConstant(0, NVT), ISD::SETNE);
1619 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1620 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1622 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1623 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1624 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1625 Hi = DAG.getConstant(0, NVT);
1628 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1629 SDValue &Lo, SDValue &Hi) {
1630 DebugLoc dl = N->getDebugLoc();
1631 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1632 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1633 EVT NVT = Lo.getValueType();
1634 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1635 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1636 Hi = DAG.getConstant(0, NVT);
1639 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1640 SDValue &Lo, SDValue &Hi) {
1641 DebugLoc dl = N->getDebugLoc();
1642 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1643 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1644 EVT NVT = Lo.getValueType();
1646 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1647 DAG.getConstant(0, NVT), ISD::SETNE);
1649 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1650 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1652 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1653 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1654 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1655 Hi = DAG.getConstant(0, NVT);
1658 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1660 DebugLoc dl = N->getDebugLoc();
1661 EVT VT = N->getValueType(0);
1662 SDValue Op = N->getOperand(0);
1663 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1664 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1665 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1668 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1670 DebugLoc dl = N->getDebugLoc();
1671 EVT VT = N->getValueType(0);
1672 SDValue Op = N->getOperand(0);
1673 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1674 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1675 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1678 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1679 SDValue &Lo, SDValue &Hi) {
1680 if (ISD::isNormalLoad(N)) {
1681 ExpandRes_NormalLoad(N, Lo, Hi);
1685 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1687 EVT VT = N->getValueType(0);
1688 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1689 SDValue Ch = N->getChain();
1690 SDValue Ptr = N->getBasePtr();
1691 ISD::LoadExtType ExtType = N->getExtensionType();
1692 unsigned Alignment = N->getAlignment();
1693 bool isVolatile = N->isVolatile();
1694 bool isNonTemporal = N->isNonTemporal();
1695 DebugLoc dl = N->getDebugLoc();
1697 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1699 if (N->getMemoryVT().bitsLE(NVT)) {
1700 EVT MemVT = N->getMemoryVT();
1702 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1703 MemVT, isVolatile, isNonTemporal, Alignment);
1705 // Remember the chain.
1706 Ch = Lo.getValue(1);
1708 if (ExtType == ISD::SEXTLOAD) {
1709 // The high part is obtained by SRA'ing all but one of the bits of the
1711 unsigned LoSize = Lo.getValueType().getSizeInBits();
1712 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1713 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1714 } else if (ExtType == ISD::ZEXTLOAD) {
1715 // The high part is just a zero.
1716 Hi = DAG.getConstant(0, NVT);
1718 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1719 // The high part is undefined.
1720 Hi = DAG.getUNDEF(NVT);
1722 } else if (TLI.isLittleEndian()) {
1723 // Little-endian - low bits are at low addresses.
1724 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1725 isVolatile, isNonTemporal, Alignment);
1727 unsigned ExcessBits =
1728 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1729 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1731 // Increment the pointer to the other half.
1732 unsigned IncrementSize = NVT.getSizeInBits()/8;
1733 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1734 DAG.getIntPtrConstant(IncrementSize));
1735 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1736 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1737 isVolatile, isNonTemporal,
1738 MinAlign(Alignment, IncrementSize));
1740 // Build a factor node to remember that this load is independent of the
1742 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1745 // Big-endian - high bits are at low addresses. Favor aligned loads at
1746 // the cost of some bit-fiddling.
1747 EVT MemVT = N->getMemoryVT();
1748 unsigned EBytes = MemVT.getStoreSize();
1749 unsigned IncrementSize = NVT.getSizeInBits()/8;
1750 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1752 // Load both the high bits and maybe some of the low bits.
1753 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1754 EVT::getIntegerVT(*DAG.getContext(),
1755 MemVT.getSizeInBits() - ExcessBits),
1756 isVolatile, isNonTemporal, Alignment);
1758 // Increment the pointer to the other half.
1759 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1760 DAG.getIntPtrConstant(IncrementSize));
1761 // Load the rest of the low bits.
1762 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1763 N->getPointerInfo().getWithOffset(IncrementSize),
1764 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1765 isVolatile, isNonTemporal,
1766 MinAlign(Alignment, IncrementSize));
1768 // Build a factor node to remember that this load is independent of the
1770 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1773 if (ExcessBits < NVT.getSizeInBits()) {
1774 // Transfer low bits from the bottom of Hi to the top of Lo.
1775 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1776 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1777 DAG.getConstant(ExcessBits,
1778 TLI.getPointerTy())));
1779 // Move high bits to the right position in Hi.
1780 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1782 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1783 TLI.getPointerTy()));
1787 // Legalized the chain result - switch anything that used the old chain to
1789 ReplaceValueWith(SDValue(N, 1), Ch);
1792 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1793 SDValue &Lo, SDValue &Hi) {
1794 DebugLoc dl = N->getDebugLoc();
1795 SDValue LL, LH, RL, RH;
1796 GetExpandedInteger(N->getOperand(0), LL, LH);
1797 GetExpandedInteger(N->getOperand(1), RL, RH);
1798 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1799 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1802 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1803 SDValue &Lo, SDValue &Hi) {
1804 EVT VT = N->getValueType(0);
1805 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1806 DebugLoc dl = N->getDebugLoc();
1808 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1809 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1810 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1811 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1812 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1813 SDValue LL, LH, RL, RH;
1814 GetExpandedInteger(N->getOperand(0), LL, LH);
1815 GetExpandedInteger(N->getOperand(1), RL, RH);
1816 unsigned OuterBitSize = VT.getSizeInBits();
1817 unsigned InnerBitSize = NVT.getSizeInBits();
1818 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1819 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1821 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1822 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1823 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1824 // The inputs are both zero-extended.
1826 // We can emit a umul_lohi.
1827 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1828 Hi = SDValue(Lo.getNode(), 1);
1832 // We can emit a mulhu+mul.
1833 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1834 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1838 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1839 // The input values are both sign-extended.
1841 // We can emit a smul_lohi.
1842 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1843 Hi = SDValue(Lo.getNode(), 1);
1847 // We can emit a mulhs+mul.
1848 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1849 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1854 // Lo,Hi = umul LHS, RHS.
1855 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1856 DAG.getVTList(NVT, NVT), LL, RL);
1858 Hi = UMulLOHI.getValue(1);
1859 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1860 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1861 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1862 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1866 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1867 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1868 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1869 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1870 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1871 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1876 // If nothing else, we can make a libcall.
1877 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1879 LC = RTLIB::MUL_I16;
1880 else if (VT == MVT::i32)
1881 LC = RTLIB::MUL_I32;
1882 else if (VT == MVT::i64)
1883 LC = RTLIB::MUL_I64;
1884 else if (VT == MVT::i128)
1885 LC = RTLIB::MUL_I128;
1886 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1888 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1889 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1892 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1893 SDValue &Lo, SDValue &Hi) {
1894 SDValue LHS = Node->getOperand(0);
1895 SDValue RHS = Node->getOperand(1);
1896 DebugLoc dl = Node->getDebugLoc();
1898 // Expand the result by simply replacing it with the equivalent
1899 // non-overflow-checking operation.
1900 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1901 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1903 SplitInteger(Sum, Lo, Hi);
1905 // Compute the overflow.
1907 // LHSSign -> LHS >= 0
1908 // RHSSign -> RHS >= 0
1909 // SumSign -> Sum >= 0
1912 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
1914 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
1916 EVT OType = Node->getValueType(1);
1917 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
1919 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
1920 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
1921 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
1922 Node->getOpcode() == ISD::SADDO ?
1923 ISD::SETEQ : ISD::SETNE);
1925 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
1926 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
1928 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
1930 // Use the calculated overflow everywhere.
1931 ReplaceValueWith(SDValue(Node, 1), Cmp);
1934 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1935 SDValue &Lo, SDValue &Hi) {
1936 EVT VT = N->getValueType(0);
1937 DebugLoc dl = N->getDebugLoc();
1939 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1941 LC = RTLIB::SDIV_I16;
1942 else if (VT == MVT::i32)
1943 LC = RTLIB::SDIV_I32;
1944 else if (VT == MVT::i64)
1945 LC = RTLIB::SDIV_I64;
1946 else if (VT == MVT::i128)
1947 LC = RTLIB::SDIV_I128;
1948 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1950 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1951 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1954 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1955 SDValue &Lo, SDValue &Hi) {
1956 EVT VT = N->getValueType(0);
1957 DebugLoc dl = N->getDebugLoc();
1959 // If we can emit an efficient shift operation, do so now. Check to see if
1960 // the RHS is a constant.
1961 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1962 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1964 // If we can determine that the high bit of the shift is zero or one, even if
1965 // the low bits are variable, emit this shift in an optimized form.
1966 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1969 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1971 if (N->getOpcode() == ISD::SHL) {
1972 PartsOpc = ISD::SHL_PARTS;
1973 } else if (N->getOpcode() == ISD::SRL) {
1974 PartsOpc = ISD::SRL_PARTS;
1976 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1977 PartsOpc = ISD::SRA_PARTS;
1980 // Next check to see if the target supports this SHL_PARTS operation or if it
1981 // will custom expand it.
1982 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1983 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1984 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1985 Action == TargetLowering::Custom) {
1986 // Expand the subcomponents.
1988 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1990 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1991 EVT VT = LHSL.getValueType();
1992 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1993 Hi = Lo.getValue(1);
1997 // Otherwise, emit a libcall.
1998 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2000 if (N->getOpcode() == ISD::SHL) {
2001 isSigned = false; /*sign irrelevant*/
2003 LC = RTLIB::SHL_I16;
2004 else if (VT == MVT::i32)
2005 LC = RTLIB::SHL_I32;
2006 else if (VT == MVT::i64)
2007 LC = RTLIB::SHL_I64;
2008 else if (VT == MVT::i128)
2009 LC = RTLIB::SHL_I128;
2010 } else if (N->getOpcode() == ISD::SRL) {
2013 LC = RTLIB::SRL_I16;
2014 else if (VT == MVT::i32)
2015 LC = RTLIB::SRL_I32;
2016 else if (VT == MVT::i64)
2017 LC = RTLIB::SRL_I64;
2018 else if (VT == MVT::i128)
2019 LC = RTLIB::SRL_I128;
2021 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2024 LC = RTLIB::SRA_I16;
2025 else if (VT == MVT::i32)
2026 LC = RTLIB::SRA_I32;
2027 else if (VT == MVT::i64)
2028 LC = RTLIB::SRA_I64;
2029 else if (VT == MVT::i128)
2030 LC = RTLIB::SRA_I128;
2033 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2034 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2035 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
2039 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2040 llvm_unreachable("Unsupported shift!");
2043 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2044 SDValue &Lo, SDValue &Hi) {
2045 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2046 DebugLoc dl = N->getDebugLoc();
2047 SDValue Op = N->getOperand(0);
2048 if (Op.getValueType().bitsLE(NVT)) {
2049 // The low part is sign extension of the input (degenerates to a copy).
2050 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2051 // The high part is obtained by SRA'ing all but one of the bits of low part.
2052 unsigned LoSize = NVT.getSizeInBits();
2053 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2054 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2056 // For example, extension of an i48 to an i64. The operand type necessarily
2057 // promotes to the result type, so will end up being expanded too.
2058 assert(getTypeAction(Op.getValueType()) ==
2059 TargetLowering::TypePromoteInteger &&
2060 "Only know how to promote this result!");
2061 SDValue Res = GetPromotedInteger(Op);
2062 assert(Res.getValueType() == N->getValueType(0) &&
2063 "Operand over promoted?");
2064 // Split the promoted operand. This will simplify when it is expanded.
2065 SplitInteger(Res, Lo, Hi);
2066 unsigned ExcessBits =
2067 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2068 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2069 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2074 void DAGTypeLegalizer::
2075 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2076 DebugLoc dl = N->getDebugLoc();
2077 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2078 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2080 if (EVT.bitsLE(Lo.getValueType())) {
2081 // sext_inreg the low part if needed.
2082 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2085 // The high part gets the sign extension from the lo-part. This handles
2086 // things like sextinreg V:i64 from i8.
2087 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2088 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2089 TLI.getPointerTy()));
2091 // For example, extension of an i48 to an i64. Leave the low part alone,
2092 // sext_inreg the high part.
2093 unsigned ExcessBits =
2094 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2095 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2096 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2101 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2102 SDValue &Lo, SDValue &Hi) {
2103 EVT VT = N->getValueType(0);
2104 DebugLoc dl = N->getDebugLoc();
2106 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2108 LC = RTLIB::SREM_I16;
2109 else if (VT == MVT::i32)
2110 LC = RTLIB::SREM_I32;
2111 else if (VT == MVT::i64)
2112 LC = RTLIB::SREM_I64;
2113 else if (VT == MVT::i128)
2114 LC = RTLIB::SREM_I128;
2115 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2117 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2118 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2121 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2122 SDValue &Lo, SDValue &Hi) {
2123 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2124 DebugLoc dl = N->getDebugLoc();
2125 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2126 Hi = DAG.getNode(ISD::SRL, dl,
2127 N->getOperand(0).getValueType(), N->getOperand(0),
2128 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2129 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2132 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2133 SDValue &Lo, SDValue &Hi) {
2134 SDValue LHS = N->getOperand(0);
2135 SDValue RHS = N->getOperand(1);
2136 DebugLoc dl = N->getDebugLoc();
2138 // Expand the result by simply replacing it with the equivalent
2139 // non-overflow-checking operation.
2140 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2141 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2143 SplitInteger(Sum, Lo, Hi);
2145 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2146 // overflows iff a - b > a.
2147 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2148 N->getOpcode () == ISD::UADDO ?
2149 ISD::SETULT : ISD::SETUGT);
2151 // Use the calculated overflow everywhere.
2152 ReplaceValueWith(SDValue(N, 1), Ofl);
2155 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2156 SDValue &Lo, SDValue &Hi) {
2157 EVT VT = N->getValueType(0);
2158 const Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2159 EVT PtrVT = TLI.getPointerTy();
2160 const Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2161 DebugLoc dl = N->getDebugLoc();
2163 // A divide for UMULO should be faster than a function call.
2164 if (N->getOpcode() == ISD::UMULO) {
2165 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2166 DebugLoc DL = N->getDebugLoc();
2168 SDValue MUL = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
2169 SplitInteger(MUL, Lo, Hi);
2171 // A divide for UMULO will be faster than a function call. Select to
2172 // make sure we aren't using 0.
2173 SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2174 RHS, DAG.getConstant(0, VT), ISD::SETNE);
2175 SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
2176 DAG.getConstant(1, VT), RHS);
2177 SDValue DIV = DAG.getNode(ISD::UDIV, DL, LHS.getValueType(), MUL, NotZero);
2179 Overflow = DAG.getSetCC(DL, N->getValueType(1), DIV, LHS, ISD::SETNE);
2180 ReplaceValueWith(SDValue(N, 1), Overflow);
2184 // Replace this with a libcall that will check overflow.
2185 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2187 LC = RTLIB::MULO_I32;
2188 else if (VT == MVT::i64)
2189 LC = RTLIB::MULO_I64;
2190 else if (VT == MVT::i128)
2191 LC = RTLIB::MULO_I128;
2192 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2194 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2195 // Temporary for the overflow value, default it to zero.
2196 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2197 DAG.getConstant(0, PtrVT), Temp,
2198 MachinePointerInfo(), false, false, 0);
2200 TargetLowering::ArgListTy Args;
2201 TargetLowering::ArgListEntry Entry;
2202 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2203 EVT ArgVT = N->getOperand(i).getValueType();
2204 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2205 Entry.Node = N->getOperand(i);
2207 Entry.isSExt = true;
2208 Entry.isZExt = false;
2209 Args.push_back(Entry);
2212 // Also pass the address of the overflow check.
2214 Entry.Ty = PtrTy->getPointerTo();
2215 Entry.isSExt = true;
2216 Entry.isZExt = false;
2217 Args.push_back(Entry);
2219 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2220 std::pair<SDValue, SDValue> CallInfo =
2221 TLI.LowerCallTo(Chain, RetTy, true, false, false, false,
2222 0, TLI.getLibcallCallingConv(LC), false,
2223 true, Func, Args, DAG, dl);
2225 SplitInteger(CallInfo.first, Lo, Hi);
2226 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2227 MachinePointerInfo(), false, false, 0);
2228 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2229 DAG.getConstant(0, PtrVT),
2231 // Use the overflow from the libcall everywhere.
2232 ReplaceValueWith(SDValue(N, 1), Ofl);
2235 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2236 SDValue &Lo, SDValue &Hi) {
2237 EVT VT = N->getValueType(0);
2238 DebugLoc dl = N->getDebugLoc();
2240 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2242 LC = RTLIB::UDIV_I16;
2243 else if (VT == MVT::i32)
2244 LC = RTLIB::UDIV_I32;
2245 else if (VT == MVT::i64)
2246 LC = RTLIB::UDIV_I64;
2247 else if (VT == MVT::i128)
2248 LC = RTLIB::UDIV_I128;
2249 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2251 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2252 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2255 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2256 SDValue &Lo, SDValue &Hi) {
2257 EVT VT = N->getValueType(0);
2258 DebugLoc dl = N->getDebugLoc();
2260 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2262 LC = RTLIB::UREM_I16;
2263 else if (VT == MVT::i32)
2264 LC = RTLIB::UREM_I32;
2265 else if (VT == MVT::i64)
2266 LC = RTLIB::UREM_I64;
2267 else if (VT == MVT::i128)
2268 LC = RTLIB::UREM_I128;
2269 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2271 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2272 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2275 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2276 SDValue &Lo, SDValue &Hi) {
2277 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2278 DebugLoc dl = N->getDebugLoc();
2279 SDValue Op = N->getOperand(0);
2280 if (Op.getValueType().bitsLE(NVT)) {
2281 // The low part is zero extension of the input (degenerates to a copy).
2282 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2283 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2285 // For example, extension of an i48 to an i64. The operand type necessarily
2286 // promotes to the result type, so will end up being expanded too.
2287 assert(getTypeAction(Op.getValueType()) ==
2288 TargetLowering::TypePromoteInteger &&
2289 "Only know how to promote this result!");
2290 SDValue Res = GetPromotedInteger(Op);
2291 assert(Res.getValueType() == N->getValueType(0) &&
2292 "Operand over promoted?");
2293 // Split the promoted operand. This will simplify when it is expanded.
2294 SplitInteger(Res, Lo, Hi);
2295 unsigned ExcessBits =
2296 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2297 Hi = DAG.getZeroExtendInReg(Hi, dl,
2298 EVT::getIntegerVT(*DAG.getContext(),
2304 //===----------------------------------------------------------------------===//
2305 // Integer Operand Expansion
2306 //===----------------------------------------------------------------------===//
2308 /// ExpandIntegerOperand - This method is called when the specified operand of
2309 /// the specified node is found to need expansion. At this point, all of the
2310 /// result types of the node are known to be legal, but other operands of the
2311 /// node may need promotion or expansion as well as the specified one.
2312 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2313 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2314 SDValue Res = SDValue();
2316 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2319 switch (N->getOpcode()) {
2322 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2323 N->dump(&DAG); dbgs() << "\n";
2325 llvm_unreachable("Do not know how to expand this operator's operand!");
2327 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2328 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2329 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2330 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2331 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2332 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2333 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2334 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2335 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2336 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2337 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2338 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2344 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2345 case ISD::RETURNADDR:
2346 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2349 // If the result is null, the sub-method took care of registering results etc.
2350 if (!Res.getNode()) return false;
2352 // If the result is N, the sub-method updated N in place. Tell the legalizer
2354 if (Res.getNode() == N)
2357 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2358 "Invalid operand expansion");
2360 ReplaceValueWith(SDValue(N, 0), Res);
2364 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2365 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2366 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2368 ISD::CondCode &CCCode,
2370 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2371 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2372 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2374 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2375 if (RHSLo == RHSHi) {
2376 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2377 if (RHSCST->isAllOnesValue()) {
2378 // Equality comparison to -1.
2379 NewLHS = DAG.getNode(ISD::AND, dl,
2380 LHSLo.getValueType(), LHSLo, LHSHi);
2387 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2388 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2389 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2390 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2394 // If this is a comparison of the sign bit, just look at the top part.
2396 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2397 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2398 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2404 // FIXME: This generated code sucks.
2405 ISD::CondCode LowCC;
2407 default: llvm_unreachable("Unknown integer setcc!");
2409 case ISD::SETULT: LowCC = ISD::SETULT; break;
2411 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2413 case ISD::SETULE: LowCC = ISD::SETULE; break;
2415 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2418 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2419 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2420 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2422 // NOTE: on targets without efficient SELECT of bools, we can always use
2423 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2424 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2426 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2427 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2428 if (!Tmp1.getNode())
2429 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2430 LHSLo, RHSLo, LowCC);
2431 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2432 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2433 if (!Tmp2.getNode())
2434 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2435 TLI.getSetCCResultType(LHSHi.getValueType()),
2436 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2438 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2439 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2440 if ((Tmp1C && Tmp1C->isNullValue()) ||
2441 (Tmp2C && Tmp2C->isNullValue() &&
2442 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2443 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2444 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2445 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2446 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2447 // low part is known false, returns high part.
2448 // For LE / GE, if high part is known false, ignore the low part.
2449 // For LT / GT, if high part is known true, ignore the low part.
2455 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2456 LHSHi, RHSHi, ISD::SETEQ, false,
2457 DagCombineInfo, dl);
2458 if (!NewLHS.getNode())
2459 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2460 LHSHi, RHSHi, ISD::SETEQ);
2461 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2462 NewLHS, Tmp1, Tmp2);
2466 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2467 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2468 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2469 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2471 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2472 // against zero to select between true and false values.
2473 if (NewRHS.getNode() == 0) {
2474 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2475 CCCode = ISD::SETNE;
2478 // Update N to have the operands specified.
2479 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2480 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2481 N->getOperand(4)), 0);
2484 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2485 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2486 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2487 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2489 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2490 // against zero to select between true and false values.
2491 if (NewRHS.getNode() == 0) {
2492 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2493 CCCode = ISD::SETNE;
2496 // Update N to have the operands specified.
2497 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2498 N->getOperand(2), N->getOperand(3),
2499 DAG.getCondCode(CCCode)), 0);
2502 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2503 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2504 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2505 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2507 // If ExpandSetCCOperands returned a scalar, use it.
2508 if (NewRHS.getNode() == 0) {
2509 assert(NewLHS.getValueType() == N->getValueType(0) &&
2510 "Unexpected setcc expansion!");
2514 // Otherwise, update N to have the operands specified.
2515 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2516 DAG.getCondCode(CCCode)), 0);
2519 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2520 // The value being shifted is legal, but the shift amount is too big.
2521 // It follows that either the result of the shift is undefined, or the
2522 // upper half of the shift amount is zero. Just use the lower half.
2524 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2525 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2528 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2529 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2530 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2531 // constant to valid type.
2533 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2534 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2537 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2538 SDValue Op = N->getOperand(0);
2539 EVT DstVT = N->getValueType(0);
2540 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2541 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2542 "Don't know how to expand this SINT_TO_FP!");
2543 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2546 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2547 if (ISD::isNormalStore(N))
2548 return ExpandOp_NormalStore(N, OpNo);
2550 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2551 assert(OpNo == 1 && "Can only expand the stored value so far");
2553 EVT VT = N->getOperand(1).getValueType();
2554 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2555 SDValue Ch = N->getChain();
2556 SDValue Ptr = N->getBasePtr();
2557 unsigned Alignment = N->getAlignment();
2558 bool isVolatile = N->isVolatile();
2559 bool isNonTemporal = N->isNonTemporal();
2560 DebugLoc dl = N->getDebugLoc();
2563 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2565 if (N->getMemoryVT().bitsLE(NVT)) {
2566 GetExpandedInteger(N->getValue(), Lo, Hi);
2567 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2568 N->getMemoryVT(), isVolatile, isNonTemporal,
2572 if (TLI.isLittleEndian()) {
2573 // Little-endian - low bits are at low addresses.
2574 GetExpandedInteger(N->getValue(), Lo, Hi);
2576 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2577 isVolatile, isNonTemporal, Alignment);
2579 unsigned ExcessBits =
2580 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2581 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2583 // Increment the pointer to the other half.
2584 unsigned IncrementSize = NVT.getSizeInBits()/8;
2585 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2586 DAG.getIntPtrConstant(IncrementSize));
2587 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2588 N->getPointerInfo().getWithOffset(IncrementSize),
2589 NEVT, isVolatile, isNonTemporal,
2590 MinAlign(Alignment, IncrementSize));
2591 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2594 // Big-endian - high bits are at low addresses. Favor aligned stores at
2595 // the cost of some bit-fiddling.
2596 GetExpandedInteger(N->getValue(), Lo, Hi);
2598 EVT ExtVT = N->getMemoryVT();
2599 unsigned EBytes = ExtVT.getStoreSize();
2600 unsigned IncrementSize = NVT.getSizeInBits()/8;
2601 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2602 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2603 ExtVT.getSizeInBits() - ExcessBits);
2605 if (ExcessBits < NVT.getSizeInBits()) {
2606 // Transfer high bits from the top of Lo to the bottom of Hi.
2607 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2608 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2609 TLI.getPointerTy()));
2610 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2611 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2612 DAG.getConstant(ExcessBits,
2613 TLI.getPointerTy())));
2616 // Store both the high bits and maybe some of the low bits.
2617 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2618 HiVT, isVolatile, isNonTemporal, Alignment);
2620 // Increment the pointer to the other half.
2621 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2622 DAG.getIntPtrConstant(IncrementSize));
2623 // Store the lowest ExcessBits bits in the second half.
2624 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2625 N->getPointerInfo().getWithOffset(IncrementSize),
2626 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2627 isVolatile, isNonTemporal,
2628 MinAlign(Alignment, IncrementSize));
2629 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2632 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2634 GetExpandedInteger(N->getOperand(0), InL, InH);
2635 // Just truncate the low part of the source.
2636 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2639 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2640 switch (VT.getSimpleVT().SimpleTy) {
2641 default: llvm_unreachable("Unknown FP format");
2642 case MVT::f32: return &APFloat::IEEEsingle;
2643 case MVT::f64: return &APFloat::IEEEdouble;
2644 case MVT::f80: return &APFloat::x87DoubleExtended;
2645 case MVT::f128: return &APFloat::IEEEquad;
2646 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2650 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2651 SDValue Op = N->getOperand(0);
2652 EVT SrcVT = Op.getValueType();
2653 EVT DstVT = N->getValueType(0);
2654 DebugLoc dl = N->getDebugLoc();
2656 // The following optimization is valid only if every value in SrcVT (when
2657 // treated as signed) is representable in DstVT. Check that the mantissa
2658 // size of DstVT is >= than the number of bits in SrcVT -1.
2659 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2660 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2661 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2662 // Do a signed conversion then adjust the result.
2663 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2664 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2666 // The result of the signed conversion needs adjusting if the 'sign bit' of
2667 // the incoming integer was set. To handle this, we dynamically test to see
2668 // if it is set, and, if so, add a fudge factor.
2670 const uint64_t F32TwoE32 = 0x4F800000ULL;
2671 const uint64_t F32TwoE64 = 0x5F800000ULL;
2672 const uint64_t F32TwoE128 = 0x7F800000ULL;
2675 if (SrcVT == MVT::i32)
2676 FF = APInt(32, F32TwoE32);
2677 else if (SrcVT == MVT::i64)
2678 FF = APInt(32, F32TwoE64);
2679 else if (SrcVT == MVT::i128)
2680 FF = APInt(32, F32TwoE128);
2682 assert(false && "Unsupported UINT_TO_FP!");
2684 // Check whether the sign bit is set.
2686 GetExpandedInteger(Op, Lo, Hi);
2687 SDValue SignSet = DAG.getSetCC(dl,
2688 TLI.getSetCCResultType(Hi.getValueType()),
2689 Hi, DAG.getConstant(0, Hi.getValueType()),
2692 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2693 SDValue FudgePtr = DAG.getConstantPool(
2694 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2695 TLI.getPointerTy());
2697 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2698 SDValue Zero = DAG.getIntPtrConstant(0);
2699 SDValue Four = DAG.getIntPtrConstant(4);
2700 if (TLI.isBigEndian()) std::swap(Zero, Four);
2701 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2703 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2704 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2705 Alignment = std::min(Alignment, 4u);
2707 // Load the value out, extending it from f32 to the destination float type.
2708 // FIXME: Avoid the extend by constructing the right constant pool?
2709 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2711 MachinePointerInfo::getConstantPool(),
2713 false, false, Alignment);
2714 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2717 // Otherwise, use a libcall.
2718 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2719 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2720 "Don't know how to expand this UINT_TO_FP!");
2721 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);
2724 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2725 SDValue InOp0 = N->getOperand(0);
2726 EVT InVT = InOp0.getValueType();
2728 EVT OutVT = N->getValueType(0);
2729 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2730 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2731 unsigned OutNumElems = N->getValueType(0).getVectorNumElements();
2732 EVT NOutVTElem = NOutVT.getVectorElementType();
2734 DebugLoc dl = N->getDebugLoc();
2735 SDValue BaseIdx = N->getOperand(1);
2737 SmallVector<SDValue, 8> Ops;
2738 for (unsigned i = 0; i != OutNumElems; ++i) {
2740 // Extract the element from the original vector.
2741 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2742 BaseIdx, DAG.getIntPtrConstant(i));
2743 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2744 InVT.getVectorElementType(), N->getOperand(0), Index);
2746 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2747 // Insert the converted element to the new vector.
2751 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2755 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2757 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2758 EVT VT = N->getValueType(0);
2759 DebugLoc dl = N->getDebugLoc();
2761 unsigned NumElts = VT.getVectorNumElements();
2762 SmallVector<int, 8> NewMask;
2763 for (unsigned i = 0; i != NumElts; ++i) {
2764 NewMask.push_back(SV->getMaskElt(i));
2767 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2768 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2769 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2771 return DAG.getVectorShuffle(OutVT, dl, V0,V1, &NewMask[0]);
2775 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2776 EVT OutVT = N->getValueType(0);
2777 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2778 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2779 unsigned NumElems = N->getNumOperands();
2780 EVT NOutVTElem = NOutVT.getVectorElementType();
2782 DebugLoc dl = N->getDebugLoc();
2784 SmallVector<SDValue, 8> Ops;
2785 for (unsigned i = 0; i != NumElems; ++i) {
2786 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2790 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2793 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2795 DebugLoc dl = N->getDebugLoc();
2797 assert(!N->getOperand(0).getValueType().isVector() &&
2798 "Input must be a scalar");
2800 EVT OutVT = N->getValueType(0);
2801 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2802 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2803 EVT NOutVTElem = NOutVT.getVectorElementType();
2805 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2807 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2810 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
2811 EVT OutVT = N->getValueType(0);
2812 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2813 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2815 EVT NOutVTElem = NOutVT.getVectorElementType();
2817 DebugLoc dl = N->getDebugLoc();
2819 SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
2822 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
2823 NOutVTElem, N->getOperand(1));
2824 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,NOutVT,
2825 ConvertedVector, ConvElem, N->getOperand(2));
2828 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2829 DebugLoc dl = N->getDebugLoc();
2830 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2831 SDValue V1 = N->getOperand(1);
2832 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2833 V0->getValueType(0).getScalarType(), V0, V1);
2835 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
2839 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
2841 DebugLoc dl = N->getDebugLoc();
2843 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
2845 SmallVector<SDValue, 8> NewOps;
2847 // For each incoming vector
2848 for (unsigned VecIdx = 0, E = N->getNumOperands(); VecIdx!= E; ++VecIdx) {
2849 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
2850 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
2851 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
2853 for (unsigned i=0; i<NumElem; ++i) {
2854 // Extract element from incoming vector
2855 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
2856 Incoming, DAG.getIntPtrConstant(i));
2857 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
2858 NewOps.push_back(Tr);
2862 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
2863 &NewOps[0], NewOps.size());