1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDOperand Result = SDOperand();
36 // See if the target wants to custom expand this node.
37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
38 TargetLowering::Custom) {
39 // If the target wants to, allow it to lower this itself.
40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
41 // Everything that once used N now uses P. We are guaranteed that the
42 // result value types of N and the result value types of P match.
43 ReplaceNodeWith(N, P);
48 switch (N->getOpcode()) {
51 cerr << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); cerr << "\n";
54 assert(0 && "Do not know how to promote this operator!");
56 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
57 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break;
58 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
59 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
60 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
61 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
62 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
63 case ISD::EXTRACT_VECTOR_ELT:
64 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
65 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
66 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
67 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
68 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
69 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
70 case ISD::SIGN_EXTEND_INREG:
71 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
72 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
73 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
74 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
75 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
76 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break;
78 case ISD::SIGN_EXTEND:
79 case ISD::ZERO_EXTEND:
80 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
83 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
90 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
93 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
96 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
99 // If Result is null, the sub-method took care of registering the result.
101 SetPromotedInteger(SDOperand(N, ResNo), Result);
104 SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
105 SDOperand InOp = N->getOperand(0);
106 MVT InVT = InOp.getValueType();
107 MVT NInVT = TLI.getTypeToTransformTo(InVT);
108 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
110 switch (getTypeAction(InVT)) {
112 assert(false && "Unknown type action!");
117 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
118 // The input promotes to the same size. Convert the promoted value.
119 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
122 // Promote the integer operand by hand.
123 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
127 case ScalarizeVector:
128 // Convert the element to an integer and promote it by hand.
129 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
130 BitConvertToInteger(GetScalarizedVector(InOp)));
132 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
133 // pieces of the input into integers and reassemble in the final type.
135 GetSplitVector(N->getOperand(0), Lo, Hi);
136 Lo = BitConvertToInteger(Lo);
137 Hi = BitConvertToInteger(Hi);
139 if (TLI.isBigEndian())
142 InOp = DAG.getNode(ISD::ANY_EXTEND,
143 MVT::getIntegerVT(OutVT.getSizeInBits()),
144 JoinIntegers(Lo, Hi));
145 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
148 // Otherwise, lower the bit-convert to a store/load from the stack, then
150 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
151 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
154 SDOperand DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
155 SDOperand Op = GetPromotedInteger(N->getOperand(0));
156 MVT OVT = N->getValueType(0);
157 MVT NVT = Op.getValueType();
159 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
160 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
161 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
164 SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
165 // The pair element type may be legal, or may not promote to the same type as
166 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
167 return DAG.getNode(ISD::ANY_EXTEND,
168 TLI.getTypeToTransformTo(N->getValueType(0)),
169 JoinIntegers(N->getOperand(0), N->getOperand(1)));
172 SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
173 MVT VT = N->getValueType(0);
174 // Zero extend things like i1, sign extend everything else. It shouldn't
175 // matter in theory which one we pick, but this tends to give better code?
176 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
177 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
179 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
183 SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
184 SDOperand Op = GetPromotedInteger(N->getOperand(0));
185 MVT OVT = N->getValueType(0);
186 MVT NVT = Op.getValueType();
187 // Zero extend to the promoted type and do the count there.
188 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
189 // Subtract off the extra leading bits in the bigger type.
190 return DAG.getNode(ISD::SUB, NVT, Op,
191 DAG.getConstant(NVT.getSizeInBits() -
192 OVT.getSizeInBits(), NVT));
195 SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
196 SDOperand Op = GetPromotedInteger(N->getOperand(0));
197 MVT OVT = N->getValueType(0);
198 MVT NVT = Op.getValueType();
199 // Zero extend to the promoted type and do the count there.
200 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
203 SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
204 SDOperand Op = GetPromotedInteger(N->getOperand(0));
205 MVT OVT = N->getValueType(0);
206 MVT NVT = Op.getValueType();
207 // The count is the same in the promoted type except if the original
208 // value was zero. This can be handled by setting the bit just off
209 // the top of the original type.
210 APInt TopBit(NVT.getSizeInBits(), 0);
211 TopBit.set(OVT.getSizeInBits());
212 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
213 return DAG.getNode(ISD::CTTZ, NVT, Op);
216 SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
217 MVT OldVT = N->getValueType(0);
218 SDOperand OldVec = N->getOperand(0);
219 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
222 assert(!isTypeLegal(OldVec.getValueType()) &&
223 "Legal one-element vector of a type needing promotion!");
224 // It is tempting to follow GetScalarizedVector by a call to
225 // GetPromotedInteger, but this would be wrong because the
226 // scalarized value may not yet have been processed.
227 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
228 GetScalarizedVector(OldVec));
231 // Convert to a vector half as long with an element type of twice the width,
232 // for example <4 x i16> -> <2 x i32>.
233 assert(!(OldElts & 1) && "Odd length vectors not supported!");
234 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
235 assert(OldVT.isSimple() && NewVT.isSimple());
237 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
238 MVT::getVectorVT(NewVT, OldElts / 2),
241 // Extract the element at OldIdx / 2 from the new vector.
242 SDOperand OldIdx = N->getOperand(1);
243 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
244 DAG.getConstant(1, TLI.getShiftAmountTy()));
245 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
247 // Select the appropriate half of the element: Lo if OldIdx was even,
250 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
251 DAG.getConstant(OldVT.getSizeInBits(),
252 TLI.getShiftAmountTy()));
253 if (TLI.isBigEndian())
256 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
257 DAG.getConstant(1, TLI.getShiftAmountTy()));
258 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
261 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
262 unsigned NewOpc = N->getOpcode();
263 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
265 // If we're promoting a UINT to a larger size, check to see if the new node
266 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
267 // we can use that instead. This allows us to generate better code for
268 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
269 // legal, such as PowerPC.
270 if (N->getOpcode() == ISD::FP_TO_UINT) {
271 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
272 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
273 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
274 NewOpc = ISD::FP_TO_SINT;
277 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
280 SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
281 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
283 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
284 SDOperand Res = GetPromotedInteger(N->getOperand(0));
285 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
286 "Extension doesn't make sense!");
288 // If the result and operand types are the same after promotion, simplify
289 // to an in-register extension.
290 if (NVT == Res.getValueType()) {
291 // The high bits are not guaranteed to be anything. Insert an extend.
292 if (N->getOpcode() == ISD::SIGN_EXTEND)
293 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
294 DAG.getValueType(N->getOperand(0).getValueType()));
295 if (N->getOpcode() == ISD::ZERO_EXTEND)
296 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
297 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
302 // Otherwise, just extend the original operand all the way to the larger type.
303 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
306 SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
307 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
308 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
309 ISD::LoadExtType ExtType =
310 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
311 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
312 N->getSrcValue(), N->getSrcValueOffset(),
313 N->getMemoryVT(), N->isVolatile(),
316 // Legalized the chain result - switch anything that used the old chain to
318 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
322 SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
323 // Sign extend the input.
324 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
325 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
326 MVT VT = N->getValueType(0);
327 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
328 DAG.getValueType(VT));
329 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
330 DAG.getValueType(VT));
332 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
335 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
336 SDOperand LHS = GetPromotedInteger(N->getOperand(1));
337 SDOperand RHS = GetPromotedInteger(N->getOperand(2));
338 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
341 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
342 SDOperand LHS = GetPromotedInteger(N->getOperand(2));
343 SDOperand RHS = GetPromotedInteger(N->getOperand(3));
344 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
345 N->getOperand(1), LHS, RHS, N->getOperand(4));
348 SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
349 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
350 && "SetCC type is not legal??");
351 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
352 N->getOperand(0), N->getOperand(1), N->getOperand(2));
355 SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
356 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
357 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
360 SDOperand DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
361 SDOperand Op = GetPromotedInteger(N->getOperand(0));
362 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
366 SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
367 // The input may have strange things in the top bits of the registers, but
368 // these operations don't care. They may have weird bits going out, but
369 // that too is okay if they are integer operations.
370 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
371 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
372 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
375 SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
376 // The input value must be properly sign extended.
377 MVT VT = N->getValueType(0);
378 MVT NVT = TLI.getTypeToTransformTo(VT);
379 SDOperand Res = GetPromotedInteger(N->getOperand(0));
380 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
381 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
384 SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
385 // The input value must be properly zero extended.
386 MVT VT = N->getValueType(0);
387 MVT NVT = TLI.getTypeToTransformTo(VT);
388 SDOperand Res = ZExtPromotedInteger(N->getOperand(0));
389 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
392 SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
395 switch (getTypeAction(N->getOperand(0).getValueType())) {
396 default: assert(0 && "Unknown type action!");
399 Res = N->getOperand(0);
402 Res = GetPromotedInteger(N->getOperand(0));
406 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
407 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
408 "Truncation doesn't make sense!");
409 if (Res.getValueType() == NVT)
412 // Truncate to NVT instead of VT
413 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
416 SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
417 // Zero extend the input.
418 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
419 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
420 MVT VT = N->getValueType(0);
421 LHS = DAG.getZeroExtendInReg(LHS, VT);
422 RHS = DAG.getZeroExtendInReg(RHS, VT);
424 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
427 SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
428 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
431 SDOperand DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
432 SDOperand Chain = N->getOperand(0); // Get the chain.
433 SDOperand Ptr = N->getOperand(1); // Get the pointer.
434 MVT VT = N->getValueType(0);
436 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
437 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0);
439 // Increment the arg pointer, VAList, to the next vaarg
440 // FIXME: should the ABI size be used for the increment? Think of
441 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or
442 // integers of unusual size (such MVT::i1, which gives an increment
444 unsigned Increment = VT.getSizeInBits() / 8;
445 SDOperand Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
446 DAG.getConstant(Increment, TLI.getPointerTy()));
448 // Store the incremented VAList to the pointer.
449 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0);
451 // Load the actual argument out of the arg pointer VAList.
452 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp,
453 VAList, NULL, 0, VT);
455 // Legalized the chain result - switch anything that used the old chain to
457 ReplaceValueWith(SDOperand(N, 1), Tmp.getValue(1));
462 //===----------------------------------------------------------------------===//
463 // Integer Operand Promotion
464 //===----------------------------------------------------------------------===//
466 /// PromoteIntegerOperand - This method is called when the specified operand of
467 /// the specified node is found to need promotion. At this point, all of the
468 /// result types of the node are known to be legal, but other operands of the
469 /// node may need promotion or expansion as well as the specified one.
470 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
471 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
472 SDOperand Res = SDOperand();
474 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
475 == TargetLowering::Custom)
476 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG);
479 switch (N->getOpcode()) {
482 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
483 N->dump(&DAG); cerr << "\n";
485 assert(0 && "Do not know how to promote this operator's operand!");
488 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
489 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
490 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
491 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
492 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
493 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
494 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
495 case ISD::INSERT_VECTOR_ELT:
496 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
497 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
498 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
499 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
500 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
501 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
502 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
504 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
505 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
507 case ISD::SINT_TO_FP:
508 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
512 // If the result is null, the sub-method took care of registering results etc.
513 if (!Res.Val) return false;
514 // If the result is N, the sub-method updated N in place.
516 // Mark N as new and remark N and its operands. This allows us to correctly
517 // revisit N if it needs another step of promotion and allows us to visit
518 // any new operands to N.
523 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
524 "Invalid operand expansion");
526 ReplaceValueWith(SDOperand(N, 0), Res);
530 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
531 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
532 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
533 ISD::CondCode CCCode) {
534 MVT VT = NewLHS.getValueType();
536 // Get the promoted values.
537 NewLHS = GetPromotedInteger(NewLHS);
538 NewRHS = GetPromotedInteger(NewRHS);
540 // Otherwise, we have to insert explicit sign or zero extends. Note
541 // that we could insert sign extends for ALL conditions, but zero extend
542 // is cheaper on many machines (an AND instead of two shifts), so prefer
545 default: assert(0 && "Unknown integer comparison!");
552 // ALL of these operations will work if we either sign or zero extend
553 // the operands (including the unsigned comparisons!). Zero extend is
554 // usually a simpler/cheaper operation, so prefer it.
555 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
556 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
562 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
563 DAG.getValueType(VT));
564 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
565 DAG.getValueType(VT));
570 SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
571 SDOperand Op = GetPromotedInteger(N->getOperand(0));
572 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
575 SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
576 assert(OpNo == 2 && "Don't know how to promote this operand!");
578 SDOperand LHS = N->getOperand(2);
579 SDOperand RHS = N->getOperand(3);
580 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
582 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
584 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
585 N->getOperand(1), LHS, RHS, N->getOperand(4));
588 SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
589 assert(OpNo == 1 && "only know how to promote condition");
590 SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
592 // The top bits of the promoted condition are not necessarily zero, ensure
593 // that the value is properly zero extended.
594 unsigned BitWidth = Cond.getValueSizeInBits();
595 if (!DAG.MaskedValueIsZero(Cond,
596 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
597 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
599 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
600 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
604 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
605 // Since the result type is legal, the operands must promote to it.
606 MVT OVT = N->getOperand(0).getValueType();
607 SDOperand Lo = GetPromotedInteger(N->getOperand(0));
608 SDOperand Hi = GetPromotedInteger(N->getOperand(1));
609 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
611 Lo = DAG.getZeroExtendInReg(Lo, OVT);
612 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
613 DAG.getConstant(OVT.getSizeInBits(),
614 TLI.getShiftAmountTy()));
615 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
618 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
619 // The vector type is legal but the element type is not. This implies
620 // that the vector is a power-of-two in length and that the element
621 // type does not have a strange size (eg: it is not i1).
622 MVT VecVT = N->getValueType(0);
623 unsigned NumElts = VecVT.getVectorNumElements();
624 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
626 // Build a vector of half the length out of elements of twice the bitwidth.
627 // For example <4 x i16> -> <2 x i32>.
628 MVT OldVT = N->getOperand(0).getValueType();
629 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
630 assert(OldVT.isSimple() && NewVT.isSimple());
632 std::vector<SDOperand> NewElts;
633 NewElts.reserve(NumElts/2);
635 for (unsigned i = 0; i < NumElts; i += 2) {
636 // Combine two successive elements into one promoted element.
637 SDOperand Lo = N->getOperand(i);
638 SDOperand Hi = N->getOperand(i+1);
639 if (TLI.isBigEndian())
641 NewElts.push_back(JoinIntegers(Lo, Hi));
644 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
645 MVT::getVectorVT(NewVT, NewElts.size()),
646 &NewElts[0], NewElts.size());
648 // Convert the new vector to the old vector type.
649 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
652 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
653 SDOperand Op = GetPromotedInteger(N->getOperand(0));
654 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
657 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
658 SDOperand Op = GetPromotedInteger(N->getOperand(0));
659 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
660 DAG.getIntPtrConstant(0));
663 SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
666 // Promote the inserted value. This is valid because the type does not
667 // have to match the vector element type.
669 // Check that any extra bits introduced will be truncated away.
670 assert(N->getOperand(1).getValueType().getSizeInBits() >=
671 N->getValueType(0).getVectorElementType().getSizeInBits() &&
672 "Type of inserted value narrower than vector element type!");
673 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
674 GetPromotedInteger(N->getOperand(1)),
678 assert(OpNo == 2 && "Different operand and result vector types?");
680 // Promote the index.
681 SDOperand Idx = N->getOperand(2);
682 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
683 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
684 N->getOperand(1), Idx);
687 SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
688 SDOperand In = GetPromotedInteger(N->getOperand(0));
689 MVT OpVT = N->getOperand(0).getValueType();
690 if (N->getOpcode() == ISD::UINT_TO_FP)
691 In = DAG.getZeroExtendInReg(In, OpVT);
693 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
694 In, DAG.getValueType(OpVT));
696 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
699 SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
701 NewOps[0] = N->getOperand(0);
702 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
703 SDOperand Flag = GetPromotedInteger(N->getOperand(i));
704 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
706 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
707 array_lengthof(NewOps));
710 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
711 assert(OpNo == 0 && "Only know how to promote condition");
712 SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
714 // The top bits of the promoted condition are not necessarily zero, ensure
715 // that the value is properly zero extended.
716 unsigned BitWidth = Cond.getValueSizeInBits();
717 if (!DAG.MaskedValueIsZero(Cond,
718 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
719 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
721 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
722 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
726 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
727 assert(OpNo == 0 && "Don't know how to promote this operand!");
729 SDOperand LHS = N->getOperand(0);
730 SDOperand RHS = N->getOperand(1);
731 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
733 // The CC (#4) and the possible return values (#2 and #3) have legal types.
734 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2),
735 N->getOperand(3), N->getOperand(4));
738 SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
739 assert(OpNo == 0 && "Don't know how to promote this operand!");
741 SDOperand LHS = N->getOperand(0);
742 SDOperand RHS = N->getOperand(1);
743 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
745 // The CC (#2) is always legal.
746 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
749 SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
750 SDOperand Op = GetPromotedInteger(N->getOperand(0));
751 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
752 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
753 Op, DAG.getValueType(N->getOperand(0).getValueType()));
756 SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
757 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
758 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
759 int SVOffset = N->getSrcValueOffset();
760 unsigned Alignment = N->getAlignment();
761 bool isVolatile = N->isVolatile();
763 SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value.
765 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
767 // Truncate the value and store the result.
768 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
769 SVOffset, N->getMemoryVT(),
770 isVolatile, Alignment);
773 SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
774 SDOperand Op = GetPromotedInteger(N->getOperand(0));
775 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
778 SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
779 SDOperand Op = GetPromotedInteger(N->getOperand(0));
780 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
781 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
785 //===----------------------------------------------------------------------===//
786 // Integer Result Expansion
787 //===----------------------------------------------------------------------===//
789 /// ExpandIntegerResult - This method is called when the specified result of the
790 /// specified node is found to need expansion. At this point, the node may also
791 /// have invalid operands or may have other results that need promotion, we just
792 /// know that (at least) one result needs expansion.
793 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
794 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
796 Lo = Hi = SDOperand();
798 // See if the target wants to custom expand this node.
799 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
800 TargetLowering::Custom) {
801 // If the target wants to, allow it to lower this itself.
802 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
803 // Everything that once used N now uses P. We are guaranteed that the
804 // result value types of N and the result value types of P match.
805 ReplaceNodeWith(N, P);
810 switch (N->getOpcode()) {
813 cerr << "ExpandIntegerResult #" << ResNo << ": ";
814 N->dump(&DAG); cerr << "\n";
816 assert(0 && "Do not know how to expand the result of this operator!");
819 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
820 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
821 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
822 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
824 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
825 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
826 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
827 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
829 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
830 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
831 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
832 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
833 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
834 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
835 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
836 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
837 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
838 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
839 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
840 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
841 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
842 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
843 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
844 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
845 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
846 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
847 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
851 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
854 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
857 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
860 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
864 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
867 // If Lo/Hi is null, the sub-method took care of registering results etc.
869 SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi);
872 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
873 /// and the shift amount is a constant 'Amt'. Expand the operation.
874 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
875 SDOperand &Lo, SDOperand &Hi) {
876 // Expand the incoming operand to be shifted, so that we have its parts
878 GetExpandedInteger(N->getOperand(0), InL, InH);
880 MVT NVT = InL.getValueType();
881 unsigned VTBits = N->getValueType(0).getSizeInBits();
882 unsigned NVTBits = NVT.getSizeInBits();
883 MVT ShTy = N->getOperand(1).getValueType();
885 if (N->getOpcode() == ISD::SHL) {
887 Lo = Hi = DAG.getConstant(0, NVT);
888 } else if (Amt > NVTBits) {
889 Lo = DAG.getConstant(0, NVT);
890 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
891 } else if (Amt == NVTBits) {
892 Lo = DAG.getConstant(0, NVT);
894 } else if (Amt == 1) {
895 // Emit this X << 1 as X+X.
896 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
897 SDOperand LoOps[2] = { InL, InL };
898 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
899 SDOperand HiOps[3] = { InH, InH, Lo.getValue(1) };
900 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
902 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
903 Hi = DAG.getNode(ISD::OR, NVT,
904 DAG.getNode(ISD::SHL, NVT, InH,
905 DAG.getConstant(Amt, ShTy)),
906 DAG.getNode(ISD::SRL, NVT, InL,
907 DAG.getConstant(NVTBits-Amt, ShTy)));
912 if (N->getOpcode() == ISD::SRL) {
914 Lo = DAG.getConstant(0, NVT);
915 Hi = DAG.getConstant(0, NVT);
916 } else if (Amt > NVTBits) {
917 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
918 Hi = DAG.getConstant(0, NVT);
919 } else if (Amt == NVTBits) {
921 Hi = DAG.getConstant(0, NVT);
923 Lo = DAG.getNode(ISD::OR, NVT,
924 DAG.getNode(ISD::SRL, NVT, InL,
925 DAG.getConstant(Amt, ShTy)),
926 DAG.getNode(ISD::SHL, NVT, InH,
927 DAG.getConstant(NVTBits-Amt, ShTy)));
928 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
933 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
935 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
936 DAG.getConstant(NVTBits-1, ShTy));
937 } else if (Amt > NVTBits) {
938 Lo = DAG.getNode(ISD::SRA, NVT, InH,
939 DAG.getConstant(Amt-NVTBits, ShTy));
940 Hi = DAG.getNode(ISD::SRA, NVT, InH,
941 DAG.getConstant(NVTBits-1, ShTy));
942 } else if (Amt == NVTBits) {
944 Hi = DAG.getNode(ISD::SRA, NVT, InH,
945 DAG.getConstant(NVTBits-1, ShTy));
947 Lo = DAG.getNode(ISD::OR, NVT,
948 DAG.getNode(ISD::SRL, NVT, InL,
949 DAG.getConstant(Amt, ShTy)),
950 DAG.getNode(ISD::SHL, NVT, InH,
951 DAG.getConstant(NVTBits-Amt, ShTy)));
952 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
956 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
957 /// this shift based on knowledge of the high bit of the shift amount. If we
958 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
960 bool DAGTypeLegalizer::
961 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
962 SDOperand Amt = N->getOperand(1);
963 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
964 MVT ShTy = Amt.getValueType();
965 unsigned ShBits = ShTy.getSizeInBits();
966 unsigned NVTBits = NVT.getSizeInBits();
967 assert(isPowerOf2_32(NVTBits) &&
968 "Expanded integer type size not a power of two!");
970 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
971 APInt KnownZero, KnownOne;
972 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
974 // If we don't know anything about the high bits, exit.
975 if (((KnownZero|KnownOne) & HighBitMask) == 0)
978 // Get the incoming operand to be shifted.
980 GetExpandedInteger(N->getOperand(0), InL, InH);
982 // If we know that any of the high bits of the shift amount are one, then we
983 // can do this as a couple of simple shifts.
984 if (KnownOne.intersects(HighBitMask)) {
985 // Mask out the high bit, which we know is set.
986 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
987 DAG.getConstant(~HighBitMask, ShTy));
989 switch (N->getOpcode()) {
990 default: assert(0 && "Unknown shift");
992 Lo = DAG.getConstant(0, NVT); // Low part is zero.
993 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
996 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
997 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1000 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1001 DAG.getConstant(NVTBits-1, ShTy));
1002 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1007 // If we know that all of the high bits of the shift amount are zero, then we
1008 // can do this as a couple of simple shifts.
1009 if ((KnownZero & HighBitMask) == HighBitMask) {
1011 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
1012 DAG.getConstant(NVTBits, ShTy),
1015 switch (N->getOpcode()) {
1016 default: assert(0 && "Unknown shift");
1017 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1019 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1022 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1023 Hi = DAG.getNode(ISD::OR, NVT,
1024 DAG.getNode(Op1, NVT, InH, Amt),
1025 DAG.getNode(Op2, NVT, InL, Amt2));
1032 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1033 SDOperand &Lo, SDOperand &Hi) {
1034 // Expand the subcomponents.
1035 SDOperand LHSL, LHSH, RHSL, RHSH;
1036 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1037 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1038 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1039 SDOperand LoOps[2] = { LHSL, RHSL };
1040 SDOperand HiOps[3] = { LHSH, RHSH };
1042 if (N->getOpcode() == ISD::ADD) {
1043 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1044 HiOps[2] = Lo.getValue(1);
1045 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1047 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1048 HiOps[2] = Lo.getValue(1);
1049 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1053 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1054 SDOperand &Lo, SDOperand &Hi) {
1055 // Expand the subcomponents.
1056 SDOperand LHSL, LHSH, RHSL, RHSH;
1057 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1058 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1059 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1060 SDOperand LoOps[2] = { LHSL, RHSL };
1061 SDOperand HiOps[3] = { LHSH, RHSH };
1063 if (N->getOpcode() == ISD::ADDC) {
1064 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1065 HiOps[2] = Lo.getValue(1);
1066 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1068 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1069 HiOps[2] = Lo.getValue(1);
1070 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1073 // Legalized the flag result - switch anything that used the old flag to
1075 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1078 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1079 SDOperand &Lo, SDOperand &Hi) {
1080 // Expand the subcomponents.
1081 SDOperand LHSL, LHSH, RHSL, RHSH;
1082 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1083 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1084 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1085 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1086 SDOperand HiOps[3] = { LHSH, RHSH };
1088 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1089 HiOps[2] = Lo.getValue(1);
1090 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1092 // Legalized the flag result - switch anything that used the old flag to
1094 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1097 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1098 SDOperand &Lo, SDOperand &Hi) {
1099 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1100 SDOperand Op = N->getOperand(0);
1101 if (Op.getValueType().bitsLE(NVT)) {
1102 // The low part is any extension of the input (which degenerates to a copy).
1103 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
1104 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
1106 // For example, extension of an i48 to an i64. The operand type necessarily
1107 // promotes to the result type, so will end up being expanded too.
1108 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1109 "Only know how to promote this result!");
1110 SDOperand Res = GetPromotedInteger(Op);
1111 assert(Res.getValueType() == N->getValueType(0) &&
1112 "Operand over promoted?");
1113 // Split the promoted operand. This will simplify when it is expanded.
1114 SplitInteger(Res, Lo, Hi);
1118 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1119 SDOperand &Lo, SDOperand &Hi) {
1120 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1121 MVT NVT = Lo.getValueType();
1122 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1123 unsigned NVTBits = NVT.getSizeInBits();
1124 unsigned EVTBits = EVT.getSizeInBits();
1126 if (NVTBits < EVTBits) {
1127 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
1128 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1130 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
1131 // The high part must be zero, make it explicit.
1132 Hi = DAG.getConstant(0, NVT);
1136 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1137 SDOperand &Lo, SDOperand &Hi) {
1138 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1139 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1140 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1143 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1144 SDOperand &Lo, SDOperand &Hi) {
1145 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1146 unsigned NBitWidth = NVT.getSizeInBits();
1147 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1148 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1149 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1152 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1153 SDOperand &Lo, SDOperand &Hi) {
1154 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1155 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1156 MVT NVT = Lo.getValueType();
1158 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1159 DAG.getConstant(0, NVT), ISD::SETNE);
1161 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1162 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1164 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1165 DAG.getNode(ISD::ADD, NVT, LoLZ,
1166 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1167 Hi = DAG.getConstant(0, NVT);
1170 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1171 SDOperand &Lo, SDOperand &Hi) {
1172 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1173 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1174 MVT NVT = Lo.getValueType();
1175 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1176 DAG.getNode(ISD::CTPOP, NVT, Hi));
1177 Hi = DAG.getConstant(0, NVT);
1180 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1181 SDOperand &Lo, SDOperand &Hi) {
1182 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1183 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1184 MVT NVT = Lo.getValueType();
1186 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1187 DAG.getConstant(0, NVT), ISD::SETNE);
1189 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1190 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1192 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1193 DAG.getNode(ISD::ADD, NVT, HiLZ,
1194 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1195 Hi = DAG.getConstant(0, NVT);
1198 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo,
1200 MVT VT = N->getValueType(0);
1201 SDOperand Op = N->getOperand(0);
1202 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1204 if (VT == MVT::i32) {
1205 if (Op.getValueType() == MVT::f32)
1206 LC = RTLIB::FPTOSINT_F32_I32;
1207 else if (Op.getValueType() == MVT::f64)
1208 LC = RTLIB::FPTOSINT_F64_I32;
1209 else if (Op.getValueType() == MVT::f80)
1210 LC = RTLIB::FPTOSINT_F80_I32;
1211 else if (Op.getValueType() == MVT::ppcf128)
1212 LC = RTLIB::FPTOSINT_PPCF128_I32;
1213 } else if (VT == MVT::i64) {
1214 if (Op.getValueType() == MVT::f32)
1215 LC = RTLIB::FPTOSINT_F32_I64;
1216 else if (Op.getValueType() == MVT::f64)
1217 LC = RTLIB::FPTOSINT_F64_I64;
1218 else if (Op.getValueType() == MVT::f80)
1219 LC = RTLIB::FPTOSINT_F80_I64;
1220 else if (Op.getValueType() == MVT::ppcf128)
1221 LC = RTLIB::FPTOSINT_PPCF128_I64;
1222 } else if (VT == MVT::i128) {
1223 if (Op.getValueType() == MVT::f32)
1224 LC = RTLIB::FPTOSINT_F32_I128;
1225 else if (Op.getValueType() == MVT::f64)
1226 LC = RTLIB::FPTOSINT_F64_I128;
1227 else if (Op.getValueType() == MVT::f80)
1228 LC = RTLIB::FPTOSINT_F80_I128;
1229 else if (Op.getValueType() == MVT::ppcf128)
1230 LC = RTLIB::FPTOSINT_PPCF128_I128;
1232 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1233 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1236 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo,
1238 MVT VT = N->getValueType(0);
1239 SDOperand Op = N->getOperand(0);
1240 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1241 if (VT == MVT::i32) {
1242 if (Op.getValueType() == MVT::f32)
1243 LC = RTLIB::FPTOUINT_F32_I32;
1244 else if (Op.getValueType() == MVT::f64)
1245 LC = RTLIB::FPTOUINT_F64_I32;
1246 else if (Op.getValueType() == MVT::f80)
1247 LC = RTLIB::FPTOUINT_F80_I32;
1248 else if (Op.getValueType() == MVT::ppcf128)
1249 LC = RTLIB::FPTOUINT_PPCF128_I32;
1250 } else if (VT == MVT::i64) {
1251 if (Op.getValueType() == MVT::f32)
1252 LC = RTLIB::FPTOUINT_F32_I64;
1253 else if (Op.getValueType() == MVT::f64)
1254 LC = RTLIB::FPTOUINT_F64_I64;
1255 else if (Op.getValueType() == MVT::f80)
1256 LC = RTLIB::FPTOUINT_F80_I64;
1257 else if (Op.getValueType() == MVT::ppcf128)
1258 LC = RTLIB::FPTOUINT_PPCF128_I64;
1259 } else if (VT == MVT::i128) {
1260 if (Op.getValueType() == MVT::f32)
1261 LC = RTLIB::FPTOUINT_F32_I128;
1262 else if (Op.getValueType() == MVT::f64)
1263 LC = RTLIB::FPTOUINT_F64_I128;
1264 else if (Op.getValueType() == MVT::f80)
1265 LC = RTLIB::FPTOUINT_F80_I128;
1266 else if (Op.getValueType() == MVT::ppcf128)
1267 LC = RTLIB::FPTOUINT_PPCF128_I128;
1269 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1270 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1273 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1274 SDOperand &Lo, SDOperand &Hi) {
1275 if (ISD::isNormalLoad(N)) {
1276 ExpandRes_NormalLoad(N, Lo, Hi);
1280 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1282 MVT VT = N->getValueType(0);
1283 MVT NVT = TLI.getTypeToTransformTo(VT);
1284 SDOperand Ch = N->getChain();
1285 SDOperand Ptr = N->getBasePtr();
1286 ISD::LoadExtType ExtType = N->getExtensionType();
1287 int SVOffset = N->getSrcValueOffset();
1288 unsigned Alignment = N->getAlignment();
1289 bool isVolatile = N->isVolatile();
1291 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1293 if (N->getMemoryVT().bitsLE(NVT)) {
1294 MVT EVT = N->getMemoryVT();
1296 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1297 isVolatile, Alignment);
1299 // Remember the chain.
1300 Ch = Lo.getValue(1);
1302 if (ExtType == ISD::SEXTLOAD) {
1303 // The high part is obtained by SRA'ing all but one of the bits of the
1305 unsigned LoSize = Lo.getValueType().getSizeInBits();
1306 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1307 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1308 } else if (ExtType == ISD::ZEXTLOAD) {
1309 // The high part is just a zero.
1310 Hi = DAG.getConstant(0, NVT);
1312 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1313 // The high part is undefined.
1314 Hi = DAG.getNode(ISD::UNDEF, NVT);
1316 } else if (TLI.isLittleEndian()) {
1317 // Little-endian - low bits are at low addresses.
1318 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1319 isVolatile, Alignment);
1321 unsigned ExcessBits =
1322 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1323 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1325 // Increment the pointer to the other half.
1326 unsigned IncrementSize = NVT.getSizeInBits()/8;
1327 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1328 DAG.getIntPtrConstant(IncrementSize));
1329 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1330 SVOffset+IncrementSize, NEVT,
1331 isVolatile, MinAlign(Alignment, IncrementSize));
1333 // Build a factor node to remember that this load is independent of the
1335 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1338 // Big-endian - high bits are at low addresses. Favor aligned loads at
1339 // the cost of some bit-fiddling.
1340 MVT EVT = N->getMemoryVT();
1341 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1342 unsigned IncrementSize = NVT.getSizeInBits()/8;
1343 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1345 // Load both the high bits and maybe some of the low bits.
1346 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1347 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1348 isVolatile, Alignment);
1350 // Increment the pointer to the other half.
1351 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1352 DAG.getIntPtrConstant(IncrementSize));
1353 // Load the rest of the low bits.
1354 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1355 SVOffset+IncrementSize,
1356 MVT::getIntegerVT(ExcessBits),
1357 isVolatile, MinAlign(Alignment, IncrementSize));
1359 // Build a factor node to remember that this load is independent of the
1361 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1364 if (ExcessBits < NVT.getSizeInBits()) {
1365 // Transfer low bits from the bottom of Hi to the top of Lo.
1366 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1367 DAG.getNode(ISD::SHL, NVT, Hi,
1368 DAG.getConstant(ExcessBits,
1369 TLI.getShiftAmountTy())));
1370 // Move high bits to the right position in Hi.
1371 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1372 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1373 TLI.getShiftAmountTy()));
1377 // Legalized the chain result - switch anything that used the old chain to
1379 ReplaceValueWith(SDOperand(N, 1), Ch);
1382 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1383 SDOperand &Lo, SDOperand &Hi) {
1384 SDOperand LL, LH, RL, RH;
1385 GetExpandedInteger(N->getOperand(0), LL, LH);
1386 GetExpandedInteger(N->getOperand(1), RL, RH);
1387 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1388 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1391 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1392 SDOperand &Lo, SDOperand &Hi) {
1393 MVT VT = N->getValueType(0);
1394 MVT NVT = TLI.getTypeToTransformTo(VT);
1396 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1397 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1398 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1399 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1400 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1401 SDOperand LL, LH, RL, RH;
1402 GetExpandedInteger(N->getOperand(0), LL, LH);
1403 GetExpandedInteger(N->getOperand(1), RL, RH);
1404 unsigned OuterBitSize = VT.getSizeInBits();
1405 unsigned InnerBitSize = NVT.getSizeInBits();
1406 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1407 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1409 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1410 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1411 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1412 // The inputs are both zero-extended.
1414 // We can emit a umul_lohi.
1415 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1416 Hi = SDOperand(Lo.Val, 1);
1420 // We can emit a mulhu+mul.
1421 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1422 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1426 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1427 // The input values are both sign-extended.
1429 // We can emit a smul_lohi.
1430 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1431 Hi = SDOperand(Lo.Val, 1);
1435 // We can emit a mulhs+mul.
1436 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1437 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1442 // Lo,Hi = umul LHS, RHS.
1443 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1444 DAG.getVTList(NVT, NVT), LL, RL);
1446 Hi = UMulLOHI.getValue(1);
1447 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1448 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1449 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1450 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1454 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1455 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1456 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1457 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1458 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1459 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1464 // If nothing else, we can make a libcall.
1465 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1467 LC = RTLIB::MUL_I32;
1468 else if (VT == MVT::i64)
1469 LC = RTLIB::MUL_I64;
1470 else if (VT == MVT::i128)
1471 LC = RTLIB::MUL_I128;
1472 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1474 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1475 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1478 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1479 SDOperand &Lo, SDOperand &Hi) {
1480 MVT VT = N->getValueType(0);
1482 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1484 LC = RTLIB::SDIV_I32;
1485 else if (VT == MVT::i64)
1486 LC = RTLIB::SDIV_I64;
1487 else if (VT == MVT::i128)
1488 LC = RTLIB::SDIV_I128;
1489 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1491 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1492 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1495 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1496 SDOperand &Lo, SDOperand &Hi) {
1497 MVT VT = N->getValueType(0);
1499 // If we can emit an efficient shift operation, do so now. Check to see if
1500 // the RHS is a constant.
1501 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1502 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
1504 // If we can determine that the high bit of the shift is zero or one, even if
1505 // the low bits are variable, emit this shift in an optimized form.
1506 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1509 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1511 if (N->getOpcode() == ISD::SHL) {
1512 PartsOpc = ISD::SHL_PARTS;
1513 } else if (N->getOpcode() == ISD::SRL) {
1514 PartsOpc = ISD::SRL_PARTS;
1516 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1517 PartsOpc = ISD::SRA_PARTS;
1520 // Next check to see if the target supports this SHL_PARTS operation or if it
1521 // will custom expand it.
1522 MVT NVT = TLI.getTypeToTransformTo(VT);
1523 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1524 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1525 Action == TargetLowering::Custom) {
1526 // Expand the subcomponents.
1527 SDOperand LHSL, LHSH;
1528 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1530 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
1531 MVT VT = LHSL.getValueType();
1532 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1533 Hi = Lo.getValue(1);
1537 // Otherwise, emit a libcall.
1538 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1540 if (N->getOpcode() == ISD::SHL) {
1541 isSigned = false; /*sign irrelevant*/
1543 LC = RTLIB::SHL_I32;
1544 else if (VT == MVT::i64)
1545 LC = RTLIB::SHL_I64;
1546 else if (VT == MVT::i128)
1547 LC = RTLIB::SHL_I128;
1548 } else if (N->getOpcode() == ISD::SRL) {
1551 LC = RTLIB::SRL_I32;
1552 else if (VT == MVT::i64)
1553 LC = RTLIB::SRL_I64;
1554 else if (VT == MVT::i128)
1555 LC = RTLIB::SRL_I128;
1557 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1560 LC = RTLIB::SRA_I32;
1561 else if (VT == MVT::i64)
1562 LC = RTLIB::SRA_I64;
1563 else if (VT == MVT::i128)
1564 LC = RTLIB::SRA_I128;
1566 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1568 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1569 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1572 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1573 SDOperand &Lo, SDOperand &Hi) {
1574 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1575 SDOperand Op = N->getOperand(0);
1576 if (Op.getValueType().bitsLE(NVT)) {
1577 // The low part is sign extension of the input (which degenerates to a copy).
1578 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
1579 // The high part is obtained by SRA'ing all but one of the bits of low part.
1580 unsigned LoSize = NVT.getSizeInBits();
1581 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1582 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1584 // For example, extension of an i48 to an i64. The operand type necessarily
1585 // promotes to the result type, so will end up being expanded too.
1586 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1587 "Only know how to promote this result!");
1588 SDOperand Res = GetPromotedInteger(Op);
1589 assert(Res.getValueType() == N->getValueType(0) &&
1590 "Operand over promoted?");
1591 // Split the promoted operand. This will simplify when it is expanded.
1592 SplitInteger(Res, Lo, Hi);
1593 unsigned ExcessBits =
1594 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1595 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1596 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1600 void DAGTypeLegalizer::
1601 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
1602 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1603 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1605 if (EVT.bitsLE(Lo.getValueType())) {
1606 // sext_inreg the low part if needed.
1607 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1610 // The high part gets the sign extension from the lo-part. This handles
1611 // things like sextinreg V:i64 from i8.
1612 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1613 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1614 TLI.getShiftAmountTy()));
1616 // For example, extension of an i48 to an i64. Leave the low part alone,
1617 // sext_inreg the high part.
1618 unsigned ExcessBits =
1619 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1620 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1621 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1625 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1626 SDOperand &Lo, SDOperand &Hi) {
1627 MVT VT = N->getValueType(0);
1629 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1631 LC = RTLIB::SREM_I32;
1632 else if (VT == MVT::i64)
1633 LC = RTLIB::SREM_I64;
1634 else if (VT == MVT::i128)
1635 LC = RTLIB::SREM_I128;
1636 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1638 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1639 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1642 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1643 SDOperand &Lo, SDOperand &Hi) {
1644 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1645 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
1646 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
1647 DAG.getConstant(NVT.getSizeInBits(),
1648 TLI.getShiftAmountTy()));
1649 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
1652 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1653 SDOperand &Lo, SDOperand &Hi) {
1654 MVT VT = N->getValueType(0);
1656 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1658 LC = RTLIB::UDIV_I32;
1659 else if (VT == MVT::i64)
1660 LC = RTLIB::UDIV_I64;
1661 else if (VT == MVT::i128)
1662 LC = RTLIB::UDIV_I128;
1663 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1665 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1666 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1669 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1670 SDOperand &Lo, SDOperand &Hi) {
1671 MVT VT = N->getValueType(0);
1673 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1675 LC = RTLIB::UREM_I32;
1676 else if (VT == MVT::i64)
1677 LC = RTLIB::UREM_I64;
1678 else if (VT == MVT::i128)
1679 LC = RTLIB::UREM_I128;
1680 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1682 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1683 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1686 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1687 SDOperand &Lo, SDOperand &Hi) {
1688 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1689 SDOperand Op = N->getOperand(0);
1690 if (Op.getValueType().bitsLE(NVT)) {
1691 // The low part is zero extension of the input (which degenerates to a copy).
1692 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
1693 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1695 // For example, extension of an i48 to an i64. The operand type necessarily
1696 // promotes to the result type, so will end up being expanded too.
1697 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1698 "Only know how to promote this result!");
1699 SDOperand Res = GetPromotedInteger(Op);
1700 assert(Res.getValueType() == N->getValueType(0) &&
1701 "Operand over promoted?");
1702 // Split the promoted operand. This will simplify when it is expanded.
1703 SplitInteger(Res, Lo, Hi);
1704 unsigned ExcessBits =
1705 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1706 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
1711 //===----------------------------------------------------------------------===//
1712 // Integer Operand Expansion
1713 //===----------------------------------------------------------------------===//
1715 /// ExpandIntegerOperand - This method is called when the specified operand of
1716 /// the specified node is found to need expansion. At this point, all of the
1717 /// result types of the node are known to be legal, but other operands of the
1718 /// node may need promotion or expansion as well as the specified one.
1719 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1720 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1721 SDOperand Res = SDOperand();
1723 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1724 == TargetLowering::Custom)
1725 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG);
1728 switch (N->getOpcode()) {
1731 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1732 N->dump(&DAG); cerr << "\n";
1734 assert(0 && "Do not know how to expand this operator's operand!");
1737 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1738 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1739 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1741 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1742 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1743 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1744 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1745 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1747 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1748 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1752 // If the result is null, the sub-method took care of registering results etc.
1753 if (!Res.Val) return false;
1754 // If the result is N, the sub-method updated N in place. Check to see if any
1755 // operands are new, and if so, mark them.
1757 // Mark N as new and remark N and its operands. This allows us to correctly
1758 // revisit N if it needs another step of expansion and allows us to visit
1759 // any new operands to N.
1764 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1765 "Invalid operand expansion");
1767 ReplaceValueWith(SDOperand(N, 0), Res);
1771 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1772 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1773 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDOperand &NewLHS,
1775 ISD::CondCode &CCCode) {
1776 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1777 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1778 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1780 MVT VT = NewLHS.getValueType();
1782 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1783 if (RHSLo == RHSHi) {
1784 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1785 if (RHSCST->isAllOnesValue()) {
1786 // Equality comparison to -1.
1787 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1794 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1795 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1796 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1797 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1801 // If this is a comparison of the sign bit, just look at the top part.
1803 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1804 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1805 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1811 // FIXME: This generated code sucks.
1812 ISD::CondCode LowCC;
1814 default: assert(0 && "Unknown integer setcc!");
1816 case ISD::SETULT: LowCC = ISD::SETULT; break;
1818 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1820 case ISD::SETULE: LowCC = ISD::SETULE; break;
1822 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1825 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1826 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1827 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1829 // NOTE: on targets without efficient SELECT of bools, we can always use
1830 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1831 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1832 SDOperand Tmp1, Tmp2;
1833 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
1834 false, DagCombineInfo);
1836 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
1837 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1838 CCCode, false, DagCombineInfo);
1840 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1841 DAG.getCondCode(CCCode));
1843 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
1844 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
1845 if ((Tmp1C && Tmp1C->isNullValue()) ||
1846 (Tmp2C && Tmp2C->isNullValue() &&
1847 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1848 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1849 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1850 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1851 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1852 // low part is known false, returns high part.
1853 // For LE / GE, if high part is known false, ignore the low part.
1854 // For LT / GT, if high part is known true, ignore the low part.
1856 NewRHS = SDOperand();
1860 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1861 ISD::SETEQ, false, DagCombineInfo);
1863 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1865 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1866 NewLHS, Tmp1, Tmp2);
1867 NewRHS = SDOperand();
1870 SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
1871 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1872 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1873 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1875 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1876 // against zero to select between true and false values.
1877 if (NewRHS.Val == 0) {
1878 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1879 CCCode = ISD::SETNE;
1882 // Update N to have the operands specified.
1883 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
1884 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1888 SDOperand DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
1889 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1890 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1891 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1893 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1894 // against zero to select between true and false values.
1895 if (NewRHS.Val == 0) {
1896 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1897 CCCode = ISD::SETNE;
1900 // Update N to have the operands specified.
1901 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1902 N->getOperand(2), N->getOperand(3),
1903 DAG.getCondCode(CCCode));
1906 SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
1907 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1908 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1909 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1911 // If ExpandSetCCOperands returned a scalar, use it.
1912 if (NewRHS.Val == 0) {
1913 assert(NewLHS.getValueType() == N->getValueType(0) &&
1914 "Unexpected setcc expansion!");
1918 // Otherwise, update N to have the operands specified.
1919 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1920 DAG.getCondCode(CCCode));
1923 SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
1924 SDOperand Op = N->getOperand(0);
1925 MVT SrcVT = Op.getValueType();
1926 MVT DstVT = N->getValueType(0);
1928 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1929 if (SrcVT == MVT::i32) {
1930 if (DstVT == MVT::f32)
1931 LC = RTLIB::SINTTOFP_I32_F32;
1932 else if (DstVT == MVT::f64)
1933 LC = RTLIB::SINTTOFP_I32_F64;
1934 else if (DstVT == MVT::f80)
1935 LC = RTLIB::SINTTOFP_I32_F80;
1936 else if (DstVT == MVT::ppcf128)
1937 LC = RTLIB::SINTTOFP_I32_PPCF128;
1938 } else if (SrcVT == MVT::i64) {
1939 if (DstVT == MVT::f32)
1940 LC = RTLIB::SINTTOFP_I64_F32;
1941 else if (DstVT == MVT::f64)
1942 LC = RTLIB::SINTTOFP_I64_F64;
1943 else if (DstVT == MVT::f80)
1944 LC = RTLIB::SINTTOFP_I64_F80;
1945 else if (DstVT == MVT::ppcf128)
1946 LC = RTLIB::SINTTOFP_I64_PPCF128;
1947 } else if (SrcVT == MVT::i128) {
1948 if (DstVT == MVT::f32)
1949 LC = RTLIB::SINTTOFP_I128_F32;
1950 else if (DstVT == MVT::f64)
1951 LC = RTLIB::SINTTOFP_I128_F64;
1952 else if (DstVT == MVT::f80)
1953 LC = RTLIB::SINTTOFP_I128_F80;
1954 else if (DstVT == MVT::ppcf128)
1955 LC = RTLIB::SINTTOFP_I128_PPCF128;
1957 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
1958 "Don't know how to expand this SINT_TO_FP!");
1960 return MakeLibCall(LC, DstVT, &Op, 1, true);
1963 SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
1964 if (ISD::isNormalStore(N))
1965 return ExpandOp_NormalStore(N, OpNo);
1967 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1968 assert(OpNo == 1 && "Can only expand the stored value so far");
1970 MVT VT = N->getOperand(1).getValueType();
1971 MVT NVT = TLI.getTypeToTransformTo(VT);
1972 SDOperand Ch = N->getChain();
1973 SDOperand Ptr = N->getBasePtr();
1974 int SVOffset = N->getSrcValueOffset();
1975 unsigned Alignment = N->getAlignment();
1976 bool isVolatile = N->isVolatile();
1979 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1981 if (N->getMemoryVT().bitsLE(NVT)) {
1982 GetExpandedInteger(N->getValue(), Lo, Hi);
1983 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1984 N->getMemoryVT(), isVolatile, Alignment);
1985 } else if (TLI.isLittleEndian()) {
1986 // Little-endian - low bits are at low addresses.
1987 GetExpandedInteger(N->getValue(), Lo, Hi);
1989 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1990 isVolatile, Alignment);
1992 unsigned ExcessBits =
1993 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1994 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1996 // Increment the pointer to the other half.
1997 unsigned IncrementSize = NVT.getSizeInBits()/8;
1998 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1999 DAG.getIntPtrConstant(IncrementSize));
2000 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2001 SVOffset+IncrementSize, NEVT,
2002 isVolatile, MinAlign(Alignment, IncrementSize));
2003 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2005 // Big-endian - high bits are at low addresses. Favor aligned stores at
2006 // the cost of some bit-fiddling.
2007 GetExpandedInteger(N->getValue(), Lo, Hi);
2009 MVT EVT = N->getMemoryVT();
2010 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2011 unsigned IncrementSize = NVT.getSizeInBits()/8;
2012 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2013 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2015 if (ExcessBits < NVT.getSizeInBits()) {
2016 // Transfer high bits from the top of Lo to the bottom of Hi.
2017 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
2018 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2019 TLI.getShiftAmountTy()));
2020 Hi = DAG.getNode(ISD::OR, NVT, Hi,
2021 DAG.getNode(ISD::SRL, NVT, Lo,
2022 DAG.getConstant(ExcessBits,
2023 TLI.getShiftAmountTy())));
2026 // Store both the high bits and maybe some of the low bits.
2027 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2028 SVOffset, HiVT, isVolatile, Alignment);
2030 // Increment the pointer to the other half.
2031 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2032 DAG.getIntPtrConstant(IncrementSize));
2033 // Store the lowest ExcessBits bits in the second half.
2034 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2035 SVOffset+IncrementSize,
2036 MVT::getIntegerVT(ExcessBits),
2037 isVolatile, MinAlign(Alignment, IncrementSize));
2038 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2042 SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2044 GetExpandedInteger(N->getOperand(0), InL, InH);
2045 // Just truncate the low part of the source.
2046 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
2049 SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2050 SDOperand Op = N->getOperand(0);
2051 MVT SrcVT = Op.getValueType();
2052 MVT DstVT = N->getValueType(0);
2054 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2055 // Do a signed conversion then adjust the result.
2056 SDOperand SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
2057 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2059 // The result of the signed conversion needs adjusting if the 'sign bit' of
2060 // the incoming integer was set. To handle this, we dynamically test to see
2061 // if it is set, and, if so, add a fudge factor.
2063 const uint64_t F32TwoE32 = 0x4F800000ULL;
2064 const uint64_t F32TwoE64 = 0x5F800000ULL;
2065 const uint64_t F32TwoE128 = 0x7F800000ULL;
2068 if (SrcVT == MVT::i32)
2069 FF = APInt(32, F32TwoE32);
2070 else if (SrcVT == MVT::i64)
2071 FF = APInt(32, F32TwoE64);
2072 else if (SrcVT == MVT::i128)
2073 FF = APInt(32, F32TwoE128);
2075 assert(false && "Unsupported UINT_TO_FP!");
2077 // Check whether the sign bit is set.
2079 GetExpandedInteger(Op, Lo, Hi);
2080 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
2081 DAG.getConstant(0, Hi.getValueType()),
2084 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2085 SDOperand FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2086 TLI.getPointerTy());
2088 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2089 SDOperand Zero = DAG.getIntPtrConstant(0);
2090 SDOperand Four = DAG.getIntPtrConstant(4);
2091 if (TLI.isBigEndian()) std::swap(Zero, Four);
2092 SDOperand Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
2094 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
2096 // Load the value out, extending it from f32 to the destination float type.
2097 // FIXME: Avoid the extend by constructing the right constant pool?
2098 SDOperand Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
2099 FudgePtr, NULL, 0, MVT::f32);
2100 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
2103 // Otherwise, use a libcall.
2104 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2105 if (SrcVT == MVT::i32) {
2106 if (DstVT == MVT::f32)
2107 LC = RTLIB::UINTTOFP_I32_F32;
2108 else if (DstVT == MVT::f64)
2109 LC = RTLIB::UINTTOFP_I32_F64;
2110 else if (DstVT == MVT::f80)
2111 LC = RTLIB::UINTTOFP_I32_F80;
2112 else if (DstVT == MVT::ppcf128)
2113 LC = RTLIB::UINTTOFP_I32_PPCF128;
2114 } else if (SrcVT == MVT::i64) {
2115 if (DstVT == MVT::f32)
2116 LC = RTLIB::UINTTOFP_I64_F32;
2117 else if (DstVT == MVT::f64)
2118 LC = RTLIB::UINTTOFP_I64_F64;
2119 else if (DstVT == MVT::f80)
2120 LC = RTLIB::UINTTOFP_I64_F80;
2121 else if (DstVT == MVT::ppcf128)
2122 LC = RTLIB::UINTTOFP_I64_PPCF128;
2123 } else if (SrcVT == MVT::i128) {
2124 if (DstVT == MVT::f32)
2125 LC = RTLIB::UINTTOFP_I128_F32;
2126 else if (DstVT == MVT::f64)
2127 LC = RTLIB::UINTTOFP_I128_F64;
2128 else if (DstVT == MVT::f80)
2129 LC = RTLIB::UINTTOFP_I128_F80;
2130 else if (DstVT == MVT::ppcf128)
2131 LC = RTLIB::UINTTOFP_I128_PPCF128;
2133 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2134 "Don't know how to expand this UINT_TO_FP!");
2136 return MakeLibCall(LC, DstVT, &Op, 1, true);