1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
52 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
56 case ISD::CONVERT_RNDSAT:
57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
61 case ISD::EXTRACT_VECTOR_ELT:
62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
68 case ISD::SIGN_EXTEND_INREG:
69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
76 case ISD::SIGN_EXTEND:
77 case ISD::ZERO_EXTEND:
78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
83 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
90 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
93 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
96 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
99 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
101 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
103 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
105 case ISD::ATOMIC_LOAD_ADD:
106 case ISD::ATOMIC_LOAD_SUB:
107 case ISD::ATOMIC_LOAD_AND:
108 case ISD::ATOMIC_LOAD_OR:
109 case ISD::ATOMIC_LOAD_XOR:
110 case ISD::ATOMIC_LOAD_NAND:
111 case ISD::ATOMIC_LOAD_MIN:
112 case ISD::ATOMIC_LOAD_MAX:
113 case ISD::ATOMIC_LOAD_UMIN:
114 case ISD::ATOMIC_LOAD_UMAX:
115 case ISD::ATOMIC_SWAP:
116 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
118 case ISD::ATOMIC_CMP_SWAP:
119 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
122 // If the result is null then the sub-method took care of registering it.
124 SetPromotedInteger(SDValue(N, ResNo), Res);
127 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
128 // Sign-extend the new bits, and continue the assertion.
129 SDValue Op = SExtPromotedInteger(N->getOperand(0));
130 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
131 Op.getValueType(), Op, N->getOperand(1));
134 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
135 // Zero the new bits, and continue the assertion.
136 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
137 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
138 Op.getValueType(), Op, N->getOperand(1));
141 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
142 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
143 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
145 N->getChain(), N->getBasePtr(),
146 Op2, N->getMemOperand());
147 // Legalized the chain result - switch anything that used the old chain to
149 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
153 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
154 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
155 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
156 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
157 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
158 Op2, Op3, N->getMemOperand());
159 // Legalized the chain result - switch anything that used the old chain to
161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
165 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
166 SDValue InOp = N->getOperand(0);
167 EVT InVT = InOp.getValueType();
168 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
169 EVT OutVT = N->getValueType(0);
170 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
171 DebugLoc dl = N->getDebugLoc();
173 switch (getTypeAction(InVT)) {
175 assert(false && "Unknown type action!");
180 if (NOutVT.bitsEq(NInVT))
181 // The input promotes to the same size. Convert the promoted value.
182 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
185 // Promote the integer operand by hand.
186 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
190 case ScalarizeVector:
191 // Convert the element to an integer and promote it by hand.
192 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
193 BitConvertToInteger(GetScalarizedVector(InOp)));
195 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
196 // pieces of the input into integers and reassemble in the final type.
198 GetSplitVector(N->getOperand(0), Lo, Hi);
199 Lo = BitConvertToInteger(Lo);
200 Hi = BitConvertToInteger(Hi);
202 if (TLI.isBigEndian())
205 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
206 EVT::getIntegerVT(*DAG.getContext(),
207 NOutVT.getSizeInBits()),
208 JoinIntegers(Lo, Hi));
209 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
212 if (OutVT.bitsEq(NInVT))
213 // The input is widened to the same size. Convert to the widened value.
214 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp));
217 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
218 CreateStackStoreLoad(InOp, OutVT));
221 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
222 SDValue Op = GetPromotedInteger(N->getOperand(0));
223 EVT OVT = N->getValueType(0);
224 EVT NVT = Op.getValueType();
225 DebugLoc dl = N->getDebugLoc();
227 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
228 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
229 DAG.getConstant(DiffBits, TLI.getPointerTy()));
232 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
233 // The pair element type may be legal, or may not promote to the same type as
234 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
235 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
236 TLI.getTypeToTransformTo(*DAG.getContext(),
237 N->getValueType(0)), JoinIntegers(N->getOperand(0),
241 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
242 EVT VT = N->getValueType(0);
243 // FIXME there is no actual debug info here
244 DebugLoc dl = N->getDebugLoc();
245 // Zero extend things like i1, sign extend everything else. It shouldn't
246 // matter in theory which one we pick, but this tends to give better code?
247 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
248 SDValue Result = DAG.getNode(Opc, dl,
249 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
251 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
255 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
256 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
257 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
258 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
259 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
260 "can only promote integers");
261 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
262 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
263 N->getOperand(1), N->getOperand(2),
264 N->getOperand(3), N->getOperand(4), CvtCode);
267 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
268 // Zero extend to the promoted type and do the count there.
269 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
270 DebugLoc dl = N->getDebugLoc();
271 EVT OVT = N->getValueType(0);
272 EVT NVT = Op.getValueType();
273 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
274 // Subtract off the extra leading bits in the bigger type.
275 return DAG.getNode(ISD::SUB, dl, NVT, Op,
276 DAG.getConstant(NVT.getSizeInBits() -
277 OVT.getSizeInBits(), NVT));
280 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
281 // Zero extend to the promoted type and do the count there.
282 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
283 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
286 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
287 SDValue Op = GetPromotedInteger(N->getOperand(0));
288 EVT OVT = N->getValueType(0);
289 EVT NVT = Op.getValueType();
290 DebugLoc dl = N->getDebugLoc();
291 // The count is the same in the promoted type except if the original
292 // value was zero. This can be handled by setting the bit just off
293 // the top of the original type.
294 APInt TopBit(NVT.getSizeInBits(), 0);
295 TopBit.setBit(OVT.getSizeInBits());
296 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
297 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
300 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
301 DebugLoc dl = N->getDebugLoc();
302 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
303 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
307 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
308 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
309 unsigned NewOpc = N->getOpcode();
310 DebugLoc dl = N->getDebugLoc();
312 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
313 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
314 // and SINT conversions are Custom, there is no way to tell which is
315 // preferable. We choose SINT because that's the right thing on PPC.)
316 if (N->getOpcode() == ISD::FP_TO_UINT &&
317 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
318 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
319 NewOpc = ISD::FP_TO_SINT;
321 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
323 // Assert that the converted value fits in the original type. If it doesn't
324 // (eg: because the value being converted is too big), then the result of the
325 // original operation was undefined anyway, so the assert is still correct.
326 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
327 ISD::AssertZext : ISD::AssertSext, dl,
328 NVT, Res, DAG.getValueType(N->getValueType(0)));
331 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
332 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
333 DebugLoc dl = N->getDebugLoc();
335 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
337 return DAG.getNode(ISD::AssertZext, dl,
338 NVT, Res, DAG.getValueType(N->getValueType(0)));
341 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
342 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
343 DebugLoc dl = N->getDebugLoc();
345 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
346 SDValue Res = GetPromotedInteger(N->getOperand(0));
347 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
349 // If the result and operand types are the same after promotion, simplify
350 // to an in-register extension.
351 if (NVT == Res.getValueType()) {
352 // The high bits are not guaranteed to be anything. Insert an extend.
353 if (N->getOpcode() == ISD::SIGN_EXTEND)
354 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
355 DAG.getValueType(N->getOperand(0).getValueType()));
356 if (N->getOpcode() == ISD::ZERO_EXTEND)
357 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
358 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
363 // Otherwise, just extend the original operand all the way to the larger type.
364 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
367 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
368 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
369 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
370 ISD::LoadExtType ExtType =
371 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
372 DebugLoc dl = N->getDebugLoc();
373 SDValue Res = DAG.getExtLoad(ExtType, NVT, dl, N->getChain(), N->getBasePtr(),
375 N->getMemoryVT(), N->isVolatile(),
376 N->isNonTemporal(), N->getAlignment());
378 // Legalized the chain result - switch anything that used the old chain to
380 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
384 /// Promote the overflow flag of an overflowing arithmetic node.
385 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
386 // Simply change the return type of the boolean result.
387 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
388 EVT ValueVTs[] = { N->getValueType(0), NVT };
389 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
390 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
391 DAG.getVTList(ValueVTs, 2), Ops, 2);
393 // Modified the sum result - switch anything that used the old sum to use
395 ReplaceValueWith(SDValue(N, 0), Res);
397 return SDValue(Res.getNode(), 1);
400 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
402 return PromoteIntRes_Overflow(N);
404 // The operation overflowed iff the result in the larger type is not the
405 // sign extension of its truncation to the original type.
406 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
407 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
408 EVT OVT = N->getOperand(0).getValueType();
409 EVT NVT = LHS.getValueType();
410 DebugLoc dl = N->getDebugLoc();
412 // Do the arithmetic in the larger type.
413 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
414 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
416 // Calculate the overflow flag: sign extend the arithmetic result from
417 // the original type.
418 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
419 DAG.getValueType(OVT));
420 // Overflowed if and only if this is not equal to Res.
421 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
423 // Use the calculated overflow everywhere.
424 ReplaceValueWith(SDValue(N, 1), Ofl);
429 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
430 // Sign extend the input.
431 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
432 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
433 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
434 LHS.getValueType(), LHS, RHS);
437 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
438 SDValue LHS = GetPromotedInteger(N->getOperand(1));
439 SDValue RHS = GetPromotedInteger(N->getOperand(2));
440 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
441 LHS.getValueType(), N->getOperand(0),LHS,RHS);
444 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
445 SDValue LHS = GetPromotedInteger(N->getOperand(2));
446 SDValue RHS = GetPromotedInteger(N->getOperand(3));
447 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
448 LHS.getValueType(), N->getOperand(0),
449 N->getOperand(1), LHS, RHS, N->getOperand(4));
452 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
453 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
454 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
455 DebugLoc dl = N->getDebugLoc();
457 // Get the SETCC result using the canonical SETCC type.
458 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
459 N->getOperand(1), N->getOperand(2));
461 // Convert to the expected type.
462 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
463 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
464 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
467 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
468 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
469 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
470 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
473 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
474 SDValue Op = GetPromotedInteger(N->getOperand(0));
475 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
476 Op.getValueType(), Op, N->getOperand(1));
479 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
480 // The input may have strange things in the top bits of the registers, but
481 // these operations don't care. They may have weird bits going out, but
482 // that too is okay if they are integer operations.
483 SDValue LHS = GetPromotedInteger(N->getOperand(0));
484 SDValue RHS = GetPromotedInteger(N->getOperand(1));
485 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
486 LHS.getValueType(), LHS, RHS);
489 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
490 // The input value must be properly sign extended.
491 SDValue Res = SExtPromotedInteger(N->getOperand(0));
492 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
493 Res.getValueType(), Res, N->getOperand(1));
496 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
497 // The input value must be properly zero extended.
498 EVT VT = N->getValueType(0);
499 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
500 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
501 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
504 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
505 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
508 switch (getTypeAction(N->getOperand(0).getValueType())) {
509 default: llvm_unreachable("Unknown type action!");
512 Res = N->getOperand(0);
515 Res = GetPromotedInteger(N->getOperand(0));
519 // Truncate to NVT instead of VT
520 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
523 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
525 return PromoteIntRes_Overflow(N);
527 // The operation overflowed iff the result in the larger type is not the
528 // zero extension of its truncation to the original type.
529 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
530 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
531 EVT OVT = N->getOperand(0).getValueType();
532 EVT NVT = LHS.getValueType();
533 DebugLoc dl = N->getDebugLoc();
535 // Do the arithmetic in the larger type.
536 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
537 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
539 // Calculate the overflow flag: zero extend the arithmetic result from
540 // the original type.
541 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
542 // Overflowed if and only if this is not equal to Res.
543 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
545 // Use the calculated overflow everywhere.
546 ReplaceValueWith(SDValue(N, 1), Ofl);
552 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
553 // Promote the overflow bit trivially.
555 return PromoteIntRes_Overflow(N);
557 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
558 DebugLoc DL = N->getDebugLoc();
559 unsigned SmallSize = LHS.getValueType().getSizeInBits();
561 // To determine if the result overflowed in a larger type, we extend the input
562 // to the larger type, do the multiply, then check the high bits of the result
563 // to see if the overflow happened.
564 if (N->getOpcode() == ISD::SMULO) {
565 LHS = SExtPromotedInteger(LHS);
566 RHS = SExtPromotedInteger(RHS);
568 LHS = ZExtPromotedInteger(LHS);
569 RHS = ZExtPromotedInteger(RHS);
572 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
575 // For an unsigned overflow, we check to see if the high part is != 0;
577 if (N->getOpcode() == ISD::UMULO) {
578 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
579 DAG.getIntPtrConstant(SmallSize));
580 // Overflowed if and only if this is not equal to Res.
581 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
582 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
584 // Signed multiply overflowed if the high part is not 0 and not -1.
585 SDValue Hi = DAG.getNode(ISD::SRA, DL, Mul.getValueType(), Mul,
586 DAG.getIntPtrConstant(SmallSize));
587 Hi = DAG.getNode(ISD::ADD, DL, Hi.getValueType(), Hi,
588 DAG.getConstant(1, Hi.getValueType()));
589 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
590 DAG.getConstant(1, Hi.getValueType()), ISD::SETUGT);
593 // Use the calculated overflow everywhere.
594 ReplaceValueWith(SDValue(N, 1), Overflow);
599 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
600 // Zero extend the input.
601 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
602 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
603 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
604 LHS.getValueType(), LHS, RHS);
607 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
608 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
609 N->getValueType(0)));
612 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
613 SDValue Chain = N->getOperand(0); // Get the chain.
614 SDValue Ptr = N->getOperand(1); // Get the pointer.
615 EVT VT = N->getValueType(0);
616 DebugLoc dl = N->getDebugLoc();
618 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
619 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
620 // The argument is passed as NumRegs registers of type RegVT.
622 SmallVector<SDValue, 8> Parts(NumRegs);
623 for (unsigned i = 0; i < NumRegs; ++i) {
624 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
625 N->getConstantOperandVal(3));
626 Chain = Parts[i].getValue(1);
629 // Handle endianness of the load.
630 if (TLI.isBigEndian())
631 std::reverse(Parts.begin(), Parts.end());
633 // Assemble the parts in the promoted type.
634 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
635 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
636 for (unsigned i = 1; i < NumRegs; ++i) {
637 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
638 // Shift it to the right position and "or" it in.
639 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
640 DAG.getConstant(i * RegVT.getSizeInBits(),
641 TLI.getPointerTy()));
642 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
645 // Modified the chain result - switch anything that used the old chain to
647 ReplaceValueWith(SDValue(N, 1), Chain);
652 //===----------------------------------------------------------------------===//
653 // Integer Operand Promotion
654 //===----------------------------------------------------------------------===//
656 /// PromoteIntegerOperand - This method is called when the specified operand of
657 /// the specified node is found to need promotion. At this point, all of the
658 /// result types of the node are known to be legal, but other operands of the
659 /// node may need promotion or expansion as well as the specified one.
660 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
661 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
662 SDValue Res = SDValue();
664 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
667 switch (N->getOpcode()) {
670 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
671 N->dump(&DAG); dbgs() << "\n";
673 llvm_unreachable("Do not know how to promote this operator's operand!");
675 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
676 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
677 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
678 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
679 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
680 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
681 case ISD::CONVERT_RNDSAT:
682 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
683 case ISD::INSERT_VECTOR_ELT:
684 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
685 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
686 case ISD::SCALAR_TO_VECTOR:
687 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
688 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
689 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
690 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
691 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
692 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
693 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
695 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
696 case ISD::FP16_TO_FP32:
697 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
698 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
704 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
707 // If the result is null, the sub-method took care of registering results etc.
708 if (!Res.getNode()) return false;
710 // If the result is N, the sub-method updated N in place. Tell the legalizer
712 if (Res.getNode() == N)
715 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
716 "Invalid operand expansion");
718 ReplaceValueWith(SDValue(N, 0), Res);
722 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
723 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
724 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
725 ISD::CondCode CCCode) {
726 // We have to insert explicit sign or zero extends. Note that we could
727 // insert sign extends for ALL conditions, but zero extend is cheaper on
728 // many machines (an AND instead of two shifts), so prefer it.
730 default: llvm_unreachable("Unknown integer comparison!");
737 // ALL of these operations will work if we either sign or zero extend
738 // the operands (including the unsigned comparisons!). Zero extend is
739 // usually a simpler/cheaper operation, so prefer it.
740 NewLHS = ZExtPromotedInteger(NewLHS);
741 NewRHS = ZExtPromotedInteger(NewRHS);
747 NewLHS = SExtPromotedInteger(NewLHS);
748 NewRHS = SExtPromotedInteger(NewRHS);
753 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
754 SDValue Op = GetPromotedInteger(N->getOperand(0));
755 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
758 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
759 // This should only occur in unusual situations like bitcasting to an
760 // x86_fp80, so just turn it into a store+load
761 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
764 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
765 assert(OpNo == 2 && "Don't know how to promote this operand!");
767 SDValue LHS = N->getOperand(2);
768 SDValue RHS = N->getOperand(3);
769 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
771 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
773 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
774 N->getOperand(1), LHS, RHS, N->getOperand(4)),
778 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
779 assert(OpNo == 1 && "only know how to promote condition");
781 // Promote all the way up to the canonical SetCC type.
782 EVT SVT = TLI.getSetCCResultType(MVT::Other);
783 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
785 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
786 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
787 N->getOperand(2)), 0);
790 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
791 // Since the result type is legal, the operands must promote to it.
792 EVT OVT = N->getOperand(0).getValueType();
793 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
794 SDValue Hi = GetPromotedInteger(N->getOperand(1));
795 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
796 DebugLoc dl = N->getDebugLoc();
798 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
799 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
800 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
803 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
804 // The vector type is legal but the element type is not. This implies
805 // that the vector is a power-of-two in length and that the element
806 // type does not have a strange size (eg: it is not i1).
807 EVT VecVT = N->getValueType(0);
808 unsigned NumElts = VecVT.getVectorNumElements();
809 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
811 // Promote the inserted value. The type does not need to match the
812 // vector element type. Check that any extra bits introduced will be
814 assert(N->getOperand(0).getValueType().getSizeInBits() >=
815 N->getValueType(0).getVectorElementType().getSizeInBits() &&
816 "Type of inserted value narrower than vector element type!");
818 SmallVector<SDValue, 16> NewOps;
819 for (unsigned i = 0; i < NumElts; ++i)
820 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
822 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
825 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
826 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
827 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
828 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
829 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
830 "can only promote integer arguments");
831 SDValue InOp = GetPromotedInteger(N->getOperand(0));
832 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
833 N->getOperand(1), N->getOperand(2),
834 N->getOperand(3), N->getOperand(4), CvtCode);
837 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
840 // Promote the inserted value. This is valid because the type does not
841 // have to match the vector element type.
843 // Check that any extra bits introduced will be truncated away.
844 assert(N->getOperand(1).getValueType().getSizeInBits() >=
845 N->getValueType(0).getVectorElementType().getSizeInBits() &&
846 "Type of inserted value narrower than vector element type!");
847 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
848 GetPromotedInteger(N->getOperand(1)),
853 assert(OpNo == 2 && "Different operand and result vector types?");
855 // Promote the index.
856 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
857 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
858 N->getOperand(1), Idx), 0);
861 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
863 DebugLoc dl = N->getDebugLoc();
864 NewOps[0] = N->getOperand(0);
865 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
866 SDValue Flag = GetPromotedInteger(N->getOperand(i));
867 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
869 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
872 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
873 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
874 // the operand in place.
875 return SDValue(DAG.UpdateNodeOperands(N,
876 GetPromotedInteger(N->getOperand(0))), 0);
879 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
880 assert(OpNo == 0 && "Only know how to promote condition");
882 // Promote all the way up to the canonical SetCC type.
883 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
884 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
886 return SDValue(DAG.UpdateNodeOperands(N, Cond,
887 N->getOperand(1), N->getOperand(2)), 0);
890 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
891 assert(OpNo == 0 && "Don't know how to promote this operand!");
893 SDValue LHS = N->getOperand(0);
894 SDValue RHS = N->getOperand(1);
895 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
897 // The CC (#4) and the possible return values (#2 and #3) have legal types.
898 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
899 N->getOperand(3), N->getOperand(4)), 0);
902 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
903 assert(OpNo == 0 && "Don't know how to promote this operand!");
905 SDValue LHS = N->getOperand(0);
906 SDValue RHS = N->getOperand(1);
907 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
909 // The CC (#2) is always legal.
910 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
913 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
914 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
915 ZExtPromotedInteger(N->getOperand(1))), 0);
918 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
919 SDValue Op = GetPromotedInteger(N->getOperand(0));
920 DebugLoc dl = N->getDebugLoc();
921 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
922 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
923 Op, DAG.getValueType(N->getOperand(0).getValueType()));
926 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
927 return SDValue(DAG.UpdateNodeOperands(N,
928 SExtPromotedInteger(N->getOperand(0))), 0);
931 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
932 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
933 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
934 unsigned Alignment = N->getAlignment();
935 bool isVolatile = N->isVolatile();
936 bool isNonTemporal = N->isNonTemporal();
937 DebugLoc dl = N->getDebugLoc();
939 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
941 // Truncate the value and store the result.
942 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
944 isVolatile, isNonTemporal, Alignment);
947 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
948 SDValue Op = GetPromotedInteger(N->getOperand(0));
949 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
952 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
953 return SDValue(DAG.UpdateNodeOperands(N,
954 ZExtPromotedInteger(N->getOperand(0))), 0);
957 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
958 DebugLoc dl = N->getDebugLoc();
959 SDValue Op = GetPromotedInteger(N->getOperand(0));
960 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
961 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
965 //===----------------------------------------------------------------------===//
966 // Integer Result Expansion
967 //===----------------------------------------------------------------------===//
969 /// ExpandIntegerResult - This method is called when the specified result of the
970 /// specified node is found to need expansion. At this point, the node may also
971 /// have invalid operands or may have other results that need promotion, we just
972 /// know that (at least) one result needs expansion.
973 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
974 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
978 // See if the target wants to custom expand this node.
979 if (CustomLowerNode(N, N->getValueType(ResNo), true))
982 switch (N->getOpcode()) {
985 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
986 N->dump(&DAG); dbgs() << "\n";
988 llvm_unreachable("Do not know how to expand the result of this operator!");
990 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
991 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
992 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
993 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
995 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
996 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
997 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
998 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
999 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1001 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1002 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1003 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1004 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1005 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1006 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1007 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1008 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1009 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1010 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1011 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1012 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1013 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1014 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1015 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1016 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1017 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1018 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1019 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1020 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1022 case ISD::ATOMIC_LOAD_ADD:
1023 case ISD::ATOMIC_LOAD_SUB:
1024 case ISD::ATOMIC_LOAD_AND:
1025 case ISD::ATOMIC_LOAD_OR:
1026 case ISD::ATOMIC_LOAD_XOR:
1027 case ISD::ATOMIC_LOAD_NAND:
1028 case ISD::ATOMIC_LOAD_MIN:
1029 case ISD::ATOMIC_LOAD_MAX:
1030 case ISD::ATOMIC_LOAD_UMIN:
1031 case ISD::ATOMIC_LOAD_UMAX:
1032 case ISD::ATOMIC_SWAP: {
1033 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1034 SplitInteger(Tmp.first, Lo, Hi);
1035 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1041 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1044 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1047 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1050 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1054 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1057 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1059 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1062 // If Lo/Hi is null, the sub-method took care of registering results etc.
1064 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1067 /// Lower an atomic node to the appropriate builtin call.
1068 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1069 unsigned Opc = Node->getOpcode();
1070 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1075 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1077 case ISD::ATOMIC_SWAP:
1078 switch (VT.SimpleTy) {
1079 default: llvm_unreachable("Unexpected value type for atomic!");
1080 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1081 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1082 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1083 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1086 case ISD::ATOMIC_CMP_SWAP:
1087 switch (VT.SimpleTy) {
1088 default: llvm_unreachable("Unexpected value type for atomic!");
1089 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1090 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1091 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1092 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1095 case ISD::ATOMIC_LOAD_ADD:
1096 switch (VT.SimpleTy) {
1097 default: llvm_unreachable("Unexpected value type for atomic!");
1098 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1099 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1100 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1101 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1104 case ISD::ATOMIC_LOAD_SUB:
1105 switch (VT.SimpleTy) {
1106 default: llvm_unreachable("Unexpected value type for atomic!");
1107 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1108 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1109 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1110 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1113 case ISD::ATOMIC_LOAD_AND:
1114 switch (VT.SimpleTy) {
1115 default: llvm_unreachable("Unexpected value type for atomic!");
1116 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1117 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1118 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1119 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1122 case ISD::ATOMIC_LOAD_OR:
1123 switch (VT.SimpleTy) {
1124 default: llvm_unreachable("Unexpected value type for atomic!");
1125 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1126 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1127 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1128 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1131 case ISD::ATOMIC_LOAD_XOR:
1132 switch (VT.SimpleTy) {
1133 default: llvm_unreachable("Unexpected value type for atomic!");
1134 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1135 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1136 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1137 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1140 case ISD::ATOMIC_LOAD_NAND:
1141 switch (VT.SimpleTy) {
1142 default: llvm_unreachable("Unexpected value type for atomic!");
1143 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1144 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1145 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1146 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1151 return ExpandChainLibCall(LC, Node, false);
1154 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1155 /// and the shift amount is a constant 'Amt'. Expand the operation.
1156 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1157 SDValue &Lo, SDValue &Hi) {
1158 DebugLoc dl = N->getDebugLoc();
1159 // Expand the incoming operand to be shifted, so that we have its parts
1161 GetExpandedInteger(N->getOperand(0), InL, InH);
1163 EVT NVT = InL.getValueType();
1164 unsigned VTBits = N->getValueType(0).getSizeInBits();
1165 unsigned NVTBits = NVT.getSizeInBits();
1166 EVT ShTy = N->getOperand(1).getValueType();
1168 if (N->getOpcode() == ISD::SHL) {
1170 Lo = Hi = DAG.getConstant(0, NVT);
1171 } else if (Amt > NVTBits) {
1172 Lo = DAG.getConstant(0, NVT);
1173 Hi = DAG.getNode(ISD::SHL, dl,
1174 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1175 } else if (Amt == NVTBits) {
1176 Lo = DAG.getConstant(0, NVT);
1178 } else if (Amt == 1 &&
1179 TLI.isOperationLegalOrCustom(ISD::ADDC,
1180 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1181 // Emit this X << 1 as X+X.
1182 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1183 SDValue LoOps[2] = { InL, InL };
1184 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1185 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1186 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1188 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1189 Hi = DAG.getNode(ISD::OR, dl, NVT,
1190 DAG.getNode(ISD::SHL, dl, NVT, InH,
1191 DAG.getConstant(Amt, ShTy)),
1192 DAG.getNode(ISD::SRL, dl, NVT, InL,
1193 DAG.getConstant(NVTBits-Amt, ShTy)));
1198 if (N->getOpcode() == ISD::SRL) {
1200 Lo = DAG.getConstant(0, NVT);
1201 Hi = DAG.getConstant(0, NVT);
1202 } else if (Amt > NVTBits) {
1203 Lo = DAG.getNode(ISD::SRL, dl,
1204 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1205 Hi = DAG.getConstant(0, NVT);
1206 } else if (Amt == NVTBits) {
1208 Hi = DAG.getConstant(0, NVT);
1210 Lo = DAG.getNode(ISD::OR, dl, NVT,
1211 DAG.getNode(ISD::SRL, dl, NVT, InL,
1212 DAG.getConstant(Amt, ShTy)),
1213 DAG.getNode(ISD::SHL, dl, NVT, InH,
1214 DAG.getConstant(NVTBits-Amt, ShTy)));
1215 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1220 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1222 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1223 DAG.getConstant(NVTBits-1, ShTy));
1224 } else if (Amt > NVTBits) {
1225 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1226 DAG.getConstant(Amt-NVTBits, ShTy));
1227 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1228 DAG.getConstant(NVTBits-1, ShTy));
1229 } else if (Amt == NVTBits) {
1231 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1232 DAG.getConstant(NVTBits-1, ShTy));
1234 Lo = DAG.getNode(ISD::OR, dl, NVT,
1235 DAG.getNode(ISD::SRL, dl, NVT, InL,
1236 DAG.getConstant(Amt, ShTy)),
1237 DAG.getNode(ISD::SHL, dl, NVT, InH,
1238 DAG.getConstant(NVTBits-Amt, ShTy)));
1239 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1243 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1244 /// this shift based on knowledge of the high bit of the shift amount. If we
1245 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1247 bool DAGTypeLegalizer::
1248 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1249 SDValue Amt = N->getOperand(1);
1250 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1251 EVT ShTy = Amt.getValueType();
1252 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1253 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1254 assert(isPowerOf2_32(NVTBits) &&
1255 "Expanded integer type size not a power of two!");
1256 DebugLoc dl = N->getDebugLoc();
1258 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1259 APInt KnownZero, KnownOne;
1260 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1262 // If we don't know anything about the high bits, exit.
1263 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1266 // Get the incoming operand to be shifted.
1268 GetExpandedInteger(N->getOperand(0), InL, InH);
1270 // If we know that any of the high bits of the shift amount are one, then we
1271 // can do this as a couple of simple shifts.
1272 if (KnownOne.intersects(HighBitMask)) {
1273 // Mask out the high bit, which we know is set.
1274 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1275 DAG.getConstant(~HighBitMask, ShTy));
1277 switch (N->getOpcode()) {
1278 default: llvm_unreachable("Unknown shift");
1280 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1281 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1284 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1285 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1288 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1289 DAG.getConstant(NVTBits-1, ShTy));
1290 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1296 // FIXME: This code is broken for shifts with a zero amount!
1297 // If we know that all of the high bits of the shift amount are zero, then we
1298 // can do this as a couple of simple shifts.
1299 if ((KnownZero & HighBitMask) == HighBitMask) {
1301 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1302 DAG.getConstant(NVTBits, ShTy),
1305 switch (N->getOpcode()) {
1306 default: llvm_unreachable("Unknown shift");
1307 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1309 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1312 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1313 Hi = DAG.getNode(ISD::OR, NVT,
1314 DAG.getNode(Op1, NVT, InH, Amt),
1315 DAG.getNode(Op2, NVT, InL, Amt2));
1323 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1325 bool DAGTypeLegalizer::
1326 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1327 SDValue Amt = N->getOperand(1);
1328 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1329 EVT ShTy = Amt.getValueType();
1330 unsigned NVTBits = NVT.getSizeInBits();
1331 assert(isPowerOf2_32(NVTBits) &&
1332 "Expanded integer type size not a power of two!");
1333 DebugLoc dl = N->getDebugLoc();
1335 // Get the incoming operand to be shifted.
1337 GetExpandedInteger(N->getOperand(0), InL, InH);
1339 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1340 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1341 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1342 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1343 Amt, NVBitsNode, ISD::SETULT);
1345 SDValue LoS, HiS, LoL, HiL;
1346 switch (N->getOpcode()) {
1347 default: llvm_unreachable("Unknown shift");
1349 // Short: ShAmt < NVTBits
1350 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1351 HiS = DAG.getNode(ISD::OR, dl, NVT,
1352 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1353 // FIXME: If Amt is zero, the following shift generates an undefined result
1354 // on some architectures.
1355 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1357 // Long: ShAmt >= NVTBits
1358 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1359 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1361 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1362 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1365 // Short: ShAmt < NVTBits
1366 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1367 LoS = DAG.getNode(ISD::OR, dl, NVT,
1368 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1369 // FIXME: If Amt is zero, the following shift generates an undefined result
1370 // on some architectures.
1371 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1373 // Long: ShAmt >= NVTBits
1374 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1375 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1377 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1378 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1381 // Short: ShAmt < NVTBits
1382 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1383 LoS = DAG.getNode(ISD::OR, dl, NVT,
1384 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1385 // FIXME: If Amt is zero, the following shift generates an undefined result
1386 // on some architectures.
1387 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1389 // Long: ShAmt >= NVTBits
1390 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1391 DAG.getConstant(NVTBits-1, ShTy));
1392 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1394 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1395 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1402 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1403 SDValue &Lo, SDValue &Hi) {
1404 DebugLoc dl = N->getDebugLoc();
1405 // Expand the subcomponents.
1406 SDValue LHSL, LHSH, RHSL, RHSH;
1407 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1408 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1410 EVT NVT = LHSL.getValueType();
1411 SDValue LoOps[2] = { LHSL, RHSL };
1412 SDValue HiOps[3] = { LHSH, RHSH };
1414 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1415 // them. TODO: Teach operation legalization how to expand unsupported
1416 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1417 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1418 // generate a value of this type in the expanded code sequence.
1420 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1421 ISD::ADDC : ISD::SUBC,
1422 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1425 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1426 if (N->getOpcode() == ISD::ADD) {
1427 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1428 HiOps[2] = Lo.getValue(1);
1429 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1431 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1432 HiOps[2] = Lo.getValue(1);
1433 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1438 if (N->getOpcode() == ISD::ADD) {
1439 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1440 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1441 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1443 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1444 DAG.getConstant(1, NVT),
1445 DAG.getConstant(0, NVT));
1446 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1448 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1449 DAG.getConstant(1, NVT), Carry1);
1450 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1452 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1453 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1455 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1456 LoOps[0], LoOps[1], ISD::SETULT);
1457 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1458 DAG.getConstant(1, NVT),
1459 DAG.getConstant(0, NVT));
1460 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1464 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1465 SDValue &Lo, SDValue &Hi) {
1466 // Expand the subcomponents.
1467 SDValue LHSL, LHSH, RHSL, RHSH;
1468 DebugLoc dl = N->getDebugLoc();
1469 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1470 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1471 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1472 SDValue LoOps[2] = { LHSL, RHSL };
1473 SDValue HiOps[3] = { LHSH, RHSH };
1475 if (N->getOpcode() == ISD::ADDC) {
1476 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1477 HiOps[2] = Lo.getValue(1);
1478 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1480 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1481 HiOps[2] = Lo.getValue(1);
1482 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1485 // Legalized the flag result - switch anything that used the old flag to
1487 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1490 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1491 SDValue &Lo, SDValue &Hi) {
1492 // Expand the subcomponents.
1493 SDValue LHSL, LHSH, RHSL, RHSH;
1494 DebugLoc dl = N->getDebugLoc();
1495 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1496 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1497 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1498 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1499 SDValue HiOps[3] = { LHSH, RHSH };
1501 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1502 HiOps[2] = Lo.getValue(1);
1503 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1505 // Legalized the flag result - switch anything that used the old flag to
1507 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1510 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1511 SDValue &Lo, SDValue &Hi) {
1512 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1513 DebugLoc dl = N->getDebugLoc();
1514 SDValue Op = N->getOperand(0);
1515 if (Op.getValueType().bitsLE(NVT)) {
1516 // The low part is any extension of the input (which degenerates to a copy).
1517 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1518 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1520 // For example, extension of an i48 to an i64. The operand type necessarily
1521 // promotes to the result type, so will end up being expanded too.
1522 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1523 "Only know how to promote this result!");
1524 SDValue Res = GetPromotedInteger(Op);
1525 assert(Res.getValueType() == N->getValueType(0) &&
1526 "Operand over promoted?");
1527 // Split the promoted operand. This will simplify when it is expanded.
1528 SplitInteger(Res, Lo, Hi);
1532 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1533 SDValue &Lo, SDValue &Hi) {
1534 DebugLoc dl = N->getDebugLoc();
1535 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1536 EVT NVT = Lo.getValueType();
1537 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1538 unsigned NVTBits = NVT.getSizeInBits();
1539 unsigned EVTBits = EVT.getSizeInBits();
1541 if (NVTBits < EVTBits) {
1542 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1543 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1544 EVTBits - NVTBits)));
1546 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1547 // The high part replicates the sign bit of Lo, make it explicit.
1548 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1549 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1553 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1554 SDValue &Lo, SDValue &Hi) {
1555 DebugLoc dl = N->getDebugLoc();
1556 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1557 EVT NVT = Lo.getValueType();
1558 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1559 unsigned NVTBits = NVT.getSizeInBits();
1560 unsigned EVTBits = EVT.getSizeInBits();
1562 if (NVTBits < EVTBits) {
1563 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1564 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1565 EVTBits - NVTBits)));
1567 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1568 // The high part must be zero, make it explicit.
1569 Hi = DAG.getConstant(0, NVT);
1573 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1574 SDValue &Lo, SDValue &Hi) {
1575 DebugLoc dl = N->getDebugLoc();
1576 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1577 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1578 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1581 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1582 SDValue &Lo, SDValue &Hi) {
1583 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1584 unsigned NBitWidth = NVT.getSizeInBits();
1585 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1586 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1587 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1590 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1591 SDValue &Lo, SDValue &Hi) {
1592 DebugLoc dl = N->getDebugLoc();
1593 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1594 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1595 EVT NVT = Lo.getValueType();
1597 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1598 DAG.getConstant(0, NVT), ISD::SETNE);
1600 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1601 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1603 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1604 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1605 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1606 Hi = DAG.getConstant(0, NVT);
1609 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1610 SDValue &Lo, SDValue &Hi) {
1611 DebugLoc dl = N->getDebugLoc();
1612 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1613 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1614 EVT NVT = Lo.getValueType();
1615 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1616 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1617 Hi = DAG.getConstant(0, NVT);
1620 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1621 SDValue &Lo, SDValue &Hi) {
1622 DebugLoc dl = N->getDebugLoc();
1623 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1624 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1625 EVT NVT = Lo.getValueType();
1627 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1628 DAG.getConstant(0, NVT), ISD::SETNE);
1630 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1631 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1633 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1634 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1635 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1636 Hi = DAG.getConstant(0, NVT);
1639 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1641 DebugLoc dl = N->getDebugLoc();
1642 EVT VT = N->getValueType(0);
1643 SDValue Op = N->getOperand(0);
1644 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1645 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1646 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1649 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1651 DebugLoc dl = N->getDebugLoc();
1652 EVT VT = N->getValueType(0);
1653 SDValue Op = N->getOperand(0);
1654 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1655 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1656 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1659 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1660 SDValue &Lo, SDValue &Hi) {
1661 if (ISD::isNormalLoad(N)) {
1662 ExpandRes_NormalLoad(N, Lo, Hi);
1666 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1668 EVT VT = N->getValueType(0);
1669 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1670 SDValue Ch = N->getChain();
1671 SDValue Ptr = N->getBasePtr();
1672 ISD::LoadExtType ExtType = N->getExtensionType();
1673 unsigned Alignment = N->getAlignment();
1674 bool isVolatile = N->isVolatile();
1675 bool isNonTemporal = N->isNonTemporal();
1676 DebugLoc dl = N->getDebugLoc();
1678 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1680 if (N->getMemoryVT().bitsLE(NVT)) {
1681 EVT MemVT = N->getMemoryVT();
1683 Lo = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(),
1684 MemVT, isVolatile, isNonTemporal, Alignment);
1686 // Remember the chain.
1687 Ch = Lo.getValue(1);
1689 if (ExtType == ISD::SEXTLOAD) {
1690 // The high part is obtained by SRA'ing all but one of the bits of the
1692 unsigned LoSize = Lo.getValueType().getSizeInBits();
1693 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1694 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1695 } else if (ExtType == ISD::ZEXTLOAD) {
1696 // The high part is just a zero.
1697 Hi = DAG.getConstant(0, NVT);
1699 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1700 // The high part is undefined.
1701 Hi = DAG.getUNDEF(NVT);
1703 } else if (TLI.isLittleEndian()) {
1704 // Little-endian - low bits are at low addresses.
1705 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1706 isVolatile, isNonTemporal, Alignment);
1708 unsigned ExcessBits =
1709 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1710 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1712 // Increment the pointer to the other half.
1713 unsigned IncrementSize = NVT.getSizeInBits()/8;
1714 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1715 DAG.getIntPtrConstant(IncrementSize));
1716 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr,
1717 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1718 isVolatile, isNonTemporal,
1719 MinAlign(Alignment, IncrementSize));
1721 // Build a factor node to remember that this load is independent of the
1723 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1726 // Big-endian - high bits are at low addresses. Favor aligned loads at
1727 // the cost of some bit-fiddling.
1728 EVT MemVT = N->getMemoryVT();
1729 unsigned EBytes = MemVT.getStoreSize();
1730 unsigned IncrementSize = NVT.getSizeInBits()/8;
1731 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1733 // Load both the high bits and maybe some of the low bits.
1734 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(),
1735 EVT::getIntegerVT(*DAG.getContext(),
1736 MemVT.getSizeInBits() - ExcessBits),
1737 isVolatile, isNonTemporal, Alignment);
1739 // Increment the pointer to the other half.
1740 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1741 DAG.getIntPtrConstant(IncrementSize));
1742 // Load the rest of the low bits.
1743 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, dl, Ch, Ptr,
1744 N->getPointerInfo().getWithOffset(IncrementSize),
1745 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1746 isVolatile, isNonTemporal,
1747 MinAlign(Alignment, IncrementSize));
1749 // Build a factor node to remember that this load is independent of the
1751 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1754 if (ExcessBits < NVT.getSizeInBits()) {
1755 // Transfer low bits from the bottom of Hi to the top of Lo.
1756 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1757 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1758 DAG.getConstant(ExcessBits,
1759 TLI.getPointerTy())));
1760 // Move high bits to the right position in Hi.
1761 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1763 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1764 TLI.getPointerTy()));
1768 // Legalized the chain result - switch anything that used the old chain to
1770 ReplaceValueWith(SDValue(N, 1), Ch);
1773 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1774 SDValue &Lo, SDValue &Hi) {
1775 DebugLoc dl = N->getDebugLoc();
1776 SDValue LL, LH, RL, RH;
1777 GetExpandedInteger(N->getOperand(0), LL, LH);
1778 GetExpandedInteger(N->getOperand(1), RL, RH);
1779 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1780 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1783 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1784 SDValue &Lo, SDValue &Hi) {
1785 EVT VT = N->getValueType(0);
1786 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1787 DebugLoc dl = N->getDebugLoc();
1789 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1790 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1791 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1792 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1793 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1794 SDValue LL, LH, RL, RH;
1795 GetExpandedInteger(N->getOperand(0), LL, LH);
1796 GetExpandedInteger(N->getOperand(1), RL, RH);
1797 unsigned OuterBitSize = VT.getSizeInBits();
1798 unsigned InnerBitSize = NVT.getSizeInBits();
1799 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1800 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1802 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1803 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1804 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1805 // The inputs are both zero-extended.
1807 // We can emit a umul_lohi.
1808 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1809 Hi = SDValue(Lo.getNode(), 1);
1813 // We can emit a mulhu+mul.
1814 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1815 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1819 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1820 // The input values are both sign-extended.
1822 // We can emit a smul_lohi.
1823 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1824 Hi = SDValue(Lo.getNode(), 1);
1828 // We can emit a mulhs+mul.
1829 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1830 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1835 // Lo,Hi = umul LHS, RHS.
1836 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1837 DAG.getVTList(NVT, NVT), LL, RL);
1839 Hi = UMulLOHI.getValue(1);
1840 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1841 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1842 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1843 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1847 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1848 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1849 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1850 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1851 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1852 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1857 // If nothing else, we can make a libcall.
1858 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1860 LC = RTLIB::MUL_I16;
1861 else if (VT == MVT::i32)
1862 LC = RTLIB::MUL_I32;
1863 else if (VT == MVT::i64)
1864 LC = RTLIB::MUL_I64;
1865 else if (VT == MVT::i128)
1866 LC = RTLIB::MUL_I128;
1867 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1869 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1870 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1873 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1874 SDValue &Lo, SDValue &Hi) {
1875 SDValue LHS = Node->getOperand(0);
1876 SDValue RHS = Node->getOperand(1);
1877 DebugLoc dl = Node->getDebugLoc();
1879 // Expand the result by simply replacing it with the equivalent
1880 // non-overflow-checking operation.
1881 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1882 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1884 SplitInteger(Sum, Lo, Hi);
1886 // Compute the overflow.
1888 // LHSSign -> LHS >= 0
1889 // RHSSign -> RHS >= 0
1890 // SumSign -> Sum >= 0
1893 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
1895 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
1897 EVT OType = Node->getValueType(1);
1898 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
1900 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
1901 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
1902 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
1903 Node->getOpcode() == ISD::SADDO ?
1904 ISD::SETEQ : ISD::SETNE);
1906 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
1907 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
1909 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
1911 // Use the calculated overflow everywhere.
1912 ReplaceValueWith(SDValue(Node, 1), Cmp);
1915 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1916 SDValue &Lo, SDValue &Hi) {
1917 EVT VT = N->getValueType(0);
1918 DebugLoc dl = N->getDebugLoc();
1920 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1922 LC = RTLIB::SDIV_I16;
1923 else if (VT == MVT::i32)
1924 LC = RTLIB::SDIV_I32;
1925 else if (VT == MVT::i64)
1926 LC = RTLIB::SDIV_I64;
1927 else if (VT == MVT::i128)
1928 LC = RTLIB::SDIV_I128;
1929 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1931 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1932 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1935 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1936 SDValue &Lo, SDValue &Hi) {
1937 EVT VT = N->getValueType(0);
1938 DebugLoc dl = N->getDebugLoc();
1940 // If we can emit an efficient shift operation, do so now. Check to see if
1941 // the RHS is a constant.
1942 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1943 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1945 // If we can determine that the high bit of the shift is zero or one, even if
1946 // the low bits are variable, emit this shift in an optimized form.
1947 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1950 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1952 if (N->getOpcode() == ISD::SHL) {
1953 PartsOpc = ISD::SHL_PARTS;
1954 } else if (N->getOpcode() == ISD::SRL) {
1955 PartsOpc = ISD::SRL_PARTS;
1957 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1958 PartsOpc = ISD::SRA_PARTS;
1961 // Next check to see if the target supports this SHL_PARTS operation or if it
1962 // will custom expand it.
1963 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1964 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1965 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1966 Action == TargetLowering::Custom) {
1967 // Expand the subcomponents.
1969 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1971 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1972 EVT VT = LHSL.getValueType();
1973 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1974 Hi = Lo.getValue(1);
1978 // Otherwise, emit a libcall.
1979 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1981 if (N->getOpcode() == ISD::SHL) {
1982 isSigned = false; /*sign irrelevant*/
1984 LC = RTLIB::SHL_I16;
1985 else if (VT == MVT::i32)
1986 LC = RTLIB::SHL_I32;
1987 else if (VT == MVT::i64)
1988 LC = RTLIB::SHL_I64;
1989 else if (VT == MVT::i128)
1990 LC = RTLIB::SHL_I128;
1991 } else if (N->getOpcode() == ISD::SRL) {
1994 LC = RTLIB::SRL_I16;
1995 else if (VT == MVT::i32)
1996 LC = RTLIB::SRL_I32;
1997 else if (VT == MVT::i64)
1998 LC = RTLIB::SRL_I64;
1999 else if (VT == MVT::i128)
2000 LC = RTLIB::SRL_I128;
2002 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2005 LC = RTLIB::SRA_I16;
2006 else if (VT == MVT::i32)
2007 LC = RTLIB::SRA_I32;
2008 else if (VT == MVT::i64)
2009 LC = RTLIB::SRA_I64;
2010 else if (VT == MVT::i128)
2011 LC = RTLIB::SRA_I128;
2014 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2015 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2016 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
2020 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2021 llvm_unreachable("Unsupported shift!");
2024 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2025 SDValue &Lo, SDValue &Hi) {
2026 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2027 DebugLoc dl = N->getDebugLoc();
2028 SDValue Op = N->getOperand(0);
2029 if (Op.getValueType().bitsLE(NVT)) {
2030 // The low part is sign extension of the input (degenerates to a copy).
2031 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2032 // The high part is obtained by SRA'ing all but one of the bits of low part.
2033 unsigned LoSize = NVT.getSizeInBits();
2034 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2035 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2037 // For example, extension of an i48 to an i64. The operand type necessarily
2038 // promotes to the result type, so will end up being expanded too.
2039 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
2040 "Only know how to promote this result!");
2041 SDValue Res = GetPromotedInteger(Op);
2042 assert(Res.getValueType() == N->getValueType(0) &&
2043 "Operand over promoted?");
2044 // Split the promoted operand. This will simplify when it is expanded.
2045 SplitInteger(Res, Lo, Hi);
2046 unsigned ExcessBits =
2047 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2048 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2049 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2054 void DAGTypeLegalizer::
2055 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2056 DebugLoc dl = N->getDebugLoc();
2057 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2058 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2060 if (EVT.bitsLE(Lo.getValueType())) {
2061 // sext_inreg the low part if needed.
2062 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2065 // The high part gets the sign extension from the lo-part. This handles
2066 // things like sextinreg V:i64 from i8.
2067 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2068 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2069 TLI.getPointerTy()));
2071 // For example, extension of an i48 to an i64. Leave the low part alone,
2072 // sext_inreg the high part.
2073 unsigned ExcessBits =
2074 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2075 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2076 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2081 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2082 SDValue &Lo, SDValue &Hi) {
2083 EVT VT = N->getValueType(0);
2084 DebugLoc dl = N->getDebugLoc();
2086 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2088 LC = RTLIB::SREM_I16;
2089 else if (VT == MVT::i32)
2090 LC = RTLIB::SREM_I32;
2091 else if (VT == MVT::i64)
2092 LC = RTLIB::SREM_I64;
2093 else if (VT == MVT::i128)
2094 LC = RTLIB::SREM_I128;
2095 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2097 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2098 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2101 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2102 SDValue &Lo, SDValue &Hi) {
2103 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2104 DebugLoc dl = N->getDebugLoc();
2105 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2106 Hi = DAG.getNode(ISD::SRL, dl,
2107 N->getOperand(0).getValueType(), N->getOperand(0),
2108 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2109 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2112 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2113 SDValue &Lo, SDValue &Hi) {
2114 SDValue LHS = N->getOperand(0);
2115 SDValue RHS = N->getOperand(1);
2116 DebugLoc dl = N->getDebugLoc();
2118 // Expand the result by simply replacing it with the equivalent
2119 // non-overflow-checking operation.
2120 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2121 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2123 SplitInteger(Sum, Lo, Hi);
2125 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2126 // overflows iff a - b > a.
2127 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2128 N->getOpcode () == ISD::UADDO ?
2129 ISD::SETULT : ISD::SETUGT);
2131 // Use the calculated overflow everywhere.
2132 ReplaceValueWith(SDValue(N, 1), Ofl);
2135 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2136 SDValue &Lo, SDValue &Hi) {
2137 EVT VT = N->getValueType(0);
2138 DebugLoc dl = N->getDebugLoc();
2140 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2142 LC = RTLIB::UDIV_I16;
2143 else if (VT == MVT::i32)
2144 LC = RTLIB::UDIV_I32;
2145 else if (VT == MVT::i64)
2146 LC = RTLIB::UDIV_I64;
2147 else if (VT == MVT::i128)
2148 LC = RTLIB::UDIV_I128;
2149 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2151 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2152 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2155 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2156 SDValue &Lo, SDValue &Hi) {
2157 EVT VT = N->getValueType(0);
2158 DebugLoc dl = N->getDebugLoc();
2160 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2162 LC = RTLIB::UREM_I16;
2163 else if (VT == MVT::i32)
2164 LC = RTLIB::UREM_I32;
2165 else if (VT == MVT::i64)
2166 LC = RTLIB::UREM_I64;
2167 else if (VT == MVT::i128)
2168 LC = RTLIB::UREM_I128;
2169 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2171 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2172 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2175 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2176 SDValue &Lo, SDValue &Hi) {
2177 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2178 DebugLoc dl = N->getDebugLoc();
2179 SDValue Op = N->getOperand(0);
2180 if (Op.getValueType().bitsLE(NVT)) {
2181 // The low part is zero extension of the input (degenerates to a copy).
2182 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2183 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2185 // For example, extension of an i48 to an i64. The operand type necessarily
2186 // promotes to the result type, so will end up being expanded too.
2187 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
2188 "Only know how to promote this result!");
2189 SDValue Res = GetPromotedInteger(Op);
2190 assert(Res.getValueType() == N->getValueType(0) &&
2191 "Operand over promoted?");
2192 // Split the promoted operand. This will simplify when it is expanded.
2193 SplitInteger(Res, Lo, Hi);
2194 unsigned ExcessBits =
2195 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2196 Hi = DAG.getZeroExtendInReg(Hi, dl,
2197 EVT::getIntegerVT(*DAG.getContext(),
2203 //===----------------------------------------------------------------------===//
2204 // Integer Operand Expansion
2205 //===----------------------------------------------------------------------===//
2207 /// ExpandIntegerOperand - This method is called when the specified operand of
2208 /// the specified node is found to need expansion. At this point, all of the
2209 /// result types of the node are known to be legal, but other operands of the
2210 /// node may need promotion or expansion as well as the specified one.
2211 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2212 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2213 SDValue Res = SDValue();
2215 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2218 switch (N->getOpcode()) {
2221 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2222 N->dump(&DAG); dbgs() << "\n";
2224 llvm_unreachable("Do not know how to expand this operator's operand!");
2226 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2227 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2228 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2229 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2230 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2231 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2232 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2233 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2234 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2235 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2236 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2237 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2243 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2244 case ISD::RETURNADDR:
2245 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2248 // If the result is null, the sub-method took care of registering results etc.
2249 if (!Res.getNode()) return false;
2251 // If the result is N, the sub-method updated N in place. Tell the legalizer
2253 if (Res.getNode() == N)
2256 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2257 "Invalid operand expansion");
2259 ReplaceValueWith(SDValue(N, 0), Res);
2263 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2264 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2265 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2267 ISD::CondCode &CCCode,
2269 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2270 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2271 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2273 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2274 if (RHSLo == RHSHi) {
2275 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2276 if (RHSCST->isAllOnesValue()) {
2277 // Equality comparison to -1.
2278 NewLHS = DAG.getNode(ISD::AND, dl,
2279 LHSLo.getValueType(), LHSLo, LHSHi);
2286 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2287 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2288 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2289 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2293 // If this is a comparison of the sign bit, just look at the top part.
2295 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2296 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2297 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2303 // FIXME: This generated code sucks.
2304 ISD::CondCode LowCC;
2306 default: llvm_unreachable("Unknown integer setcc!");
2308 case ISD::SETULT: LowCC = ISD::SETULT; break;
2310 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2312 case ISD::SETULE: LowCC = ISD::SETULE; break;
2314 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2317 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2318 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2319 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2321 // NOTE: on targets without efficient SELECT of bools, we can always use
2322 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2323 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2325 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2326 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2327 if (!Tmp1.getNode())
2328 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2329 LHSLo, RHSLo, LowCC);
2330 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2331 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2332 if (!Tmp2.getNode())
2333 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2334 TLI.getSetCCResultType(LHSHi.getValueType()),
2335 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2337 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2338 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2339 if ((Tmp1C && Tmp1C->isNullValue()) ||
2340 (Tmp2C && Tmp2C->isNullValue() &&
2341 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2342 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2343 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2344 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2345 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2346 // low part is known false, returns high part.
2347 // For LE / GE, if high part is known false, ignore the low part.
2348 // For LT / GT, if high part is known true, ignore the low part.
2354 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2355 LHSHi, RHSHi, ISD::SETEQ, false,
2356 DagCombineInfo, dl);
2357 if (!NewLHS.getNode())
2358 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2359 LHSHi, RHSHi, ISD::SETEQ);
2360 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2361 NewLHS, Tmp1, Tmp2);
2365 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2366 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2367 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2368 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2370 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2371 // against zero to select between true and false values.
2372 if (NewRHS.getNode() == 0) {
2373 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2374 CCCode = ISD::SETNE;
2377 // Update N to have the operands specified.
2378 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2379 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2380 N->getOperand(4)), 0);
2383 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2384 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2385 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2386 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2388 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2389 // against zero to select between true and false values.
2390 if (NewRHS.getNode() == 0) {
2391 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2392 CCCode = ISD::SETNE;
2395 // Update N to have the operands specified.
2396 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2397 N->getOperand(2), N->getOperand(3),
2398 DAG.getCondCode(CCCode)), 0);
2401 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2402 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2403 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2404 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2406 // If ExpandSetCCOperands returned a scalar, use it.
2407 if (NewRHS.getNode() == 0) {
2408 assert(NewLHS.getValueType() == N->getValueType(0) &&
2409 "Unexpected setcc expansion!");
2413 // Otherwise, update N to have the operands specified.
2414 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2415 DAG.getCondCode(CCCode)), 0);
2418 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2419 // The value being shifted is legal, but the shift amount is too big.
2420 // It follows that either the result of the shift is undefined, or the
2421 // upper half of the shift amount is zero. Just use the lower half.
2423 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2424 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2427 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2428 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2429 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2430 // constant to valid type.
2432 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2433 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2436 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2437 SDValue Op = N->getOperand(0);
2438 EVT DstVT = N->getValueType(0);
2439 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2440 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2441 "Don't know how to expand this SINT_TO_FP!");
2442 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2445 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2446 if (ISD::isNormalStore(N))
2447 return ExpandOp_NormalStore(N, OpNo);
2449 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2450 assert(OpNo == 1 && "Can only expand the stored value so far");
2452 EVT VT = N->getOperand(1).getValueType();
2453 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2454 SDValue Ch = N->getChain();
2455 SDValue Ptr = N->getBasePtr();
2456 unsigned Alignment = N->getAlignment();
2457 bool isVolatile = N->isVolatile();
2458 bool isNonTemporal = N->isNonTemporal();
2459 DebugLoc dl = N->getDebugLoc();
2462 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2464 if (N->getMemoryVT().bitsLE(NVT)) {
2465 GetExpandedInteger(N->getValue(), Lo, Hi);
2466 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2467 N->getMemoryVT(), isVolatile, isNonTemporal,
2471 if (TLI.isLittleEndian()) {
2472 // Little-endian - low bits are at low addresses.
2473 GetExpandedInteger(N->getValue(), Lo, Hi);
2475 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2476 isVolatile, isNonTemporal, Alignment);
2478 unsigned ExcessBits =
2479 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2480 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2482 // Increment the pointer to the other half.
2483 unsigned IncrementSize = NVT.getSizeInBits()/8;
2484 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2485 DAG.getIntPtrConstant(IncrementSize));
2486 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2487 N->getPointerInfo().getWithOffset(IncrementSize),
2488 NEVT, isVolatile, isNonTemporal,
2489 MinAlign(Alignment, IncrementSize));
2490 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2493 // Big-endian - high bits are at low addresses. Favor aligned stores at
2494 // the cost of some bit-fiddling.
2495 GetExpandedInteger(N->getValue(), Lo, Hi);
2497 EVT ExtVT = N->getMemoryVT();
2498 unsigned EBytes = ExtVT.getStoreSize();
2499 unsigned IncrementSize = NVT.getSizeInBits()/8;
2500 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2501 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2502 ExtVT.getSizeInBits() - ExcessBits);
2504 if (ExcessBits < NVT.getSizeInBits()) {
2505 // Transfer high bits from the top of Lo to the bottom of Hi.
2506 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2507 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2508 TLI.getPointerTy()));
2509 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2510 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2511 DAG.getConstant(ExcessBits,
2512 TLI.getPointerTy())));
2515 // Store both the high bits and maybe some of the low bits.
2516 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2517 HiVT, isVolatile, isNonTemporal, Alignment);
2519 // Increment the pointer to the other half.
2520 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2521 DAG.getIntPtrConstant(IncrementSize));
2522 // Store the lowest ExcessBits bits in the second half.
2523 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2524 N->getPointerInfo().getWithOffset(IncrementSize),
2525 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2526 isVolatile, isNonTemporal,
2527 MinAlign(Alignment, IncrementSize));
2528 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2531 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2533 GetExpandedInteger(N->getOperand(0), InL, InH);
2534 // Just truncate the low part of the source.
2535 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2538 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2539 switch (VT.getSimpleVT().SimpleTy) {
2540 default: llvm_unreachable("Unknown FP format");
2541 case MVT::f32: return &APFloat::IEEEsingle;
2542 case MVT::f64: return &APFloat::IEEEdouble;
2543 case MVT::f80: return &APFloat::x87DoubleExtended;
2544 case MVT::f128: return &APFloat::IEEEquad;
2545 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2549 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2550 SDValue Op = N->getOperand(0);
2551 EVT SrcVT = Op.getValueType();
2552 EVT DstVT = N->getValueType(0);
2553 DebugLoc dl = N->getDebugLoc();
2555 // The following optimization is valid only if every value in SrcVT (when
2556 // treated as signed) is representable in DstVT. Check that the mantissa
2557 // size of DstVT is >= than the number of bits in SrcVT -1.
2558 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2559 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2560 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2561 // Do a signed conversion then adjust the result.
2562 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2563 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2565 // The result of the signed conversion needs adjusting if the 'sign bit' of
2566 // the incoming integer was set. To handle this, we dynamically test to see
2567 // if it is set, and, if so, add a fudge factor.
2569 const uint64_t F32TwoE32 = 0x4F800000ULL;
2570 const uint64_t F32TwoE64 = 0x5F800000ULL;
2571 const uint64_t F32TwoE128 = 0x7F800000ULL;
2574 if (SrcVT == MVT::i32)
2575 FF = APInt(32, F32TwoE32);
2576 else if (SrcVT == MVT::i64)
2577 FF = APInt(32, F32TwoE64);
2578 else if (SrcVT == MVT::i128)
2579 FF = APInt(32, F32TwoE128);
2581 assert(false && "Unsupported UINT_TO_FP!");
2583 // Check whether the sign bit is set.
2585 GetExpandedInteger(Op, Lo, Hi);
2586 SDValue SignSet = DAG.getSetCC(dl,
2587 TLI.getSetCCResultType(Hi.getValueType()),
2588 Hi, DAG.getConstant(0, Hi.getValueType()),
2591 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2592 SDValue FudgePtr = DAG.getConstantPool(
2593 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2594 TLI.getPointerTy());
2596 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2597 SDValue Zero = DAG.getIntPtrConstant(0);
2598 SDValue Four = DAG.getIntPtrConstant(4);
2599 if (TLI.isBigEndian()) std::swap(Zero, Four);
2600 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2602 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2603 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2604 Alignment = std::min(Alignment, 4u);
2606 // Load the value out, extending it from f32 to the destination float type.
2607 // FIXME: Avoid the extend by constructing the right constant pool?
2608 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, dl, DAG.getEntryNode(),
2610 MachinePointerInfo::getConstantPool(),
2612 false, false, Alignment);
2613 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2616 // Otherwise, use a libcall.
2617 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2618 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2619 "Don't know how to expand this UINT_TO_FP!");
2620 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);