1 //===-- LegalizeDAGTypes.cpp - Implement SelectionDAG::LegalizeTypes ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeTypes method. It transforms
11 // an arbitrary well-formed SelectionDAG to only consist of legal types.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "legalize-types"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/Support/Alignment.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Support/Debug.h"
26 //===----------------------------------------------------------------------===//
27 /// DAGTypeLegalizer - This takes an arbitrary SelectionDAG as input and
28 /// hacks on it until the target machine can handle it. This involves
29 /// eliminating value sizes the machine cannot handle (promoting small sizes to
30 /// large sizes or splitting up large values into small values) as well as
31 /// eliminating operations the machine cannot handle.
33 /// This code also does a small amount of optimization and recognition of idioms
34 /// as part of its processing. For example, if a target does not support a
35 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
36 /// will attempt merge setcc and brc instructions into brcc's.
39 class VISIBILITY_HIDDEN DAGTypeLegalizer {
43 // NodeIDFlags - This pass uses the NodeID on the SDNodes to hold information
44 // about the state of the node. The enum has all the values.
46 /// ReadyToProcess - All operands have been processed, so this node is ready
50 /// NewNode - This is a new node that was created in the process of
51 /// legalizing some other node.
54 /// Processed - This is a node that has already been processed.
57 // 1+ - This is a node which has this many unlegalized operands.
61 Legal, // The target natively supports this type.
62 Promote, // This type should be executed in a larger type.
63 Expand // This type should be split into two types of half the size.
66 /// ValueTypeActions - This is a bitvector that contains two bits for each
67 /// simple value type, where the two bits correspond to the LegalizeAction
68 /// enum. This can be queried with "getTypeAction(VT)".
69 TargetLowering::ValueTypeActionImpl ValueTypeActions;
71 /// getTypeAction - Return how we should legalize values of this type, either
72 /// it is already legal or we need to expand it into multiple registers of
73 /// smaller integer type, or we need to promote it to a larger type.
74 LegalizeAction getTypeAction(MVT::ValueType VT) const {
75 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
78 /// isTypeLegal - Return true if this type is legal on this target.
80 bool isTypeLegal(MVT::ValueType VT) const {
81 return getTypeAction(VT) == Legal;
84 SDOperand getIntPtrConstant(uint64_t Val) {
85 return DAG.getConstant(Val, TLI.getPointerTy());
88 /// PromotedNodes - For nodes that are below legal width, and that have more
89 /// than one use, this map indicates what promoted value to use.
90 DenseMap<SDOperand, SDOperand> PromotedNodes;
92 /// ExpandedNodes - For nodes that need to be expanded this map indicates
93 /// which operands are the expanded version of the input.
94 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
96 /// Worklist - This defines a worklist of nodes to process. In order to be
97 /// pushed onto this worklist, all operands of a node must have already been
99 SmallVector<SDNode*, 128> Worklist;
102 explicit DAGTypeLegalizer(SelectionDAG &dag)
103 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
104 ValueTypeActions(TLI.getValueTypeActions()) {
105 assert(MVT::LAST_VALUETYPE <= 32 &&
106 "Too many value types for ValueTypeActions to hold!");
112 void MarkNewNodes(SDNode *N);
114 void ReplaceLegalValueWith(SDOperand From, SDOperand To);
116 SDOperand GetPromotedOp(SDOperand Op) {
117 Op = PromotedNodes[Op];
118 assert(Op.Val && "Operand wasn't promoted?");
121 void SetPromotedOp(SDOperand Op, SDOperand Result);
123 /// GetPromotedZExtOp - Get a promoted operand and zero extend it to the final
125 SDOperand GetPromotedZExtOp(SDOperand Op) {
126 MVT::ValueType OldVT = Op.getValueType();
127 Op = GetPromotedOp(Op);
128 return DAG.getZeroExtendInReg(Op, OldVT);
131 void GetExpandedOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
132 void SetExpandedOp(SDOperand Op, SDOperand Lo, SDOperand Hi);
135 SDOperand CreateStackStoreLoad(SDOperand Op, MVT::ValueType DestVT);
136 SDOperand HandleMemIntrinsic(SDNode *N);
137 void SplitOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
140 void PromoteResult(SDNode *N, unsigned ResNo);
141 SDOperand PromoteResult_UNDEF(SDNode *N);
142 SDOperand PromoteResult_Constant(SDNode *N);
143 SDOperand PromoteResult_TRUNCATE(SDNode *N);
144 SDOperand PromoteResult_INT_EXTEND(SDNode *N);
145 SDOperand PromoteResult_FP_ROUND(SDNode *N);
146 SDOperand PromoteResult_FP_TO_XINT(SDNode *N);
147 SDOperand PromoteResult_SETCC(SDNode *N);
148 SDOperand PromoteResult_LOAD(LoadSDNode *N);
149 SDOperand PromoteResult_SimpleIntBinOp(SDNode *N);
150 SDOperand PromoteResult_SHL(SDNode *N);
151 SDOperand PromoteResult_SRA(SDNode *N);
152 SDOperand PromoteResult_SRL(SDNode *N);
153 SDOperand PromoteResult_SELECT (SDNode *N);
154 SDOperand PromoteResult_SELECT_CC(SDNode *N);
157 void ExpandResult(SDNode *N, unsigned ResNo);
158 void ExpandResult_UNDEF (SDNode *N, SDOperand &Lo, SDOperand &Hi);
159 void ExpandResult_Constant (SDNode *N, SDOperand &Lo, SDOperand &Hi);
160 void ExpandResult_BUILD_PAIR (SDNode *N, SDOperand &Lo, SDOperand &Hi);
161 void ExpandResult_ANY_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
162 void ExpandResult_ZERO_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
163 void ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi);
164 void ExpandResult_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
165 void ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi);
166 void ExpandResult_LOAD (LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
168 void ExpandResult_Logical (SDNode *N, SDOperand &Lo, SDOperand &Hi);
169 void ExpandResult_BSWAP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
170 void ExpandResult_ADDSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
171 void ExpandResult_ADDSUBC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
172 void ExpandResult_ADDSUBE (SDNode *N, SDOperand &Lo, SDOperand &Hi);
173 void ExpandResult_SELECT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
174 void ExpandResult_SELECT_CC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
175 void ExpandResult_MUL (SDNode *N, SDOperand &Lo, SDOperand &Hi);
176 void ExpandResult_Shift (SDNode *N, SDOperand &Lo, SDOperand &Hi);
178 void ExpandShiftByConstant(SDNode *N, unsigned Amt,
179 SDOperand &Lo, SDOperand &Hi);
180 bool ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi);
182 // Operand Promotion.
183 bool PromoteOperand(SDNode *N, unsigned OperandNo);
184 SDOperand PromoteOperand_ANY_EXTEND(SDNode *N);
185 SDOperand PromoteOperand_ZERO_EXTEND(SDNode *N);
186 SDOperand PromoteOperand_SIGN_EXTEND(SDNode *N);
187 SDOperand PromoteOperand_TRUNCATE(SDNode *N);
188 SDOperand PromoteOperand_FP_EXTEND(SDNode *N);
189 SDOperand PromoteOperand_FP_ROUND(SDNode *N);
190 SDOperand PromoteOperand_INT_TO_FP(SDNode *N);
191 SDOperand PromoteOperand_SELECT(SDNode *N, unsigned OpNo);
192 SDOperand PromoteOperand_BRCOND(SDNode *N, unsigned OpNo);
193 SDOperand PromoteOperand_BR_CC(SDNode *N, unsigned OpNo);
194 SDOperand PromoteOperand_SETCC(SDNode *N, unsigned OpNo);
195 SDOperand PromoteOperand_STORE(StoreSDNode *N, unsigned OpNo);
197 void PromoteSetCCOperands(SDOperand &LHS,SDOperand &RHS, ISD::CondCode Code);
199 // Operand Expansion.
200 bool ExpandOperand(SDNode *N, unsigned OperandNo);
201 SDOperand ExpandOperand_TRUNCATE(SDNode *N);
202 SDOperand ExpandOperand_BIT_CONVERT(SDNode *N);
203 SDOperand ExpandOperand_UINT_TO_FP(SDOperand Source, MVT::ValueType DestTy);
204 SDOperand ExpandOperand_SINT_TO_FP(SDOperand Source, MVT::ValueType DestTy);
205 SDOperand ExpandOperand_EXTRACT_ELEMENT(SDNode *N);
206 SDOperand ExpandOperand_SETCC(SDNode *N);
207 SDOperand ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo);
209 void ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
210 ISD::CondCode &CCCode);
212 } // end anonymous namespace
216 /// run - This is the main entry point for the type legalizer. This does a
217 /// top-down traversal of the dag, legalizing types as it goes.
218 void DAGTypeLegalizer::run() {
219 // Create a dummy node (which is not added to allnodes), that adds a reference
220 // to the root node, preventing it from being deleted, and tracking any
221 // changes of the root.
222 HandleSDNode Dummy(DAG.getRoot());
224 // The root of the dag may dangle to deleted nodes until the type legalizer is
225 // done. Set it to null to avoid confusion.
226 DAG.setRoot(SDOperand());
228 // Walk all nodes in the graph, assigning them a NodeID of 'ReadyToProcess'
229 // (and remembering them) if they are leaves and assigning 'NewNode' if
231 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
232 E = DAG.allnodes_end(); I != E; ++I) {
233 if (I->getNumOperands() == 0) {
234 I->setNodeId(ReadyToProcess);
235 Worklist.push_back(I);
237 I->setNodeId(NewNode);
241 // Now that we have a set of nodes to process, handle them all.
242 while (!Worklist.empty()) {
243 SDNode *N = Worklist.back();
245 assert(N->getNodeId() == ReadyToProcess &&
246 "Node should be ready if on worklist!");
248 // Scan the values produced by the node, checking to see if any result
249 // types are illegal.
251 unsigned NumResults = N->getNumValues();
253 LegalizeAction Action = getTypeAction(N->getValueType(i));
254 if (Action == Promote) {
257 } else if (Action == Expand) {
261 assert(Action == Legal && "Unknown action!");
263 } while (++i < NumResults);
265 // Scan the operand list for the node, handling any nodes with operands that
268 unsigned NumOperands = N->getNumOperands();
269 bool NeedsRevisit = false;
270 for (i = 0; i != NumOperands; ++i) {
271 LegalizeAction Action = getTypeAction(N->getOperand(i).getValueType());
272 if (Action == Promote) {
273 NeedsRevisit = PromoteOperand(N, i);
275 } else if (Action == Expand) {
276 NeedsRevisit = ExpandOperand(N, i);
279 assert(Action == Legal && "Unknown action!");
283 // If the node needs revisiting, don't add all users to the worklist etc.
287 if (i == NumOperands)
288 DEBUG(cerr << "Legally typed node: "; N->dump(&DAG); cerr << "\n");
292 // If we reach here, the node was processed, potentially creating new nodes.
293 // Mark it as processed and add its users to the worklist as appropriate.
294 N->setNodeId(Processed);
296 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
299 int NodeID = User->getNodeId();
300 assert(NodeID != ReadyToProcess && NodeID != Processed &&
301 "Invalid node id for user of unprocessed node!");
303 // This node has two options: it can either be a new node or its Node ID
304 // may be a count of the number of operands it has that are not ready.
306 User->setNodeId(NodeID-1);
308 // If this was the last use it was waiting on, add it to the ready list.
309 if (NodeID-1 == ReadyToProcess)
310 Worklist.push_back(User);
314 // Otherwise, this node is new: this is the first operand of it that
315 // became ready. Its new NodeID is the number of operands it has minus 1
316 // (as this node is now processed).
317 assert(NodeID == NewNode && "Unknown node ID!");
318 User->setNodeId(User->getNumOperands()-1);
320 // If the node only has a single operand, it is now ready.
321 if (User->getNumOperands() == 1)
322 Worklist.push_back(User);
326 // If the root changed (e.g. it was a dead load, update the root).
327 DAG.setRoot(Dummy.getValue());
331 // Remove dead nodes. This is important to do for cleanliness but also before
332 // the checking loop below. Implicit folding by the DAG.getNode operators can
333 // cause unreachable nodes to be around with their flags set to new.
334 DAG.RemoveDeadNodes();
336 // In a debug build, scan all the nodes to make sure we found them all. This
337 // ensures that there are no cycles and that everything got processed.
339 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
340 E = DAG.allnodes_end(); I != E; ++I) {
341 if (I->getNodeId() == Processed)
343 cerr << "Unprocessed node: ";
344 I->dump(&DAG); cerr << "\n";
346 if (I->getNodeId() == NewNode)
347 cerr << "New node not 'noticed'?\n";
348 else if (I->getNodeId() > 0)
349 cerr << "Operand not processed?\n";
350 else if (I->getNodeId() == ReadyToProcess)
351 cerr << "Not added to worklist?\n";
357 /// MarkNewNodes - The specified node is the root of a subtree of potentially
358 /// new nodes. Add the correct NodeId to mark it.
359 void DAGTypeLegalizer::MarkNewNodes(SDNode *N) {
360 // If this was an existing node that is already done, we're done.
361 if (N->getNodeId() != NewNode)
364 // Okay, we know that this node is new. Recursively walk all of its operands
365 // to see if they are new also. The depth of this walk is bounded by the size
366 // of the new tree that was constructed (usually 2-3 nodes), so we don't worry
367 // about revisiting of nodes.
369 // As we walk the operands, keep track of the number of nodes that are
370 // processed. If non-zero, this will become the new nodeid of this node.
371 unsigned NumProcessed = 0;
372 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
373 int OpId = N->getOperand(i).Val->getNodeId();
375 MarkNewNodes(N->getOperand(i).Val);
376 else if (OpId == Processed)
380 N->setNodeId(N->getNumOperands()-NumProcessed);
381 if (N->getNodeId() == ReadyToProcess)
382 Worklist.push_back(N);
385 /// ReplaceLegalValueWith - The specified value with a legal type was legalized
386 /// to the specified other value. If they are different, update the DAG and
387 /// NodeIDs replacing any uses of From to use To instead.
388 void DAGTypeLegalizer::ReplaceLegalValueWith(SDOperand From, SDOperand To) {
389 if (From == To) return;
391 // If expansion produced new nodes, make sure they are properly marked.
392 if (To.Val->getNodeId() == NewNode)
393 MarkNewNodes(To.Val);
395 // Anything that used the old node should now use the new one. Note that this
396 // can potentially cause recursive merging.
397 DAG.ReplaceAllUsesOfValueWith(From, To);
399 // Since we just made an unstructured update to the DAG, which could wreak
400 // general havoc on anything that once used N and now uses Res, walk all users
401 // of the result, updating their flags.
402 for (SDNode::use_iterator I = To.Val->use_begin(), E = To.Val->use_end();
405 // If the node isn't already processed or in the worklist, mark it as new,
406 // then use MarkNewNodes to recompute its ID.
407 int NodeId = User->getNodeId();
408 if (NodeId != ReadyToProcess && NodeId != Processed) {
409 User->setNodeId(NewNode);
415 void DAGTypeLegalizer::SetPromotedOp(SDOperand Op, SDOperand Result) {
416 if (Result.Val->getNodeId() == NewNode)
417 MarkNewNodes(Result.Val);
419 SDOperand &OpEntry = PromotedNodes[Op];
420 assert(OpEntry.Val == 0 && "Node is already promoted!");
424 void DAGTypeLegalizer::GetExpandedOp(SDOperand Op, SDOperand &Lo,
426 std::pair<SDOperand, SDOperand> &Entry = ExpandedNodes[Op];
427 assert(Entry.first.Val && "Operand isn't expanded");
432 void DAGTypeLegalizer::SetExpandedOp(SDOperand Op, SDOperand Lo,
434 // Remember that this is the result of the node.
435 std::pair<SDOperand, SDOperand> &Entry = ExpandedNodes[Op];
436 assert(Entry.first.Val == 0 && "Node already expanded");
440 // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
441 if (Lo.Val->getNodeId() == NewNode)
442 MarkNewNodes(Lo.Val);
443 if (Hi.Val->getNodeId() == NewNode)
444 MarkNewNodes(Hi.Val);
447 SDOperand DAGTypeLegalizer::CreateStackStoreLoad(SDOperand Op,
448 MVT::ValueType DestVT) {
449 // Create the stack frame object.
450 SDOperand FIPtr = DAG.CreateStackTemporary(DestVT);
452 // Emit a store to the stack slot.
453 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Op, FIPtr, NULL, 0);
454 // Result is a load from the stack slot.
455 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
458 /// HandleMemIntrinsic - This handles memcpy/memset/memmove with invalid
459 /// operands. This promotes or expands the operands as required.
460 SDOperand DAGTypeLegalizer::HandleMemIntrinsic(SDNode *N) {
461 // The chain and pointer [operands #0 and #1] are always valid types.
462 SDOperand Chain = N->getOperand(0);
463 SDOperand Ptr = N->getOperand(1);
464 SDOperand Op2 = N->getOperand(2);
466 // Op #2 is either a value (memset) or a pointer. Promote it if required.
467 switch (getTypeAction(Op2.getValueType())) {
468 default: assert(0 && "Unknown action for pointer/value operand");
470 case Promote: Op2 = GetPromotedOp(Op2); break;
473 // The length could have any action required.
474 SDOperand Length = N->getOperand(3);
475 switch (getTypeAction(Length.getValueType())) {
476 default: assert(0 && "Unknown action for memop operand");
478 case Promote: Length = GetPromotedZExtOp(Length); break;
480 SDOperand Dummy; // discard the high part.
481 GetExpandedOp(Length, Length, Dummy);
485 SDOperand Align = N->getOperand(4);
486 switch (getTypeAction(Align.getValueType())) {
487 default: assert(0 && "Unknown action for memop operand");
489 case Promote: Align = GetPromotedZExtOp(Align); break;
492 SDOperand AlwaysInline = N->getOperand(5);
493 switch (getTypeAction(AlwaysInline.getValueType())) {
494 default: assert(0 && "Unknown action for memop operand");
496 case Promote: AlwaysInline = GetPromotedZExtOp(AlwaysInline); break;
499 SDOperand Ops[] = { Chain, Ptr, Op2, Length, Align, AlwaysInline };
500 return DAG.UpdateNodeOperands(SDOperand(N, 0), Ops, 6);
503 /// SplitOp - Return the lower and upper halves of Op's bits in a value type
504 /// half the size of Op's.
505 void DAGTypeLegalizer::SplitOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi) {
506 unsigned NVTBits = MVT::getSizeInBits(Op.getValueType())/2;
507 assert(MVT::getSizeInBits(Op.getValueType()) == 2*NVTBits &&
508 "Cannot split odd sized integer type");
509 MVT::ValueType NVT = MVT::getIntegerType(NVTBits);
510 Lo = DAG.getNode(ISD::TRUNCATE, NVT, Op);
511 Hi = DAG.getNode(ISD::SRL, Op.getValueType(), Op,
512 DAG.getConstant(NVTBits, TLI.getShiftAmountTy()));
513 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
517 //===----------------------------------------------------------------------===//
519 //===----------------------------------------------------------------------===//
521 /// PromoteResult - This method is called when a result of a node is found to be
522 /// in need of promotion to a larger type. At this point, the node may also
523 /// have invalid operands or may have other results that need expansion, we just
524 /// know that (at least) one result needs promotion.
525 void DAGTypeLegalizer::PromoteResult(SDNode *N, unsigned ResNo) {
526 DEBUG(cerr << "Promote node result: "; N->dump(&DAG); cerr << "\n");
527 SDOperand Result = SDOperand();
529 switch (N->getOpcode()) {
532 cerr << "PromoteResult #" << ResNo << ": ";
533 N->dump(&DAG); cerr << "\n";
535 assert(0 && "Do not know how to promote this operator!");
537 case ISD::UNDEF: Result = PromoteResult_UNDEF(N); break;
538 case ISD::Constant: Result = PromoteResult_Constant(N); break;
540 case ISD::TRUNCATE: Result = PromoteResult_TRUNCATE(N); break;
541 case ISD::SIGN_EXTEND:
542 case ISD::ZERO_EXTEND:
543 case ISD::ANY_EXTEND: Result = PromoteResult_INT_EXTEND(N); break;
544 case ISD::FP_ROUND: Result = PromoteResult_FP_ROUND(N); break;
545 case ISD::FP_TO_SINT:
546 case ISD::FP_TO_UINT: Result = PromoteResult_FP_TO_XINT(N); break;
547 case ISD::SETCC: Result = PromoteResult_SETCC(N); break;
548 case ISD::LOAD: Result = PromoteResult_LOAD(cast<LoadSDNode>(N)); break;
555 case ISD::MUL: Result = PromoteResult_SimpleIntBinOp(N); break;
557 case ISD::SHL: Result = PromoteResult_SHL(N); break;
558 case ISD::SRA: Result = PromoteResult_SRA(N); break;
559 case ISD::SRL: Result = PromoteResult_SRL(N); break;
561 case ISD::SELECT: Result = PromoteResult_SELECT(N); break;
562 case ISD::SELECT_CC: Result = PromoteResult_SELECT_CC(N); break;
566 // If Result is null, the sub-method took care of registering the result.
568 SetPromotedOp(SDOperand(N, ResNo), Result);
571 SDOperand DAGTypeLegalizer::PromoteResult_UNDEF(SDNode *N) {
572 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
575 SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) {
576 MVT::ValueType VT = N->getValueType(0);
577 // Zero extend things like i1, sign extend everything else. It shouldn't
578 // matter in theory which one we pick, but this tends to give better code?
579 unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
580 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
582 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
586 SDOperand DAGTypeLegalizer::PromoteResult_TRUNCATE(SDNode *N) {
589 switch (getTypeAction(N->getOperand(0).getValueType())) {
590 default: assert(0 && "Unknown type action!");
593 Res = N->getOperand(0);
596 Res = GetPromotedOp(N->getOperand(0));
600 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
601 assert(MVT::getSizeInBits(Res.getValueType()) >= MVT::getSizeInBits(NVT) &&
602 "Truncation doesn't make sense!");
603 if (Res.getValueType() == NVT)
606 // Truncate to NVT instead of VT
607 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
610 SDOperand DAGTypeLegalizer::PromoteResult_INT_EXTEND(SDNode *N) {
611 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
613 if (getTypeAction(N->getOperand(0).getValueType()) == Promote) {
614 SDOperand Res = GetPromotedOp(N->getOperand(0));
615 assert(MVT::getSizeInBits(Res.getValueType()) <= MVT::getSizeInBits(NVT) &&
616 "Extension doesn't make sense!");
618 // If the result and operand types are the same after promotion, simplify
619 // to an in-register extension.
620 if (NVT == Res.getValueType()) {
621 // The high bits are not guaranteed to be anything. Insert an extend.
622 if (N->getOpcode() == ISD::SIGN_EXTEND)
623 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
624 DAG.getValueType(N->getOperand(0).getValueType()));
625 if (N->getOpcode() == ISD::ZERO_EXTEND)
626 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
627 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
632 // Otherwise, just extend the original operand all the way to the larger type.
633 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
636 SDOperand DAGTypeLegalizer::PromoteResult_FP_ROUND(SDNode *N) {
637 // NOTE: Assumes input is legal.
638 return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
639 N->getOperand(0), DAG.getValueType(N->getValueType(0)));
642 SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
643 SDOperand Op = N->getOperand(0);
644 // If the operand needed to be promoted, do so now.
645 if (getTypeAction(Op.getValueType()) == Promote)
646 // The input result is prerounded, so we don't have to do anything special.
647 Op = GetPromotedOp(Op);
649 unsigned NewOpc = N->getOpcode();
650 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
652 // If we're promoting a UINT to a larger size, check to see if the new node
653 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
654 // we can use that instead. This allows us to generate better code for
655 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
656 // legal, such as PowerPC.
657 if (N->getOpcode() == ISD::FP_TO_UINT) {
658 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
659 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
660 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
661 NewOpc = ISD::FP_TO_SINT;
664 return DAG.getNode(NewOpc, NVT, Op);
667 SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
668 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
669 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), N->getOperand(0),
670 N->getOperand(1), N->getOperand(2));
673 SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
674 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
675 ISD::LoadExtType ExtType =
676 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
677 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
678 N->getSrcValue(), N->getSrcValueOffset(),
679 N->getLoadedVT(), N->isVolatile(),
682 // Legalized the chain result - switch anything that used the old chain to
684 ReplaceLegalValueWith(SDOperand(N, 1), Res.getValue(1));
688 SDOperand DAGTypeLegalizer::PromoteResult_SimpleIntBinOp(SDNode *N) {
689 // The input may have strange things in the top bits of the registers, but
690 // these operations don't care. They may have weird bits going out, but
691 // that too is okay if they are integer operations.
692 SDOperand LHS = GetPromotedOp(N->getOperand(0));
693 SDOperand RHS = GetPromotedOp(N->getOperand(1));
694 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
697 SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) {
698 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
699 GetPromotedOp(N->getOperand(0)), N->getOperand(1));
702 SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) {
703 // The input value must be properly sign extended.
704 MVT::ValueType VT = N->getValueType(0);
705 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
706 SDOperand Res = GetPromotedOp(N->getOperand(0));
707 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
708 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
711 SDOperand DAGTypeLegalizer::PromoteResult_SRL(SDNode *N) {
712 // The input value must be properly zero extended.
713 MVT::ValueType VT = N->getValueType(0);
714 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
715 SDOperand Res = GetPromotedZExtOp(N->getOperand(0));
716 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
719 SDOperand DAGTypeLegalizer::PromoteResult_SELECT(SDNode *N) {
720 SDOperand LHS = GetPromotedOp(N->getOperand(1));
721 SDOperand RHS = GetPromotedOp(N->getOperand(2));
722 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
725 SDOperand DAGTypeLegalizer::PromoteResult_SELECT_CC(SDNode *N) {
726 SDOperand LHS = GetPromotedOp(N->getOperand(2));
727 SDOperand RHS = GetPromotedOp(N->getOperand(3));
728 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
729 N->getOperand(1), LHS, RHS, N->getOperand(4));
733 //===----------------------------------------------------------------------===//
735 //===----------------------------------------------------------------------===//
737 /// ExpandResult - This method is called when the specified result of the
738 /// specified node is found to need expansion. At this point, the node may also
739 /// have invalid operands or may have other results that need promotion, we just
740 /// know that (at least) one result needs expansion.
741 void DAGTypeLegalizer::ExpandResult(SDNode *N, unsigned ResNo) {
742 DEBUG(cerr << "Expand node result: "; N->dump(&DAG); cerr << "\n");
744 Lo = Hi = SDOperand();
746 // If this is a single-result node, see if the target wants to custom expand
748 if (N->getNumValues() == 1 &&
749 TLI.getOperationAction(N->getOpcode(),
750 N->getValueType(0)) == TargetLowering::Custom) {
751 // If the target wants to, allow it to lower this itself.
752 std::pair<SDOperand,SDOperand> P = TLI.ExpandOperationResult(N, DAG);
760 switch (N->getOpcode()) {
763 cerr << "ExpandResult #" << ResNo << ": ";
764 N->dump(&DAG); cerr << "\n";
766 assert(0 && "Do not know how to expand this operator!");
769 case ISD::UNDEF: ExpandResult_UNDEF(N, Lo, Hi); break;
770 case ISD::Constant: ExpandResult_Constant(N, Lo, Hi); break;
771 case ISD::BUILD_PAIR: ExpandResult_BUILD_PAIR(N, Lo, Hi); break;
772 case ISD::ANY_EXTEND: ExpandResult_ANY_EXTEND(N, Lo, Hi); break;
773 case ISD::ZERO_EXTEND: ExpandResult_ZERO_EXTEND(N, Lo, Hi); break;
774 case ISD::SIGN_EXTEND: ExpandResult_SIGN_EXTEND(N, Lo, Hi); break;
775 case ISD::BIT_CONVERT: ExpandResult_BIT_CONVERT(N, Lo, Hi); break;
776 case ISD::SIGN_EXTEND_INREG: ExpandResult_SIGN_EXTEND_INREG(N, Lo, Hi); break;
777 case ISD::LOAD: ExpandResult_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
781 case ISD::XOR: ExpandResult_Logical(N, Lo, Hi); break;
782 case ISD::BSWAP: ExpandResult_BSWAP(N, Lo, Hi); break;
784 case ISD::SUB: ExpandResult_ADDSUB(N, Lo, Hi); break;
786 case ISD::SUBC: ExpandResult_ADDSUBC(N, Lo, Hi); break;
788 case ISD::SUBE: ExpandResult_ADDSUBE(N, Lo, Hi); break;
789 case ISD::SELECT: ExpandResult_SELECT(N, Lo, Hi); break;
790 case ISD::SELECT_CC: ExpandResult_SELECT_CC(N, Lo, Hi); break;
791 case ISD::MUL: ExpandResult_MUL(N, Lo, Hi); break;
794 case ISD::SRL: ExpandResult_Shift(N, Lo, Hi); break;
798 // If Lo/Hi is null, the sub-method took care of registering results etc.
800 SetExpandedOp(SDOperand(N, ResNo), Lo, Hi);
803 void DAGTypeLegalizer::ExpandResult_UNDEF(SDNode *N,
804 SDOperand &Lo, SDOperand &Hi) {
805 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
806 Lo = Hi = DAG.getNode(ISD::UNDEF, NVT);
809 void DAGTypeLegalizer::ExpandResult_Constant(SDNode *N,
810 SDOperand &Lo, SDOperand &Hi) {
811 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
812 uint64_t Cst = cast<ConstantSDNode>(N)->getValue();
813 Lo = DAG.getConstant(Cst, NVT);
814 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
817 void DAGTypeLegalizer::ExpandResult_BUILD_PAIR(SDNode *N,
818 SDOperand &Lo, SDOperand &Hi) {
819 // Return the operands.
820 Lo = N->getOperand(0);
821 Hi = N->getOperand(1);
824 void DAGTypeLegalizer::ExpandResult_ANY_EXTEND(SDNode *N,
825 SDOperand &Lo, SDOperand &Hi) {
826 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
827 SDOperand Op = N->getOperand(0);
828 if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
829 // The low part is any extension of the input (which degenerates to a copy).
830 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
831 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
833 // For example, extension of an i48 to an i64. The operand type necessarily
834 // promotes to the result type, so will end up being expanded too.
835 assert(getTypeAction(Op.getValueType()) == Promote &&
836 "Don't know how to expand this result!");
837 SDOperand Res = GetPromotedOp(Op);
838 assert(Res.getValueType() == N->getValueType(0) &&
839 "Operand over promoted?");
840 // Split the promoted operand. This will simplify when it is expanded.
841 SplitOp(Res, Lo, Hi);
845 void DAGTypeLegalizer::ExpandResult_ZERO_EXTEND(SDNode *N,
846 SDOperand &Lo, SDOperand &Hi) {
847 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
848 SDOperand Op = N->getOperand(0);
849 if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
850 // The low part is zero extension of the input (which degenerates to a copy).
851 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
852 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
854 // For example, extension of an i48 to an i64. The operand type necessarily
855 // promotes to the result type, so will end up being expanded too.
856 assert(getTypeAction(Op.getValueType()) == Promote &&
857 "Don't know how to expand this result!");
858 SDOperand Res = GetPromotedOp(Op);
859 assert(Res.getValueType() == N->getValueType(0) &&
860 "Operand over promoted?");
861 // Split the promoted operand. This will simplify when it is expanded.
862 SplitOp(Res, Lo, Hi);
863 unsigned ExcessBits =
864 MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT);
865 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerType(ExcessBits));
869 void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N,
870 SDOperand &Lo, SDOperand &Hi) {
871 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
872 SDOperand Op = N->getOperand(0);
873 if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
874 // The low part is sign extension of the input (which degenerates to a copy).
875 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
876 // The high part is obtained by SRA'ing all but one of the bits of low part.
877 unsigned LoSize = MVT::getSizeInBits(NVT);
878 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
879 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
881 // For example, extension of an i48 to an i64. The operand type necessarily
882 // promotes to the result type, so will end up being expanded too.
883 assert(getTypeAction(Op.getValueType()) == Promote &&
884 "Don't know how to expand this result!");
885 SDOperand Res = GetPromotedOp(Op);
886 assert(Res.getValueType() == N->getValueType(0) &&
887 "Operand over promoted?");
888 // Split the promoted operand. This will simplify when it is expanded.
889 SplitOp(Res, Lo, Hi);
890 unsigned ExcessBits =
891 MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT);
892 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
893 DAG.getValueType(MVT::getIntegerType(ExcessBits)));
897 void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N,
898 SDOperand &Lo, SDOperand &Hi) {
899 // Lower the bit-convert to a store/load from the stack, then expand the load.
900 SDOperand Op = CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
901 ExpandResult_LOAD(cast<LoadSDNode>(Op.Val), Lo, Hi);
904 void DAGTypeLegalizer::
905 ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
906 GetExpandedOp(N->getOperand(0), Lo, Hi);
907 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
909 if (MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(Lo.getValueType())) {
910 // sext_inreg the low part if needed.
911 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
914 // The high part gets the sign extension from the lo-part. This handles
915 // things like sextinreg V:i64 from i8.
916 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
917 DAG.getConstant(MVT::getSizeInBits(Hi.getValueType())-1,
918 TLI.getShiftAmountTy()));
920 // For example, extension of an i48 to an i64. Leave the low part alone,
921 // sext_inreg the high part.
922 unsigned ExcessBits =
923 MVT::getSizeInBits(EVT) - MVT::getSizeInBits(Lo.getValueType());
924 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
925 DAG.getValueType(MVT::getIntegerType(ExcessBits)));
929 void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
930 SDOperand &Lo, SDOperand &Hi) {
931 MVT::ValueType VT = N->getValueType(0);
932 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
933 SDOperand Ch = N->getChain(); // Legalize the chain.
934 SDOperand Ptr = N->getBasePtr(); // Legalize the pointer.
935 ISD::LoadExtType ExtType = N->getExtensionType();
936 int SVOffset = N->getSrcValueOffset();
937 unsigned Alignment = N->getAlignment();
938 bool isVolatile = N->isVolatile();
940 assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!");
942 if (ExtType == ISD::NON_EXTLOAD) {
943 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
944 isVolatile, Alignment);
945 // Increment the pointer to the other half.
946 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
947 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
948 getIntPtrConstant(IncrementSize));
949 Hi = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
950 isVolatile, MinAlign(Alignment, IncrementSize));
952 // Build a factor node to remember that this load is independent of the
954 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
957 // Handle endianness of the load.
958 if (!TLI.isLittleEndian())
960 } else if (MVT::getSizeInBits(N->getLoadedVT()) <= MVT::getSizeInBits(NVT)) {
961 MVT::ValueType EVT = N->getLoadedVT();
963 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
964 isVolatile, Alignment);
966 // Remember the chain.
969 if (ExtType == ISD::SEXTLOAD) {
970 // The high part is obtained by SRA'ing all but one of the bits of the
972 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
973 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
974 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
975 } else if (ExtType == ISD::ZEXTLOAD) {
976 // The high part is just a zero.
977 Hi = DAG.getConstant(0, NVT);
979 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
980 // The high part is undefined.
981 Hi = DAG.getNode(ISD::UNDEF, NVT);
983 } else if (TLI.isLittleEndian()) {
984 // Little-endian - low bits are at low addresses.
985 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
986 isVolatile, Alignment);
988 unsigned ExcessBits =
989 MVT::getSizeInBits(N->getLoadedVT()) - MVT::getSizeInBits(NVT);
990 MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits);
992 // Increment the pointer to the other half.
993 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
994 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
995 getIntPtrConstant(IncrementSize));
996 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
997 SVOffset+IncrementSize, NEVT,
998 isVolatile, MinAlign(Alignment, IncrementSize));
1000 // Build a factor node to remember that this load is independent of the
1002 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1005 // Big-endian - high bits are at low addresses. Favor aligned loads at
1006 // the cost of some bit-fiddling.
1007 MVT::ValueType EVT = N->getLoadedVT();
1008 unsigned EBytes = (MVT::getSizeInBits(EVT) + 7)/8;
1009 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
1010 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1012 // Load both the high bits and maybe some of the low bits.
1013 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1014 MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits),
1015 isVolatile, Alignment);
1017 // Increment the pointer to the other half.
1018 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1019 getIntPtrConstant(IncrementSize));
1020 // Load the rest of the low bits.
1021 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1022 SVOffset+IncrementSize, MVT::getIntegerType(ExcessBits),
1023 isVolatile, MinAlign(Alignment, IncrementSize));
1025 // Build a factor node to remember that this load is independent of the
1027 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1030 if (ExcessBits < MVT::getSizeInBits(NVT)) {
1031 // Transfer low bits from the bottom of Hi to the top of Lo.
1032 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1033 DAG.getNode(ISD::SHL, NVT, Hi,
1034 DAG.getConstant(ExcessBits,
1035 TLI.getShiftAmountTy())));
1036 // Move high bits to the right position in Hi.
1037 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1038 DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits,
1039 TLI.getShiftAmountTy()));
1043 // Legalized the chain result - switch anything that used the old chain to
1045 ReplaceLegalValueWith(SDOperand(N, 1), Ch);
1048 void DAGTypeLegalizer::ExpandResult_Logical(SDNode *N,
1049 SDOperand &Lo, SDOperand &Hi) {
1050 SDOperand LL, LH, RL, RH;
1051 GetExpandedOp(N->getOperand(0), LL, LH);
1052 GetExpandedOp(N->getOperand(1), RL, RH);
1053 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1054 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1057 void DAGTypeLegalizer::ExpandResult_BSWAP(SDNode *N,
1058 SDOperand &Lo, SDOperand &Hi) {
1059 GetExpandedOp(N->getOperand(0), Hi, Lo); // Note swapped operands.
1060 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1061 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1064 void DAGTypeLegalizer::ExpandResult_SELECT(SDNode *N,
1065 SDOperand &Lo, SDOperand &Hi) {
1066 SDOperand LL, LH, RL, RH;
1067 GetExpandedOp(N->getOperand(1), LL, LH);
1068 GetExpandedOp(N->getOperand(2), RL, RH);
1069 Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), N->getOperand(0), LL, RL);
1071 assert(N->getOperand(0).getValueType() != MVT::f32 &&
1072 "FIXME: softfp shouldn't use expand!");
1073 Hi = DAG.getNode(ISD::SELECT, LL.getValueType(), N->getOperand(0), LH, RH);
1076 void DAGTypeLegalizer::ExpandResult_SELECT_CC(SDNode *N,
1077 SDOperand &Lo, SDOperand &Hi) {
1078 SDOperand LL, LH, RL, RH;
1079 GetExpandedOp(N->getOperand(2), LL, LH);
1080 GetExpandedOp(N->getOperand(3), RL, RH);
1081 Lo = DAG.getNode(ISD::SELECT_CC, LL.getValueType(), N->getOperand(0),
1082 N->getOperand(1), LL, RL, N->getOperand(4));
1084 assert(N->getOperand(0).getValueType() != MVT::f32 &&
1085 "FIXME: softfp shouldn't use expand!");
1086 Hi = DAG.getNode(ISD::SELECT_CC, LL.getValueType(), N->getOperand(0),
1087 N->getOperand(1), LH, RH, N->getOperand(4));
1090 void DAGTypeLegalizer::ExpandResult_ADDSUB(SDNode *N,
1091 SDOperand &Lo, SDOperand &Hi) {
1092 // Expand the subcomponents.
1093 SDOperand LHSL, LHSH, RHSL, RHSH;
1094 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
1095 GetExpandedOp(N->getOperand(1), RHSL, RHSH);
1096 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1097 SDOperand LoOps[2] = { LHSL, RHSL };
1098 SDOperand HiOps[3] = { LHSH, RHSH };
1100 if (N->getOpcode() == ISD::ADD) {
1101 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1102 HiOps[2] = Lo.getValue(1);
1103 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1105 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1106 HiOps[2] = Lo.getValue(1);
1107 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1111 void DAGTypeLegalizer::ExpandResult_ADDSUBC(SDNode *N,
1112 SDOperand &Lo, SDOperand &Hi) {
1113 // Expand the subcomponents.
1114 SDOperand LHSL, LHSH, RHSL, RHSH;
1115 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
1116 GetExpandedOp(N->getOperand(1), RHSL, RHSH);
1117 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1118 SDOperand LoOps[2] = { LHSL, RHSL };
1119 SDOperand HiOps[3] = { LHSH, RHSH };
1121 if (N->getOpcode() == ISD::ADDC) {
1122 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1123 HiOps[2] = Lo.getValue(1);
1124 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1126 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1127 HiOps[2] = Lo.getValue(1);
1128 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1131 // Legalized the flag result - switch anything that used the old flag to
1133 ReplaceLegalValueWith(SDOperand(N, 1), Hi.getValue(1));
1136 void DAGTypeLegalizer::ExpandResult_ADDSUBE(SDNode *N,
1137 SDOperand &Lo, SDOperand &Hi) {
1138 // Expand the subcomponents.
1139 SDOperand LHSL, LHSH, RHSL, RHSH;
1140 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
1141 GetExpandedOp(N->getOperand(1), RHSL, RHSH);
1142 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1143 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1144 SDOperand HiOps[3] = { LHSH, RHSH };
1146 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1147 HiOps[2] = Lo.getValue(1);
1148 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1150 // Legalized the flag result - switch anything that used the old flag to
1152 ReplaceLegalValueWith(SDOperand(N, 1), Hi.getValue(1));
1155 void DAGTypeLegalizer::ExpandResult_MUL(SDNode *N,
1156 SDOperand &Lo, SDOperand &Hi) {
1157 MVT::ValueType VT = N->getValueType(0);
1158 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1160 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1161 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1162 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1163 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1164 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1165 SDOperand LL, LH, RL, RH;
1166 GetExpandedOp(N->getOperand(0), LL, LH);
1167 GetExpandedOp(N->getOperand(1), RL, RH);
1168 unsigned BitSize = MVT::getSizeInBits(NVT);
1169 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1170 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1172 // FIXME: generalize this to handle other bit sizes
1173 if (LHSSB == 32 && RHSSB == 32 &&
1174 DAG.MaskedValueIsZero(N->getOperand(0), 0xFFFFFFFF00000000ULL) &&
1175 DAG.MaskedValueIsZero(N->getOperand(1), 0xFFFFFFFF00000000ULL)) {
1176 // The inputs are both zero-extended.
1178 // We can emit a umul_lohi.
1179 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1180 Hi = SDOperand(Lo.Val, 1);
1184 // We can emit a mulhu+mul.
1185 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1186 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1190 if (LHSSB > BitSize && RHSSB > BitSize) {
1191 // The input values are both sign-extended.
1193 // We can emit a smul_lohi.
1194 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1195 Hi = SDOperand(Lo.Val, 1);
1199 // We can emit a mulhs+mul.
1200 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1201 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1206 // Lo,Hi = umul LHS, RHS.
1207 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1208 DAG.getVTList(NVT, NVT), LL, RL);
1210 Hi = UMulLOHI.getValue(1);
1211 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1212 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1213 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1214 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1221 // If nothing else, we can make a libcall.
1222 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), N,
1223 false/*sign irrelevant*/, Hi);
1228 void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N,
1229 SDOperand &Lo, SDOperand &Hi) {
1230 MVT::ValueType VT = N->getValueType(0);
1232 // If we can emit an efficient shift operation, do so now. Check to see if
1233 // the RHS is a constant.
1234 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1235 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
1237 // If we can determine that the high bit of the shift is zero or one, even if
1238 // the low bits are variable, emit this shift in an optimized form.
1239 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1242 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1244 if (N->getOpcode() == ISD::SHL)
1245 PartsOpc = ISD::SHL_PARTS;
1246 else if (N->getOpcode() == ISD::SRL)
1247 PartsOpc = ISD::SRL_PARTS;
1249 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1250 PartsOpc = ISD::SRA_PARTS;
1253 // Next check to see if the target supports this SHL_PARTS operation or if it
1254 // will custom expand it.
1255 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1256 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1257 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1258 Action == TargetLowering::Custom) {
1259 // Expand the subcomponents.
1260 SDOperand LHSL, LHSH;
1261 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
1263 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
1264 MVT::ValueType VT = LHSL.getValueType();
1265 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1266 Hi = Lo.getValue(1);
1272 // Otherwise, emit a libcall.
1273 unsigned RuntimeCode = ; // SRL -> SRL_I64 etc.
1275 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), N,
1276 false/*lshr is unsigned*/, Hi);
1281 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1282 /// and the shift amount is a constant 'Amt'. Expand the operation.
1283 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1284 SDOperand &Lo, SDOperand &Hi) {
1285 // Expand the incoming operand to be shifted, so that we have its parts
1287 GetExpandedOp(N->getOperand(0), InL, InH);
1289 MVT::ValueType NVT = InL.getValueType();
1290 unsigned VTBits = MVT::getSizeInBits(N->getValueType(0));
1291 unsigned NVTBits = MVT::getSizeInBits(NVT);
1292 MVT::ValueType ShTy = N->getOperand(1).getValueType();
1294 if (N->getOpcode() == ISD::SHL) {
1296 Lo = Hi = DAG.getConstant(0, NVT);
1297 } else if (Amt > NVTBits) {
1298 Lo = DAG.getConstant(0, NVT);
1299 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1300 } else if (Amt == NVTBits) {
1301 Lo = DAG.getConstant(0, NVT);
1304 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1305 Hi = DAG.getNode(ISD::OR, NVT,
1306 DAG.getNode(ISD::SHL, NVT, InH,
1307 DAG.getConstant(Amt, ShTy)),
1308 DAG.getNode(ISD::SRL, NVT, InL,
1309 DAG.getConstant(NVTBits-Amt, ShTy)));
1314 if (N->getOpcode() == ISD::SRL) {
1316 Lo = DAG.getConstant(0, NVT);
1317 Hi = DAG.getConstant(0, NVT);
1318 } else if (Amt > NVTBits) {
1319 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1320 Hi = DAG.getConstant(0, NVT);
1321 } else if (Amt == NVTBits) {
1323 Hi = DAG.getConstant(0, NVT);
1325 Lo = DAG.getNode(ISD::OR, NVT,
1326 DAG.getNode(ISD::SRL, NVT, InL,
1327 DAG.getConstant(Amt, ShTy)),
1328 DAG.getNode(ISD::SHL, NVT, InH,
1329 DAG.getConstant(NVTBits-Amt, ShTy)));
1330 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1335 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1337 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1338 DAG.getConstant(NVTBits-1, ShTy));
1339 } else if (Amt > NVTBits) {
1340 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1341 DAG.getConstant(Amt-NVTBits, ShTy));
1342 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1343 DAG.getConstant(NVTBits-1, ShTy));
1344 } else if (Amt == NVTBits) {
1346 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1347 DAG.getConstant(NVTBits-1, ShTy));
1349 Lo = DAG.getNode(ISD::OR, NVT,
1350 DAG.getNode(ISD::SRL, NVT, InL,
1351 DAG.getConstant(Amt, ShTy)),
1352 DAG.getNode(ISD::SHL, NVT, InH,
1353 DAG.getConstant(NVTBits-Amt, ShTy)));
1354 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1358 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1359 /// this shift based on knowledge of the high bit of the shift amount. If we
1360 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1362 bool DAGTypeLegalizer::
1363 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
1364 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1365 unsigned NVTBits = MVT::getSizeInBits(NVT);
1366 assert(!(NVTBits & (NVTBits - 1)) &&
1367 "Expanded integer type size not a power of two!");
1369 uint64_t HighBitMask = NVTBits, KnownZero, KnownOne;
1370 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1372 // If we don't know anything about the high bit, exit.
1373 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1376 // Get the incoming operand to be shifted.
1378 GetExpandedOp(N->getOperand(0), InL, InH);
1379 SDOperand Amt = N->getOperand(1);
1381 // If we know that the high bit of the shift amount is one, then we can do
1382 // this as a couple of simple shifts.
1383 if (KnownOne & HighBitMask) {
1384 // Mask out the high bit, which we know is set.
1385 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
1386 DAG.getConstant(NVTBits-1, Amt.getValueType()));
1388 switch (N->getOpcode()) {
1389 default: assert(0 && "Unknown shift");
1391 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1392 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1395 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1396 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1399 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1400 DAG.getConstant(NVTBits-1, Amt.getValueType()));
1401 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1406 // If we know that the high bit of the shift amount is zero, then we can do
1407 // this as a couple of simple shifts.
1408 assert((KnownZero & HighBitMask) && "Bad mask computation above");
1411 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
1412 DAG.getConstant(NVTBits, Amt.getValueType()),
1415 switch (N->getOpcode()) {
1416 default: assert(0 && "Unknown shift");
1417 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1419 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1422 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1423 Hi = DAG.getNode(ISD::OR, NVT,
1424 DAG.getNode(Op1, NVT, InH, Amt),
1425 DAG.getNode(Op2, NVT, InL, Amt2));
1430 //===----------------------------------------------------------------------===//
1431 // Operand Promotion
1432 //===----------------------------------------------------------------------===//
1434 /// PromoteOperand - This method is called when the specified operand of the
1435 /// specified node is found to need promotion. At this point, all of the result
1436 /// types of the node are known to be legal, but other operands of the node may
1437 /// need promotion or expansion as well as the specified one.
1438 bool DAGTypeLegalizer::PromoteOperand(SDNode *N, unsigned OpNo) {
1439 DEBUG(cerr << "Promote node operand: "; N->dump(&DAG); cerr << "\n");
1441 switch (N->getOpcode()) {
1444 cerr << "PromoteOperand Op #" << OpNo << ": ";
1445 N->dump(&DAG); cerr << "\n";
1447 assert(0 && "Do not know how to promote this operator's operand!");
1450 case ISD::ANY_EXTEND: Res = PromoteOperand_ANY_EXTEND(N); break;
1451 case ISD::ZERO_EXTEND: Res = PromoteOperand_ZERO_EXTEND(N); break;
1452 case ISD::SIGN_EXTEND: Res = PromoteOperand_SIGN_EXTEND(N); break;
1453 case ISD::TRUNCATE: Res = PromoteOperand_TRUNCATE(N); break;
1454 case ISD::FP_EXTEND: Res = PromoteOperand_FP_EXTEND(N); break;
1455 case ISD::FP_ROUND: Res = PromoteOperand_FP_ROUND(N); break;
1456 case ISD::SINT_TO_FP:
1457 case ISD::UINT_TO_FP: Res = PromoteOperand_INT_TO_FP(N); break;
1459 case ISD::SELECT: Res = PromoteOperand_SELECT(N, OpNo); break;
1460 case ISD::BRCOND: Res = PromoteOperand_BRCOND(N, OpNo); break;
1461 case ISD::BR_CC: Res = PromoteOperand_BR_CC(N, OpNo); break;
1462 case ISD::SETCC: Res = PromoteOperand_SETCC(N, OpNo); break;
1464 case ISD::STORE: Res = PromoteOperand_STORE(cast<StoreSDNode>(N),
1468 case ISD::MEMMOVE: Res = HandleMemIntrinsic(N); break;
1471 // If the result is null, the sub-method took care of registering results etc.
1472 if (!Res.Val) return false;
1473 // If the result is N, the sub-method updated N in place.
1475 // Mark N as new and remark N and its operands. This allows us to correctly
1476 // revisit N if it needs another step of promotion and allows us to visit
1477 // any new operands to N.
1478 N->setNodeId(NewNode);
1483 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1484 "Invalid operand expansion");
1486 ReplaceLegalValueWith(SDOperand(N, 0), Res);
1490 SDOperand DAGTypeLegalizer::PromoteOperand_ANY_EXTEND(SDNode *N) {
1491 SDOperand Op = GetPromotedOp(N->getOperand(0));
1492 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
1495 SDOperand DAGTypeLegalizer::PromoteOperand_ZERO_EXTEND(SDNode *N) {
1496 SDOperand Op = GetPromotedOp(N->getOperand(0));
1497 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
1498 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
1501 SDOperand DAGTypeLegalizer::PromoteOperand_SIGN_EXTEND(SDNode *N) {
1502 SDOperand Op = GetPromotedOp(N->getOperand(0));
1503 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
1504 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
1505 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1508 SDOperand DAGTypeLegalizer::PromoteOperand_TRUNCATE(SDNode *N) {
1509 SDOperand Op = GetPromotedOp(N->getOperand(0));
1510 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
1513 SDOperand DAGTypeLegalizer::PromoteOperand_FP_EXTEND(SDNode *N) {
1514 SDOperand Op = GetPromotedOp(N->getOperand(0));
1515 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
1518 SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) {
1519 SDOperand Op = GetPromotedOp(N->getOperand(0));
1520 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op);
1523 SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {
1524 SDOperand In = GetPromotedOp(N->getOperand(0));
1525 MVT::ValueType OpVT = N->getOperand(0).getValueType();
1526 if (N->getOpcode() == ISD::UINT_TO_FP)
1527 In = DAG.getZeroExtendInReg(In, OpVT);
1529 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
1530 In, DAG.getValueType(OpVT));
1532 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
1535 SDOperand DAGTypeLegalizer::PromoteOperand_SELECT(SDNode *N, unsigned OpNo) {
1536 assert(OpNo == 0 && "Only know how to promote condition");
1537 SDOperand Cond = GetPromotedOp(N->getOperand(0)); // Promote the condition.
1539 // The top bits of the promoted condition are not necessarily zero, ensure
1540 // that the value is properly zero extended.
1541 if (!DAG.MaskedValueIsZero(Cond,
1542 MVT::getIntVTBitMask(Cond.getValueType())^1)) {
1543 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
1544 MarkNewNodes(Cond.Val);
1547 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1548 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
1552 SDOperand DAGTypeLegalizer::PromoteOperand_BRCOND(SDNode *N, unsigned OpNo) {
1553 assert(OpNo == 1 && "only know how to promote condition");
1554 SDOperand Cond = GetPromotedOp(N->getOperand(1)); // Promote the condition.
1556 // The top bits of the promoted condition are not necessarily zero, ensure
1557 // that the value is properly zero extended.
1558 if (!DAG.MaskedValueIsZero(Cond,
1559 MVT::getIntVTBitMask(Cond.getValueType())^1)) {
1560 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
1561 MarkNewNodes(Cond.Val);
1564 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1565 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
1569 SDOperand DAGTypeLegalizer::PromoteOperand_BR_CC(SDNode *N, unsigned OpNo) {
1570 assert(OpNo == 2 && "Don't know how to promote this operand");
1572 SDOperand LHS = N->getOperand(2);
1573 SDOperand RHS = N->getOperand(3);
1574 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1576 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1578 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
1579 N->getOperand(1), LHS, RHS, N->getOperand(4));
1582 SDOperand DAGTypeLegalizer::PromoteOperand_SETCC(SDNode *N, unsigned OpNo) {
1583 assert(OpNo == 0 && "Don't know how to promote this operand");
1585 SDOperand LHS = N->getOperand(0);
1586 SDOperand RHS = N->getOperand(1);
1587 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1589 // The CC (#2) is always legal.
1590 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
1593 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1594 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
1595 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
1596 ISD::CondCode CCCode) {
1597 MVT::ValueType VT = NewLHS.getValueType();
1599 // Get the promoted values.
1600 NewLHS = GetPromotedOp(NewLHS);
1601 NewRHS = GetPromotedOp(NewRHS);
1603 // If this is an FP compare, the operands have already been extended.
1604 if (!MVT::isInteger(NewLHS.getValueType()))
1607 // Otherwise, we have to insert explicit sign or zero extends. Note
1608 // that we could insert sign extends for ALL conditions, but zero extend
1609 // is cheaper on many machines (an AND instead of two shifts), so prefer
1612 default: assert(0 && "Unknown integer comparison!");
1619 // ALL of these operations will work if we either sign or zero extend
1620 // the operands (including the unsigned comparisons!). Zero extend is
1621 // usually a simpler/cheaper operation, so prefer it.
1622 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
1623 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
1629 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
1630 DAG.getValueType(VT));
1631 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
1632 DAG.getValueType(VT));
1637 SDOperand DAGTypeLegalizer::PromoteOperand_STORE(StoreSDNode *N, unsigned OpNo){
1638 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
1639 int SVOffset = N->getSrcValueOffset();
1640 unsigned Alignment = N->getAlignment();
1641 bool isVolatile = N->isVolatile();
1643 SDOperand Val = GetPromotedOp(N->getValue()); // Get promoted value.
1645 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
1647 // Truncate the value and store the result.
1648 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
1649 SVOffset, N->getStoredVT(),
1650 isVolatile, Alignment);
1654 //===----------------------------------------------------------------------===//
1655 // Operand Expansion
1656 //===----------------------------------------------------------------------===//
1658 /// ExpandOperand - This method is called when the specified operand of the
1659 /// specified node is found to need expansion. At this point, all of the result
1660 /// types of the node are known to be legal, but other operands of the node may
1661 /// need promotion or expansion as well as the specified one.
1662 bool DAGTypeLegalizer::ExpandOperand(SDNode *N, unsigned OpNo) {
1663 DEBUG(cerr << "Expand node operand: "; N->dump(&DAG); cerr << "\n");
1665 switch (N->getOpcode()) {
1668 cerr << "ExpandOperand Op #" << OpNo << ": ";
1669 N->dump(&DAG); cerr << "\n";
1671 assert(0 && "Do not know how to expand this operator's operand!");
1674 case ISD::TRUNCATE: Res = ExpandOperand_TRUNCATE(N); break;
1675 case ISD::BIT_CONVERT: Res = ExpandOperand_BIT_CONVERT(N); break;
1677 case ISD::SINT_TO_FP:
1678 Res = ExpandOperand_SINT_TO_FP(N->getOperand(0), N->getValueType(0));
1680 case ISD::UINT_TO_FP:
1681 Res = ExpandOperand_UINT_TO_FP(N->getOperand(0), N->getValueType(0));
1683 case ISD::EXTRACT_ELEMENT: Res = ExpandOperand_EXTRACT_ELEMENT(N); break;
1684 case ISD::SETCC: Res = ExpandOperand_SETCC(N); break;
1686 case ISD::STORE: Res = ExpandOperand_STORE(cast<StoreSDNode>(N), OpNo); break;
1689 case ISD::MEMMOVE: Res = HandleMemIntrinsic(N); break;
1692 // If the result is null, the sub-method took care of registering results etc.
1693 if (!Res.Val) return false;
1694 // If the result is N, the sub-method updated N in place. Check to see if any
1695 // operands are new, and if so, mark them.
1697 // Mark N as new and remark N and its operands. This allows us to correctly
1698 // revisit N if it needs another step of promotion and allows us to visit
1699 // any new operands to N.
1700 N->setNodeId(NewNode);
1705 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1706 "Invalid operand expansion");
1708 ReplaceLegalValueWith(SDOperand(N, 0), Res);
1712 SDOperand DAGTypeLegalizer::ExpandOperand_TRUNCATE(SDNode *N) {
1714 GetExpandedOp(N->getOperand(0), InL, InH);
1715 // Just truncate the low part of the source.
1716 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
1719 SDOperand DAGTypeLegalizer::ExpandOperand_BIT_CONVERT(SDNode *N) {
1720 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1723 SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source,
1724 MVT::ValueType DestTy) {
1725 // We know the destination is legal, but that the input needs to be expanded.
1726 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
1728 // Check to see if the target has a custom way to lower this. If so, use it.
1729 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
1730 default: assert(0 && "This action not implemented for this operation!");
1731 case TargetLowering::Legal:
1732 case TargetLowering::Expand:
1733 break; // This case is handled below.
1734 case TargetLowering::Custom:
1735 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
1737 if (NV.Val) return NV;
1738 break; // The target lowered this.
1742 if (DestTy == MVT::f32)
1743 LC = RTLIB::SINTTOFP_I64_F32;
1745 assert(DestTy == MVT::f64 && "Unknown fp value type!");
1746 LC = RTLIB::SINTTOFP_I64_F64;
1749 assert(0 && "FIXME: no libcalls yet!");
1752 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
1753 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
1754 SDOperand UnusedHiPart;
1755 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, true, UnusedHiPart);
1759 SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source,
1760 MVT::ValueType DestTy) {
1761 // We know the destination is legal, but that the input needs to be expanded.
1762 assert(getTypeAction(Source.getValueType()) == Expand &&
1763 "This is not an expansion!");
1764 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
1766 // If this is unsigned, and not supported, first perform the conversion to
1767 // signed, then adjust the result if the sign bit is set.
1768 SDOperand SignedConv = ExpandOperand_SINT_TO_FP(Source, DestTy);
1770 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
1771 // incoming integer is set. To handle this, we dynamically test to see if
1772 // it is set, and, if so, add a fudge factor.
1774 GetExpandedOp(Source, Lo, Hi);
1776 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
1777 DAG.getConstant(0, Hi.getValueType()),
1779 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
1780 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
1781 SignSet, Four, Zero);
1782 uint64_t FF = 0x5f800000ULL;
1783 if (TLI.isLittleEndian()) FF <<= 32;
1784 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
1786 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
1787 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
1788 SDOperand FudgeInReg;
1789 if (DestTy == MVT::f32)
1790 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
1791 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
1792 // FIXME: Avoid the extend by construction the right constantpool?
1793 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
1794 CPIdx, NULL, 0, MVT::f32);
1796 assert(0 && "Unexpected conversion");
1798 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
1801 SDOperand DAGTypeLegalizer::ExpandOperand_EXTRACT_ELEMENT(SDNode *N) {
1803 GetExpandedOp(N->getOperand(0), Lo, Hi);
1804 return cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
1807 SDOperand DAGTypeLegalizer::ExpandOperand_SETCC(SDNode *N) {
1808 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1809 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1810 ExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1812 // If ExpandSetCCOperands returned a scalar, use it.
1813 if (NewRHS.Val == 0) return NewLHS;
1815 // Otherwise, update N to have the operands specified.
1816 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1817 DAG.getCondCode(CCCode));
1820 /// ExpandSetCCOperands - Expand the operands of a comparison. This code is
1821 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
1822 void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
1823 ISD::CondCode &CCCode) {
1824 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1825 GetExpandedOp(NewLHS, LHSLo, LHSHi);
1826 GetExpandedOp(NewRHS, RHSLo, RHSHi);
1828 MVT::ValueType VT = NewLHS.getValueType();
1829 if (VT == MVT::f32 || VT == MVT::f64) {
1830 assert(0 && "FIXME: softfp not implemented yet! should be promote not exp");
1833 if (VT == MVT::ppcf128) {
1834 // FIXME: This generated code sucks. We want to generate
1835 // FCMP crN, hi1, hi2
1837 // FCMP crN, lo1, lo2
1838 // The following can be improved, but not that much.
1839 SDOperand Tmp1, Tmp2, Tmp3;
1840 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
1841 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
1842 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
1843 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
1844 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
1845 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
1846 NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
1847 NewRHS = SDOperand(); // LHS is the result, not a compare.
1852 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1854 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1855 if (RHSCST->isAllOnesValue()) {
1856 // Equality comparison to -1.
1857 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1862 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1863 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1864 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1865 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1869 // If this is a comparison of the sign bit, just look at the top part.
1871 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1872 if ((CCCode == ISD::SETLT && CST->getValue() == 0) || // X < 0
1873 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1879 // FIXME: This generated code sucks.
1880 ISD::CondCode LowCC;
1882 default: assert(0 && "Unknown integer setcc!");
1884 case ISD::SETULT: LowCC = ISD::SETULT; break;
1886 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1888 case ISD::SETULE: LowCC = ISD::SETULE; break;
1890 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1893 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1894 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1895 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1897 // NOTE: on targets without efficient SELECT of bools, we can always use
1898 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1899 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1900 SDOperand Tmp1, Tmp2;
1901 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
1902 false, DagCombineInfo);
1904 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
1905 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
1906 CCCode, false, DagCombineInfo);
1908 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,
1909 DAG.getCondCode(CCCode));
1911 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
1912 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
1913 if ((Tmp1C && Tmp1C->getValue() == 0) ||
1914 (Tmp2C && Tmp2C->getValue() == 0 &&
1915 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1916 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1917 (Tmp2C && Tmp2C->getValue() == 1 &&
1918 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1919 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1920 // low part is known false, returns high part.
1921 // For LE / GE, if high part is known false, ignore the low part.
1922 // For LT / GT, if high part is known true, ignore the low part.
1924 NewRHS = SDOperand();
1928 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
1929 ISD::SETEQ, false, DagCombineInfo);
1931 NewLHS = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
1932 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1933 NewLHS, Tmp1, Tmp2);
1934 NewRHS = SDOperand();
1937 SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
1938 assert(OpNo == 1 && "Can only expand the stored value so far");
1939 assert(!N->isTruncatingStore() && "Can't expand truncstore!");
1941 unsigned IncrementSize = 0;
1944 // If this is a vector type, then we have to calculate the increment as
1945 // the product of the element size in bytes, and the number of elements
1946 // in the high half of the vector.
1947 if (MVT::isVector(N->getValue().getValueType())) {
1948 assert(0 && "Vectors not supported yet");
1950 SDNode *InVal = ST->getValue().Val;
1951 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1952 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1954 // Figure out if there is a simple type corresponding to this Vector
1955 // type. If so, convert to the vector type.
1956 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1957 if (TLI.isTypeLegal(TVT)) {
1958 // Turn this into a normal store of the vector type.
1959 Tmp3 = LegalizeOp(Node->getOperand(1));
1960 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1961 SVOffset, isVolatile, Alignment);
1962 Result = LegalizeOp(Result);
1964 } else if (NumElems == 1) {
1965 // Turn this into a normal store of the scalar type.
1966 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
1967 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1968 SVOffset, isVolatile, Alignment);
1969 // The scalarized value type may not be legal, e.g. it might require
1970 // promotion or expansion. Relegalize the scalar store.
1971 return LegalizeOp(Result);
1973 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1974 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1978 GetExpandedOp(N->getValue(), Lo, Hi);
1979 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
1981 if (!TLI.isLittleEndian())
1985 SDOperand Chain = N->getChain();
1986 SDOperand Ptr = N->getBasePtr();
1987 int SVOffset = N->getSrcValueOffset();
1988 unsigned Alignment = N->getAlignment();
1989 bool isVolatile = N->isVolatile();
1991 Lo = DAG.getStore(Chain, Lo, Ptr, N->getSrcValue(),
1992 SVOffset, isVolatile, Alignment);
1994 assert(Hi.Val && "FIXME: int <-> float should be handled with promote!");
1996 if (Hi.Val == NULL) {
1997 // Must be int <-> float one-to-one expansion.
2002 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2003 getIntPtrConstant(IncrementSize));
2004 assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!");
2005 Hi = DAG.getStore(Chain, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
2006 isVolatile, MinAlign(Alignment, IncrementSize));
2007 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2011 //===----------------------------------------------------------------------===//
2013 //===----------------------------------------------------------------------===//
2015 /// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
2016 /// only uses types natively supported by the target.
2018 /// Note that this is an involved process that may invalidate pointers into
2020 void SelectionDAG::LegalizeTypes() {
2021 DAGTypeLegalizer(*this).run();