1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/DebugInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/LLVMContext.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetMachine.h"
37 //===----------------------------------------------------------------------===//
38 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
39 /// hacks on it until the target machine can handle it. This involves
40 /// eliminating value sizes the machine cannot handle (promoting small sizes to
41 /// large sizes or splitting up large values into small values) as well as
42 /// eliminating operations the machine cannot handle.
44 /// This code also does a small amount of optimization and recognition of idioms
45 /// as part of its processing. For example, if a target does not support a
46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
50 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
51 const TargetMachine &TM;
52 const TargetLowering &TLI;
55 /// LegalizePosition - The iterator for walking through the node list.
56 SelectionDAG::allnodes_iterator LegalizePosition;
58 /// LegalizedNodes - The set of nodes which have already been legalized.
59 SmallPtrSet<SDNode *, 16> LegalizedNodes;
61 // Libcall insertion helpers.
64 explicit SelectionDAGLegalize(SelectionDAG &DAG);
69 /// LegalizeOp - Legalizes the given operation.
70 void LegalizeOp(SDNode *Node);
72 SDValue OptimizeFloatStore(StoreSDNode *ST);
74 void LegalizeLoadOps(SDNode *Node);
75 void LegalizeStoreOps(SDNode *Node);
77 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
78 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
79 /// is necessary to spill the vector being inserted into to memory, perform
80 /// the insert there, and then read the result back.
81 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
82 SDValue Idx, DebugLoc dl);
83 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
84 SDValue Idx, DebugLoc dl);
86 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
87 /// performs the same shuffe in terms of order or result bytes, but on a type
88 /// whose vector element type is narrower than the original shuffle type.
89 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
90 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
91 SDValue N1, SDValue N2,
92 ArrayRef<int> Mask) const;
94 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
97 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
98 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
99 unsigned NumOps, bool isSigned, DebugLoc dl);
101 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
102 SDNode *Node, bool isSigned);
103 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
104 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
105 RTLIB::Libcall Call_F128,
106 RTLIB::Libcall Call_PPCF128);
107 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
108 RTLIB::Libcall Call_I8,
109 RTLIB::Libcall Call_I16,
110 RTLIB::Libcall Call_I32,
111 RTLIB::Libcall Call_I64,
112 RTLIB::Libcall Call_I128);
113 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
114 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
116 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
117 SDValue ExpandBUILD_VECTOR(SDNode *Node);
118 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
119 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
120 SmallVectorImpl<SDValue> &Results);
121 SDValue ExpandFCOPYSIGN(SDNode *Node);
122 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
124 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
126 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
129 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
130 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
132 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
133 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
134 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
136 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
138 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
140 void ExpandNode(SDNode *Node);
141 void PromoteNode(SDNode *Node);
143 void ForgetNode(SDNode *N) {
144 LegalizedNodes.erase(N);
145 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
150 // DAGUpdateListener implementation.
151 virtual void NodeDeleted(SDNode *N, SDNode *E) {
154 virtual void NodeUpdated(SDNode *N) {}
156 // Node replacement helpers
157 void ReplacedNode(SDNode *N) {
158 if (N->use_empty()) {
159 DAG.RemoveDeadNode(N);
164 void ReplaceNode(SDNode *Old, SDNode *New) {
165 DAG.ReplaceAllUsesWith(Old, New);
168 void ReplaceNode(SDValue Old, SDValue New) {
169 DAG.ReplaceAllUsesWith(Old, New);
170 ReplacedNode(Old.getNode());
172 void ReplaceNode(SDNode *Old, const SDValue *New) {
173 DAG.ReplaceAllUsesWith(Old, New);
179 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
180 /// performs the same shuffe in terms of order or result bytes, but on a type
181 /// whose vector element type is narrower than the original shuffle type.
182 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
184 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
185 SDValue N1, SDValue N2,
186 ArrayRef<int> Mask) const {
187 unsigned NumMaskElts = VT.getVectorNumElements();
188 unsigned NumDestElts = NVT.getVectorNumElements();
189 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
191 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
193 if (NumEltsGrowth == 1)
194 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
196 SmallVector<int, 8> NewMask;
197 for (unsigned i = 0; i != NumMaskElts; ++i) {
199 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
201 NewMask.push_back(-1);
203 NewMask.push_back(Idx * NumEltsGrowth + j);
206 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
207 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
208 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
211 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
212 : SelectionDAG::DAGUpdateListener(dag),
213 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
217 void SelectionDAGLegalize::LegalizeDAG() {
218 DAG.AssignTopologicalOrder();
220 // Visit all the nodes. We start in topological order, so that we see
221 // nodes with their original operands intact. Legalization can produce
222 // new nodes which may themselves need to be legalized. Iterate until all
223 // nodes have been legalized.
225 bool AnyLegalized = false;
226 for (LegalizePosition = DAG.allnodes_end();
227 LegalizePosition != DAG.allnodes_begin(); ) {
230 SDNode *N = LegalizePosition;
231 if (LegalizedNodes.insert(N)) {
241 // Remove dead nodes now.
242 DAG.RemoveDeadNodes();
245 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
246 /// a load from the constant pool.
248 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
250 DebugLoc dl = CFP->getDebugLoc();
252 // If a FP immediate is precise when represented as a float and if the
253 // target can do an extending load from float to double, we put it into
254 // the constant pool as a float, even if it's is statically typed as a
255 // double. This shrinks FP constants and canonicalizes them for targets where
256 // an FP extending load is the same cost as a normal load (such as on the x87
257 // fp stack or PPC FP unit).
258 EVT VT = CFP->getValueType(0);
259 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
261 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
262 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
263 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
268 while (SVT != MVT::f32) {
269 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
270 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
271 // Only do this if the target has a native EXTLOAD instruction from
273 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
274 TLI.ShouldShrinkFPConstant(OrigVT)) {
275 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
276 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
282 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
283 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
286 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
288 CPIdx, MachinePointerInfo::getConstantPool(),
289 VT, false, false, Alignment);
293 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
294 MachinePointerInfo::getConstantPool(), false, false, false,
299 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
300 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
301 const TargetLowering &TLI,
302 SelectionDAGLegalize *DAGLegalize) {
303 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
304 "unaligned indexed stores not implemented!");
305 SDValue Chain = ST->getChain();
306 SDValue Ptr = ST->getBasePtr();
307 SDValue Val = ST->getValue();
308 EVT VT = Val.getValueType();
309 int Alignment = ST->getAlignment();
310 DebugLoc dl = ST->getDebugLoc();
311 if (ST->getMemoryVT().isFloatingPoint() ||
312 ST->getMemoryVT().isVector()) {
313 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
314 if (TLI.isTypeLegal(intVT)) {
315 // Expand to a bitconvert of the value to the integer type of the
316 // same size, then a (misaligned) int store.
317 // FIXME: Does not handle truncating floating point stores!
318 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
319 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
320 ST->isVolatile(), ST->isNonTemporal(), Alignment);
321 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
324 // Do a (aligned) store to a stack slot, then copy from the stack slot
325 // to the final destination using (unaligned) integer loads and stores.
326 EVT StoredVT = ST->getMemoryVT();
328 TLI.getRegisterType(*DAG.getContext(),
329 EVT::getIntegerVT(*DAG.getContext(),
330 StoredVT.getSizeInBits()));
331 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
332 unsigned RegBytes = RegVT.getSizeInBits() / 8;
333 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
335 // Make sure the stack slot is also aligned for the register type.
336 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
338 // Perform the original store, only redirected to the stack slot.
339 SDValue Store = DAG.getTruncStore(Chain, dl,
340 Val, StackPtr, MachinePointerInfo(),
341 StoredVT, false, false, 0);
342 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
343 SmallVector<SDValue, 8> Stores;
346 // Do all but one copies using the full register width.
347 for (unsigned i = 1; i < NumRegs; i++) {
348 // Load one integer register's worth from the stack slot.
349 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
350 MachinePointerInfo(),
351 false, false, false, 0);
352 // Store it to the final location. Remember the store.
353 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
354 ST->getPointerInfo().getWithOffset(Offset),
355 ST->isVolatile(), ST->isNonTemporal(),
356 MinAlign(ST->getAlignment(), Offset)));
357 // Increment the pointers.
359 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
361 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
364 // The last store may be partial. Do a truncating store. On big-endian
365 // machines this requires an extending load from the stack slot to ensure
366 // that the bits are in the right place.
367 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
368 8 * (StoredBytes - Offset));
370 // Load from the stack slot.
371 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
372 MachinePointerInfo(),
373 MemVT, false, false, 0);
375 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
377 .getWithOffset(Offset),
378 MemVT, ST->isVolatile(),
380 MinAlign(ST->getAlignment(), Offset)));
381 // The order of the stores doesn't matter - say it with a TokenFactor.
383 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
385 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
388 assert(ST->getMemoryVT().isInteger() &&
389 !ST->getMemoryVT().isVector() &&
390 "Unaligned store of unknown type.");
391 // Get the half-size VT
392 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
393 int NumBits = NewStoredVT.getSizeInBits();
394 int IncrementSize = NumBits / 8;
396 // Divide the stored value in two parts.
397 SDValue ShiftAmount = DAG.getConstant(NumBits,
398 TLI.getShiftAmountTy(Val.getValueType()));
400 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
402 // Store the two parts
403 SDValue Store1, Store2;
404 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
405 ST->getPointerInfo(), NewStoredVT,
406 ST->isVolatile(), ST->isNonTemporal(), Alignment);
407 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
408 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
409 Alignment = MinAlign(Alignment, IncrementSize);
410 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
411 ST->getPointerInfo().getWithOffset(IncrementSize),
412 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
416 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
417 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
420 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
422 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
423 const TargetLowering &TLI,
424 SDValue &ValResult, SDValue &ChainResult) {
425 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
426 "unaligned indexed loads not implemented!");
427 SDValue Chain = LD->getChain();
428 SDValue Ptr = LD->getBasePtr();
429 EVT VT = LD->getValueType(0);
430 EVT LoadedVT = LD->getMemoryVT();
431 DebugLoc dl = LD->getDebugLoc();
432 if (VT.isFloatingPoint() || VT.isVector()) {
433 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
434 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
435 // Expand to a (misaligned) integer load of the same size,
436 // then bitconvert to floating point or vector.
437 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
440 LD->isInvariant(), LD->getAlignment());
441 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
443 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
444 ISD::ANY_EXTEND, dl, VT, Result);
451 // Copy the value to a (aligned) stack slot using (unaligned) integer
452 // loads and stores, then do a (aligned) load from the stack slot.
453 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
454 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
455 unsigned RegBytes = RegVT.getSizeInBits() / 8;
456 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
458 // Make sure the stack slot is also aligned for the register type.
459 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
461 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
462 SmallVector<SDValue, 8> Stores;
463 SDValue StackPtr = StackBase;
466 // Do all but one copies using the full register width.
467 for (unsigned i = 1; i < NumRegs; i++) {
468 // Load one integer register's worth from the original location.
469 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
470 LD->getPointerInfo().getWithOffset(Offset),
471 LD->isVolatile(), LD->isNonTemporal(),
473 MinAlign(LD->getAlignment(), Offset));
474 // Follow the load with a store to the stack slot. Remember the store.
475 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
476 MachinePointerInfo(), false, false, 0));
477 // Increment the pointers.
479 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
480 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
484 // The last copy may be partial. Do an extending load.
485 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
486 8 * (LoadedBytes - Offset));
487 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
488 LD->getPointerInfo().getWithOffset(Offset),
489 MemVT, LD->isVolatile(),
491 MinAlign(LD->getAlignment(), Offset));
492 // Follow the load with a store to the stack slot. Remember the store.
493 // On big-endian machines this requires a truncating store to ensure
494 // that the bits end up in the right place.
495 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
496 MachinePointerInfo(), MemVT,
499 // The order of the stores doesn't matter - say it with a TokenFactor.
500 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
503 // Finally, perform the original load only redirected to the stack slot.
504 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
505 MachinePointerInfo(), LoadedVT, false, false, 0);
507 // Callers expect a MERGE_VALUES node.
512 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
513 "Unaligned load of unsupported type.");
515 // Compute the new VT that is half the size of the old one. This is an
517 unsigned NumBits = LoadedVT.getSizeInBits();
519 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
522 unsigned Alignment = LD->getAlignment();
523 unsigned IncrementSize = NumBits / 8;
524 ISD::LoadExtType HiExtType = LD->getExtensionType();
526 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
527 if (HiExtType == ISD::NON_EXTLOAD)
528 HiExtType = ISD::ZEXTLOAD;
530 // Load the value in two parts
532 if (TLI.isLittleEndian()) {
533 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
534 NewLoadedVT, LD->isVolatile(),
535 LD->isNonTemporal(), Alignment);
536 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
537 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
538 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
539 LD->getPointerInfo().getWithOffset(IncrementSize),
540 NewLoadedVT, LD->isVolatile(),
541 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
543 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
544 NewLoadedVT, LD->isVolatile(),
545 LD->isNonTemporal(), Alignment);
546 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
547 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
548 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
549 LD->getPointerInfo().getWithOffset(IncrementSize),
550 NewLoadedVT, LD->isVolatile(),
551 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
554 // aggregate the two parts
555 SDValue ShiftAmount = DAG.getConstant(NumBits,
556 TLI.getShiftAmountTy(Hi.getValueType()));
557 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
558 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
560 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
567 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
568 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
569 /// is necessary to spill the vector being inserted into to memory, perform
570 /// the insert there, and then read the result back.
571 SDValue SelectionDAGLegalize::
572 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
578 // If the target doesn't support this, we have to spill the input vector
579 // to a temporary stack slot, update the element, then reload it. This is
580 // badness. We could also load the value into a vector register (either
581 // with a "move to register" or "extload into register" instruction, then
582 // permute it into place, if the idx is a constant and if the idx is
583 // supported by the target.
584 EVT VT = Tmp1.getValueType();
585 EVT EltVT = VT.getVectorElementType();
586 EVT IdxVT = Tmp3.getValueType();
587 EVT PtrVT = TLI.getPointerTy();
588 SDValue StackPtr = DAG.CreateStackTemporary(VT);
590 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
593 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
594 MachinePointerInfo::getFixedStack(SPFI),
597 // Truncate or zero extend offset to target pointer type.
598 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
599 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
600 // Add the offset to the index.
601 unsigned EltSize = EltVT.getSizeInBits()/8;
602 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
603 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
604 // Store the scalar value.
605 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
607 // Load the updated vector.
608 return DAG.getLoad(VT, dl, Ch, StackPtr,
609 MachinePointerInfo::getFixedStack(SPFI), false, false,
614 SDValue SelectionDAGLegalize::
615 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
616 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
617 // SCALAR_TO_VECTOR requires that the type of the value being inserted
618 // match the element type of the vector being created, except for
619 // integers in which case the inserted value can be over width.
620 EVT EltVT = Vec.getValueType().getVectorElementType();
621 if (Val.getValueType() == EltVT ||
622 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
623 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
624 Vec.getValueType(), Val);
626 unsigned NumElts = Vec.getValueType().getVectorNumElements();
627 // We generate a shuffle of InVec and ScVec, so the shuffle mask
628 // should be 0,1,2,3,4,5... with the appropriate element replaced with
630 SmallVector<int, 8> ShufOps;
631 for (unsigned i = 0; i != NumElts; ++i)
632 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
634 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
638 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
641 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
642 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
643 // FIXME: We shouldn't do this for TargetConstantFP's.
644 // FIXME: move this to the DAG Combiner! Note that we can't regress due
645 // to phase ordering between legalized code and the dag combiner. This
646 // probably means that we need to integrate dag combiner and legalizer
648 // We generally can't do this one for long doubles.
649 SDValue Chain = ST->getChain();
650 SDValue Ptr = ST->getBasePtr();
651 unsigned Alignment = ST->getAlignment();
652 bool isVolatile = ST->isVolatile();
653 bool isNonTemporal = ST->isNonTemporal();
654 DebugLoc dl = ST->getDebugLoc();
655 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
656 if (CFP->getValueType(0) == MVT::f32 &&
657 TLI.isTypeLegal(MVT::i32)) {
658 SDValue Con = DAG.getConstant(CFP->getValueAPF().
659 bitcastToAPInt().zextOrTrunc(32),
661 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
662 isVolatile, isNonTemporal, Alignment);
665 if (CFP->getValueType(0) == MVT::f64) {
666 // If this target supports 64-bit registers, do a single 64-bit store.
667 if (TLI.isTypeLegal(MVT::i64)) {
668 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
669 zextOrTrunc(64), MVT::i64);
670 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
671 isVolatile, isNonTemporal, Alignment);
674 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
675 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
676 // stores. If the target supports neither 32- nor 64-bits, this
677 // xform is certainly not worth it.
678 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
679 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
680 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
681 if (TLI.isBigEndian()) std::swap(Lo, Hi);
683 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
684 isNonTemporal, Alignment);
685 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
686 DAG.getIntPtrConstant(4));
687 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
688 ST->getPointerInfo().getWithOffset(4),
689 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
691 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
695 return SDValue(0, 0);
698 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
699 StoreSDNode *ST = cast<StoreSDNode>(Node);
700 SDValue Chain = ST->getChain();
701 SDValue Ptr = ST->getBasePtr();
702 DebugLoc dl = Node->getDebugLoc();
704 unsigned Alignment = ST->getAlignment();
705 bool isVolatile = ST->isVolatile();
706 bool isNonTemporal = ST->isNonTemporal();
708 if (!ST->isTruncatingStore()) {
709 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
710 ReplaceNode(ST, OptStore);
715 SDValue Value = ST->getValue();
716 MVT VT = Value.getSimpleValueType();
717 switch (TLI.getOperationAction(ISD::STORE, VT)) {
718 default: llvm_unreachable("This action is not supported yet!");
719 case TargetLowering::Legal:
720 // If this is an unaligned store and the target doesn't support it,
722 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
723 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
724 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
725 if (ST->getAlignment() < ABIAlignment)
726 ExpandUnalignedStore(cast<StoreSDNode>(Node),
730 case TargetLowering::Custom: {
731 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
733 ReplaceNode(SDValue(Node, 0), Res);
736 case TargetLowering::Promote: {
737 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
738 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
739 "Can only promote stores to same size type");
740 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
742 DAG.getStore(Chain, dl, Value, Ptr,
743 ST->getPointerInfo(), isVolatile,
744 isNonTemporal, Alignment);
745 ReplaceNode(SDValue(Node, 0), Result);
752 SDValue Value = ST->getValue();
754 EVT StVT = ST->getMemoryVT();
755 unsigned StWidth = StVT.getSizeInBits();
757 if (StWidth != StVT.getStoreSizeInBits()) {
758 // Promote to a byte-sized store with upper bits zero if not
759 // storing an integral number of bytes. For example, promote
760 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
761 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
762 StVT.getStoreSizeInBits());
763 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
765 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
766 NVT, isVolatile, isNonTemporal, Alignment);
767 ReplaceNode(SDValue(Node, 0), Result);
768 } else if (StWidth & (StWidth - 1)) {
769 // If not storing a power-of-2 number of bits, expand as two stores.
770 assert(!StVT.isVector() && "Unsupported truncstore!");
771 unsigned RoundWidth = 1 << Log2_32(StWidth);
772 assert(RoundWidth < StWidth);
773 unsigned ExtraWidth = StWidth - RoundWidth;
774 assert(ExtraWidth < RoundWidth);
775 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
776 "Store size not an integral number of bytes!");
777 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
778 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
780 unsigned IncrementSize;
782 if (TLI.isLittleEndian()) {
783 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
784 // Store the bottom RoundWidth bits.
785 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
787 isVolatile, isNonTemporal, Alignment);
789 // Store the remaining ExtraWidth bits.
790 IncrementSize = RoundWidth / 8;
791 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
792 DAG.getIntPtrConstant(IncrementSize));
793 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
794 DAG.getConstant(RoundWidth,
795 TLI.getShiftAmountTy(Value.getValueType())));
796 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
797 ST->getPointerInfo().getWithOffset(IncrementSize),
798 ExtraVT, isVolatile, isNonTemporal,
799 MinAlign(Alignment, IncrementSize));
801 // Big endian - avoid unaligned stores.
802 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
803 // Store the top RoundWidth bits.
804 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
805 DAG.getConstant(ExtraWidth,
806 TLI.getShiftAmountTy(Value.getValueType())));
807 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
808 RoundVT, isVolatile, isNonTemporal, Alignment);
810 // Store the remaining ExtraWidth bits.
811 IncrementSize = RoundWidth / 8;
812 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
813 DAG.getIntPtrConstant(IncrementSize));
814 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
815 ST->getPointerInfo().getWithOffset(IncrementSize),
816 ExtraVT, isVolatile, isNonTemporal,
817 MinAlign(Alignment, IncrementSize));
820 // The order of the stores doesn't matter.
821 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
822 ReplaceNode(SDValue(Node, 0), Result);
824 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
825 StVT.getSimpleVT())) {
826 default: llvm_unreachable("This action is not supported yet!");
827 case TargetLowering::Legal:
828 // If this is an unaligned store and the target doesn't support it,
830 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
831 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
832 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
833 if (ST->getAlignment() < ABIAlignment)
834 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
837 case TargetLowering::Custom: {
838 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
840 ReplaceNode(SDValue(Node, 0), Res);
843 case TargetLowering::Expand:
844 assert(!StVT.isVector() &&
845 "Vector Stores are handled in LegalizeVectorOps");
847 // TRUNCSTORE:i16 i32 -> STORE i16
848 assert(TLI.isTypeLegal(StVT) &&
849 "Do not know how to expand this store!");
850 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
852 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
853 isVolatile, isNonTemporal, Alignment);
854 ReplaceNode(SDValue(Node, 0), Result);
861 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
862 LoadSDNode *LD = cast<LoadSDNode>(Node);
863 SDValue Chain = LD->getChain(); // The chain.
864 SDValue Ptr = LD->getBasePtr(); // The base pointer.
865 SDValue Value; // The value returned by the load op.
866 DebugLoc dl = Node->getDebugLoc();
868 ISD::LoadExtType ExtType = LD->getExtensionType();
869 if (ExtType == ISD::NON_EXTLOAD) {
870 MVT VT = Node->getSimpleValueType(0);
871 SDValue RVal = SDValue(Node, 0);
872 SDValue RChain = SDValue(Node, 1);
874 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
875 default: llvm_unreachable("This action is not supported yet!");
876 case TargetLowering::Legal:
877 // If this is an unaligned load and the target doesn't support it,
879 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
880 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
881 unsigned ABIAlignment =
882 TLI.getDataLayout()->getABITypeAlignment(Ty);
883 if (LD->getAlignment() < ABIAlignment){
884 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
888 case TargetLowering::Custom: {
889 SDValue Res = TLI.LowerOperation(RVal, DAG);
892 RChain = Res.getValue(1);
896 case TargetLowering::Promote: {
897 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
898 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
899 "Can only promote loads to same size type");
901 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
902 LD->isVolatile(), LD->isNonTemporal(),
903 LD->isInvariant(), LD->getAlignment());
904 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
905 RChain = Res.getValue(1);
909 if (RChain.getNode() != Node) {
910 assert(RVal.getNode() != Node && "Load must be completely replaced");
911 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
912 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
918 EVT SrcVT = LD->getMemoryVT();
919 unsigned SrcWidth = SrcVT.getSizeInBits();
920 unsigned Alignment = LD->getAlignment();
921 bool isVolatile = LD->isVolatile();
922 bool isNonTemporal = LD->isNonTemporal();
924 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
925 // Some targets pretend to have an i1 loading operation, and actually
926 // load an i8. This trick is correct for ZEXTLOAD because the top 7
927 // bits are guaranteed to be zero; it helps the optimizers understand
928 // that these bits are zero. It is also useful for EXTLOAD, since it
929 // tells the optimizers that those bits are undefined. It would be
930 // nice to have an effective generic way of getting these benefits...
931 // Until such a way is found, don't insist on promoting i1 here.
933 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
934 // Promote to a byte-sized load if not loading an integral number of
935 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
936 unsigned NewWidth = SrcVT.getStoreSizeInBits();
937 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
940 // The extra bits are guaranteed to be zero, since we stored them that
941 // way. A zext load from NVT thus automatically gives zext from SrcVT.
943 ISD::LoadExtType NewExtType =
944 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
947 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
948 Chain, Ptr, LD->getPointerInfo(),
949 NVT, isVolatile, isNonTemporal, Alignment);
951 Ch = Result.getValue(1); // The chain.
953 if (ExtType == ISD::SEXTLOAD)
954 // Having the top bits zero doesn't help when sign extending.
955 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
956 Result.getValueType(),
957 Result, DAG.getValueType(SrcVT));
958 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
959 // All the top bits are guaranteed to be zero - inform the optimizers.
960 Result = DAG.getNode(ISD::AssertZext, dl,
961 Result.getValueType(), Result,
962 DAG.getValueType(SrcVT));
966 } else if (SrcWidth & (SrcWidth - 1)) {
967 // If not loading a power-of-2 number of bits, expand as two loads.
968 assert(!SrcVT.isVector() && "Unsupported extload!");
969 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
970 assert(RoundWidth < SrcWidth);
971 unsigned ExtraWidth = SrcWidth - RoundWidth;
972 assert(ExtraWidth < RoundWidth);
973 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
974 "Load size not an integral number of bytes!");
975 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
976 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
978 unsigned IncrementSize;
980 if (TLI.isLittleEndian()) {
981 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
982 // Load the bottom RoundWidth bits.
983 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
985 LD->getPointerInfo(), RoundVT, isVolatile,
986 isNonTemporal, Alignment);
988 // Load the remaining ExtraWidth bits.
989 IncrementSize = RoundWidth / 8;
990 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
991 DAG.getIntPtrConstant(IncrementSize));
992 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
993 LD->getPointerInfo().getWithOffset(IncrementSize),
994 ExtraVT, isVolatile, isNonTemporal,
995 MinAlign(Alignment, IncrementSize));
997 // Build a factor node to remember that this load is independent of
999 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1002 // Move the top bits to the right place.
1003 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1004 DAG.getConstant(RoundWidth,
1005 TLI.getShiftAmountTy(Hi.getValueType())));
1007 // Join the hi and lo parts.
1008 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1010 // Big endian - avoid unaligned loads.
1011 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1012 // Load the top RoundWidth bits.
1013 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1014 LD->getPointerInfo(), RoundVT, isVolatile,
1015 isNonTemporal, Alignment);
1017 // Load the remaining ExtraWidth bits.
1018 IncrementSize = RoundWidth / 8;
1019 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1020 DAG.getIntPtrConstant(IncrementSize));
1021 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1022 dl, Node->getValueType(0), Chain, Ptr,
1023 LD->getPointerInfo().getWithOffset(IncrementSize),
1024 ExtraVT, isVolatile, isNonTemporal,
1025 MinAlign(Alignment, IncrementSize));
1027 // Build a factor node to remember that this load is independent of
1029 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1032 // Move the top bits to the right place.
1033 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1034 DAG.getConstant(ExtraWidth,
1035 TLI.getShiftAmountTy(Hi.getValueType())));
1037 // Join the hi and lo parts.
1038 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1043 bool isCustom = false;
1044 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1045 default: llvm_unreachable("This action is not supported yet!");
1046 case TargetLowering::Custom:
1049 case TargetLowering::Legal: {
1050 Value = SDValue(Node, 0);
1051 Chain = SDValue(Node, 1);
1054 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1055 if (Res.getNode()) {
1057 Chain = Res.getValue(1);
1060 // If this is an unaligned load and the target doesn't support it,
1062 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1064 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1065 unsigned ABIAlignment =
1066 TLI.getDataLayout()->getABITypeAlignment(Ty);
1067 if (LD->getAlignment() < ABIAlignment){
1068 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1069 DAG, TLI, Value, Chain);
1075 case TargetLowering::Expand:
1076 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1077 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1078 LD->getPointerInfo(),
1079 LD->isVolatile(), LD->isNonTemporal(),
1080 LD->isInvariant(), LD->getAlignment());
1084 ExtendOp = (SrcVT.isFloatingPoint() ?
1085 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1087 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1088 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1089 default: llvm_unreachable("Unexpected extend load type!");
1091 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1092 Chain = Load.getValue(1);
1096 assert(!SrcVT.isVector() &&
1097 "Vector Loads are handled in LegalizeVectorOps");
1099 // FIXME: This does not work for vectors on most targets. Sign- and
1100 // zero-extend operations are currently folded into extending loads,
1101 // whether they are legal or not, and then we end up here without any
1102 // support for legalizing them.
1103 assert(ExtType != ISD::EXTLOAD &&
1104 "EXTLOAD should always be supported!");
1105 // Turn the unsupported load into an EXTLOAD followed by an explicit
1106 // zero/sign extend inreg.
1107 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1108 Chain, Ptr, LD->getPointerInfo(), SrcVT,
1109 LD->isVolatile(), LD->isNonTemporal(),
1110 LD->getAlignment());
1112 if (ExtType == ISD::SEXTLOAD)
1113 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1114 Result.getValueType(),
1115 Result, DAG.getValueType(SrcVT));
1117 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1119 Chain = Result.getValue(1);
1124 // Since loads produce two values, make sure to remember that we legalized
1126 if (Chain.getNode() != Node) {
1127 assert(Value.getNode() != Node && "Load must be completely replaced");
1128 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1129 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1134 /// LegalizeOp - Return a legal replacement for the given operation, with
1135 /// all legal operands.
1136 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1137 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1140 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1141 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1142 TargetLowering::TypeLegal &&
1143 "Unexpected illegal type!");
1145 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1146 assert((TLI.getTypeAction(*DAG.getContext(),
1147 Node->getOperand(i).getValueType()) ==
1148 TargetLowering::TypeLegal ||
1149 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1150 "Unexpected illegal type!");
1152 // Figure out the correct action; the way to query this varies by opcode
1153 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1154 bool SimpleFinishLegalizing = true;
1155 switch (Node->getOpcode()) {
1156 case ISD::INTRINSIC_W_CHAIN:
1157 case ISD::INTRINSIC_WO_CHAIN:
1158 case ISD::INTRINSIC_VOID:
1159 case ISD::STACKSAVE:
1160 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1163 Action = TLI.getOperationAction(Node->getOpcode(),
1164 Node->getValueType(0));
1165 if (Action != TargetLowering::Promote)
1166 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1168 case ISD::SINT_TO_FP:
1169 case ISD::UINT_TO_FP:
1170 case ISD::EXTRACT_VECTOR_ELT:
1171 Action = TLI.getOperationAction(Node->getOpcode(),
1172 Node->getOperand(0).getValueType());
1174 case ISD::FP_ROUND_INREG:
1175 case ISD::SIGN_EXTEND_INREG: {
1176 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1177 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1180 case ISD::ATOMIC_STORE: {
1181 Action = TLI.getOperationAction(Node->getOpcode(),
1182 Node->getOperand(2).getValueType());
1185 case ISD::SELECT_CC:
1188 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1189 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1190 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1191 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1192 ISD::CondCode CCCode =
1193 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1194 Action = TLI.getCondCodeAction(CCCode, OpVT);
1195 if (Action == TargetLowering::Legal) {
1196 if (Node->getOpcode() == ISD::SELECT_CC)
1197 Action = TLI.getOperationAction(Node->getOpcode(),
1198 Node->getValueType(0));
1200 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1206 // FIXME: Model these properly. LOAD and STORE are complicated, and
1207 // STORE expects the unlegalized operand in some cases.
1208 SimpleFinishLegalizing = false;
1210 case ISD::CALLSEQ_START:
1211 case ISD::CALLSEQ_END:
1212 // FIXME: This shouldn't be necessary. These nodes have special properties
1213 // dealing with the recursive nature of legalization. Removing this
1214 // special case should be done as part of making LegalizeDAG non-recursive.
1215 SimpleFinishLegalizing = false;
1217 case ISD::EXTRACT_ELEMENT:
1218 case ISD::FLT_ROUNDS_:
1226 case ISD::MERGE_VALUES:
1227 case ISD::EH_RETURN:
1228 case ISD::FRAME_TO_ARGS_OFFSET:
1229 case ISD::EH_SJLJ_SETJMP:
1230 case ISD::EH_SJLJ_LONGJMP:
1231 // These operations lie about being legal: when they claim to be legal,
1232 // they should actually be expanded.
1233 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1234 if (Action == TargetLowering::Legal)
1235 Action = TargetLowering::Expand;
1237 case ISD::INIT_TRAMPOLINE:
1238 case ISD::ADJUST_TRAMPOLINE:
1239 case ISD::FRAMEADDR:
1240 case ISD::RETURNADDR:
1241 // These operations lie about being legal: when they claim to be legal,
1242 // they should actually be custom-lowered.
1243 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1244 if (Action == TargetLowering::Legal)
1245 Action = TargetLowering::Custom;
1247 case ISD::DEBUGTRAP:
1248 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1249 if (Action == TargetLowering::Expand) {
1250 // replace ISD::DEBUGTRAP with ISD::TRAP
1252 NewVal = DAG.getNode(ISD::TRAP, Node->getDebugLoc(), Node->getVTList(),
1253 Node->getOperand(0));
1254 ReplaceNode(Node, NewVal.getNode());
1255 LegalizeOp(NewVal.getNode());
1261 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1262 Action = TargetLowering::Legal;
1264 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1269 if (SimpleFinishLegalizing) {
1270 SDNode *NewNode = Node;
1271 switch (Node->getOpcode()) {
1278 // Legalizing shifts/rotates requires adjusting the shift amount
1279 // to the appropriate width.
1280 if (!Node->getOperand(1).getValueType().isVector()) {
1282 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1283 Node->getOperand(1));
1284 HandleSDNode Handle(SAO);
1285 LegalizeOp(SAO.getNode());
1286 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1290 case ISD::SRL_PARTS:
1291 case ISD::SRA_PARTS:
1292 case ISD::SHL_PARTS:
1293 // Legalizing shifts/rotates requires adjusting the shift amount
1294 // to the appropriate width.
1295 if (!Node->getOperand(2).getValueType().isVector()) {
1297 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1298 Node->getOperand(2));
1299 HandleSDNode Handle(SAO);
1300 LegalizeOp(SAO.getNode());
1301 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1302 Node->getOperand(1),
1308 if (NewNode != Node) {
1309 DAG.ReplaceAllUsesWith(Node, NewNode);
1310 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1311 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1316 case TargetLowering::Legal:
1318 case TargetLowering::Custom: {
1319 // FIXME: The handling for custom lowering with multiple results is
1321 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1322 if (Res.getNode()) {
1323 SmallVector<SDValue, 8> ResultVals;
1324 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1326 ResultVals.push_back(Res);
1328 ResultVals.push_back(Res.getValue(i));
1330 if (Res.getNode() != Node || Res.getResNo() != 0) {
1331 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1332 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1333 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1340 case TargetLowering::Expand:
1343 case TargetLowering::Promote:
1349 switch (Node->getOpcode()) {
1356 llvm_unreachable("Do not know how to legalize this operator!");
1358 case ISD::CALLSEQ_START:
1359 case ISD::CALLSEQ_END:
1362 return LegalizeLoadOps(Node);
1365 return LegalizeStoreOps(Node);
1370 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1371 SDValue Vec = Op.getOperand(0);
1372 SDValue Idx = Op.getOperand(1);
1373 DebugLoc dl = Op.getDebugLoc();
1374 // Store the value to a temporary stack slot, then LOAD the returned part.
1375 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1376 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1377 MachinePointerInfo(), false, false, 0);
1379 // Add the offset to the index.
1381 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1382 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1383 DAG.getConstant(EltSize, Idx.getValueType()));
1385 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1386 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1388 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1390 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1392 if (Op.getValueType().isVector())
1393 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1394 false, false, false, 0);
1395 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1396 MachinePointerInfo(),
1397 Vec.getValueType().getVectorElementType(),
1401 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1402 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1404 SDValue Vec = Op.getOperand(0);
1405 SDValue Part = Op.getOperand(1);
1406 SDValue Idx = Op.getOperand(2);
1407 DebugLoc dl = Op.getDebugLoc();
1409 // Store the value to a temporary stack slot, then LOAD the returned part.
1411 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1412 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1413 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1415 // First store the whole vector.
1416 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1419 // Then store the inserted part.
1421 // Add the offset to the index.
1423 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1425 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1426 DAG.getConstant(EltSize, Idx.getValueType()));
1428 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1429 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1431 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1433 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1436 // Store the subvector.
1437 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1438 MachinePointerInfo(), false, false, 0);
1440 // Finally, load the updated vector.
1441 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1442 false, false, false, 0);
1445 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1446 // We can't handle this case efficiently. Allocate a sufficiently
1447 // aligned object on the stack, store each element into it, then load
1448 // the result as a vector.
1449 // Create the stack frame object.
1450 EVT VT = Node->getValueType(0);
1451 EVT EltVT = VT.getVectorElementType();
1452 DebugLoc dl = Node->getDebugLoc();
1453 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1454 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1455 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1457 // Emit a store of each element to the stack slot.
1458 SmallVector<SDValue, 8> Stores;
1459 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1460 // Store (in the right endianness) the elements to memory.
1461 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1462 // Ignore undef elements.
1463 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1465 unsigned Offset = TypeByteSize*i;
1467 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1468 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1470 // If the destination vector element type is narrower than the source
1471 // element type, only store the bits necessary.
1472 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1473 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1474 Node->getOperand(i), Idx,
1475 PtrInfo.getWithOffset(Offset),
1476 EltVT, false, false, 0));
1478 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1479 Node->getOperand(i), Idx,
1480 PtrInfo.getWithOffset(Offset),
1485 if (!Stores.empty()) // Not all undef elements?
1486 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1487 &Stores[0], Stores.size());
1489 StoreChain = DAG.getEntryNode();
1491 // Result is a load from the stack slot.
1492 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1493 false, false, false, 0);
1496 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1497 DebugLoc dl = Node->getDebugLoc();
1498 SDValue Tmp1 = Node->getOperand(0);
1499 SDValue Tmp2 = Node->getOperand(1);
1501 // Get the sign bit of the RHS. First obtain a value that has the same
1502 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1504 EVT FloatVT = Tmp2.getValueType();
1505 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1506 if (TLI.isTypeLegal(IVT)) {
1507 // Convert to an integer with the same sign bit.
1508 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1510 // Store the float to memory, then load the sign part out as an integer.
1511 MVT LoadTy = TLI.getPointerTy();
1512 // First create a temporary that is aligned for both the load and store.
1513 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1514 // Then store the float to it.
1516 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1518 if (TLI.isBigEndian()) {
1519 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1520 // Load out a legal integer with the same sign bit as the float.
1521 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1522 false, false, false, 0);
1523 } else { // Little endian
1524 SDValue LoadPtr = StackPtr;
1525 // The float may be wider than the integer we are going to load. Advance
1526 // the pointer so that the loaded integer will contain the sign bit.
1527 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1528 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1529 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1530 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1531 // Load a legal integer containing the sign bit.
1532 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1533 false, false, false, 0);
1534 // Move the sign bit to the top bit of the loaded integer.
1535 unsigned BitShift = LoadTy.getSizeInBits() -
1536 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1537 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1539 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1540 DAG.getConstant(BitShift,
1541 TLI.getShiftAmountTy(SignBit.getValueType())));
1544 // Now get the sign bit proper, by seeing whether the value is negative.
1545 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1546 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1548 // Get the absolute value of the result.
1549 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1550 // Select between the nabs and abs value based on the sign bit of
1552 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1553 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1557 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1558 SmallVectorImpl<SDValue> &Results) {
1559 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1560 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1561 " not tell us which reg is the stack pointer!");
1562 DebugLoc dl = Node->getDebugLoc();
1563 EVT VT = Node->getValueType(0);
1564 SDValue Tmp1 = SDValue(Node, 0);
1565 SDValue Tmp2 = SDValue(Node, 1);
1566 SDValue Tmp3 = Node->getOperand(2);
1567 SDValue Chain = Tmp1.getOperand(0);
1569 // Chain the dynamic stack allocation so that it doesn't modify the stack
1570 // pointer when other instructions are using the stack.
1571 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1573 SDValue Size = Tmp2.getOperand(1);
1574 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1575 Chain = SP.getValue(1);
1576 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1577 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1578 if (Align > StackAlign)
1579 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1580 DAG.getConstant(-(uint64_t)Align, VT));
1581 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1582 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1584 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1585 DAG.getIntPtrConstant(0, true), SDValue());
1587 Results.push_back(Tmp1);
1588 Results.push_back(Tmp2);
1591 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1592 /// condition code CC on the current target. This routine expands SETCC with
1593 /// illegal condition code into AND / OR of multiple SETCC values.
1594 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1595 SDValue &LHS, SDValue &RHS,
1598 MVT OpVT = LHS.getSimpleValueType();
1599 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1600 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1601 default: llvm_unreachable("Unknown condition code action!");
1602 case TargetLowering::Legal:
1605 case TargetLowering::Expand: {
1606 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1607 ISD::CondCode InvCC = ISD::SETCC_INVALID;
1610 default: llvm_unreachable("Don't know how to expand this condition!");
1612 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1613 == TargetLowering::Legal
1614 && "If SETO is expanded, SETOEQ must be legal!");
1615 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1617 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1618 == TargetLowering::Legal
1619 && "If SETUO is expanded, SETUNE must be legal!");
1620 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1633 // If we are floating point, assign and break, otherwise fall through.
1634 if (!OpVT.isInteger()) {
1635 // We can use the 4th bit to tell if we are the unordered
1636 // or ordered version of the opcode.
1637 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1638 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1639 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1642 // Fallthrough if we are unsigned integer.
1649 InvCC = ISD::getSetCCSwappedOperands(CCCode);
1650 if (TLI.getCondCodeAction(InvCC, OpVT) == TargetLowering::Expand) {
1651 // We only support using the inverted operation and not a
1652 // different manner of supporting expanding these cases.
1653 llvm_unreachable("Don't know how to expand this condition!");
1655 LHS = DAG.getSetCC(dl, VT, RHS, LHS, InvCC);
1661 SDValue SetCC1, SetCC2;
1662 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1663 // If we aren't the ordered or unorder operation,
1664 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1665 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1666 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1668 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1669 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1670 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1672 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1680 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1681 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1682 /// a load from the stack slot to DestVT, extending it if needed.
1683 /// The resultant code need not be legal.
1684 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1688 // Create the stack frame object.
1690 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1691 getTypeForEVT(*DAG.getContext()));
1692 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1694 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1695 int SPFI = StackPtrFI->getIndex();
1696 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1698 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1699 unsigned SlotSize = SlotVT.getSizeInBits();
1700 unsigned DestSize = DestVT.getSizeInBits();
1701 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1702 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1704 // Emit a store to the stack slot. Use a truncstore if the input value is
1705 // later than DestVT.
1708 if (SrcSize > SlotSize)
1709 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1710 PtrInfo, SlotVT, false, false, SrcAlign);
1712 assert(SrcSize == SlotSize && "Invalid store");
1713 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1714 PtrInfo, false, false, SrcAlign);
1717 // Result is a load from the stack slot.
1718 if (SlotSize == DestSize)
1719 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1720 false, false, false, DestAlign);
1722 assert(SlotSize < DestSize && "Unknown extension!");
1723 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1724 PtrInfo, SlotVT, false, false, DestAlign);
1727 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1728 DebugLoc dl = Node->getDebugLoc();
1729 // Create a vector sized/aligned stack slot, store the value to element #0,
1730 // then load the whole vector back out.
1731 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1733 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1734 int SPFI = StackPtrFI->getIndex();
1736 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1738 MachinePointerInfo::getFixedStack(SPFI),
1739 Node->getValueType(0).getVectorElementType(),
1741 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1742 MachinePointerInfo::getFixedStack(SPFI),
1743 false, false, false, 0);
1747 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1748 /// support the operation, but do support the resultant vector type.
1749 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1750 unsigned NumElems = Node->getNumOperands();
1751 SDValue Value1, Value2;
1752 DebugLoc dl = Node->getDebugLoc();
1753 EVT VT = Node->getValueType(0);
1754 EVT OpVT = Node->getOperand(0).getValueType();
1755 EVT EltVT = VT.getVectorElementType();
1757 // If the only non-undef value is the low element, turn this into a
1758 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1759 bool isOnlyLowElement = true;
1760 bool MoreThanTwoValues = false;
1761 bool isConstant = true;
1762 for (unsigned i = 0; i < NumElems; ++i) {
1763 SDValue V = Node->getOperand(i);
1764 if (V.getOpcode() == ISD::UNDEF)
1767 isOnlyLowElement = false;
1768 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1771 if (!Value1.getNode()) {
1773 } else if (!Value2.getNode()) {
1776 } else if (V != Value1 && V != Value2) {
1777 MoreThanTwoValues = true;
1781 if (!Value1.getNode())
1782 return DAG.getUNDEF(VT);
1784 if (isOnlyLowElement)
1785 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1787 // If all elements are constants, create a load from the constant pool.
1789 SmallVector<Constant*, 16> CV;
1790 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1791 if (ConstantFPSDNode *V =
1792 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1793 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1794 } else if (ConstantSDNode *V =
1795 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1797 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1799 // If OpVT and EltVT don't match, EltVT is not legal and the
1800 // element values have been promoted/truncated earlier. Undo this;
1801 // we don't want a v16i8 to become a v16i32 for example.
1802 const ConstantInt *CI = V->getConstantIntValue();
1803 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1804 CI->getZExtValue()));
1807 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1808 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1809 CV.push_back(UndefValue::get(OpNTy));
1812 Constant *CP = ConstantVector::get(CV);
1813 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1814 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1815 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1816 MachinePointerInfo::getConstantPool(),
1817 false, false, false, Alignment);
1820 if (!MoreThanTwoValues) {
1821 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1822 for (unsigned i = 0; i < NumElems; ++i) {
1823 SDValue V = Node->getOperand(i);
1824 if (V.getOpcode() == ISD::UNDEF)
1826 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1828 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1829 // Get the splatted value into the low element of a vector register.
1830 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1832 if (Value2.getNode())
1833 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1835 Vec2 = DAG.getUNDEF(VT);
1837 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1838 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1842 // Otherwise, we can't handle this case efficiently.
1843 return ExpandVectorBuildThroughStack(Node);
1846 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1847 // does not fit into a register, return the lo part and set the hi part to the
1848 // by-reg argument. If it does fit into a single register, return the result
1849 // and leave the Hi part unset.
1850 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1852 TargetLowering::ArgListTy Args;
1853 TargetLowering::ArgListEntry Entry;
1854 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1855 EVT ArgVT = Node->getOperand(i).getValueType();
1856 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1857 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1858 Entry.isSExt = isSigned;
1859 Entry.isZExt = !isSigned;
1860 Args.push_back(Entry);
1862 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1863 TLI.getPointerTy());
1865 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1867 // By default, the input chain to this libcall is the entry node of the
1868 // function. If the libcall is going to be emitted as a tail call then
1869 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1870 // node which is being folded has a non-entry input chain.
1871 SDValue InChain = DAG.getEntryNode();
1873 // isTailCall may be true since the callee does not reference caller stack
1874 // frame. Check if it's in the right position.
1875 SDValue TCChain = InChain;
1876 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
1881 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1882 0, TLI.getLibcallCallingConv(LC), isTailCall,
1883 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1884 Callee, Args, DAG, Node->getDebugLoc());
1885 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1888 if (!CallInfo.second.getNode())
1889 // It's a tailcall, return the chain (which is the DAG root).
1890 return DAG.getRoot();
1892 return CallInfo.first;
1895 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1896 /// and returning a result of type RetVT.
1897 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1898 const SDValue *Ops, unsigned NumOps,
1899 bool isSigned, DebugLoc dl) {
1900 TargetLowering::ArgListTy Args;
1901 Args.reserve(NumOps);
1903 TargetLowering::ArgListEntry Entry;
1904 for (unsigned i = 0; i != NumOps; ++i) {
1905 Entry.Node = Ops[i];
1906 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1907 Entry.isSExt = isSigned;
1908 Entry.isZExt = !isSigned;
1909 Args.push_back(Entry);
1911 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1912 TLI.getPointerTy());
1914 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1916 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1917 false, 0, TLI.getLibcallCallingConv(LC),
1918 /*isTailCall=*/false,
1919 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1920 Callee, Args, DAG, dl);
1921 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1923 return CallInfo.first;
1926 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1927 // ExpandLibCall except that the first operand is the in-chain.
1928 std::pair<SDValue, SDValue>
1929 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1932 SDValue InChain = Node->getOperand(0);
1934 TargetLowering::ArgListTy Args;
1935 TargetLowering::ArgListEntry Entry;
1936 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1937 EVT ArgVT = Node->getOperand(i).getValueType();
1938 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1939 Entry.Node = Node->getOperand(i);
1941 Entry.isSExt = isSigned;
1942 Entry.isZExt = !isSigned;
1943 Args.push_back(Entry);
1945 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1946 TLI.getPointerTy());
1948 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1950 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1951 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1952 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1953 Callee, Args, DAG, Node->getDebugLoc());
1954 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1959 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1960 RTLIB::Libcall Call_F32,
1961 RTLIB::Libcall Call_F64,
1962 RTLIB::Libcall Call_F80,
1963 RTLIB::Libcall Call_F128,
1964 RTLIB::Libcall Call_PPCF128) {
1966 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1967 default: llvm_unreachable("Unexpected request for libcall!");
1968 case MVT::f32: LC = Call_F32; break;
1969 case MVT::f64: LC = Call_F64; break;
1970 case MVT::f80: LC = Call_F80; break;
1971 case MVT::f128: LC = Call_F128; break;
1972 case MVT::ppcf128: LC = Call_PPCF128; break;
1974 return ExpandLibCall(LC, Node, false);
1977 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1978 RTLIB::Libcall Call_I8,
1979 RTLIB::Libcall Call_I16,
1980 RTLIB::Libcall Call_I32,
1981 RTLIB::Libcall Call_I64,
1982 RTLIB::Libcall Call_I128) {
1984 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1985 default: llvm_unreachable("Unexpected request for libcall!");
1986 case MVT::i8: LC = Call_I8; break;
1987 case MVT::i16: LC = Call_I16; break;
1988 case MVT::i32: LC = Call_I32; break;
1989 case MVT::i64: LC = Call_I64; break;
1990 case MVT::i128: LC = Call_I128; break;
1992 return ExpandLibCall(LC, Node, isSigned);
1995 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
1996 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
1997 const TargetLowering &TLI) {
1999 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2000 default: llvm_unreachable("Unexpected request for libcall!");
2001 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2002 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2003 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2004 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2005 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2008 return TLI.getLibcallName(LC) != 0;
2011 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2013 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2014 // The other use might have been replaced with a divrem already.
2015 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2016 unsigned OtherOpcode = 0;
2018 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2020 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2022 SDValue Op0 = Node->getOperand(0);
2023 SDValue Op1 = Node->getOperand(1);
2024 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2025 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2029 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2030 User->getOperand(0) == Op0 &&
2031 User->getOperand(1) == Op1)
2037 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2040 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2041 SmallVectorImpl<SDValue> &Results) {
2042 unsigned Opcode = Node->getOpcode();
2043 bool isSigned = Opcode == ISD::SDIVREM;
2046 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2047 default: llvm_unreachable("Unexpected request for libcall!");
2048 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2049 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2050 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2051 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2052 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2055 // The input chain to this libcall is the entry node of the function.
2056 // Legalizing the call will automatically add the previous call to the
2058 SDValue InChain = DAG.getEntryNode();
2060 EVT RetVT = Node->getValueType(0);
2061 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2063 TargetLowering::ArgListTy Args;
2064 TargetLowering::ArgListEntry Entry;
2065 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2066 EVT ArgVT = Node->getOperand(i).getValueType();
2067 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2068 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2069 Entry.isSExt = isSigned;
2070 Entry.isZExt = !isSigned;
2071 Args.push_back(Entry);
2074 // Also pass the return address of the remainder.
2075 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2077 Entry.Ty = RetTy->getPointerTo();
2078 Entry.isSExt = isSigned;
2079 Entry.isZExt = !isSigned;
2080 Args.push_back(Entry);
2082 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2083 TLI.getPointerTy());
2085 DebugLoc dl = Node->getDebugLoc();
2087 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2088 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2089 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2090 Callee, Args, DAG, dl);
2091 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2093 // Remainder is loaded back from the stack frame.
2094 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2095 MachinePointerInfo(), false, false, false, 0);
2096 Results.push_back(CallInfo.first);
2097 Results.push_back(Rem);
2100 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2101 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2103 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2104 default: llvm_unreachable("Unexpected request for libcall!");
2105 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2106 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2107 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2108 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2109 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2111 return TLI.getLibcallName(LC) != 0;
2114 /// useSinCos - Only issue sincos libcall if both sin and cos are
2116 static bool useSinCos(SDNode *Node) {
2117 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2118 ? ISD::FCOS : ISD::FSIN;
2120 SDValue Op0 = Node->getOperand(0);
2121 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2122 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2126 // The other user might have been turned into sincos already.
2127 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2133 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2136 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2137 SmallVectorImpl<SDValue> &Results) {
2139 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2140 default: llvm_unreachable("Unexpected request for libcall!");
2141 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2142 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2143 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2144 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2145 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2148 // The input chain to this libcall is the entry node of the function.
2149 // Legalizing the call will automatically add the previous call to the
2151 SDValue InChain = DAG.getEntryNode();
2153 EVT RetVT = Node->getValueType(0);
2154 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2156 TargetLowering::ArgListTy Args;
2157 TargetLowering::ArgListEntry Entry;
2159 // Pass the argument.
2160 Entry.Node = Node->getOperand(0);
2162 Entry.isSExt = false;
2163 Entry.isZExt = false;
2164 Args.push_back(Entry);
2166 // Pass the return address of sin.
2167 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2168 Entry.Node = SinPtr;
2169 Entry.Ty = RetTy->getPointerTo();
2170 Entry.isSExt = false;
2171 Entry.isZExt = false;
2172 Args.push_back(Entry);
2174 // Also pass the return address of the cos.
2175 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2176 Entry.Node = CosPtr;
2177 Entry.Ty = RetTy->getPointerTo();
2178 Entry.isSExt = false;
2179 Entry.isZExt = false;
2180 Args.push_back(Entry);
2182 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2183 TLI.getPointerTy());
2185 DebugLoc dl = Node->getDebugLoc();
2187 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2188 false, false, false, false,
2189 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2190 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2191 Callee, Args, DAG, dl);
2192 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2194 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2195 MachinePointerInfo(), false, false, false, 0));
2196 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2197 MachinePointerInfo(), false, false, false, 0));
2200 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2201 /// INT_TO_FP operation of the specified operand when the target requests that
2202 /// we expand it. At this point, we know that the result and operand types are
2203 /// legal for the target.
2204 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2208 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2209 // simple 32-bit [signed|unsigned] integer to float/double expansion
2211 // Get the stack frame index of a 8 byte buffer.
2212 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2214 // word offset constant for Hi/Lo address computation
2215 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2216 // set up Hi and Lo (into buffer) address based on endian
2217 SDValue Hi = StackSlot;
2218 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2219 TLI.getPointerTy(), StackSlot, WordOff);
2220 if (TLI.isLittleEndian())
2223 // if signed map to unsigned space
2226 // constant used to invert sign bit (signed to unsigned mapping)
2227 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2228 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2232 // store the lo of the constructed double - based on integer input
2233 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2234 Op0Mapped, Lo, MachinePointerInfo(),
2236 // initial hi portion of constructed double
2237 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2238 // store the hi of the constructed double - biased exponent
2239 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2240 MachinePointerInfo(),
2242 // load the constructed double
2243 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2244 MachinePointerInfo(), false, false, false, 0);
2245 // FP constant to bias correct the final result
2246 SDValue Bias = DAG.getConstantFP(isSigned ?
2247 BitsToDouble(0x4330000080000000ULL) :
2248 BitsToDouble(0x4330000000000000ULL),
2250 // subtract the bias
2251 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2254 // handle final rounding
2255 if (DestVT == MVT::f64) {
2258 } else if (DestVT.bitsLT(MVT::f64)) {
2259 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2260 DAG.getIntPtrConstant(0));
2261 } else if (DestVT.bitsGT(MVT::f64)) {
2262 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2266 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2267 // Code below here assumes !isSigned without checking again.
2269 // Implementation of unsigned i64 to f64 following the algorithm in
2270 // __floatundidf in compiler_rt. This implementation has the advantage
2271 // of performing rounding correctly, both in the default rounding mode
2272 // and in all alternate rounding modes.
2273 // TODO: Generalize this for use with other types.
2274 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2276 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2277 SDValue TwoP84PlusTwoP52 =
2278 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2280 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2282 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2283 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2284 DAG.getConstant(32, MVT::i64));
2285 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2286 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2287 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2288 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2289 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2291 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2294 // Implementation of unsigned i64 to f32.
2295 // TODO: Generalize this for use with other types.
2296 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2297 // For unsigned conversions, convert them to signed conversions using the
2298 // algorithm from the x86_64 __floatundidf in compiler_rt.
2300 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2302 SDValue ShiftConst =
2303 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2304 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2305 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2306 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2307 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2309 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2310 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2312 // TODO: This really should be implemented using a branch rather than a
2313 // select. We happen to get lucky and machinesink does the right
2314 // thing most of the time. This would be a good candidate for a
2315 //pseudo-op, or, even better, for whole-function isel.
2316 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2317 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2318 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2321 // Otherwise, implement the fully general conversion.
2323 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2324 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2325 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2326 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2327 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2328 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2329 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2330 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2331 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2332 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2333 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2335 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2336 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2338 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2339 DAG.getConstant(32, SHVT));
2340 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2341 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2343 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2344 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2345 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2346 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2347 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2348 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2349 DAG.getIntPtrConstant(0));
2352 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2354 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2355 Op0, DAG.getConstant(0, Op0.getValueType()),
2357 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2358 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2359 SignSet, Four, Zero);
2361 // If the sign bit of the integer is set, the large number will be treated
2362 // as a negative number. To counteract this, the dynamic code adds an
2363 // offset depending on the data type.
2365 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2366 default: llvm_unreachable("Unsupported integer type!");
2367 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2368 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2369 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2370 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2372 if (TLI.isLittleEndian()) FF <<= 32;
2373 Constant *FudgeFactor = ConstantInt::get(
2374 Type::getInt64Ty(*DAG.getContext()), FF);
2376 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2377 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2378 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2379 Alignment = std::min(Alignment, 4u);
2381 if (DestVT == MVT::f32)
2382 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2383 MachinePointerInfo::getConstantPool(),
2384 false, false, false, Alignment);
2386 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2387 DAG.getEntryNode(), CPIdx,
2388 MachinePointerInfo::getConstantPool(),
2389 MVT::f32, false, false, Alignment);
2390 HandleSDNode Handle(Load);
2391 LegalizeOp(Load.getNode());
2392 FudgeInReg = Handle.getValue();
2395 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2398 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2399 /// *INT_TO_FP operation of the specified operand when the target requests that
2400 /// we promote it. At this point, we know that the result and operand types are
2401 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2402 /// operation that takes a larger input.
2403 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2407 // First step, figure out the appropriate *INT_TO_FP operation to use.
2408 EVT NewInTy = LegalOp.getValueType();
2410 unsigned OpToUse = 0;
2412 // Scan for the appropriate larger type to use.
2414 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2415 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2417 // If the target supports SINT_TO_FP of this type, use it.
2418 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2419 OpToUse = ISD::SINT_TO_FP;
2422 if (isSigned) continue;
2424 // If the target supports UINT_TO_FP of this type, use it.
2425 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2426 OpToUse = ISD::UINT_TO_FP;
2430 // Otherwise, try a larger type.
2433 // Okay, we found the operation and type to use. Zero extend our input to the
2434 // desired type then run the operation on it.
2435 return DAG.getNode(OpToUse, dl, DestVT,
2436 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2437 dl, NewInTy, LegalOp));
2440 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2441 /// FP_TO_*INT operation of the specified operand when the target requests that
2442 /// we promote it. At this point, we know that the result and operand types are
2443 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2444 /// operation that returns a larger result.
2445 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2449 // First step, figure out the appropriate FP_TO*INT operation to use.
2450 EVT NewOutTy = DestVT;
2452 unsigned OpToUse = 0;
2454 // Scan for the appropriate larger type to use.
2456 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2457 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2459 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2460 OpToUse = ISD::FP_TO_SINT;
2464 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2465 OpToUse = ISD::FP_TO_UINT;
2469 // Otherwise, try a larger type.
2473 // Okay, we found the operation and type to use.
2474 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2476 // Truncate the result of the extended FP_TO_*INT operation to the desired
2478 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2481 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2483 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2484 EVT VT = Op.getValueType();
2485 EVT SHVT = TLI.getShiftAmountTy(VT);
2486 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2487 switch (VT.getSimpleVT().SimpleTy) {
2488 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2490 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2491 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2492 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2494 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2495 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2496 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2497 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2498 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2499 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2500 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2501 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2502 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2504 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2505 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2506 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2507 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2508 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2509 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2510 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2511 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2512 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2513 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2514 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2515 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2516 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2517 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2518 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2519 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2520 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2521 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2522 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2523 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2524 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2528 /// SplatByte - Distribute ByteVal over NumBits bits.
2529 // FIXME: Move this helper to a common place.
2530 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2531 APInt Val = APInt(NumBits, ByteVal);
2533 for (unsigned i = NumBits; i > 8; i >>= 1) {
2534 Val = (Val << Shift) | Val;
2540 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2542 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2545 default: llvm_unreachable("Cannot expand this yet!");
2547 EVT VT = Op.getValueType();
2548 EVT ShVT = TLI.getShiftAmountTy(VT);
2549 unsigned Len = VT.getSizeInBits();
2551 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2552 "CTPOP not implemented for this type.");
2554 // This is the "best" algorithm from
2555 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2557 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2558 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2559 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2560 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2562 // v = v - ((v >> 1) & 0x55555555...)
2563 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2564 DAG.getNode(ISD::AND, dl, VT,
2565 DAG.getNode(ISD::SRL, dl, VT, Op,
2566 DAG.getConstant(1, ShVT)),
2568 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2569 Op = DAG.getNode(ISD::ADD, dl, VT,
2570 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2571 DAG.getNode(ISD::AND, dl, VT,
2572 DAG.getNode(ISD::SRL, dl, VT, Op,
2573 DAG.getConstant(2, ShVT)),
2575 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2576 Op = DAG.getNode(ISD::AND, dl, VT,
2577 DAG.getNode(ISD::ADD, dl, VT, Op,
2578 DAG.getNode(ISD::SRL, dl, VT, Op,
2579 DAG.getConstant(4, ShVT))),
2581 // v = (v * 0x01010101...) >> (Len - 8)
2582 Op = DAG.getNode(ISD::SRL, dl, VT,
2583 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2584 DAG.getConstant(Len - 8, ShVT));
2588 case ISD::CTLZ_ZERO_UNDEF:
2589 // This trivially expands to CTLZ.
2590 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2592 // for now, we do this:
2593 // x = x | (x >> 1);
2594 // x = x | (x >> 2);
2596 // x = x | (x >>16);
2597 // x = x | (x >>32); // for 64-bit input
2598 // return popcount(~x);
2600 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2601 EVT VT = Op.getValueType();
2602 EVT ShVT = TLI.getShiftAmountTy(VT);
2603 unsigned len = VT.getSizeInBits();
2604 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2605 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2606 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2607 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2609 Op = DAG.getNOT(dl, Op, VT);
2610 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2612 case ISD::CTTZ_ZERO_UNDEF:
2613 // This trivially expands to CTTZ.
2614 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2616 // for now, we use: { return popcount(~x & (x - 1)); }
2617 // unless the target has ctlz but not ctpop, in which case we use:
2618 // { return 32 - nlz(~x & (x-1)); }
2619 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2620 EVT VT = Op.getValueType();
2621 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2622 DAG.getNOT(dl, Op, VT),
2623 DAG.getNode(ISD::SUB, dl, VT, Op,
2624 DAG.getConstant(1, VT)));
2625 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2626 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2627 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2628 return DAG.getNode(ISD::SUB, dl, VT,
2629 DAG.getConstant(VT.getSizeInBits(), VT),
2630 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2631 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2636 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2637 unsigned Opc = Node->getOpcode();
2638 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2643 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2644 case ISD::ATOMIC_SWAP:
2645 switch (VT.SimpleTy) {
2646 default: llvm_unreachable("Unexpected value type for atomic!");
2647 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2648 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2649 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2650 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2653 case ISD::ATOMIC_CMP_SWAP:
2654 switch (VT.SimpleTy) {
2655 default: llvm_unreachable("Unexpected value type for atomic!");
2656 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2657 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2658 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2659 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2662 case ISD::ATOMIC_LOAD_ADD:
2663 switch (VT.SimpleTy) {
2664 default: llvm_unreachable("Unexpected value type for atomic!");
2665 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2666 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2667 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2668 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2671 case ISD::ATOMIC_LOAD_SUB:
2672 switch (VT.SimpleTy) {
2673 default: llvm_unreachable("Unexpected value type for atomic!");
2674 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2675 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2676 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2677 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2680 case ISD::ATOMIC_LOAD_AND:
2681 switch (VT.SimpleTy) {
2682 default: llvm_unreachable("Unexpected value type for atomic!");
2683 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2684 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2685 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2686 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2689 case ISD::ATOMIC_LOAD_OR:
2690 switch (VT.SimpleTy) {
2691 default: llvm_unreachable("Unexpected value type for atomic!");
2692 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2693 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2694 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2695 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2698 case ISD::ATOMIC_LOAD_XOR:
2699 switch (VT.SimpleTy) {
2700 default: llvm_unreachable("Unexpected value type for atomic!");
2701 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2702 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2703 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2704 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2707 case ISD::ATOMIC_LOAD_NAND:
2708 switch (VT.SimpleTy) {
2709 default: llvm_unreachable("Unexpected value type for atomic!");
2710 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2711 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2712 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2713 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2718 return ExpandChainLibCall(LC, Node, false);
2721 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2722 SmallVector<SDValue, 8> Results;
2723 DebugLoc dl = Node->getDebugLoc();
2724 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2725 switch (Node->getOpcode()) {
2728 case ISD::CTLZ_ZERO_UNDEF:
2730 case ISD::CTTZ_ZERO_UNDEF:
2731 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2732 Results.push_back(Tmp1);
2735 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2737 case ISD::FRAMEADDR:
2738 case ISD::RETURNADDR:
2739 case ISD::FRAME_TO_ARGS_OFFSET:
2740 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2742 case ISD::FLT_ROUNDS_:
2743 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2745 case ISD::EH_RETURN:
2749 case ISD::EH_SJLJ_LONGJMP:
2750 // If the target didn't expand these, there's nothing to do, so just
2751 // preserve the chain and be done.
2752 Results.push_back(Node->getOperand(0));
2754 case ISD::EH_SJLJ_SETJMP:
2755 // If the target didn't expand this, just return 'zero' and preserve the
2757 Results.push_back(DAG.getConstant(0, MVT::i32));
2758 Results.push_back(Node->getOperand(0));
2760 case ISD::ATOMIC_FENCE:
2761 case ISD::MEMBARRIER: {
2762 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2763 // FIXME: handle "fence singlethread" more efficiently.
2764 TargetLowering::ArgListTy Args;
2766 CallLoweringInfo CLI(Node->getOperand(0),
2767 Type::getVoidTy(*DAG.getContext()),
2768 false, false, false, false, 0, CallingConv::C,
2769 /*isTailCall=*/false,
2770 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2771 DAG.getExternalSymbol("__sync_synchronize",
2772 TLI.getPointerTy()),
2774 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2776 Results.push_back(CallResult.second);
2779 case ISD::ATOMIC_LOAD: {
2780 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2781 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2782 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2783 cast<AtomicSDNode>(Node)->getMemoryVT(),
2784 Node->getOperand(0),
2785 Node->getOperand(1), Zero, Zero,
2786 cast<AtomicSDNode>(Node)->getMemOperand(),
2787 cast<AtomicSDNode>(Node)->getOrdering(),
2788 cast<AtomicSDNode>(Node)->getSynchScope());
2789 Results.push_back(Swap.getValue(0));
2790 Results.push_back(Swap.getValue(1));
2793 case ISD::ATOMIC_STORE: {
2794 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2795 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2796 cast<AtomicSDNode>(Node)->getMemoryVT(),
2797 Node->getOperand(0),
2798 Node->getOperand(1), Node->getOperand(2),
2799 cast<AtomicSDNode>(Node)->getMemOperand(),
2800 cast<AtomicSDNode>(Node)->getOrdering(),
2801 cast<AtomicSDNode>(Node)->getSynchScope());
2802 Results.push_back(Swap.getValue(1));
2805 // By default, atomic intrinsics are marked Legal and lowered. Targets
2806 // which don't support them directly, however, may want libcalls, in which
2807 // case they mark them Expand, and we get here.
2808 case ISD::ATOMIC_SWAP:
2809 case ISD::ATOMIC_LOAD_ADD:
2810 case ISD::ATOMIC_LOAD_SUB:
2811 case ISD::ATOMIC_LOAD_AND:
2812 case ISD::ATOMIC_LOAD_OR:
2813 case ISD::ATOMIC_LOAD_XOR:
2814 case ISD::ATOMIC_LOAD_NAND:
2815 case ISD::ATOMIC_LOAD_MIN:
2816 case ISD::ATOMIC_LOAD_MAX:
2817 case ISD::ATOMIC_LOAD_UMIN:
2818 case ISD::ATOMIC_LOAD_UMAX:
2819 case ISD::ATOMIC_CMP_SWAP: {
2820 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2821 Results.push_back(Tmp.first);
2822 Results.push_back(Tmp.second);
2825 case ISD::DYNAMIC_STACKALLOC:
2826 ExpandDYNAMIC_STACKALLOC(Node, Results);
2828 case ISD::MERGE_VALUES:
2829 for (unsigned i = 0; i < Node->getNumValues(); i++)
2830 Results.push_back(Node->getOperand(i));
2833 EVT VT = Node->getValueType(0);
2835 Results.push_back(DAG.getConstant(0, VT));
2837 assert(VT.isFloatingPoint() && "Unknown value type!");
2838 Results.push_back(DAG.getConstantFP(0, VT));
2843 // If this operation is not supported, lower it to 'abort()' call
2844 TargetLowering::ArgListTy Args;
2846 CallLoweringInfo CLI(Node->getOperand(0),
2847 Type::getVoidTy(*DAG.getContext()),
2848 false, false, false, false, 0, CallingConv::C,
2849 /*isTailCall=*/false,
2850 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2851 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2853 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2855 Results.push_back(CallResult.second);
2860 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2861 Node->getValueType(0), dl);
2862 Results.push_back(Tmp1);
2864 case ISD::FP_EXTEND:
2865 Tmp1 = EmitStackConvert(Node->getOperand(0),
2866 Node->getOperand(0).getValueType(),
2867 Node->getValueType(0), dl);
2868 Results.push_back(Tmp1);
2870 case ISD::SIGN_EXTEND_INREG: {
2871 // NOTE: we could fall back on load/store here too for targets without
2872 // SAR. However, it is doubtful that any exist.
2873 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2874 EVT VT = Node->getValueType(0);
2875 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2878 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2879 ExtraVT.getScalarType().getSizeInBits();
2880 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2881 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2882 Node->getOperand(0), ShiftCst);
2883 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2884 Results.push_back(Tmp1);
2887 case ISD::FP_ROUND_INREG: {
2888 // The only way we can lower this is to turn it into a TRUNCSTORE,
2889 // EXTLOAD pair, targeting a temporary location (a stack slot).
2891 // NOTE: there is a choice here between constantly creating new stack
2892 // slots and always reusing the same one. We currently always create
2893 // new ones, as reuse may inhibit scheduling.
2894 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2895 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2896 Node->getValueType(0), dl);
2897 Results.push_back(Tmp1);
2900 case ISD::SINT_TO_FP:
2901 case ISD::UINT_TO_FP:
2902 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2903 Node->getOperand(0), Node->getValueType(0), dl);
2904 Results.push_back(Tmp1);
2906 case ISD::FP_TO_UINT: {
2907 SDValue True, False;
2908 EVT VT = Node->getOperand(0).getValueType();
2909 EVT NVT = Node->getValueType(0);
2910 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
2911 APInt::getNullValue(VT.getSizeInBits()));
2912 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2913 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2914 Tmp1 = DAG.getConstantFP(apf, VT);
2915 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2916 Node->getOperand(0),
2918 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2919 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2920 DAG.getNode(ISD::FSUB, dl, VT,
2921 Node->getOperand(0), Tmp1));
2922 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2923 DAG.getConstant(x, NVT));
2924 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2925 Results.push_back(Tmp1);
2929 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2930 EVT VT = Node->getValueType(0);
2931 Tmp1 = Node->getOperand(0);
2932 Tmp2 = Node->getOperand(1);
2933 unsigned Align = Node->getConstantOperandVal(3);
2935 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2936 MachinePointerInfo(V),
2937 false, false, false, 0);
2938 SDValue VAList = VAListLoad;
2940 if (Align > TLI.getMinStackArgumentAlignment()) {
2941 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2943 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2944 DAG.getConstant(Align - 1,
2945 TLI.getPointerTy()));
2947 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2948 DAG.getConstant(-(int64_t)Align,
2949 TLI.getPointerTy()));
2952 // Increment the pointer, VAList, to the next vaarg
2953 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2954 DAG.getConstant(TLI.getDataLayout()->
2955 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2956 TLI.getPointerTy()));
2957 // Store the incremented VAList to the legalized pointer
2958 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2959 MachinePointerInfo(V), false, false, 0);
2960 // Load the actual argument out of the pointer VAList
2961 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2962 false, false, false, 0));
2963 Results.push_back(Results[0].getValue(1));
2967 // This defaults to loading a pointer from the input and storing it to the
2968 // output, returning the chain.
2969 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2970 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2971 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2972 Node->getOperand(2), MachinePointerInfo(VS),
2973 false, false, false, 0);
2974 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2975 MachinePointerInfo(VD), false, false, 0);
2976 Results.push_back(Tmp1);
2979 case ISD::EXTRACT_VECTOR_ELT:
2980 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2981 // This must be an access of the only element. Return it.
2982 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2983 Node->getOperand(0));
2985 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2986 Results.push_back(Tmp1);
2988 case ISD::EXTRACT_SUBVECTOR:
2989 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2991 case ISD::INSERT_SUBVECTOR:
2992 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2994 case ISD::CONCAT_VECTORS: {
2995 Results.push_back(ExpandVectorBuildThroughStack(Node));
2998 case ISD::SCALAR_TO_VECTOR:
2999 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3001 case ISD::INSERT_VECTOR_ELT:
3002 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3003 Node->getOperand(1),
3004 Node->getOperand(2), dl));
3006 case ISD::VECTOR_SHUFFLE: {
3007 SmallVector<int, 32> NewMask;
3008 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3010 EVT VT = Node->getValueType(0);
3011 EVT EltVT = VT.getVectorElementType();
3012 SDValue Op0 = Node->getOperand(0);
3013 SDValue Op1 = Node->getOperand(1);
3014 if (!TLI.isTypeLegal(EltVT)) {
3016 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3018 // BUILD_VECTOR operands are allowed to be wider than the element type.
3019 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
3020 if (NewEltVT.bitsLT(EltVT)) {
3022 // Convert shuffle node.
3023 // If original node was v4i64 and the new EltVT is i32,
3024 // cast operands to v8i32 and re-build the mask.
3026 // Calculate new VT, the size of the new VT should be equal to original.
3027 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3028 VT.getSizeInBits()/NewEltVT.getSizeInBits());
3029 assert(NewVT.bitsEq(VT));
3031 // cast operands to new VT
3032 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3033 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3035 // Convert the shuffle mask
3036 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
3038 // EltVT gets smaller
3041 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3043 for (unsigned fi = 0; fi < factor; ++fi)
3044 NewMask.push_back(Mask[i]);
3047 for (unsigned fi = 0; fi < factor; ++fi)
3048 NewMask.push_back(Mask[i]*factor+fi);
3056 unsigned NumElems = VT.getVectorNumElements();
3057 SmallVector<SDValue, 16> Ops;
3058 for (unsigned i = 0; i != NumElems; ++i) {
3060 Ops.push_back(DAG.getUNDEF(EltVT));
3063 unsigned Idx = Mask[i];
3065 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3067 DAG.getIntPtrConstant(Idx)));
3069 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3071 DAG.getIntPtrConstant(Idx - NumElems)));
3074 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3075 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3076 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3077 Results.push_back(Tmp1);
3080 case ISD::EXTRACT_ELEMENT: {
3081 EVT OpTy = Node->getOperand(0).getValueType();
3082 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3084 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3085 DAG.getConstant(OpTy.getSizeInBits()/2,
3086 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3087 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3090 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3091 Node->getOperand(0));
3093 Results.push_back(Tmp1);
3096 case ISD::STACKSAVE:
3097 // Expand to CopyFromReg if the target set
3098 // StackPointerRegisterToSaveRestore.
3099 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3100 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3101 Node->getValueType(0)));
3102 Results.push_back(Results[0].getValue(1));
3104 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3105 Results.push_back(Node->getOperand(0));
3108 case ISD::STACKRESTORE:
3109 // Expand to CopyToReg if the target set
3110 // StackPointerRegisterToSaveRestore.
3111 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3112 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3113 Node->getOperand(1)));
3115 Results.push_back(Node->getOperand(0));
3118 case ISD::FCOPYSIGN:
3119 Results.push_back(ExpandFCOPYSIGN(Node));
3122 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3123 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3124 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3125 Node->getOperand(0));
3126 Results.push_back(Tmp1);
3129 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3130 EVT VT = Node->getValueType(0);
3131 Tmp1 = Node->getOperand(0);
3132 Tmp2 = DAG.getConstantFP(0.0, VT);
3133 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3134 Tmp1, Tmp2, ISD::SETUGT);
3135 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3136 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3137 Results.push_back(Tmp1);
3141 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3142 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3143 RTLIB::SQRT_PPCF128));
3147 EVT VT = Node->getValueType(0);
3148 bool isSIN = Node->getOpcode() == ISD::FSIN;
3149 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3150 // fcos which share the same operand and both are used.
3151 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3152 isSinCosLibcallAvailable(Node, TLI))
3153 && useSinCos(Node)) {
3154 SDVTList VTs = DAG.getVTList(VT, VT);
3155 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3157 Tmp1 = Tmp1.getValue(1);
3158 Results.push_back(Tmp1);
3160 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3161 RTLIB::SIN_F80, RTLIB::SIN_F128,
3162 RTLIB::SIN_PPCF128));
3164 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3165 RTLIB::COS_F80, RTLIB::COS_F128,
3166 RTLIB::COS_PPCF128));
3171 // Expand into sincos libcall.
3172 ExpandSinCosLibCall(Node, Results);
3175 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3176 RTLIB::LOG_F80, RTLIB::LOG_F128,
3177 RTLIB::LOG_PPCF128));
3180 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3181 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3182 RTLIB::LOG2_PPCF128));
3185 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3186 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3187 RTLIB::LOG10_PPCF128));
3190 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3191 RTLIB::EXP_F80, RTLIB::EXP_F128,
3192 RTLIB::EXP_PPCF128));
3195 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3196 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3197 RTLIB::EXP2_PPCF128));
3200 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3201 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3202 RTLIB::TRUNC_PPCF128));
3205 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3206 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3207 RTLIB::FLOOR_PPCF128));
3210 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3211 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3212 RTLIB::CEIL_PPCF128));
3215 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3216 RTLIB::RINT_F80, RTLIB::RINT_F128,
3217 RTLIB::RINT_PPCF128));
3219 case ISD::FNEARBYINT:
3220 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3221 RTLIB::NEARBYINT_F64,
3222 RTLIB::NEARBYINT_F80,
3223 RTLIB::NEARBYINT_F128,
3224 RTLIB::NEARBYINT_PPCF128));
3227 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3228 RTLIB::POWI_F80, RTLIB::POWI_F128,
3229 RTLIB::POWI_PPCF128));
3232 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3233 RTLIB::POW_F80, RTLIB::POW_F128,
3234 RTLIB::POW_PPCF128));
3237 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3238 RTLIB::DIV_F80, RTLIB::DIV_F128,
3239 RTLIB::DIV_PPCF128));
3242 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3243 RTLIB::REM_F80, RTLIB::REM_F128,
3244 RTLIB::REM_PPCF128));
3247 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3248 RTLIB::FMA_F80, RTLIB::FMA_F128,
3249 RTLIB::FMA_PPCF128));
3251 case ISD::FP16_TO_FP32:
3252 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3254 case ISD::FP32_TO_FP16:
3255 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3257 case ISD::ConstantFP: {
3258 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3259 // Check to see if this FP immediate is already legal.
3260 // If this is a legal constant, turn it into a TargetConstantFP node.
3261 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3262 Results.push_back(ExpandConstantFP(CFP, true));
3265 case ISD::EHSELECTION: {
3266 unsigned Reg = TLI.getExceptionSelectorRegister();
3267 assert(Reg && "Can't expand to unknown register!");
3268 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3269 Node->getValueType(0)));
3270 Results.push_back(Results[0].getValue(1));
3273 case ISD::EXCEPTIONADDR: {
3274 unsigned Reg = TLI.getExceptionPointerRegister();
3275 assert(Reg && "Can't expand to unknown register!");
3276 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3277 Node->getValueType(0)));
3278 Results.push_back(Results[0].getValue(1));
3282 EVT VT = Node->getValueType(0);
3283 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3284 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3285 "Don't know how to expand this FP subtraction!");
3286 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3287 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3288 Results.push_back(Tmp1);
3292 EVT VT = Node->getValueType(0);
3293 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3294 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3295 "Don't know how to expand this subtraction!");
3296 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3297 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3298 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3299 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3304 EVT VT = Node->getValueType(0);
3305 bool isSigned = Node->getOpcode() == ISD::SREM;
3306 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3307 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3308 Tmp2 = Node->getOperand(0);
3309 Tmp3 = Node->getOperand(1);
3310 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3311 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3312 // If div is legal, it's better to do the normal expansion
3313 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3314 useDivRem(Node, isSigned, false))) {
3315 SDVTList VTs = DAG.getVTList(VT, VT);
3316 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3317 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3319 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3320 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3321 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3322 } else if (isSigned)
3323 Tmp1 = ExpandIntLibCall(Node, true,
3325 RTLIB::SREM_I16, RTLIB::SREM_I32,
3326 RTLIB::SREM_I64, RTLIB::SREM_I128);
3328 Tmp1 = ExpandIntLibCall(Node, false,
3330 RTLIB::UREM_I16, RTLIB::UREM_I32,
3331 RTLIB::UREM_I64, RTLIB::UREM_I128);
3332 Results.push_back(Tmp1);
3337 bool isSigned = Node->getOpcode() == ISD::SDIV;
3338 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3339 EVT VT = Node->getValueType(0);
3340 SDVTList VTs = DAG.getVTList(VT, VT);
3341 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3342 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3343 useDivRem(Node, isSigned, true)))
3344 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3345 Node->getOperand(1));
3347 Tmp1 = ExpandIntLibCall(Node, true,
3349 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3350 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3352 Tmp1 = ExpandIntLibCall(Node, false,
3354 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3355 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3356 Results.push_back(Tmp1);
3361 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3363 EVT VT = Node->getValueType(0);
3364 SDVTList VTs = DAG.getVTList(VT, VT);
3365 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3366 "If this wasn't legal, it shouldn't have been created!");
3367 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3368 Node->getOperand(1));
3369 Results.push_back(Tmp1.getValue(1));
3374 // Expand into divrem libcall
3375 ExpandDivRemLibCall(Node, Results);
3378 EVT VT = Node->getValueType(0);
3379 SDVTList VTs = DAG.getVTList(VT, VT);
3380 // See if multiply or divide can be lowered using two-result operations.
3381 // We just need the low half of the multiply; try both the signed
3382 // and unsigned forms. If the target supports both SMUL_LOHI and
3383 // UMUL_LOHI, form a preference by checking which forms of plain
3384 // MULH it supports.
3385 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3386 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3387 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3388 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3389 unsigned OpToUse = 0;
3390 if (HasSMUL_LOHI && !HasMULHS) {
3391 OpToUse = ISD::SMUL_LOHI;
3392 } else if (HasUMUL_LOHI && !HasMULHU) {
3393 OpToUse = ISD::UMUL_LOHI;
3394 } else if (HasSMUL_LOHI) {
3395 OpToUse = ISD::SMUL_LOHI;
3396 } else if (HasUMUL_LOHI) {
3397 OpToUse = ISD::UMUL_LOHI;
3400 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3401 Node->getOperand(1)));
3404 Tmp1 = ExpandIntLibCall(Node, false,
3406 RTLIB::MUL_I16, RTLIB::MUL_I32,
3407 RTLIB::MUL_I64, RTLIB::MUL_I128);
3408 Results.push_back(Tmp1);
3413 SDValue LHS = Node->getOperand(0);
3414 SDValue RHS = Node->getOperand(1);
3415 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3416 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3418 Results.push_back(Sum);
3419 EVT OType = Node->getValueType(1);
3421 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3423 // LHSSign -> LHS >= 0
3424 // RHSSign -> RHS >= 0
3425 // SumSign -> Sum >= 0
3428 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3430 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3432 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3433 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3434 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3435 Node->getOpcode() == ISD::SADDO ?
3436 ISD::SETEQ : ISD::SETNE);
3438 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3439 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3441 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3442 Results.push_back(Cmp);
3447 SDValue LHS = Node->getOperand(0);
3448 SDValue RHS = Node->getOperand(1);
3449 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3450 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3452 Results.push_back(Sum);
3453 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3454 Node->getOpcode () == ISD::UADDO ?
3455 ISD::SETULT : ISD::SETUGT));
3460 EVT VT = Node->getValueType(0);
3461 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3462 SDValue LHS = Node->getOperand(0);
3463 SDValue RHS = Node->getOperand(1);
3466 static const unsigned Ops[2][3] =
3467 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3468 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3469 bool isSigned = Node->getOpcode() == ISD::SMULO;
3470 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3471 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3472 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3473 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3474 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3476 TopHalf = BottomHalf.getValue(1);
3477 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3478 VT.getSizeInBits() * 2))) {
3479 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3480 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3481 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3482 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3483 DAG.getIntPtrConstant(0));
3484 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3485 DAG.getIntPtrConstant(1));
3487 // We can fall back to a libcall with an illegal type for the MUL if we
3488 // have a libcall big enough.
3489 // Also, we can fall back to a division in some cases, but that's a big
3490 // performance hit in the general case.
3491 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3492 if (WideVT == MVT::i16)
3493 LC = RTLIB::MUL_I16;
3494 else if (WideVT == MVT::i32)
3495 LC = RTLIB::MUL_I32;
3496 else if (WideVT == MVT::i64)
3497 LC = RTLIB::MUL_I64;
3498 else if (WideVT == MVT::i128)
3499 LC = RTLIB::MUL_I128;
3500 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3502 // The high part is obtained by SRA'ing all but one of the bits of low
3504 unsigned LoSize = VT.getSizeInBits();
3505 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3506 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3507 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3508 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3510 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3511 // pre-lowered to the correct types. This all depends upon WideVT not
3512 // being a legal type for the architecture and thus has to be split to
3514 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3515 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3516 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3517 DAG.getIntPtrConstant(0));
3518 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3519 DAG.getIntPtrConstant(1));
3520 // Ret is a node with an illegal type. Because such things are not
3521 // generally permitted during this phase of legalization, delete the
3522 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3523 DAG.DeleteNode(Ret.getNode());
3527 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3528 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3529 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3530 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3533 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3534 DAG.getConstant(0, VT), ISD::SETNE);
3536 Results.push_back(BottomHalf);
3537 Results.push_back(TopHalf);
3540 case ISD::BUILD_PAIR: {
3541 EVT PairTy = Node->getValueType(0);
3542 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3543 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3544 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3545 DAG.getConstant(PairTy.getSizeInBits()/2,
3546 TLI.getShiftAmountTy(PairTy)));
3547 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3551 Tmp1 = Node->getOperand(0);
3552 Tmp2 = Node->getOperand(1);
3553 Tmp3 = Node->getOperand(2);
3554 if (Tmp1.getOpcode() == ISD::SETCC) {
3555 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3557 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3559 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3560 DAG.getConstant(0, Tmp1.getValueType()),
3561 Tmp2, Tmp3, ISD::SETNE);
3563 Results.push_back(Tmp1);
3566 SDValue Chain = Node->getOperand(0);
3567 SDValue Table = Node->getOperand(1);
3568 SDValue Index = Node->getOperand(2);
3570 EVT PTy = TLI.getPointerTy();
3572 const DataLayout &TD = *TLI.getDataLayout();
3573 unsigned EntrySize =
3574 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3576 Index = DAG.getNode(ISD::MUL, dl, PTy,
3577 Index, DAG.getConstant(EntrySize, PTy));
3578 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3580 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3581 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3582 MachinePointerInfo::getJumpTable(), MemVT,
3585 if (TM.getRelocationModel() == Reloc::PIC_) {
3586 // For PIC, the sequence is:
3587 // BRIND(load(Jumptable + index) + RelocBase)
3588 // RelocBase can be JumpTable, GOT or some sort of global base.
3589 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3590 TLI.getPICJumpTableRelocBase(Table, DAG));
3592 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3593 Results.push_back(Tmp1);
3597 // Expand brcond's setcc into its constituent parts and create a BR_CC
3599 Tmp1 = Node->getOperand(0);
3600 Tmp2 = Node->getOperand(1);
3601 if (Tmp2.getOpcode() == ISD::SETCC) {
3602 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3603 Tmp1, Tmp2.getOperand(2),
3604 Tmp2.getOperand(0), Tmp2.getOperand(1),
3605 Node->getOperand(2));
3607 // We test only the i1 bit. Skip the AND if UNDEF.
3608 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3609 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3610 DAG.getConstant(1, Tmp2.getValueType()));
3611 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3612 DAG.getCondCode(ISD::SETNE), Tmp3,
3613 DAG.getConstant(0, Tmp3.getValueType()),
3614 Node->getOperand(2));
3616 Results.push_back(Tmp1);
3619 Tmp1 = Node->getOperand(0);
3620 Tmp2 = Node->getOperand(1);
3621 Tmp3 = Node->getOperand(2);
3622 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3624 // If we expanded the SETCC into an AND/OR, return the new node
3625 if (Tmp2.getNode() == 0) {
3626 Results.push_back(Tmp1);
3630 // Otherwise, SETCC for the given comparison type must be completely
3631 // illegal; expand it into a SELECT_CC.
3632 EVT VT = Node->getValueType(0);
3633 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3634 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3635 Results.push_back(Tmp1);
3638 case ISD::SELECT_CC: {
3639 Tmp1 = Node->getOperand(0); // LHS
3640 Tmp2 = Node->getOperand(1); // RHS
3641 Tmp3 = Node->getOperand(2); // True
3642 Tmp4 = Node->getOperand(3); // False
3643 SDValue CC = Node->getOperand(4);
3645 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3646 Tmp1, Tmp2, CC, dl);
3648 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3649 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3650 CC = DAG.getCondCode(ISD::SETNE);
3651 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3653 Results.push_back(Tmp1);
3657 Tmp1 = Node->getOperand(0); // Chain
3658 Tmp2 = Node->getOperand(2); // LHS
3659 Tmp3 = Node->getOperand(3); // RHS
3660 Tmp4 = Node->getOperand(1); // CC
3662 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3663 Tmp2, Tmp3, Tmp4, dl);
3665 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3666 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3667 Tmp4 = DAG.getCondCode(ISD::SETNE);
3668 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3669 Tmp3, Node->getOperand(4));
3670 Results.push_back(Tmp1);
3673 case ISD::BUILD_VECTOR:
3674 Results.push_back(ExpandBUILD_VECTOR(Node));
3679 // Scalarize vector SRA/SRL/SHL.
3680 EVT VT = Node->getValueType(0);
3681 assert(VT.isVector() && "Unable to legalize non-vector shift");
3682 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3683 unsigned NumElem = VT.getVectorNumElements();
3685 SmallVector<SDValue, 8> Scalars;
3686 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3687 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3689 Node->getOperand(0), DAG.getIntPtrConstant(Idx));
3690 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3692 Node->getOperand(1), DAG.getIntPtrConstant(Idx));
3693 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3694 VT.getScalarType(), Ex, Sh));
3697 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3698 &Scalars[0], Scalars.size());
3699 ReplaceNode(SDValue(Node, 0), Result);
3702 case ISD::GLOBAL_OFFSET_TABLE:
3703 case ISD::GlobalAddress:
3704 case ISD::GlobalTLSAddress:
3705 case ISD::ExternalSymbol:
3706 case ISD::ConstantPool:
3707 case ISD::JumpTable:
3708 case ISD::INTRINSIC_W_CHAIN:
3709 case ISD::INTRINSIC_WO_CHAIN:
3710 case ISD::INTRINSIC_VOID:
3711 // FIXME: Custom lowering for these operations shouldn't return null!
3715 // Replace the original node with the legalized result.
3716 if (!Results.empty())
3717 ReplaceNode(Node, Results.data());
3720 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3721 SmallVector<SDValue, 8> Results;
3722 MVT OVT = Node->getSimpleValueType(0);
3723 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3724 Node->getOpcode() == ISD::SINT_TO_FP ||
3725 Node->getOpcode() == ISD::SETCC) {
3726 OVT = Node->getOperand(0).getSimpleValueType();
3728 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3729 DebugLoc dl = Node->getDebugLoc();
3730 SDValue Tmp1, Tmp2, Tmp3;
3731 switch (Node->getOpcode()) {
3733 case ISD::CTTZ_ZERO_UNDEF:
3735 case ISD::CTLZ_ZERO_UNDEF:
3737 // Zero extend the argument.
3738 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3739 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3740 // already the correct result.
3741 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3742 if (Node->getOpcode() == ISD::CTTZ) {
3743 // FIXME: This should set a bit in the zero extended value instead.
3744 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3745 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3747 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3748 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3749 } else if (Node->getOpcode() == ISD::CTLZ ||
3750 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3751 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3752 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3753 DAG.getConstant(NVT.getSizeInBits() -
3754 OVT.getSizeInBits(), NVT));
3756 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3759 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3760 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3761 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3762 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3763 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3764 Results.push_back(Tmp1);
3767 case ISD::FP_TO_UINT:
3768 case ISD::FP_TO_SINT:
3769 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3770 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3771 Results.push_back(Tmp1);
3773 case ISD::UINT_TO_FP:
3774 case ISD::SINT_TO_FP:
3775 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3776 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3777 Results.push_back(Tmp1);
3780 SDValue Chain = Node->getOperand(0); // Get the chain.
3781 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3784 if (OVT.isVector()) {
3785 TruncOp = ISD::BITCAST;
3787 assert(OVT.isInteger()
3788 && "VAARG promotion is supported only for vectors or integer types");
3789 TruncOp = ISD::TRUNCATE;
3792 // Perform the larger operation, then convert back
3793 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3794 Node->getConstantOperandVal(3));
3795 Chain = Tmp1.getValue(1);
3797 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3799 // Modified the chain result - switch anything that used the old chain to
3801 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3802 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3809 unsigned ExtOp, TruncOp;
3810 if (OVT.isVector()) {
3811 ExtOp = ISD::BITCAST;
3812 TruncOp = ISD::BITCAST;
3814 assert(OVT.isInteger() && "Cannot promote logic operation");
3815 ExtOp = ISD::ANY_EXTEND;
3816 TruncOp = ISD::TRUNCATE;
3818 // Promote each of the values to the new type.
3819 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3820 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3821 // Perform the larger operation, then convert back
3822 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3823 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3827 unsigned ExtOp, TruncOp;
3828 if (Node->getValueType(0).isVector()) {
3829 ExtOp = ISD::BITCAST;
3830 TruncOp = ISD::BITCAST;
3831 } else if (Node->getValueType(0).isInteger()) {
3832 ExtOp = ISD::ANY_EXTEND;
3833 TruncOp = ISD::TRUNCATE;
3835 ExtOp = ISD::FP_EXTEND;
3836 TruncOp = ISD::FP_ROUND;
3838 Tmp1 = Node->getOperand(0);
3839 // Promote each of the values to the new type.
3840 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3841 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3842 // Perform the larger operation, then round down.
3843 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3844 if (TruncOp != ISD::FP_ROUND)
3845 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3847 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3848 DAG.getIntPtrConstant(0));
3849 Results.push_back(Tmp1);
3852 case ISD::VECTOR_SHUFFLE: {
3853 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3855 // Cast the two input vectors.
3856 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3857 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3859 // Convert the shuffle mask to the right # elements.
3860 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3861 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3862 Results.push_back(Tmp1);
3866 unsigned ExtOp = ISD::FP_EXTEND;
3867 if (NVT.isInteger()) {
3868 ISD::CondCode CCCode =
3869 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3870 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3872 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3873 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3874 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3875 Tmp1, Tmp2, Node->getOperand(2)));
3881 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3882 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3883 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3884 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3885 Tmp3, DAG.getIntPtrConstant(0)));
3892 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3893 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3894 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3895 Tmp2, DAG.getIntPtrConstant(0)));
3900 // Replace the original node with the legalized result.
3901 if (!Results.empty())
3902 ReplaceNode(Node, Results.data());
3905 // SelectionDAG::Legalize - This is the entry point for the file.
3907 void SelectionDAG::Legalize() {
3908 /// run - This is the main entry point to this class.
3910 SelectionDAGLegalize(*this).LegalizeDAG();