1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetLowering.h"
35 #include "llvm/Target/TargetMachine.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
52 const TargetMachine &TM;
53 const TargetLowering &TLI;
56 /// LegalizePosition - The iterator for walking through the node list.
57 SelectionDAG::allnodes_iterator LegalizePosition;
59 /// LegalizedNodes - The set of nodes which have already been legalized.
60 SmallPtrSet<SDNode *, 16> LegalizedNodes;
62 EVT getSetCCResultType(EVT VT) const {
63 return TLI.getSetCCResultType(*DAG.getContext(), VT);
66 // Libcall insertion helpers.
69 explicit SelectionDAGLegalize(SelectionDAG &DAG);
74 /// LegalizeOp - Legalizes the given operation.
75 void LegalizeOp(SDNode *Node);
77 SDValue OptimizeFloatStore(StoreSDNode *ST);
79 void LegalizeLoadOps(SDNode *Node);
80 void LegalizeStoreOps(SDNode *Node);
82 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
83 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
84 /// is necessary to spill the vector being inserted into to memory, perform
85 /// the insert there, and then read the result back.
86 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
87 SDValue Idx, SDLoc dl);
88 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
89 SDValue Idx, SDLoc dl);
91 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
92 /// performs the same shuffe in terms of order or result bytes, but on a type
93 /// whose vector element type is narrower than the original shuffle type.
94 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
95 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
96 SDValue N1, SDValue N2,
97 ArrayRef<int> Mask) const;
99 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
100 bool &NeedInvert, SDLoc dl);
102 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
103 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
104 unsigned NumOps, bool isSigned, SDLoc dl);
106 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
107 SDNode *Node, bool isSigned);
108 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
109 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
110 RTLIB::Libcall Call_F128,
111 RTLIB::Libcall Call_PPCF128);
112 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
113 RTLIB::Libcall Call_I8,
114 RTLIB::Libcall Call_I16,
115 RTLIB::Libcall Call_I32,
116 RTLIB::Libcall Call_I64,
117 RTLIB::Libcall Call_I128);
118 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
119 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
121 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
122 SDValue ExpandBUILD_VECTOR(SDNode *Node);
123 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
124 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
125 SmallVectorImpl<SDValue> &Results);
126 SDValue ExpandFCOPYSIGN(SDNode *Node);
127 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
129 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
131 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
134 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
135 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
137 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
138 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
139 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
141 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
143 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
145 void ExpandNode(SDNode *Node);
146 void PromoteNode(SDNode *Node);
148 void ForgetNode(SDNode *N) {
149 LegalizedNodes.erase(N);
150 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
155 // DAGUpdateListener implementation.
156 void NodeDeleted(SDNode *N, SDNode *E) override {
159 void NodeUpdated(SDNode *N) override {}
161 // Node replacement helpers
162 void ReplacedNode(SDNode *N) {
163 if (N->use_empty()) {
164 DAG.RemoveDeadNode(N);
169 void ReplaceNode(SDNode *Old, SDNode *New) {
170 DAG.ReplaceAllUsesWith(Old, New);
173 void ReplaceNode(SDValue Old, SDValue New) {
174 DAG.ReplaceAllUsesWith(Old, New);
175 ReplacedNode(Old.getNode());
177 void ReplaceNode(SDNode *Old, const SDValue *New) {
178 DAG.ReplaceAllUsesWith(Old, New);
184 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
185 /// performs the same shuffe in terms of order or result bytes, but on a type
186 /// whose vector element type is narrower than the original shuffle type.
187 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
189 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
190 SDValue N1, SDValue N2,
191 ArrayRef<int> Mask) const {
192 unsigned NumMaskElts = VT.getVectorNumElements();
193 unsigned NumDestElts = NVT.getVectorNumElements();
194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
198 if (NumEltsGrowth == 1)
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
201 SmallVector<int, 8> NewMask;
202 for (unsigned i = 0; i != NumMaskElts; ++i) {
204 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
206 NewMask.push_back(-1);
208 NewMask.push_back(Idx * NumEltsGrowth + j);
211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
216 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
217 : SelectionDAG::DAGUpdateListener(dag),
218 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
222 void SelectionDAGLegalize::LegalizeDAG() {
223 DAG.AssignTopologicalOrder();
225 // Visit all the nodes. We start in topological order, so that we see
226 // nodes with their original operands intact. Legalization can produce
227 // new nodes which may themselves need to be legalized. Iterate until all
228 // nodes have been legalized.
230 bool AnyLegalized = false;
231 for (LegalizePosition = DAG.allnodes_end();
232 LegalizePosition != DAG.allnodes_begin(); ) {
235 SDNode *N = LegalizePosition;
236 if (LegalizedNodes.insert(N)) {
246 // Remove dead nodes now.
247 DAG.RemoveDeadNodes();
250 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
251 /// a load from the constant pool.
253 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
257 // If a FP immediate is precise when represented as a float and if the
258 // target can do an extending load from float to double, we put it into
259 // the constant pool as a float, even if it's is statically typed as a
260 // double. This shrinks FP constants and canonicalizes them for targets where
261 // an FP extending load is the same cost as a normal load (such as on the x87
262 // fp stack or PPC FP unit).
263 EVT VT = CFP->getValueType(0);
264 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
266 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
267 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
268 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
273 while (SVT != MVT::f32) {
274 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
275 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
276 // Only do this if the target has a native EXTLOAD instruction from
278 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
279 TLI.ShouldShrinkFPConstant(OrigVT)) {
280 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
281 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
287 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
288 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
291 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
293 CPIdx, MachinePointerInfo::getConstantPool(),
294 VT, false, false, Alignment);
298 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
299 MachinePointerInfo::getConstantPool(), false, false, false,
304 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
305 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
306 const TargetLowering &TLI,
307 SelectionDAGLegalize *DAGLegalize) {
308 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
309 "unaligned indexed stores not implemented!");
310 SDValue Chain = ST->getChain();
311 SDValue Ptr = ST->getBasePtr();
312 SDValue Val = ST->getValue();
313 EVT VT = Val.getValueType();
314 int Alignment = ST->getAlignment();
315 unsigned AS = ST->getAddressSpace();
318 if (ST->getMemoryVT().isFloatingPoint() ||
319 ST->getMemoryVT().isVector()) {
320 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
321 if (TLI.isTypeLegal(intVT)) {
322 // Expand to a bitconvert of the value to the integer type of the
323 // same size, then a (misaligned) int store.
324 // FIXME: Does not handle truncating floating point stores!
325 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
326 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
327 ST->isVolatile(), ST->isNonTemporal(), Alignment);
328 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
331 // Do a (aligned) store to a stack slot, then copy from the stack slot
332 // to the final destination using (unaligned) integer loads and stores.
333 EVT StoredVT = ST->getMemoryVT();
335 TLI.getRegisterType(*DAG.getContext(),
336 EVT::getIntegerVT(*DAG.getContext(),
337 StoredVT.getSizeInBits()));
338 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
339 unsigned RegBytes = RegVT.getSizeInBits() / 8;
340 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
342 // Make sure the stack slot is also aligned for the register type.
343 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
345 // Perform the original store, only redirected to the stack slot.
346 SDValue Store = DAG.getTruncStore(Chain, dl,
347 Val, StackPtr, MachinePointerInfo(),
348 StoredVT, false, false, 0);
349 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
350 SmallVector<SDValue, 8> Stores;
353 // Do all but one copies using the full register width.
354 for (unsigned i = 1; i < NumRegs; i++) {
355 // Load one integer register's worth from the stack slot.
356 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
357 MachinePointerInfo(),
358 false, false, false, 0);
359 // Store it to the final location. Remember the store.
360 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
361 ST->getPointerInfo().getWithOffset(Offset),
362 ST->isVolatile(), ST->isNonTemporal(),
363 MinAlign(ST->getAlignment(), Offset)));
364 // Increment the pointers.
366 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
368 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
371 // The last store may be partial. Do a truncating store. On big-endian
372 // machines this requires an extending load from the stack slot to ensure
373 // that the bits are in the right place.
374 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
375 8 * (StoredBytes - Offset));
377 // Load from the stack slot.
378 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
379 MachinePointerInfo(),
380 MemVT, false, false, 0);
382 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
384 .getWithOffset(Offset),
385 MemVT, ST->isVolatile(),
387 MinAlign(ST->getAlignment(), Offset),
389 // The order of the stores doesn't matter - say it with a TokenFactor.
390 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
391 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
394 assert(ST->getMemoryVT().isInteger() &&
395 !ST->getMemoryVT().isVector() &&
396 "Unaligned store of unknown type.");
397 // Get the half-size VT
398 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
399 int NumBits = NewStoredVT.getSizeInBits();
400 int IncrementSize = NumBits / 8;
402 // Divide the stored value in two parts.
403 SDValue ShiftAmount = DAG.getConstant(NumBits,
404 TLI.getShiftAmountTy(Val.getValueType()));
406 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
408 // Store the two parts
409 SDValue Store1, Store2;
410 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
411 ST->getPointerInfo(), NewStoredVT,
412 ST->isVolatile(), ST->isNonTemporal(), Alignment);
414 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
415 DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
416 Alignment = MinAlign(Alignment, IncrementSize);
417 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
418 ST->getPointerInfo().getWithOffset(IncrementSize),
419 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
420 Alignment, ST->getTBAAInfo());
423 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
424 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
427 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
429 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
430 const TargetLowering &TLI,
431 SDValue &ValResult, SDValue &ChainResult) {
432 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
433 "unaligned indexed loads not implemented!");
434 SDValue Chain = LD->getChain();
435 SDValue Ptr = LD->getBasePtr();
436 EVT VT = LD->getValueType(0);
437 EVT LoadedVT = LD->getMemoryVT();
439 if (VT.isFloatingPoint() || VT.isVector()) {
440 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
441 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
442 // Expand to a (misaligned) integer load of the same size,
443 // then bitconvert to floating point or vector.
444 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
445 LD->getMemOperand());
446 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
448 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
449 ISD::ANY_EXTEND, dl, VT, Result);
456 // Copy the value to a (aligned) stack slot using (unaligned) integer
457 // loads and stores, then do a (aligned) load from the stack slot.
458 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
459 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
460 unsigned RegBytes = RegVT.getSizeInBits() / 8;
461 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
463 // Make sure the stack slot is also aligned for the register type.
464 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
466 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
467 SmallVector<SDValue, 8> Stores;
468 SDValue StackPtr = StackBase;
471 // Do all but one copies using the full register width.
472 for (unsigned i = 1; i < NumRegs; i++) {
473 // Load one integer register's worth from the original location.
474 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
475 LD->getPointerInfo().getWithOffset(Offset),
476 LD->isVolatile(), LD->isNonTemporal(),
478 MinAlign(LD->getAlignment(), Offset),
480 // Follow the load with a store to the stack slot. Remember the store.
481 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
482 MachinePointerInfo(), false, false, 0));
483 // Increment the pointers.
485 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
486 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
490 // The last copy may be partial. Do an extending load.
491 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
492 8 * (LoadedBytes - Offset));
493 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
494 LD->getPointerInfo().getWithOffset(Offset),
495 MemVT, LD->isVolatile(),
497 MinAlign(LD->getAlignment(), Offset),
499 // Follow the load with a store to the stack slot. Remember the store.
500 // On big-endian machines this requires a truncating store to ensure
501 // that the bits end up in the right place.
502 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
503 MachinePointerInfo(), MemVT,
506 // The order of the stores doesn't matter - say it with a TokenFactor.
507 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
509 // Finally, perform the original load only redirected to the stack slot.
510 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
511 MachinePointerInfo(), LoadedVT, false, false, 0);
513 // Callers expect a MERGE_VALUES node.
518 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
519 "Unaligned load of unsupported type.");
521 // Compute the new VT that is half the size of the old one. This is an
523 unsigned NumBits = LoadedVT.getSizeInBits();
525 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
528 unsigned Alignment = LD->getAlignment();
529 unsigned IncrementSize = NumBits / 8;
530 ISD::LoadExtType HiExtType = LD->getExtensionType();
532 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
533 if (HiExtType == ISD::NON_EXTLOAD)
534 HiExtType = ISD::ZEXTLOAD;
536 // Load the value in two parts
538 if (TLI.isLittleEndian()) {
539 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
540 NewLoadedVT, LD->isVolatile(),
541 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
542 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
543 DAG.getConstant(IncrementSize, Ptr.getValueType()));
544 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
545 LD->getPointerInfo().getWithOffset(IncrementSize),
546 NewLoadedVT, LD->isVolatile(),
547 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
550 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
551 NewLoadedVT, LD->isVolatile(),
552 LD->isNonTemporal(), Alignment, LD->getTBAAInfo());
553 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
554 DAG.getConstant(IncrementSize, Ptr.getValueType()));
555 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
556 LD->getPointerInfo().getWithOffset(IncrementSize),
557 NewLoadedVT, LD->isVolatile(),
558 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize),
562 // aggregate the two parts
563 SDValue ShiftAmount = DAG.getConstant(NumBits,
564 TLI.getShiftAmountTy(Hi.getValueType()));
565 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
566 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
568 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
575 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
576 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
577 /// is necessary to spill the vector being inserted into to memory, perform
578 /// the insert there, and then read the result back.
579 SDValue SelectionDAGLegalize::
580 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
586 // If the target doesn't support this, we have to spill the input vector
587 // to a temporary stack slot, update the element, then reload it. This is
588 // badness. We could also load the value into a vector register (either
589 // with a "move to register" or "extload into register" instruction, then
590 // permute it into place, if the idx is a constant and if the idx is
591 // supported by the target.
592 EVT VT = Tmp1.getValueType();
593 EVT EltVT = VT.getVectorElementType();
594 EVT IdxVT = Tmp3.getValueType();
595 EVT PtrVT = TLI.getPointerTy();
596 SDValue StackPtr = DAG.CreateStackTemporary(VT);
598 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
601 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
602 MachinePointerInfo::getFixedStack(SPFI),
605 // Truncate or zero extend offset to target pointer type.
606 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
607 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
608 // Add the offset to the index.
609 unsigned EltSize = EltVT.getSizeInBits()/8;
610 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
611 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
612 // Store the scalar value.
613 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
615 // Load the updated vector.
616 return DAG.getLoad(VT, dl, Ch, StackPtr,
617 MachinePointerInfo::getFixedStack(SPFI), false, false,
622 SDValue SelectionDAGLegalize::
623 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
624 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
625 // SCALAR_TO_VECTOR requires that the type of the value being inserted
626 // match the element type of the vector being created, except for
627 // integers in which case the inserted value can be over width.
628 EVT EltVT = Vec.getValueType().getVectorElementType();
629 if (Val.getValueType() == EltVT ||
630 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
631 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
632 Vec.getValueType(), Val);
634 unsigned NumElts = Vec.getValueType().getVectorNumElements();
635 // We generate a shuffle of InVec and ScVec, so the shuffle mask
636 // should be 0,1,2,3,4,5... with the appropriate element replaced with
638 SmallVector<int, 8> ShufOps;
639 for (unsigned i = 0; i != NumElts; ++i)
640 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
642 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
646 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
649 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
650 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
651 // FIXME: We shouldn't do this for TargetConstantFP's.
652 // FIXME: move this to the DAG Combiner! Note that we can't regress due
653 // to phase ordering between legalized code and the dag combiner. This
654 // probably means that we need to integrate dag combiner and legalizer
656 // We generally can't do this one for long doubles.
657 SDValue Chain = ST->getChain();
658 SDValue Ptr = ST->getBasePtr();
659 unsigned Alignment = ST->getAlignment();
660 bool isVolatile = ST->isVolatile();
661 bool isNonTemporal = ST->isNonTemporal();
662 const MDNode *TBAAInfo = ST->getTBAAInfo();
664 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
665 if (CFP->getValueType(0) == MVT::f32 &&
666 TLI.isTypeLegal(MVT::i32)) {
667 SDValue Con = DAG.getConstant(CFP->getValueAPF().
668 bitcastToAPInt().zextOrTrunc(32),
670 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
671 isVolatile, isNonTemporal, Alignment, TBAAInfo);
674 if (CFP->getValueType(0) == MVT::f64) {
675 // If this target supports 64-bit registers, do a single 64-bit store.
676 if (TLI.isTypeLegal(MVT::i64)) {
677 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
678 zextOrTrunc(64), MVT::i64);
679 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
680 isVolatile, isNonTemporal, Alignment, TBAAInfo);
683 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
684 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
685 // stores. If the target supports neither 32- nor 64-bits, this
686 // xform is certainly not worth it.
687 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
688 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
689 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
690 if (TLI.isBigEndian()) std::swap(Lo, Hi);
692 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
693 isNonTemporal, Alignment, TBAAInfo);
694 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
695 DAG.getConstant(4, Ptr.getValueType()));
696 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
697 ST->getPointerInfo().getWithOffset(4),
698 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
701 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
705 return SDValue(nullptr, 0);
708 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
709 StoreSDNode *ST = cast<StoreSDNode>(Node);
710 SDValue Chain = ST->getChain();
711 SDValue Ptr = ST->getBasePtr();
714 unsigned Alignment = ST->getAlignment();
715 bool isVolatile = ST->isVolatile();
716 bool isNonTemporal = ST->isNonTemporal();
717 const MDNode *TBAAInfo = ST->getTBAAInfo();
719 if (!ST->isTruncatingStore()) {
720 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
721 ReplaceNode(ST, OptStore);
726 SDValue Value = ST->getValue();
727 MVT VT = Value.getSimpleValueType();
728 switch (TLI.getOperationAction(ISD::STORE, VT)) {
729 default: llvm_unreachable("This action is not supported yet!");
730 case TargetLowering::Legal: {
731 // If this is an unaligned store and the target doesn't support it,
733 unsigned AS = ST->getAddressSpace();
734 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
735 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
736 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
737 if (ST->getAlignment() < ABIAlignment)
738 ExpandUnalignedStore(cast<StoreSDNode>(Node),
743 case TargetLowering::Custom: {
744 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
746 ReplaceNode(SDValue(Node, 0), Res);
749 case TargetLowering::Promote: {
750 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
751 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
752 "Can only promote stores to same size type");
753 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
755 DAG.getStore(Chain, dl, Value, Ptr,
756 ST->getPointerInfo(), isVolatile,
757 isNonTemporal, Alignment, TBAAInfo);
758 ReplaceNode(SDValue(Node, 0), Result);
765 SDValue Value = ST->getValue();
767 EVT StVT = ST->getMemoryVT();
768 unsigned StWidth = StVT.getSizeInBits();
770 if (StWidth != StVT.getStoreSizeInBits()) {
771 // Promote to a byte-sized store with upper bits zero if not
772 // storing an integral number of bytes. For example, promote
773 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
774 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
775 StVT.getStoreSizeInBits());
776 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
778 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
779 NVT, isVolatile, isNonTemporal, Alignment,
781 ReplaceNode(SDValue(Node, 0), Result);
782 } else if (StWidth & (StWidth - 1)) {
783 // If not storing a power-of-2 number of bits, expand as two stores.
784 assert(!StVT.isVector() && "Unsupported truncstore!");
785 unsigned RoundWidth = 1 << Log2_32(StWidth);
786 assert(RoundWidth < StWidth);
787 unsigned ExtraWidth = StWidth - RoundWidth;
788 assert(ExtraWidth < RoundWidth);
789 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
790 "Store size not an integral number of bytes!");
791 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
792 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
794 unsigned IncrementSize;
796 if (TLI.isLittleEndian()) {
797 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
798 // Store the bottom RoundWidth bits.
799 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
801 isVolatile, isNonTemporal, Alignment,
804 // Store the remaining ExtraWidth bits.
805 IncrementSize = RoundWidth / 8;
806 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
807 DAG.getConstant(IncrementSize, Ptr.getValueType()));
808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
809 DAG.getConstant(RoundWidth,
810 TLI.getShiftAmountTy(Value.getValueType())));
811 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
812 ST->getPointerInfo().getWithOffset(IncrementSize),
813 ExtraVT, isVolatile, isNonTemporal,
814 MinAlign(Alignment, IncrementSize), TBAAInfo);
816 // Big endian - avoid unaligned stores.
817 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
818 // Store the top RoundWidth bits.
819 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
820 DAG.getConstant(ExtraWidth,
821 TLI.getShiftAmountTy(Value.getValueType())));
822 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
823 RoundVT, isVolatile, isNonTemporal, Alignment,
826 // Store the remaining ExtraWidth bits.
827 IncrementSize = RoundWidth / 8;
828 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
829 DAG.getConstant(IncrementSize, Ptr.getValueType()));
830 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
831 ST->getPointerInfo().getWithOffset(IncrementSize),
832 ExtraVT, isVolatile, isNonTemporal,
833 MinAlign(Alignment, IncrementSize), TBAAInfo);
836 // The order of the stores doesn't matter.
837 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
838 ReplaceNode(SDValue(Node, 0), Result);
840 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
841 StVT.getSimpleVT())) {
842 default: llvm_unreachable("This action is not supported yet!");
843 case TargetLowering::Legal: {
844 unsigned AS = ST->getAddressSpace();
845 // If this is an unaligned store and the target doesn't support it,
847 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT(), AS)) {
848 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
849 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
850 if (ST->getAlignment() < ABIAlignment)
851 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
855 case TargetLowering::Custom: {
856 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
858 ReplaceNode(SDValue(Node, 0), Res);
861 case TargetLowering::Expand:
862 assert(!StVT.isVector() &&
863 "Vector Stores are handled in LegalizeVectorOps");
865 // TRUNCSTORE:i16 i32 -> STORE i16
866 assert(TLI.isTypeLegal(StVT) &&
867 "Do not know how to expand this store!");
868 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
870 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
871 isVolatile, isNonTemporal, Alignment, TBAAInfo);
872 ReplaceNode(SDValue(Node, 0), Result);
879 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
880 LoadSDNode *LD = cast<LoadSDNode>(Node);
881 SDValue Chain = LD->getChain(); // The chain.
882 SDValue Ptr = LD->getBasePtr(); // The base pointer.
883 SDValue Value; // The value returned by the load op.
886 ISD::LoadExtType ExtType = LD->getExtensionType();
887 if (ExtType == ISD::NON_EXTLOAD) {
888 MVT VT = Node->getSimpleValueType(0);
889 SDValue RVal = SDValue(Node, 0);
890 SDValue RChain = SDValue(Node, 1);
892 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
893 default: llvm_unreachable("This action is not supported yet!");
894 case TargetLowering::Legal: {
895 unsigned AS = LD->getAddressSpace();
896 // If this is an unaligned load and the target doesn't support it,
898 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT(), AS)) {
899 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
900 unsigned ABIAlignment =
901 TLI.getDataLayout()->getABITypeAlignment(Ty);
902 if (LD->getAlignment() < ABIAlignment){
903 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
908 case TargetLowering::Custom: {
909 SDValue Res = TLI.LowerOperation(RVal, DAG);
912 RChain = Res.getValue(1);
916 case TargetLowering::Promote: {
917 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
918 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
919 "Can only promote loads to same size type");
921 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
922 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
923 RChain = Res.getValue(1);
927 if (RChain.getNode() != Node) {
928 assert(RVal.getNode() != Node && "Load must be completely replaced");
929 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
930 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
936 EVT SrcVT = LD->getMemoryVT();
937 unsigned SrcWidth = SrcVT.getSizeInBits();
938 unsigned Alignment = LD->getAlignment();
939 bool isVolatile = LD->isVolatile();
940 bool isNonTemporal = LD->isNonTemporal();
941 const MDNode *TBAAInfo = LD->getTBAAInfo();
943 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
944 // Some targets pretend to have an i1 loading operation, and actually
945 // load an i8. This trick is correct for ZEXTLOAD because the top 7
946 // bits are guaranteed to be zero; it helps the optimizers understand
947 // that these bits are zero. It is also useful for EXTLOAD, since it
948 // tells the optimizers that those bits are undefined. It would be
949 // nice to have an effective generic way of getting these benefits...
950 // Until such a way is found, don't insist on promoting i1 here.
952 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
953 // Promote to a byte-sized load if not loading an integral number of
954 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
955 unsigned NewWidth = SrcVT.getStoreSizeInBits();
956 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
959 // The extra bits are guaranteed to be zero, since we stored them that
960 // way. A zext load from NVT thus automatically gives zext from SrcVT.
962 ISD::LoadExtType NewExtType =
963 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
966 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
967 Chain, Ptr, LD->getPointerInfo(),
968 NVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
970 Ch = Result.getValue(1); // The chain.
972 if (ExtType == ISD::SEXTLOAD)
973 // Having the top bits zero doesn't help when sign extending.
974 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
975 Result.getValueType(),
976 Result, DAG.getValueType(SrcVT));
977 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
978 // All the top bits are guaranteed to be zero - inform the optimizers.
979 Result = DAG.getNode(ISD::AssertZext, dl,
980 Result.getValueType(), Result,
981 DAG.getValueType(SrcVT));
985 } else if (SrcWidth & (SrcWidth - 1)) {
986 // If not loading a power-of-2 number of bits, expand as two loads.
987 assert(!SrcVT.isVector() && "Unsupported extload!");
988 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
989 assert(RoundWidth < SrcWidth);
990 unsigned ExtraWidth = SrcWidth - RoundWidth;
991 assert(ExtraWidth < RoundWidth);
992 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
993 "Load size not an integral number of bytes!");
994 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
995 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
997 unsigned IncrementSize;
999 if (TLI.isLittleEndian()) {
1000 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1001 // Load the bottom RoundWidth bits.
1002 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1004 LD->getPointerInfo(), RoundVT, isVolatile,
1005 isNonTemporal, Alignment, TBAAInfo);
1007 // Load the remaining ExtraWidth bits.
1008 IncrementSize = RoundWidth / 8;
1009 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1010 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1011 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1012 LD->getPointerInfo().getWithOffset(IncrementSize),
1013 ExtraVT, isVolatile, isNonTemporal,
1014 MinAlign(Alignment, IncrementSize), TBAAInfo);
1016 // Build a factor node to remember that this load is independent of
1018 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1021 // Move the top bits to the right place.
1022 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1023 DAG.getConstant(RoundWidth,
1024 TLI.getShiftAmountTy(Hi.getValueType())));
1026 // Join the hi and lo parts.
1027 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1029 // Big endian - avoid unaligned loads.
1030 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1031 // Load the top RoundWidth bits.
1032 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1033 LD->getPointerInfo(), RoundVT, isVolatile,
1034 isNonTemporal, Alignment, TBAAInfo);
1036 // Load the remaining ExtraWidth bits.
1037 IncrementSize = RoundWidth / 8;
1038 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1039 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1040 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1041 dl, Node->getValueType(0), Chain, Ptr,
1042 LD->getPointerInfo().getWithOffset(IncrementSize),
1043 ExtraVT, isVolatile, isNonTemporal,
1044 MinAlign(Alignment, IncrementSize), TBAAInfo);
1046 // Build a factor node to remember that this load is independent of
1048 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1051 // Move the top bits to the right place.
1052 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1053 DAG.getConstant(ExtraWidth,
1054 TLI.getShiftAmountTy(Hi.getValueType())));
1056 // Join the hi and lo parts.
1057 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1062 bool isCustom = false;
1063 switch (TLI.getLoadExtAction(ExtType, SrcVT.getSimpleVT())) {
1064 default: llvm_unreachable("This action is not supported yet!");
1065 case TargetLowering::Custom:
1068 case TargetLowering::Legal: {
1069 Value = SDValue(Node, 0);
1070 Chain = SDValue(Node, 1);
1073 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1074 if (Res.getNode()) {
1076 Chain = Res.getValue(1);
1079 // If this is an unaligned load and the target doesn't support
1081 EVT MemVT = LD->getMemoryVT();
1082 unsigned AS = LD->getAddressSpace();
1083 if (!TLI.allowsUnalignedMemoryAccesses(MemVT, AS)) {
1085 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1086 unsigned ABIAlignment =
1087 TLI.getDataLayout()->getABITypeAlignment(Ty);
1088 if (LD->getAlignment() < ABIAlignment){
1089 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1090 DAG, TLI, Value, Chain);
1096 case TargetLowering::Expand:
1097 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) &&
1098 TLI.isTypeLegal(SrcVT)) {
1099 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1100 LD->getMemOperand());
1104 ExtendOp = (SrcVT.isFloatingPoint() ?
1105 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1107 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1108 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1109 default: llvm_unreachable("Unexpected extend load type!");
1111 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1112 Chain = Load.getValue(1);
1116 assert(!SrcVT.isVector() &&
1117 "Vector Loads are handled in LegalizeVectorOps");
1119 // FIXME: This does not work for vectors on most targets. Sign-
1120 // and zero-extend operations are currently folded into extending
1121 // loads, whether they are legal or not, and then we end up here
1122 // without any support for legalizing them.
1123 assert(ExtType != ISD::EXTLOAD &&
1124 "EXTLOAD should always be supported!");
1125 // Turn the unsupported load into an EXTLOAD followed by an
1126 // explicit zero/sign extend inreg.
1127 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1128 Node->getValueType(0),
1130 LD->getMemOperand());
1132 if (ExtType == ISD::SEXTLOAD)
1133 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1134 Result.getValueType(),
1135 Result, DAG.getValueType(SrcVT));
1137 ValRes = DAG.getZeroExtendInReg(Result, dl,
1138 SrcVT.getScalarType());
1140 Chain = Result.getValue(1);
1145 // Since loads produce two values, make sure to remember that we legalized
1147 if (Chain.getNode() != Node) {
1148 assert(Value.getNode() != Node && "Load must be completely replaced");
1149 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1150 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1155 /// LegalizeOp - Return a legal replacement for the given operation, with
1156 /// all legal operands.
1157 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1158 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1161 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1162 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1163 TargetLowering::TypeLegal &&
1164 "Unexpected illegal type!");
1166 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1167 assert((TLI.getTypeAction(*DAG.getContext(),
1168 Node->getOperand(i).getValueType()) ==
1169 TargetLowering::TypeLegal ||
1170 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1171 "Unexpected illegal type!");
1173 // Figure out the correct action; the way to query this varies by opcode
1174 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1175 bool SimpleFinishLegalizing = true;
1176 switch (Node->getOpcode()) {
1177 case ISD::INTRINSIC_W_CHAIN:
1178 case ISD::INTRINSIC_WO_CHAIN:
1179 case ISD::INTRINSIC_VOID:
1180 case ISD::STACKSAVE:
1181 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1184 Action = TLI.getOperationAction(Node->getOpcode(),
1185 Node->getValueType(0));
1186 if (Action != TargetLowering::Promote)
1187 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1189 case ISD::SINT_TO_FP:
1190 case ISD::UINT_TO_FP:
1191 case ISD::EXTRACT_VECTOR_ELT:
1192 Action = TLI.getOperationAction(Node->getOpcode(),
1193 Node->getOperand(0).getValueType());
1195 case ISD::FP_ROUND_INREG:
1196 case ISD::SIGN_EXTEND_INREG: {
1197 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1198 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1201 case ISD::ATOMIC_STORE: {
1202 Action = TLI.getOperationAction(Node->getOpcode(),
1203 Node->getOperand(2).getValueType());
1206 case ISD::SELECT_CC:
1209 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1210 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1211 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1212 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1213 ISD::CondCode CCCode =
1214 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1215 Action = TLI.getCondCodeAction(CCCode, OpVT);
1216 if (Action == TargetLowering::Legal) {
1217 if (Node->getOpcode() == ISD::SELECT_CC)
1218 Action = TLI.getOperationAction(Node->getOpcode(),
1219 Node->getValueType(0));
1221 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1227 // FIXME: Model these properly. LOAD and STORE are complicated, and
1228 // STORE expects the unlegalized operand in some cases.
1229 SimpleFinishLegalizing = false;
1231 case ISD::CALLSEQ_START:
1232 case ISD::CALLSEQ_END:
1233 // FIXME: This shouldn't be necessary. These nodes have special properties
1234 // dealing with the recursive nature of legalization. Removing this
1235 // special case should be done as part of making LegalizeDAG non-recursive.
1236 SimpleFinishLegalizing = false;
1238 case ISD::EXTRACT_ELEMENT:
1239 case ISD::FLT_ROUNDS_:
1247 case ISD::MERGE_VALUES:
1248 case ISD::EH_RETURN:
1249 case ISD::FRAME_TO_ARGS_OFFSET:
1250 case ISD::EH_SJLJ_SETJMP:
1251 case ISD::EH_SJLJ_LONGJMP:
1252 // These operations lie about being legal: when they claim to be legal,
1253 // they should actually be expanded.
1254 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1255 if (Action == TargetLowering::Legal)
1256 Action = TargetLowering::Expand;
1258 case ISD::INIT_TRAMPOLINE:
1259 case ISD::ADJUST_TRAMPOLINE:
1260 case ISD::FRAMEADDR:
1261 case ISD::RETURNADDR:
1262 // These operations lie about being legal: when they claim to be legal,
1263 // they should actually be custom-lowered.
1264 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1265 if (Action == TargetLowering::Legal)
1266 Action = TargetLowering::Custom;
1268 case ISD::DEBUGTRAP:
1269 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1270 if (Action == TargetLowering::Expand) {
1271 // replace ISD::DEBUGTRAP with ISD::TRAP
1273 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1274 Node->getOperand(0));
1275 ReplaceNode(Node, NewVal.getNode());
1276 LegalizeOp(NewVal.getNode());
1282 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1283 Action = TargetLowering::Legal;
1285 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1290 if (SimpleFinishLegalizing) {
1291 SDNode *NewNode = Node;
1292 switch (Node->getOpcode()) {
1299 // Legalizing shifts/rotates requires adjusting the shift amount
1300 // to the appropriate width.
1301 if (!Node->getOperand(1).getValueType().isVector()) {
1303 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1304 Node->getOperand(1));
1305 HandleSDNode Handle(SAO);
1306 LegalizeOp(SAO.getNode());
1307 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1311 case ISD::SRL_PARTS:
1312 case ISD::SRA_PARTS:
1313 case ISD::SHL_PARTS:
1314 // Legalizing shifts/rotates requires adjusting the shift amount
1315 // to the appropriate width.
1316 if (!Node->getOperand(2).getValueType().isVector()) {
1318 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1319 Node->getOperand(2));
1320 HandleSDNode Handle(SAO);
1321 LegalizeOp(SAO.getNode());
1322 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1323 Node->getOperand(1),
1329 if (NewNode != Node) {
1330 DAG.ReplaceAllUsesWith(Node, NewNode);
1331 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1332 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1337 case TargetLowering::Legal:
1339 case TargetLowering::Custom: {
1340 // FIXME: The handling for custom lowering with multiple results is
1342 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1343 if (Res.getNode()) {
1344 SmallVector<SDValue, 8> ResultVals;
1345 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1347 ResultVals.push_back(Res);
1349 ResultVals.push_back(Res.getValue(i));
1351 if (Res.getNode() != Node || Res.getResNo() != 0) {
1352 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1353 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1354 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1361 case TargetLowering::Expand:
1364 case TargetLowering::Promote:
1370 switch (Node->getOpcode()) {
1377 llvm_unreachable("Do not know how to legalize this operator!");
1379 case ISD::CALLSEQ_START:
1380 case ISD::CALLSEQ_END:
1383 return LegalizeLoadOps(Node);
1386 return LegalizeStoreOps(Node);
1391 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1392 SDValue Vec = Op.getOperand(0);
1393 SDValue Idx = Op.getOperand(1);
1396 // Before we generate a new store to a temporary stack slot, see if there is
1397 // already one that we can use. There often is because when we scalarize
1398 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1399 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1400 // the vector. If all are expanded here, we don't want one store per vector
1402 SDValue StackPtr, Ch;
1403 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1404 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1406 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1407 if (ST->isIndexed() || ST->isTruncatingStore() ||
1408 ST->getValue() != Vec)
1411 // Make sure that nothing else could have stored into the destination of
1413 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1416 StackPtr = ST->getBasePtr();
1417 Ch = SDValue(ST, 0);
1422 if (!Ch.getNode()) {
1423 // Store the value to a temporary stack slot, then LOAD the returned part.
1424 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1425 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1426 MachinePointerInfo(), false, false, 0);
1429 // Add the offset to the index.
1431 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1432 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1433 DAG.getConstant(EltSize, Idx.getValueType()));
1435 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1436 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1438 if (Op.getValueType().isVector())
1439 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1440 false, false, false, 0);
1441 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1442 MachinePointerInfo(),
1443 Vec.getValueType().getVectorElementType(),
1447 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1448 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1450 SDValue Vec = Op.getOperand(0);
1451 SDValue Part = Op.getOperand(1);
1452 SDValue Idx = Op.getOperand(2);
1455 // Store the value to a temporary stack slot, then LOAD the returned part.
1457 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1458 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1459 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1461 // First store the whole vector.
1462 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1465 // Then store the inserted part.
1467 // Add the offset to the index.
1469 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1471 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1472 DAG.getConstant(EltSize, Idx.getValueType()));
1473 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1475 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1478 // Store the subvector.
1479 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1480 MachinePointerInfo(), false, false, 0);
1482 // Finally, load the updated vector.
1483 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1484 false, false, false, 0);
1487 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1488 // We can't handle this case efficiently. Allocate a sufficiently
1489 // aligned object on the stack, store each element into it, then load
1490 // the result as a vector.
1491 // Create the stack frame object.
1492 EVT VT = Node->getValueType(0);
1493 EVT EltVT = VT.getVectorElementType();
1495 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1496 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1497 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1499 // Emit a store of each element to the stack slot.
1500 SmallVector<SDValue, 8> Stores;
1501 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1502 // Store (in the right endianness) the elements to memory.
1503 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1504 // Ignore undef elements.
1505 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1507 unsigned Offset = TypeByteSize*i;
1509 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1510 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1512 // If the destination vector element type is narrower than the source
1513 // element type, only store the bits necessary.
1514 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1515 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1516 Node->getOperand(i), Idx,
1517 PtrInfo.getWithOffset(Offset),
1518 EltVT, false, false, 0));
1520 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1521 Node->getOperand(i), Idx,
1522 PtrInfo.getWithOffset(Offset),
1527 if (!Stores.empty()) // Not all undef elements?
1528 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1530 StoreChain = DAG.getEntryNode();
1532 // Result is a load from the stack slot.
1533 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1534 false, false, false, 0);
1537 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1539 SDValue Tmp1 = Node->getOperand(0);
1540 SDValue Tmp2 = Node->getOperand(1);
1542 // Get the sign bit of the RHS. First obtain a value that has the same
1543 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1545 EVT FloatVT = Tmp2.getValueType();
1546 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1547 if (TLI.isTypeLegal(IVT)) {
1548 // Convert to an integer with the same sign bit.
1549 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1551 // Store the float to memory, then load the sign part out as an integer.
1552 MVT LoadTy = TLI.getPointerTy();
1553 // First create a temporary that is aligned for both the load and store.
1554 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1555 // Then store the float to it.
1557 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1559 if (TLI.isBigEndian()) {
1560 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1561 // Load out a legal integer with the same sign bit as the float.
1562 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1563 false, false, false, 0);
1564 } else { // Little endian
1565 SDValue LoadPtr = StackPtr;
1566 // The float may be wider than the integer we are going to load. Advance
1567 // the pointer so that the loaded integer will contain the sign bit.
1568 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1569 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1570 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1571 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1572 // Load a legal integer containing the sign bit.
1573 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1574 false, false, false, 0);
1575 // Move the sign bit to the top bit of the loaded integer.
1576 unsigned BitShift = LoadTy.getSizeInBits() -
1577 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1578 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1580 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1581 DAG.getConstant(BitShift,
1582 TLI.getShiftAmountTy(SignBit.getValueType())));
1585 // Now get the sign bit proper, by seeing whether the value is negative.
1586 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1587 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1589 // Get the absolute value of the result.
1590 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1591 // Select between the nabs and abs value based on the sign bit of
1593 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1594 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1598 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1599 SmallVectorImpl<SDValue> &Results) {
1600 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1601 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1602 " not tell us which reg is the stack pointer!");
1604 EVT VT = Node->getValueType(0);
1605 SDValue Tmp1 = SDValue(Node, 0);
1606 SDValue Tmp2 = SDValue(Node, 1);
1607 SDValue Tmp3 = Node->getOperand(2);
1608 SDValue Chain = Tmp1.getOperand(0);
1610 // Chain the dynamic stack allocation so that it doesn't modify the stack
1611 // pointer when other instructions are using the stack.
1612 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1615 SDValue Size = Tmp2.getOperand(1);
1616 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1617 Chain = SP.getValue(1);
1618 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1619 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1620 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1621 if (Align > StackAlign)
1622 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1623 DAG.getConstant(-(uint64_t)Align, VT));
1624 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1626 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1627 DAG.getIntPtrConstant(0, true), SDValue(),
1630 Results.push_back(Tmp1);
1631 Results.push_back(Tmp2);
1634 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1635 /// condition code CC on the current target.
1637 /// If the SETCC has been legalized using AND / OR, then the legalized node
1638 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1639 /// will be set to false.
1641 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1642 /// then the values of LHS and RHS will be swapped, CC will be set to the
1643 /// new condition, and NeedInvert will be set to false.
1645 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1646 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1647 /// will be set to true. The caller must invert the result of the SETCC with
1648 /// SelectionDAG::getNOT() or take equivalent action to swap the effect of a
1649 /// true/false result.
1651 /// \returns true if the SetCC has been legalized, false if it hasn't.
1652 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1653 SDValue &LHS, SDValue &RHS,
1657 MVT OpVT = LHS.getSimpleValueType();
1658 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1660 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1661 default: llvm_unreachable("Unknown condition code action!");
1662 case TargetLowering::Legal:
1665 case TargetLowering::Expand: {
1666 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1667 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1668 std::swap(LHS, RHS);
1669 CC = DAG.getCondCode(InvCC);
1672 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1675 default: llvm_unreachable("Don't know how to expand this condition!");
1677 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1678 == TargetLowering::Legal
1679 && "If SETO is expanded, SETOEQ must be legal!");
1680 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1682 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1683 == TargetLowering::Legal
1684 && "If SETUO is expanded, SETUNE must be legal!");
1685 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1698 // If we are floating point, assign and break, otherwise fall through.
1699 if (!OpVT.isInteger()) {
1700 // We can use the 4th bit to tell if we are the unordered
1701 // or ordered version of the opcode.
1702 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1703 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1704 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1707 // Fallthrough if we are unsigned integer.
1712 // We only support using the inverted operation, which is computed above
1713 // and not a different manner of supporting expanding these cases.
1714 llvm_unreachable("Don't know how to expand this condition!");
1717 // Try inverting the result of the inverse condition.
1718 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1719 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1720 CC = DAG.getCondCode(InvCC);
1724 // If inverting the condition didn't work then we have no means to expand
1726 llvm_unreachable("Don't know how to expand this condition!");
1729 SDValue SetCC1, SetCC2;
1730 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1731 // If we aren't the ordered or unorder operation,
1732 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1733 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1734 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1736 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1737 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1738 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1740 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1749 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1750 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1751 /// a load from the stack slot to DestVT, extending it if needed.
1752 /// The resultant code need not be legal.
1753 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1757 // Create the stack frame object.
1759 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1760 getTypeForEVT(*DAG.getContext()));
1761 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1763 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1764 int SPFI = StackPtrFI->getIndex();
1765 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1767 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1768 unsigned SlotSize = SlotVT.getSizeInBits();
1769 unsigned DestSize = DestVT.getSizeInBits();
1770 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1771 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1773 // Emit a store to the stack slot. Use a truncstore if the input value is
1774 // later than DestVT.
1777 if (SrcSize > SlotSize)
1778 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1779 PtrInfo, SlotVT, false, false, SrcAlign);
1781 assert(SrcSize == SlotSize && "Invalid store");
1782 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1783 PtrInfo, false, false, SrcAlign);
1786 // Result is a load from the stack slot.
1787 if (SlotSize == DestSize)
1788 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1789 false, false, false, DestAlign);
1791 assert(SlotSize < DestSize && "Unknown extension!");
1792 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1793 PtrInfo, SlotVT, false, false, DestAlign);
1796 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1798 // Create a vector sized/aligned stack slot, store the value to element #0,
1799 // then load the whole vector back out.
1800 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1802 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1803 int SPFI = StackPtrFI->getIndex();
1805 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1807 MachinePointerInfo::getFixedStack(SPFI),
1808 Node->getValueType(0).getVectorElementType(),
1810 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1811 MachinePointerInfo::getFixedStack(SPFI),
1812 false, false, false, 0);
1816 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1817 const TargetLowering &TLI, SDValue &Res) {
1818 unsigned NumElems = Node->getNumOperands();
1820 EVT VT = Node->getValueType(0);
1822 // Try to group the scalars into pairs, shuffle the pairs together, then
1823 // shuffle the pairs of pairs together, etc. until the vector has
1824 // been built. This will work only if all of the necessary shuffle masks
1827 // We do this in two phases; first to check the legality of the shuffles,
1828 // and next, assuming that all shuffles are legal, to create the new nodes.
1829 for (int Phase = 0; Phase < 2; ++Phase) {
1830 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1832 for (unsigned i = 0; i < NumElems; ++i) {
1833 SDValue V = Node->getOperand(i);
1834 if (V.getOpcode() == ISD::UNDEF)
1839 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1840 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1843 while (IntermedVals.size() > 2) {
1844 NewIntermedVals.clear();
1845 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1846 // This vector and the next vector are shuffled together (simply to
1847 // append the one to the other).
1848 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1850 SmallVector<int, 16> FinalIndices;
1851 FinalIndices.reserve(IntermedVals[i].second.size() +
1852 IntermedVals[i+1].second.size());
1855 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1858 FinalIndices.push_back(IntermedVals[i].second[j]);
1860 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1862 ShuffleVec[k] = NumElems + j;
1863 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1868 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1869 IntermedVals[i+1].first,
1871 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1873 NewIntermedVals.push_back(std::make_pair(Shuffle, FinalIndices));
1876 // If we had an odd number of defined values, then append the last
1877 // element to the array of new vectors.
1878 if ((IntermedVals.size() & 1) != 0)
1879 NewIntermedVals.push_back(IntermedVals.back());
1881 IntermedVals.swap(NewIntermedVals);
1884 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1885 "Invalid number of intermediate vectors");
1886 SDValue Vec1 = IntermedVals[0].first;
1888 if (IntermedVals.size() > 1)
1889 Vec2 = IntermedVals[1].first;
1891 Vec2 = DAG.getUNDEF(VT);
1893 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1894 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1895 ShuffleVec[IntermedVals[0].second[i]] = i;
1896 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1897 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1900 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1901 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1908 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1909 /// support the operation, but do support the resultant vector type.
1910 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1911 unsigned NumElems = Node->getNumOperands();
1912 SDValue Value1, Value2;
1914 EVT VT = Node->getValueType(0);
1915 EVT OpVT = Node->getOperand(0).getValueType();
1916 EVT EltVT = VT.getVectorElementType();
1918 // If the only non-undef value is the low element, turn this into a
1919 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1920 bool isOnlyLowElement = true;
1921 bool MoreThanTwoValues = false;
1922 bool isConstant = true;
1923 for (unsigned i = 0; i < NumElems; ++i) {
1924 SDValue V = Node->getOperand(i);
1925 if (V.getOpcode() == ISD::UNDEF)
1928 isOnlyLowElement = false;
1929 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1932 if (!Value1.getNode()) {
1934 } else if (!Value2.getNode()) {
1937 } else if (V != Value1 && V != Value2) {
1938 MoreThanTwoValues = true;
1942 if (!Value1.getNode())
1943 return DAG.getUNDEF(VT);
1945 if (isOnlyLowElement)
1946 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1948 // If all elements are constants, create a load from the constant pool.
1950 SmallVector<Constant*, 16> CV;
1951 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1952 if (ConstantFPSDNode *V =
1953 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1954 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1955 } else if (ConstantSDNode *V =
1956 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1958 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1960 // If OpVT and EltVT don't match, EltVT is not legal and the
1961 // element values have been promoted/truncated earlier. Undo this;
1962 // we don't want a v16i8 to become a v16i32 for example.
1963 const ConstantInt *CI = V->getConstantIntValue();
1964 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1965 CI->getZExtValue()));
1968 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1969 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1970 CV.push_back(UndefValue::get(OpNTy));
1973 Constant *CP = ConstantVector::get(CV);
1974 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1975 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1976 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1977 MachinePointerInfo::getConstantPool(),
1978 false, false, false, Alignment);
1981 SmallSet<SDValue, 16> DefinedValues;
1982 for (unsigned i = 0; i < NumElems; ++i) {
1983 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
1985 DefinedValues.insert(Node->getOperand(i));
1988 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1989 if (!MoreThanTwoValues) {
1990 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1991 for (unsigned i = 0; i < NumElems; ++i) {
1992 SDValue V = Node->getOperand(i);
1993 if (V.getOpcode() == ISD::UNDEF)
1995 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1997 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1998 // Get the splatted value into the low element of a vector register.
1999 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2001 if (Value2.getNode())
2002 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2004 Vec2 = DAG.getUNDEF(VT);
2006 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2007 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2011 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2016 // Otherwise, we can't handle this case efficiently.
2017 return ExpandVectorBuildThroughStack(Node);
2020 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2021 // does not fit into a register, return the lo part and set the hi part to the
2022 // by-reg argument. If it does fit into a single register, return the result
2023 // and leave the Hi part unset.
2024 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2026 TargetLowering::ArgListTy Args;
2027 TargetLowering::ArgListEntry Entry;
2028 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2029 EVT ArgVT = Node->getOperand(i).getValueType();
2030 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2031 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2032 Entry.isSExt = isSigned;
2033 Entry.isZExt = !isSigned;
2034 Args.push_back(Entry);
2036 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2037 TLI.getPointerTy());
2039 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2041 // By default, the input chain to this libcall is the entry node of the
2042 // function. If the libcall is going to be emitted as a tail call then
2043 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2044 // node which is being folded has a non-entry input chain.
2045 SDValue InChain = DAG.getEntryNode();
2047 // isTailCall may be true since the callee does not reference caller stack
2048 // frame. Check if it's in the right position.
2049 SDValue TCChain = InChain;
2050 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2055 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2056 0, TLI.getLibcallCallingConv(LC), isTailCall,
2057 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2058 Callee, Args, DAG, SDLoc(Node));
2059 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2062 if (!CallInfo.second.getNode())
2063 // It's a tailcall, return the chain (which is the DAG root).
2064 return DAG.getRoot();
2066 return CallInfo.first;
2069 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
2070 /// and returning a result of type RetVT.
2071 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2072 const SDValue *Ops, unsigned NumOps,
2073 bool isSigned, SDLoc dl) {
2074 TargetLowering::ArgListTy Args;
2075 Args.reserve(NumOps);
2077 TargetLowering::ArgListEntry Entry;
2078 for (unsigned i = 0; i != NumOps; ++i) {
2079 Entry.Node = Ops[i];
2080 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2081 Entry.isSExt = isSigned;
2082 Entry.isZExt = !isSigned;
2083 Args.push_back(Entry);
2085 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2086 TLI.getPointerTy());
2088 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2090 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
2091 false, 0, TLI.getLibcallCallingConv(LC),
2092 /*isTailCall=*/false,
2093 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2094 Callee, Args, DAG, dl);
2095 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2097 return CallInfo.first;
2100 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2101 // ExpandLibCall except that the first operand is the in-chain.
2102 std::pair<SDValue, SDValue>
2103 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2106 SDValue InChain = Node->getOperand(0);
2108 TargetLowering::ArgListTy Args;
2109 TargetLowering::ArgListEntry Entry;
2110 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2111 EVT ArgVT = Node->getOperand(i).getValueType();
2112 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2113 Entry.Node = Node->getOperand(i);
2115 Entry.isSExt = isSigned;
2116 Entry.isZExt = !isSigned;
2117 Args.push_back(Entry);
2119 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2120 TLI.getPointerTy());
2122 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2124 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2125 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2126 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2127 Callee, Args, DAG, SDLoc(Node));
2128 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2133 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2134 RTLIB::Libcall Call_F32,
2135 RTLIB::Libcall Call_F64,
2136 RTLIB::Libcall Call_F80,
2137 RTLIB::Libcall Call_F128,
2138 RTLIB::Libcall Call_PPCF128) {
2140 switch (Node->getSimpleValueType(0).SimpleTy) {
2141 default: llvm_unreachable("Unexpected request for libcall!");
2142 case MVT::f32: LC = Call_F32; break;
2143 case MVT::f64: LC = Call_F64; break;
2144 case MVT::f80: LC = Call_F80; break;
2145 case MVT::f128: LC = Call_F128; break;
2146 case MVT::ppcf128: LC = Call_PPCF128; break;
2148 return ExpandLibCall(LC, Node, false);
2151 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2152 RTLIB::Libcall Call_I8,
2153 RTLIB::Libcall Call_I16,
2154 RTLIB::Libcall Call_I32,
2155 RTLIB::Libcall Call_I64,
2156 RTLIB::Libcall Call_I128) {
2158 switch (Node->getSimpleValueType(0).SimpleTy) {
2159 default: llvm_unreachable("Unexpected request for libcall!");
2160 case MVT::i8: LC = Call_I8; break;
2161 case MVT::i16: LC = Call_I16; break;
2162 case MVT::i32: LC = Call_I32; break;
2163 case MVT::i64: LC = Call_I64; break;
2164 case MVT::i128: LC = Call_I128; break;
2166 return ExpandLibCall(LC, Node, isSigned);
2169 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2170 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2171 const TargetLowering &TLI) {
2173 switch (Node->getSimpleValueType(0).SimpleTy) {
2174 default: llvm_unreachable("Unexpected request for libcall!");
2175 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2176 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2177 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2178 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2179 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2182 return TLI.getLibcallName(LC) != nullptr;
2185 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
2187 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2188 // The other use might have been replaced with a divrem already.
2189 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2190 unsigned OtherOpcode = 0;
2192 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2194 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2196 SDValue Op0 = Node->getOperand(0);
2197 SDValue Op1 = Node->getOperand(1);
2198 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2199 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2203 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2204 User->getOperand(0) == Op0 &&
2205 User->getOperand(1) == Op1)
2211 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2214 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2215 SmallVectorImpl<SDValue> &Results) {
2216 unsigned Opcode = Node->getOpcode();
2217 bool isSigned = Opcode == ISD::SDIVREM;
2220 switch (Node->getSimpleValueType(0).SimpleTy) {
2221 default: llvm_unreachable("Unexpected request for libcall!");
2222 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2223 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2224 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2225 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2226 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2229 // The input chain to this libcall is the entry node of the function.
2230 // Legalizing the call will automatically add the previous call to the
2232 SDValue InChain = DAG.getEntryNode();
2234 EVT RetVT = Node->getValueType(0);
2235 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2237 TargetLowering::ArgListTy Args;
2238 TargetLowering::ArgListEntry Entry;
2239 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2240 EVT ArgVT = Node->getOperand(i).getValueType();
2241 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2242 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2243 Entry.isSExt = isSigned;
2244 Entry.isZExt = !isSigned;
2245 Args.push_back(Entry);
2248 // Also pass the return address of the remainder.
2249 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2251 Entry.Ty = RetTy->getPointerTo();
2252 Entry.isSExt = isSigned;
2253 Entry.isZExt = !isSigned;
2254 Args.push_back(Entry);
2256 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2257 TLI.getPointerTy());
2261 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2262 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2263 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2264 Callee, Args, DAG, dl);
2265 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2267 // Remainder is loaded back from the stack frame.
2268 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2269 MachinePointerInfo(), false, false, false, 0);
2270 Results.push_back(CallInfo.first);
2271 Results.push_back(Rem);
2274 /// isSinCosLibcallAvailable - Return true if sincos libcall is available.
2275 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2277 switch (Node->getSimpleValueType(0).SimpleTy) {
2278 default: llvm_unreachable("Unexpected request for libcall!");
2279 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2280 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2281 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2282 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2283 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2285 return TLI.getLibcallName(LC) != nullptr;
2288 /// canCombineSinCosLibcall - Return true if sincos libcall is available and
2289 /// can be used to combine sin and cos.
2290 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2291 const TargetMachine &TM) {
2292 if (!isSinCosLibcallAvailable(Node, TLI))
2294 // GNU sin/cos functions set errno while sincos does not. Therefore
2295 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2296 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2297 if (isGNU && !TM.Options.UnsafeFPMath)
2302 /// useSinCos - Only issue sincos libcall if both sin and cos are
2304 static bool useSinCos(SDNode *Node) {
2305 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2306 ? ISD::FCOS : ISD::FSIN;
2308 SDValue Op0 = Node->getOperand(0);
2309 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2310 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2314 // The other user might have been turned into sincos already.
2315 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2321 /// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
2324 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2325 SmallVectorImpl<SDValue> &Results) {
2327 switch (Node->getSimpleValueType(0).SimpleTy) {
2328 default: llvm_unreachable("Unexpected request for libcall!");
2329 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2330 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2331 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2332 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2333 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2336 // The input chain to this libcall is the entry node of the function.
2337 // Legalizing the call will automatically add the previous call to the
2339 SDValue InChain = DAG.getEntryNode();
2341 EVT RetVT = Node->getValueType(0);
2342 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2344 TargetLowering::ArgListTy Args;
2345 TargetLowering::ArgListEntry Entry;
2347 // Pass the argument.
2348 Entry.Node = Node->getOperand(0);
2350 Entry.isSExt = false;
2351 Entry.isZExt = false;
2352 Args.push_back(Entry);
2354 // Pass the return address of sin.
2355 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2356 Entry.Node = SinPtr;
2357 Entry.Ty = RetTy->getPointerTo();
2358 Entry.isSExt = false;
2359 Entry.isZExt = false;
2360 Args.push_back(Entry);
2362 // Also pass the return address of the cos.
2363 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2364 Entry.Node = CosPtr;
2365 Entry.Ty = RetTy->getPointerTo();
2366 Entry.isSExt = false;
2367 Entry.isZExt = false;
2368 Args.push_back(Entry);
2370 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2371 TLI.getPointerTy());
2375 CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
2376 false, false, false, false,
2377 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2378 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2379 Callee, Args, DAG, dl);
2380 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2382 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2383 MachinePointerInfo(), false, false, false, 0));
2384 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2385 MachinePointerInfo(), false, false, false, 0));
2388 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2389 /// INT_TO_FP operation of the specified operand when the target requests that
2390 /// we expand it. At this point, we know that the result and operand types are
2391 /// legal for the target.
2392 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2396 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2397 // simple 32-bit [signed|unsigned] integer to float/double expansion
2399 // Get the stack frame index of a 8 byte buffer.
2400 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2402 // word offset constant for Hi/Lo address computation
2403 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2404 // set up Hi and Lo (into buffer) address based on endian
2405 SDValue Hi = StackSlot;
2406 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2407 StackSlot, WordOff);
2408 if (TLI.isLittleEndian())
2411 // if signed map to unsigned space
2414 // constant used to invert sign bit (signed to unsigned mapping)
2415 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2416 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2420 // store the lo of the constructed double - based on integer input
2421 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2422 Op0Mapped, Lo, MachinePointerInfo(),
2424 // initial hi portion of constructed double
2425 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2426 // store the hi of the constructed double - biased exponent
2427 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2428 MachinePointerInfo(),
2430 // load the constructed double
2431 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2432 MachinePointerInfo(), false, false, false, 0);
2433 // FP constant to bias correct the final result
2434 SDValue Bias = DAG.getConstantFP(isSigned ?
2435 BitsToDouble(0x4330000080000000ULL) :
2436 BitsToDouble(0x4330000000000000ULL),
2438 // subtract the bias
2439 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2442 // handle final rounding
2443 if (DestVT == MVT::f64) {
2446 } else if (DestVT.bitsLT(MVT::f64)) {
2447 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2448 DAG.getIntPtrConstant(0));
2449 } else if (DestVT.bitsGT(MVT::f64)) {
2450 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2454 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2455 // Code below here assumes !isSigned without checking again.
2457 // Implementation of unsigned i64 to f64 following the algorithm in
2458 // __floatundidf in compiler_rt. This implementation has the advantage
2459 // of performing rounding correctly, both in the default rounding mode
2460 // and in all alternate rounding modes.
2461 // TODO: Generalize this for use with other types.
2462 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2464 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2465 SDValue TwoP84PlusTwoP52 =
2466 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2468 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2470 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2471 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2472 DAG.getConstant(32, MVT::i64));
2473 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2474 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2475 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2476 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2477 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2479 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2482 // Implementation of unsigned i64 to f32.
2483 // TODO: Generalize this for use with other types.
2484 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2485 // For unsigned conversions, convert them to signed conversions using the
2486 // algorithm from the x86_64 __floatundidf in compiler_rt.
2488 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2490 SDValue ShiftConst =
2491 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2492 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2493 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2494 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2495 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2497 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2498 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2500 // TODO: This really should be implemented using a branch rather than a
2501 // select. We happen to get lucky and machinesink does the right
2502 // thing most of the time. This would be a good candidate for a
2503 //pseudo-op, or, even better, for whole-function isel.
2504 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2505 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2506 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2509 // Otherwise, implement the fully general conversion.
2511 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2512 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2513 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2514 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2515 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2516 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2517 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2518 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2519 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2520 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2521 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2523 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2524 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2526 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2527 DAG.getConstant(32, SHVT));
2528 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2529 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2531 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2532 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2533 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2534 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2535 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2536 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2537 DAG.getIntPtrConstant(0));
2540 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2542 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2543 Op0, DAG.getConstant(0, Op0.getValueType()),
2545 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2546 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2547 SignSet, Four, Zero);
2549 // If the sign bit of the integer is set, the large number will be treated
2550 // as a negative number. To counteract this, the dynamic code adds an
2551 // offset depending on the data type.
2553 switch (Op0.getSimpleValueType().SimpleTy) {
2554 default: llvm_unreachable("Unsupported integer type!");
2555 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2556 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2557 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2558 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2560 if (TLI.isLittleEndian()) FF <<= 32;
2561 Constant *FudgeFactor = ConstantInt::get(
2562 Type::getInt64Ty(*DAG.getContext()), FF);
2564 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2565 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2566 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2567 Alignment = std::min(Alignment, 4u);
2569 if (DestVT == MVT::f32)
2570 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2571 MachinePointerInfo::getConstantPool(),
2572 false, false, false, Alignment);
2574 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2575 DAG.getEntryNode(), CPIdx,
2576 MachinePointerInfo::getConstantPool(),
2577 MVT::f32, false, false, Alignment);
2578 HandleSDNode Handle(Load);
2579 LegalizeOp(Load.getNode());
2580 FudgeInReg = Handle.getValue();
2583 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2586 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2587 /// *INT_TO_FP operation of the specified operand when the target requests that
2588 /// we promote it. At this point, we know that the result and operand types are
2589 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2590 /// operation that takes a larger input.
2591 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2595 // First step, figure out the appropriate *INT_TO_FP operation to use.
2596 EVT NewInTy = LegalOp.getValueType();
2598 unsigned OpToUse = 0;
2600 // Scan for the appropriate larger type to use.
2602 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2603 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2605 // If the target supports SINT_TO_FP of this type, use it.
2606 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2607 OpToUse = ISD::SINT_TO_FP;
2610 if (isSigned) continue;
2612 // If the target supports UINT_TO_FP of this type, use it.
2613 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2614 OpToUse = ISD::UINT_TO_FP;
2618 // Otherwise, try a larger type.
2621 // Okay, we found the operation and type to use. Zero extend our input to the
2622 // desired type then run the operation on it.
2623 return DAG.getNode(OpToUse, dl, DestVT,
2624 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2625 dl, NewInTy, LegalOp));
2628 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2629 /// FP_TO_*INT operation of the specified operand when the target requests that
2630 /// we promote it. At this point, we know that the result and operand types are
2631 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2632 /// operation that returns a larger result.
2633 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2637 // First step, figure out the appropriate FP_TO*INT operation to use.
2638 EVT NewOutTy = DestVT;
2640 unsigned OpToUse = 0;
2642 // Scan for the appropriate larger type to use.
2644 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2645 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2647 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2648 OpToUse = ISD::FP_TO_SINT;
2652 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2653 OpToUse = ISD::FP_TO_UINT;
2657 // Otherwise, try a larger type.
2661 // Okay, we found the operation and type to use.
2662 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2664 // Truncate the result of the extended FP_TO_*INT operation to the desired
2666 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2669 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2671 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2672 EVT VT = Op.getValueType();
2673 EVT SHVT = TLI.getShiftAmountTy(VT);
2674 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2675 switch (VT.getSimpleVT().SimpleTy) {
2676 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2678 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2679 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2680 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2682 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2683 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2684 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2685 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2686 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2687 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2688 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2689 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2690 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2692 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2693 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2694 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2695 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2696 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2697 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2698 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2699 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2700 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2701 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2702 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2703 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2704 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2705 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2706 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2707 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2708 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2709 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2710 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2711 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2712 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2716 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2718 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2721 default: llvm_unreachable("Cannot expand this yet!");
2723 EVT VT = Op.getValueType();
2724 EVT ShVT = TLI.getShiftAmountTy(VT);
2725 unsigned Len = VT.getSizeInBits();
2727 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2728 "CTPOP not implemented for this type.");
2730 // This is the "best" algorithm from
2731 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2733 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2734 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2735 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2736 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2738 // v = v - ((v >> 1) & 0x55555555...)
2739 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2740 DAG.getNode(ISD::AND, dl, VT,
2741 DAG.getNode(ISD::SRL, dl, VT, Op,
2742 DAG.getConstant(1, ShVT)),
2744 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2745 Op = DAG.getNode(ISD::ADD, dl, VT,
2746 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2747 DAG.getNode(ISD::AND, dl, VT,
2748 DAG.getNode(ISD::SRL, dl, VT, Op,
2749 DAG.getConstant(2, ShVT)),
2751 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2752 Op = DAG.getNode(ISD::AND, dl, VT,
2753 DAG.getNode(ISD::ADD, dl, VT, Op,
2754 DAG.getNode(ISD::SRL, dl, VT, Op,
2755 DAG.getConstant(4, ShVT))),
2757 // v = (v * 0x01010101...) >> (Len - 8)
2758 Op = DAG.getNode(ISD::SRL, dl, VT,
2759 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2760 DAG.getConstant(Len - 8, ShVT));
2764 case ISD::CTLZ_ZERO_UNDEF:
2765 // This trivially expands to CTLZ.
2766 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2768 // for now, we do this:
2769 // x = x | (x >> 1);
2770 // x = x | (x >> 2);
2772 // x = x | (x >>16);
2773 // x = x | (x >>32); // for 64-bit input
2774 // return popcount(~x);
2776 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2777 EVT VT = Op.getValueType();
2778 EVT ShVT = TLI.getShiftAmountTy(VT);
2779 unsigned len = VT.getSizeInBits();
2780 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2781 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2782 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2783 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2785 Op = DAG.getNOT(dl, Op, VT);
2786 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2788 case ISD::CTTZ_ZERO_UNDEF:
2789 // This trivially expands to CTTZ.
2790 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2792 // for now, we use: { return popcount(~x & (x - 1)); }
2793 // unless the target has ctlz but not ctpop, in which case we use:
2794 // { return 32 - nlz(~x & (x-1)); }
2795 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2796 EVT VT = Op.getValueType();
2797 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2798 DAG.getNOT(dl, Op, VT),
2799 DAG.getNode(ISD::SUB, dl, VT, Op,
2800 DAG.getConstant(1, VT)));
2801 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2802 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2803 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2804 return DAG.getNode(ISD::SUB, dl, VT,
2805 DAG.getConstant(VT.getSizeInBits(), VT),
2806 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2807 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2812 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2813 unsigned Opc = Node->getOpcode();
2814 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2819 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2820 case ISD::ATOMIC_SWAP:
2821 switch (VT.SimpleTy) {
2822 default: llvm_unreachable("Unexpected value type for atomic!");
2823 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2824 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2825 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2826 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2827 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2830 case ISD::ATOMIC_CMP_SWAP:
2831 switch (VT.SimpleTy) {
2832 default: llvm_unreachable("Unexpected value type for atomic!");
2833 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2834 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2835 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2836 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2837 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2840 case ISD::ATOMIC_LOAD_ADD:
2841 switch (VT.SimpleTy) {
2842 default: llvm_unreachable("Unexpected value type for atomic!");
2843 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2844 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2845 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2846 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2847 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2850 case ISD::ATOMIC_LOAD_SUB:
2851 switch (VT.SimpleTy) {
2852 default: llvm_unreachable("Unexpected value type for atomic!");
2853 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2854 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2855 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2856 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2857 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2860 case ISD::ATOMIC_LOAD_AND:
2861 switch (VT.SimpleTy) {
2862 default: llvm_unreachable("Unexpected value type for atomic!");
2863 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2864 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2865 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2866 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2867 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2870 case ISD::ATOMIC_LOAD_OR:
2871 switch (VT.SimpleTy) {
2872 default: llvm_unreachable("Unexpected value type for atomic!");
2873 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2874 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2875 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2876 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2877 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2880 case ISD::ATOMIC_LOAD_XOR:
2881 switch (VT.SimpleTy) {
2882 default: llvm_unreachable("Unexpected value type for atomic!");
2883 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2884 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2885 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2886 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2887 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2890 case ISD::ATOMIC_LOAD_NAND:
2891 switch (VT.SimpleTy) {
2892 default: llvm_unreachable("Unexpected value type for atomic!");
2893 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2894 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2895 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2896 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2897 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2900 case ISD::ATOMIC_LOAD_MAX:
2901 switch (VT.SimpleTy) {
2902 default: llvm_unreachable("Unexpected value type for atomic!");
2903 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2904 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2905 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2906 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2907 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2910 case ISD::ATOMIC_LOAD_UMAX:
2911 switch (VT.SimpleTy) {
2912 default: llvm_unreachable("Unexpected value type for atomic!");
2913 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2914 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2915 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2916 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2917 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2920 case ISD::ATOMIC_LOAD_MIN:
2921 switch (VT.SimpleTy) {
2922 default: llvm_unreachable("Unexpected value type for atomic!");
2923 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2924 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2925 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2926 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2927 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2930 case ISD::ATOMIC_LOAD_UMIN:
2931 switch (VT.SimpleTy) {
2932 default: llvm_unreachable("Unexpected value type for atomic!");
2933 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2934 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2935 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2936 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2937 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2942 return ExpandChainLibCall(LC, Node, false);
2945 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2946 SmallVector<SDValue, 8> Results;
2948 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2950 switch (Node->getOpcode()) {
2953 case ISD::CTLZ_ZERO_UNDEF:
2955 case ISD::CTTZ_ZERO_UNDEF:
2956 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2957 Results.push_back(Tmp1);
2960 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2962 case ISD::FRAMEADDR:
2963 case ISD::RETURNADDR:
2964 case ISD::FRAME_TO_ARGS_OFFSET:
2965 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2967 case ISD::FLT_ROUNDS_:
2968 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2970 case ISD::EH_RETURN:
2974 case ISD::EH_SJLJ_LONGJMP:
2975 // If the target didn't expand these, there's nothing to do, so just
2976 // preserve the chain and be done.
2977 Results.push_back(Node->getOperand(0));
2979 case ISD::EH_SJLJ_SETJMP:
2980 // If the target didn't expand this, just return 'zero' and preserve the
2982 Results.push_back(DAG.getConstant(0, MVT::i32));
2983 Results.push_back(Node->getOperand(0));
2985 case ISD::ATOMIC_FENCE: {
2986 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2987 // FIXME: handle "fence singlethread" more efficiently.
2988 TargetLowering::ArgListTy Args;
2990 CallLoweringInfo CLI(Node->getOperand(0),
2991 Type::getVoidTy(*DAG.getContext()),
2992 false, false, false, false, 0, CallingConv::C,
2993 /*isTailCall=*/false,
2994 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2995 DAG.getExternalSymbol("__sync_synchronize",
2996 TLI.getPointerTy()),
2998 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3000 Results.push_back(CallResult.second);
3003 case ISD::ATOMIC_LOAD: {
3004 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3005 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
3006 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3007 cast<AtomicSDNode>(Node)->getMemoryVT(),
3008 Node->getOperand(0),
3009 Node->getOperand(1), Zero, Zero,
3010 cast<AtomicSDNode>(Node)->getMemOperand(),
3011 cast<AtomicSDNode>(Node)->getOrdering(),
3012 cast<AtomicSDNode>(Node)->getOrdering(),
3013 cast<AtomicSDNode>(Node)->getSynchScope());
3014 Results.push_back(Swap.getValue(0));
3015 Results.push_back(Swap.getValue(1));
3018 case ISD::ATOMIC_STORE: {
3019 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3020 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3021 cast<AtomicSDNode>(Node)->getMemoryVT(),
3022 Node->getOperand(0),
3023 Node->getOperand(1), Node->getOperand(2),
3024 cast<AtomicSDNode>(Node)->getMemOperand(),
3025 cast<AtomicSDNode>(Node)->getOrdering(),
3026 cast<AtomicSDNode>(Node)->getSynchScope());
3027 Results.push_back(Swap.getValue(1));
3030 // By default, atomic intrinsics are marked Legal and lowered. Targets
3031 // which don't support them directly, however, may want libcalls, in which
3032 // case they mark them Expand, and we get here.
3033 case ISD::ATOMIC_SWAP:
3034 case ISD::ATOMIC_LOAD_ADD:
3035 case ISD::ATOMIC_LOAD_SUB:
3036 case ISD::ATOMIC_LOAD_AND:
3037 case ISD::ATOMIC_LOAD_OR:
3038 case ISD::ATOMIC_LOAD_XOR:
3039 case ISD::ATOMIC_LOAD_NAND:
3040 case ISD::ATOMIC_LOAD_MIN:
3041 case ISD::ATOMIC_LOAD_MAX:
3042 case ISD::ATOMIC_LOAD_UMIN:
3043 case ISD::ATOMIC_LOAD_UMAX:
3044 case ISD::ATOMIC_CMP_SWAP: {
3045 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
3046 Results.push_back(Tmp.first);
3047 Results.push_back(Tmp.second);
3050 case ISD::DYNAMIC_STACKALLOC:
3051 ExpandDYNAMIC_STACKALLOC(Node, Results);
3053 case ISD::MERGE_VALUES:
3054 for (unsigned i = 0; i < Node->getNumValues(); i++)
3055 Results.push_back(Node->getOperand(i));
3058 EVT VT = Node->getValueType(0);
3060 Results.push_back(DAG.getConstant(0, VT));
3062 assert(VT.isFloatingPoint() && "Unknown value type!");
3063 Results.push_back(DAG.getConstantFP(0, VT));
3068 // If this operation is not supported, lower it to 'abort()' call
3069 TargetLowering::ArgListTy Args;
3071 CallLoweringInfo CLI(Node->getOperand(0),
3072 Type::getVoidTy(*DAG.getContext()),
3073 false, false, false, false, 0, CallingConv::C,
3074 /*isTailCall=*/false,
3075 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
3076 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3078 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3080 Results.push_back(CallResult.second);
3085 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3086 Node->getValueType(0), dl);
3087 Results.push_back(Tmp1);
3089 case ISD::FP_EXTEND:
3090 Tmp1 = EmitStackConvert(Node->getOperand(0),
3091 Node->getOperand(0).getValueType(),
3092 Node->getValueType(0), dl);
3093 Results.push_back(Tmp1);
3095 case ISD::SIGN_EXTEND_INREG: {
3096 // NOTE: we could fall back on load/store here too for targets without
3097 // SAR. However, it is doubtful that any exist.
3098 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3099 EVT VT = Node->getValueType(0);
3100 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3103 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3104 ExtraVT.getScalarType().getSizeInBits();
3105 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
3106 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3107 Node->getOperand(0), ShiftCst);
3108 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3109 Results.push_back(Tmp1);
3112 case ISD::FP_ROUND_INREG: {
3113 // The only way we can lower this is to turn it into a TRUNCSTORE,
3114 // EXTLOAD pair, targeting a temporary location (a stack slot).
3116 // NOTE: there is a choice here between constantly creating new stack
3117 // slots and always reusing the same one. We currently always create
3118 // new ones, as reuse may inhibit scheduling.
3119 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3120 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3121 Node->getValueType(0), dl);
3122 Results.push_back(Tmp1);
3125 case ISD::SINT_TO_FP:
3126 case ISD::UINT_TO_FP:
3127 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3128 Node->getOperand(0), Node->getValueType(0), dl);
3129 Results.push_back(Tmp1);
3131 case ISD::FP_TO_UINT: {
3132 SDValue True, False;
3133 EVT VT = Node->getOperand(0).getValueType();
3134 EVT NVT = Node->getValueType(0);
3135 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3136 APInt::getNullValue(VT.getSizeInBits()));
3137 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3138 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3139 Tmp1 = DAG.getConstantFP(apf, VT);
3140 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3141 Node->getOperand(0),
3143 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3144 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3145 DAG.getNode(ISD::FSUB, dl, VT,
3146 Node->getOperand(0), Tmp1));
3147 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3148 DAG.getConstant(x, NVT));
3149 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3150 Results.push_back(Tmp1);
3154 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3155 EVT VT = Node->getValueType(0);
3156 Tmp1 = Node->getOperand(0);
3157 Tmp2 = Node->getOperand(1);
3158 unsigned Align = Node->getConstantOperandVal(3);
3160 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3161 MachinePointerInfo(V),
3162 false, false, false, 0);
3163 SDValue VAList = VAListLoad;
3165 if (Align > TLI.getMinStackArgumentAlignment()) {
3166 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3168 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3169 DAG.getConstant(Align - 1,
3170 VAList.getValueType()));
3172 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3173 DAG.getConstant(-(int64_t)Align,
3174 VAList.getValueType()));
3177 // Increment the pointer, VAList, to the next vaarg
3178 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3179 DAG.getConstant(TLI.getDataLayout()->
3180 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3181 VAList.getValueType()));
3182 // Store the incremented VAList to the legalized pointer
3183 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3184 MachinePointerInfo(V), false, false, 0);
3185 // Load the actual argument out of the pointer VAList
3186 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3187 false, false, false, 0));
3188 Results.push_back(Results[0].getValue(1));
3192 // This defaults to loading a pointer from the input and storing it to the
3193 // output, returning the chain.
3194 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3195 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3196 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3197 Node->getOperand(2), MachinePointerInfo(VS),
3198 false, false, false, 0);
3199 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3200 MachinePointerInfo(VD), false, false, 0);
3201 Results.push_back(Tmp1);
3204 case ISD::EXTRACT_VECTOR_ELT:
3205 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3206 // This must be an access of the only element. Return it.
3207 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3208 Node->getOperand(0));
3210 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3211 Results.push_back(Tmp1);
3213 case ISD::EXTRACT_SUBVECTOR:
3214 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3216 case ISD::INSERT_SUBVECTOR:
3217 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3219 case ISD::CONCAT_VECTORS: {
3220 Results.push_back(ExpandVectorBuildThroughStack(Node));
3223 case ISD::SCALAR_TO_VECTOR:
3224 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3226 case ISD::INSERT_VECTOR_ELT:
3227 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3228 Node->getOperand(1),
3229 Node->getOperand(2), dl));
3231 case ISD::VECTOR_SHUFFLE: {
3232 SmallVector<int, 32> NewMask;
3233 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3235 EVT VT = Node->getValueType(0);
3236 EVT EltVT = VT.getVectorElementType();
3237 SDValue Op0 = Node->getOperand(0);
3238 SDValue Op1 = Node->getOperand(1);
3239 if (!TLI.isTypeLegal(EltVT)) {
3241 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3243 // BUILD_VECTOR operands are allowed to be wider than the element type.
3244 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3246 if (NewEltVT.bitsLT(EltVT)) {
3248 // Convert shuffle node.
3249 // If original node was v4i64 and the new EltVT is i32,
3250 // cast operands to v8i32 and re-build the mask.
3252 // Calculate new VT, the size of the new VT should be equal to original.
3254 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3255 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3256 assert(NewVT.bitsEq(VT));
3258 // cast operands to new VT
3259 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3260 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3262 // Convert the shuffle mask
3263 unsigned int factor =
3264 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3266 // EltVT gets smaller
3269 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3271 for (unsigned fi = 0; fi < factor; ++fi)
3272 NewMask.push_back(Mask[i]);
3275 for (unsigned fi = 0; fi < factor; ++fi)
3276 NewMask.push_back(Mask[i]*factor+fi);
3284 unsigned NumElems = VT.getVectorNumElements();
3285 SmallVector<SDValue, 16> Ops;
3286 for (unsigned i = 0; i != NumElems; ++i) {
3288 Ops.push_back(DAG.getUNDEF(EltVT));
3291 unsigned Idx = Mask[i];
3293 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3295 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3297 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3299 DAG.getConstant(Idx - NumElems,
3300 TLI.getVectorIdxTy())));
3303 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3304 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3305 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3306 Results.push_back(Tmp1);
3309 case ISD::EXTRACT_ELEMENT: {
3310 EVT OpTy = Node->getOperand(0).getValueType();
3311 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3313 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3314 DAG.getConstant(OpTy.getSizeInBits()/2,
3315 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3316 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3319 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3320 Node->getOperand(0));
3322 Results.push_back(Tmp1);
3325 case ISD::STACKSAVE:
3326 // Expand to CopyFromReg if the target set
3327 // StackPointerRegisterToSaveRestore.
3328 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3329 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3330 Node->getValueType(0)));
3331 Results.push_back(Results[0].getValue(1));
3333 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3334 Results.push_back(Node->getOperand(0));
3337 case ISD::STACKRESTORE:
3338 // Expand to CopyToReg if the target set
3339 // StackPointerRegisterToSaveRestore.
3340 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3341 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3342 Node->getOperand(1)));
3344 Results.push_back(Node->getOperand(0));
3347 case ISD::FCOPYSIGN:
3348 Results.push_back(ExpandFCOPYSIGN(Node));
3351 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3352 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3353 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3354 Node->getOperand(0));
3355 Results.push_back(Tmp1);
3358 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3359 EVT VT = Node->getValueType(0);
3360 Tmp1 = Node->getOperand(0);
3361 Tmp2 = DAG.getConstantFP(0.0, VT);
3362 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3363 Tmp1, Tmp2, ISD::SETUGT);
3364 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3365 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3366 Results.push_back(Tmp1);
3370 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3371 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3372 RTLIB::SQRT_PPCF128));
3376 EVT VT = Node->getValueType(0);
3377 bool isSIN = Node->getOpcode() == ISD::FSIN;
3378 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3379 // fcos which share the same operand and both are used.
3380 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3381 canCombineSinCosLibcall(Node, TLI, TM))
3382 && useSinCos(Node)) {
3383 SDVTList VTs = DAG.getVTList(VT, VT);
3384 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3386 Tmp1 = Tmp1.getValue(1);
3387 Results.push_back(Tmp1);
3389 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3390 RTLIB::SIN_F80, RTLIB::SIN_F128,
3391 RTLIB::SIN_PPCF128));
3393 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3394 RTLIB::COS_F80, RTLIB::COS_F128,
3395 RTLIB::COS_PPCF128));
3400 // Expand into sincos libcall.
3401 ExpandSinCosLibCall(Node, Results);
3404 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3405 RTLIB::LOG_F80, RTLIB::LOG_F128,
3406 RTLIB::LOG_PPCF128));
3409 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3410 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3411 RTLIB::LOG2_PPCF128));
3414 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3415 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3416 RTLIB::LOG10_PPCF128));
3419 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3420 RTLIB::EXP_F80, RTLIB::EXP_F128,
3421 RTLIB::EXP_PPCF128));
3424 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3425 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3426 RTLIB::EXP2_PPCF128));
3429 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3430 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3431 RTLIB::TRUNC_PPCF128));
3434 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3435 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3436 RTLIB::FLOOR_PPCF128));
3439 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3440 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3441 RTLIB::CEIL_PPCF128));
3444 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3445 RTLIB::RINT_F80, RTLIB::RINT_F128,
3446 RTLIB::RINT_PPCF128));
3448 case ISD::FNEARBYINT:
3449 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3450 RTLIB::NEARBYINT_F64,
3451 RTLIB::NEARBYINT_F80,
3452 RTLIB::NEARBYINT_F128,
3453 RTLIB::NEARBYINT_PPCF128));
3456 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3460 RTLIB::ROUND_PPCF128));
3463 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3464 RTLIB::POWI_F80, RTLIB::POWI_F128,
3465 RTLIB::POWI_PPCF128));
3468 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3469 RTLIB::POW_F80, RTLIB::POW_F128,
3470 RTLIB::POW_PPCF128));
3473 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3474 RTLIB::DIV_F80, RTLIB::DIV_F128,
3475 RTLIB::DIV_PPCF128));
3478 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3479 RTLIB::REM_F80, RTLIB::REM_F128,
3480 RTLIB::REM_PPCF128));
3483 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3484 RTLIB::FMA_F80, RTLIB::FMA_F128,
3485 RTLIB::FMA_PPCF128));
3487 case ISD::FP16_TO_FP32:
3488 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3490 case ISD::FP32_TO_FP16:
3491 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3493 case ISD::ConstantFP: {
3494 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3495 // Check to see if this FP immediate is already legal.
3496 // If this is a legal constant, turn it into a TargetConstantFP node.
3497 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3498 Results.push_back(ExpandConstantFP(CFP, true));
3502 EVT VT = Node->getValueType(0);
3503 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3504 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3505 "Don't know how to expand this FP subtraction!");
3506 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3507 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3508 Results.push_back(Tmp1);
3512 EVT VT = Node->getValueType(0);
3513 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3514 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3515 "Don't know how to expand this subtraction!");
3516 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3517 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3518 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3519 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3524 EVT VT = Node->getValueType(0);
3525 bool isSigned = Node->getOpcode() == ISD::SREM;
3526 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3527 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3528 Tmp2 = Node->getOperand(0);
3529 Tmp3 = Node->getOperand(1);
3530 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3531 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3532 // If div is legal, it's better to do the normal expansion
3533 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3534 useDivRem(Node, isSigned, false))) {
3535 SDVTList VTs = DAG.getVTList(VT, VT);
3536 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3537 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3539 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3540 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3541 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3542 } else if (isSigned)
3543 Tmp1 = ExpandIntLibCall(Node, true,
3545 RTLIB::SREM_I16, RTLIB::SREM_I32,
3546 RTLIB::SREM_I64, RTLIB::SREM_I128);
3548 Tmp1 = ExpandIntLibCall(Node, false,
3550 RTLIB::UREM_I16, RTLIB::UREM_I32,
3551 RTLIB::UREM_I64, RTLIB::UREM_I128);
3552 Results.push_back(Tmp1);
3557 bool isSigned = Node->getOpcode() == ISD::SDIV;
3558 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3559 EVT VT = Node->getValueType(0);
3560 SDVTList VTs = DAG.getVTList(VT, VT);
3561 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3562 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3563 useDivRem(Node, isSigned, true)))
3564 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3565 Node->getOperand(1));
3567 Tmp1 = ExpandIntLibCall(Node, true,
3569 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3570 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3572 Tmp1 = ExpandIntLibCall(Node, false,
3574 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3575 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3576 Results.push_back(Tmp1);
3581 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3583 EVT VT = Node->getValueType(0);
3584 SDVTList VTs = DAG.getVTList(VT, VT);
3585 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3586 "If this wasn't legal, it shouldn't have been created!");
3587 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3588 Node->getOperand(1));
3589 Results.push_back(Tmp1.getValue(1));
3594 // Expand into divrem libcall
3595 ExpandDivRemLibCall(Node, Results);
3598 EVT VT = Node->getValueType(0);
3599 SDVTList VTs = DAG.getVTList(VT, VT);
3600 // See if multiply or divide can be lowered using two-result operations.
3601 // We just need the low half of the multiply; try both the signed
3602 // and unsigned forms. If the target supports both SMUL_LOHI and
3603 // UMUL_LOHI, form a preference by checking which forms of plain
3604 // MULH it supports.
3605 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3606 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3607 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3608 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3609 unsigned OpToUse = 0;
3610 if (HasSMUL_LOHI && !HasMULHS) {
3611 OpToUse = ISD::SMUL_LOHI;
3612 } else if (HasUMUL_LOHI && !HasMULHU) {
3613 OpToUse = ISD::UMUL_LOHI;
3614 } else if (HasSMUL_LOHI) {
3615 OpToUse = ISD::SMUL_LOHI;
3616 } else if (HasUMUL_LOHI) {
3617 OpToUse = ISD::UMUL_LOHI;
3620 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3621 Node->getOperand(1)));
3626 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3627 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3628 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3629 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3630 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3631 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3632 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3633 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3634 SDValue Shift = DAG.getConstant(HalfType.getSizeInBits(),
3635 TLI.getShiftAmountTy(HalfType));
3636 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3637 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3641 Tmp1 = ExpandIntLibCall(Node, false,
3643 RTLIB::MUL_I16, RTLIB::MUL_I32,
3644 RTLIB::MUL_I64, RTLIB::MUL_I128);
3645 Results.push_back(Tmp1);
3650 SDValue LHS = Node->getOperand(0);
3651 SDValue RHS = Node->getOperand(1);
3652 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3653 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3655 Results.push_back(Sum);
3656 EVT OType = Node->getValueType(1);
3658 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3660 // LHSSign -> LHS >= 0
3661 // RHSSign -> RHS >= 0
3662 // SumSign -> Sum >= 0
3665 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3667 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3669 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3670 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3671 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3672 Node->getOpcode() == ISD::SADDO ?
3673 ISD::SETEQ : ISD::SETNE);
3675 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3676 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3678 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3679 Results.push_back(Cmp);
3684 SDValue LHS = Node->getOperand(0);
3685 SDValue RHS = Node->getOperand(1);
3686 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3687 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3689 Results.push_back(Sum);
3690 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3691 Node->getOpcode () == ISD::UADDO ?
3692 ISD::SETULT : ISD::SETUGT));
3697 EVT VT = Node->getValueType(0);
3698 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3699 SDValue LHS = Node->getOperand(0);
3700 SDValue RHS = Node->getOperand(1);
3703 static const unsigned Ops[2][3] =
3704 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3705 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3706 bool isSigned = Node->getOpcode() == ISD::SMULO;
3707 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3708 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3709 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3710 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3711 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3713 TopHalf = BottomHalf.getValue(1);
3714 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3715 VT.getSizeInBits() * 2))) {
3716 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3717 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3718 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3719 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3720 DAG.getIntPtrConstant(0));
3721 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3722 DAG.getIntPtrConstant(1));
3724 // We can fall back to a libcall with an illegal type for the MUL if we
3725 // have a libcall big enough.
3726 // Also, we can fall back to a division in some cases, but that's a big
3727 // performance hit in the general case.
3728 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3729 if (WideVT == MVT::i16)
3730 LC = RTLIB::MUL_I16;
3731 else if (WideVT == MVT::i32)
3732 LC = RTLIB::MUL_I32;
3733 else if (WideVT == MVT::i64)
3734 LC = RTLIB::MUL_I64;
3735 else if (WideVT == MVT::i128)
3736 LC = RTLIB::MUL_I128;
3737 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3739 // The high part is obtained by SRA'ing all but one of the bits of low
3741 unsigned LoSize = VT.getSizeInBits();
3742 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3743 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3744 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3745 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3747 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3748 // pre-lowered to the correct types. This all depends upon WideVT not
3749 // being a legal type for the architecture and thus has to be split to
3751 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3752 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3753 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3754 DAG.getIntPtrConstant(0));
3755 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3756 DAG.getIntPtrConstant(1));
3757 // Ret is a node with an illegal type. Because such things are not
3758 // generally permitted during this phase of legalization, delete the
3759 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3760 DAG.DeleteNode(Ret.getNode());
3764 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3765 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3766 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3767 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3770 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3771 DAG.getConstant(0, VT), ISD::SETNE);
3773 Results.push_back(BottomHalf);
3774 Results.push_back(TopHalf);
3777 case ISD::BUILD_PAIR: {
3778 EVT PairTy = Node->getValueType(0);
3779 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3780 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3781 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3782 DAG.getConstant(PairTy.getSizeInBits()/2,
3783 TLI.getShiftAmountTy(PairTy)));
3784 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3788 Tmp1 = Node->getOperand(0);
3789 Tmp2 = Node->getOperand(1);
3790 Tmp3 = Node->getOperand(2);
3791 if (Tmp1.getOpcode() == ISD::SETCC) {
3792 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3794 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3796 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3797 DAG.getConstant(0, Tmp1.getValueType()),
3798 Tmp2, Tmp3, ISD::SETNE);
3800 Results.push_back(Tmp1);
3803 SDValue Chain = Node->getOperand(0);
3804 SDValue Table = Node->getOperand(1);
3805 SDValue Index = Node->getOperand(2);
3807 EVT PTy = TLI.getPointerTy();
3809 const DataLayout &TD = *TLI.getDataLayout();
3810 unsigned EntrySize =
3811 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3813 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3814 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3815 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3818 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3819 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3820 MachinePointerInfo::getJumpTable(), MemVT,
3823 if (TM.getRelocationModel() == Reloc::PIC_) {
3824 // For PIC, the sequence is:
3825 // BRIND(load(Jumptable + index) + RelocBase)
3826 // RelocBase can be JumpTable, GOT or some sort of global base.
3827 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3828 TLI.getPICJumpTableRelocBase(Table, DAG));
3830 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3831 Results.push_back(Tmp1);
3835 // Expand brcond's setcc into its constituent parts and create a BR_CC
3837 Tmp1 = Node->getOperand(0);
3838 Tmp2 = Node->getOperand(1);
3839 if (Tmp2.getOpcode() == ISD::SETCC) {
3840 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3841 Tmp1, Tmp2.getOperand(2),
3842 Tmp2.getOperand(0), Tmp2.getOperand(1),
3843 Node->getOperand(2));
3845 // We test only the i1 bit. Skip the AND if UNDEF.
3846 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3847 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3848 DAG.getConstant(1, Tmp2.getValueType()));
3849 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3850 DAG.getCondCode(ISD::SETNE), Tmp3,
3851 DAG.getConstant(0, Tmp3.getValueType()),
3852 Node->getOperand(2));
3854 Results.push_back(Tmp1);
3857 Tmp1 = Node->getOperand(0);
3858 Tmp2 = Node->getOperand(1);
3859 Tmp3 = Node->getOperand(2);
3860 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3861 Tmp3, NeedInvert, dl);
3864 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3865 // condition code, create a new SETCC node.
3867 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3870 // If we expanded the SETCC by inverting the condition code, then wrap
3871 // the existing SETCC in a NOT to restore the intended condition.
3873 Tmp1 = DAG.getNOT(dl, Tmp1, Tmp1->getValueType(0));
3875 Results.push_back(Tmp1);
3879 // Otherwise, SETCC for the given comparison type must be completely
3880 // illegal; expand it into a SELECT_CC.
3881 EVT VT = Node->getValueType(0);
3883 switch (TLI.getBooleanContents(VT.isVector())) {
3884 case TargetLowering::ZeroOrOneBooleanContent:
3885 case TargetLowering::UndefinedBooleanContent:
3888 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3892 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3893 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3895 Results.push_back(Tmp1);
3898 case ISD::SELECT_CC: {
3899 Tmp1 = Node->getOperand(0); // LHS
3900 Tmp2 = Node->getOperand(1); // RHS
3901 Tmp3 = Node->getOperand(2); // True
3902 Tmp4 = Node->getOperand(3); // False
3903 SDValue CC = Node->getOperand(4);
3905 bool Legalized = false;
3906 // Try to legalize by inverting the condition. This is for targets that
3907 // might support an ordered version of a condition, but not the unordered
3908 // version (or vice versa).
3909 ISD::CondCode InvCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3910 Tmp1.getValueType().isInteger());
3911 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3912 // Use the new condition code and swap true and false
3914 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3916 // If The inverse is not legal, then try to swap the arguments using
3917 // the inverse condition code.
3918 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3919 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3920 // The swapped inverse condition is legal, so swap true and false,
3923 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3928 Legalized = LegalizeSetCCCondCode(
3929 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3932 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3934 // If we expanded the SETCC by inverting the condition code, then swap
3935 // the True/False operands to match.
3937 std::swap(Tmp3, Tmp4);
3939 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3940 // condition code, create a new SELECT_CC node.
3942 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3943 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3945 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3946 CC = DAG.getCondCode(ISD::SETNE);
3947 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3948 Tmp2, Tmp3, Tmp4, CC);
3951 Results.push_back(Tmp1);
3955 Tmp1 = Node->getOperand(0); // Chain
3956 Tmp2 = Node->getOperand(2); // LHS
3957 Tmp3 = Node->getOperand(3); // RHS
3958 Tmp4 = Node->getOperand(1); // CC
3960 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3961 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3963 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3965 // If we expanded the SETCC by inverting the condition code, then wrap
3966 // the existing SETCC in a NOT to restore the intended condition.
3968 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3970 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3972 if (Tmp4.getNode()) {
3973 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3974 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3976 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3977 Tmp4 = DAG.getCondCode(ISD::SETNE);
3978 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3979 Tmp2, Tmp3, Node->getOperand(4));
3981 Results.push_back(Tmp1);
3984 case ISD::BUILD_VECTOR:
3985 Results.push_back(ExpandBUILD_VECTOR(Node));
3990 // Scalarize vector SRA/SRL/SHL.
3991 EVT VT = Node->getValueType(0);
3992 assert(VT.isVector() && "Unable to legalize non-vector shift");
3993 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3994 unsigned NumElem = VT.getVectorNumElements();
3996 SmallVector<SDValue, 8> Scalars;
3997 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3998 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4000 Node->getOperand(0), DAG.getConstant(Idx,
4001 TLI.getVectorIdxTy()));
4002 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4004 Node->getOperand(1), DAG.getConstant(Idx,
4005 TLI.getVectorIdxTy()));
4006 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
4007 VT.getScalarType(), Ex, Sh));
4010 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4011 ReplaceNode(SDValue(Node, 0), Result);
4014 case ISD::GLOBAL_OFFSET_TABLE:
4015 case ISD::GlobalAddress:
4016 case ISD::GlobalTLSAddress:
4017 case ISD::ExternalSymbol:
4018 case ISD::ConstantPool:
4019 case ISD::JumpTable:
4020 case ISD::INTRINSIC_W_CHAIN:
4021 case ISD::INTRINSIC_WO_CHAIN:
4022 case ISD::INTRINSIC_VOID:
4023 // FIXME: Custom lowering for these operations shouldn't return null!
4027 // Replace the original node with the legalized result.
4028 if (!Results.empty())
4029 ReplaceNode(Node, Results.data());
4032 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4033 SmallVector<SDValue, 8> Results;
4034 MVT OVT = Node->getSimpleValueType(0);
4035 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4036 Node->getOpcode() == ISD::SINT_TO_FP ||
4037 Node->getOpcode() == ISD::SETCC) {
4038 OVT = Node->getOperand(0).getSimpleValueType();
4040 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4042 SDValue Tmp1, Tmp2, Tmp3;
4043 switch (Node->getOpcode()) {
4045 case ISD::CTTZ_ZERO_UNDEF:
4047 case ISD::CTLZ_ZERO_UNDEF:
4049 // Zero extend the argument.
4050 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4051 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4052 // already the correct result.
4053 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4054 if (Node->getOpcode() == ISD::CTTZ) {
4055 // FIXME: This should set a bit in the zero extended value instead.
4056 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4057 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
4059 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4060 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
4061 } else if (Node->getOpcode() == ISD::CTLZ ||
4062 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4063 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4064 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4065 DAG.getConstant(NVT.getSizeInBits() -
4066 OVT.getSizeInBits(), NVT));
4068 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4071 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4072 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4073 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4074 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4075 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
4076 Results.push_back(Tmp1);
4079 case ISD::FP_TO_UINT:
4080 case ISD::FP_TO_SINT:
4081 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4082 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4083 Results.push_back(Tmp1);
4085 case ISD::UINT_TO_FP:
4086 case ISD::SINT_TO_FP:
4087 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4088 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4089 Results.push_back(Tmp1);
4092 SDValue Chain = Node->getOperand(0); // Get the chain.
4093 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4096 if (OVT.isVector()) {
4097 TruncOp = ISD::BITCAST;
4099 assert(OVT.isInteger()
4100 && "VAARG promotion is supported only for vectors or integer types");
4101 TruncOp = ISD::TRUNCATE;
4104 // Perform the larger operation, then convert back
4105 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4106 Node->getConstantOperandVal(3));
4107 Chain = Tmp1.getValue(1);
4109 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4111 // Modified the chain result - switch anything that used the old chain to
4113 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4114 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4121 unsigned ExtOp, TruncOp;
4122 if (OVT.isVector()) {
4123 ExtOp = ISD::BITCAST;
4124 TruncOp = ISD::BITCAST;
4126 assert(OVT.isInteger() && "Cannot promote logic operation");
4127 ExtOp = ISD::ANY_EXTEND;
4128 TruncOp = ISD::TRUNCATE;
4130 // Promote each of the values to the new type.
4131 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4132 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4133 // Perform the larger operation, then convert back
4134 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4135 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4139 unsigned ExtOp, TruncOp;
4140 if (Node->getValueType(0).isVector() ||
4141 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4142 ExtOp = ISD::BITCAST;
4143 TruncOp = ISD::BITCAST;
4144 } else if (Node->getValueType(0).isInteger()) {
4145 ExtOp = ISD::ANY_EXTEND;
4146 TruncOp = ISD::TRUNCATE;
4148 ExtOp = ISD::FP_EXTEND;
4149 TruncOp = ISD::FP_ROUND;
4151 Tmp1 = Node->getOperand(0);
4152 // Promote each of the values to the new type.
4153 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4154 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4155 // Perform the larger operation, then round down.
4156 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4157 if (TruncOp != ISD::FP_ROUND)
4158 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4160 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4161 DAG.getIntPtrConstant(0));
4162 Results.push_back(Tmp1);
4165 case ISD::VECTOR_SHUFFLE: {
4166 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4168 // Cast the two input vectors.
4169 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4170 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4172 // Convert the shuffle mask to the right # elements.
4173 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4174 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4175 Results.push_back(Tmp1);
4179 unsigned ExtOp = ISD::FP_EXTEND;
4180 if (NVT.isInteger()) {
4181 ISD::CondCode CCCode =
4182 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4183 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4185 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4186 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4187 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4188 Tmp1, Tmp2, Node->getOperand(2)));
4194 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4195 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4196 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4197 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4198 Tmp3, DAG.getIntPtrConstant(0)));
4205 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4206 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4207 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4208 Tmp2, DAG.getIntPtrConstant(0)));
4213 // Replace the original node with the legalized result.
4214 if (!Results.empty())
4215 ReplaceNode(Node, Results.data());
4218 // SelectionDAG::Legalize - This is the entry point for the file.
4220 void SelectionDAG::Legalize() {
4221 /// run - This is the main entry point to this class.
4223 SelectionDAGLegalize(*this).LegalizeDAG();