1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
44 struct FloatSignAsInt;
46 //===----------------------------------------------------------------------===//
47 /// This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
58 class SelectionDAGLegalize {
59 const TargetMachine &TM;
60 const TargetLowering &TLI;
63 /// \brief The set of nodes which have already been legalized. We hold a
64 /// reference to it in order to update as necessary on node deletion.
65 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
67 /// \brief A set of all the nodes updated during legalization.
68 SmallSetVector<SDNode *, 16> *UpdatedNodes;
70 EVT getSetCCResultType(EVT VT) const {
71 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
74 // Libcall insertion helpers.
77 SelectionDAGLegalize(SelectionDAG &DAG,
78 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
79 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
80 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
81 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
83 /// \brief Legalizes the given operation.
84 void LegalizeOp(SDNode *Node);
87 SDValue OptimizeFloatStore(StoreSDNode *ST);
89 void LegalizeLoadOps(SDNode *Node);
90 void LegalizeStoreOps(SDNode *Node);
92 /// Some targets cannot handle a variable
93 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
94 /// is necessary to spill the vector being inserted into to memory, perform
95 /// the insert there, and then read the result back.
96 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
97 SDValue Idx, SDLoc dl);
98 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
99 SDValue Idx, SDLoc dl);
101 /// Return a vector shuffle operation which
102 /// performs the same shuffe in terms of order or result bytes, but on a type
103 /// whose vector element type is narrower than the original shuffle type.
104 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
106 SDValue N1, SDValue N2,
107 ArrayRef<int> Mask) const;
109 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
110 bool &NeedInvert, SDLoc dl);
112 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
113 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
114 unsigned NumOps, bool isSigned, SDLoc dl);
116 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
117 SDNode *Node, bool isSigned);
118 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
119 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
120 RTLIB::Libcall Call_F128,
121 RTLIB::Libcall Call_PPCF128);
122 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
123 RTLIB::Libcall Call_I8,
124 RTLIB::Libcall Call_I16,
125 RTLIB::Libcall Call_I32,
126 RTLIB::Libcall Call_I64,
127 RTLIB::Libcall Call_I128);
128 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
129 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
132 SDValue ExpandBUILD_VECTOR(SDNode *Node);
133 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
134 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
135 SmallVectorImpl<SDValue> &Results);
136 void getSignAsIntValue(FloatSignAsInt &State, SDLoc DL, SDValue Value) const;
137 SDValue modifySignAsInt(const FloatSignAsInt &State, SDLoc DL,
138 SDValue NewIntValue) const;
139 SDValue ExpandFCOPYSIGN(SDNode *Node) const;
140 SDValue ExpandFABS(SDNode *Node) const;
141 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
143 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
145 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
148 SDValue ExpandBITREVERSE(SDValue Op, SDLoc dl);
149 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
150 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
152 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
153 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
154 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
156 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
157 SDValue ExpandConstant(ConstantSDNode *CP);
159 // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
160 bool ExpandNode(SDNode *Node);
161 void ConvertNodeToLibcall(SDNode *Node);
162 void PromoteNode(SDNode *Node);
165 // Node replacement helpers
166 void ReplacedNode(SDNode *N) {
167 LegalizedNodes.erase(N);
169 UpdatedNodes->insert(N);
171 void ReplaceNode(SDNode *Old, SDNode *New) {
172 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
173 dbgs() << " with: "; New->dump(&DAG));
175 assert(Old->getNumValues() == New->getNumValues() &&
176 "Replacing one node with another that produces a different number "
178 DAG.ReplaceAllUsesWith(Old, New);
179 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
180 DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i));
182 UpdatedNodes->insert(New);
185 void ReplaceNode(SDValue Old, SDValue New) {
186 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
187 dbgs() << " with: "; New->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
190 DAG.TransferDbgValues(Old, New);
192 UpdatedNodes->insert(New.getNode());
193 ReplacedNode(Old.getNode());
195 void ReplaceNode(SDNode *Old, const SDValue *New) {
196 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
198 DAG.ReplaceAllUsesWith(Old, New);
199 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
200 DEBUG(dbgs() << (i == 0 ? " with: "
203 DAG.TransferDbgValues(SDValue(Old, i), New[i]);
205 UpdatedNodes->insert(New[i].getNode());
212 /// Return a vector shuffle operation which
213 /// performs the same shuffe in terms of order or result bytes, but on a type
214 /// whose vector element type is narrower than the original shuffle type.
215 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
217 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
218 SDValue N1, SDValue N2,
219 ArrayRef<int> Mask) const {
220 unsigned NumMaskElts = VT.getVectorNumElements();
221 unsigned NumDestElts = NVT.getVectorNumElements();
222 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
224 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
226 if (NumEltsGrowth == 1)
227 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
229 SmallVector<int, 8> NewMask;
230 for (unsigned i = 0; i != NumMaskElts; ++i) {
232 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
234 NewMask.push_back(-1);
236 NewMask.push_back(Idx * NumEltsGrowth + j);
239 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
240 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
241 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
244 /// Expands the ConstantFP node to an integer constant or
245 /// a load from the constant pool.
247 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
251 // If a FP immediate is precise when represented as a float and if the
252 // target can do an extending load from float to double, we put it into
253 // the constant pool as a float, even if it's is statically typed as a
254 // double. This shrinks FP constants and canonicalizes them for targets where
255 // an FP extending load is the same cost as a normal load (such as on the x87
256 // fp stack or PPC FP unit).
257 EVT VT = CFP->getValueType(0);
258 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
260 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
261 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
262 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
267 while (SVT != MVT::f32 && SVT != MVT::f16) {
268 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
269 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
270 // Only do this if the target has a native EXTLOAD instruction from
272 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
273 TLI.ShouldShrinkFPConstant(OrigVT)) {
274 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
275 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
282 DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
283 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
285 SDValue Result = DAG.getExtLoad(
286 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
287 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
288 false, false, false, Alignment);
292 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
293 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
294 false, false, false, Alignment);
298 /// Expands the Constant node to a load from the constant pool.
299 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
301 EVT VT = CP->getValueType(0);
302 SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
303 TLI.getPointerTy(DAG.getDataLayout()));
304 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
306 DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
307 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
308 false, false, false, Alignment);
312 /// Expands an unaligned store to 2 half-size stores.
313 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
314 const TargetLowering &TLI,
315 SelectionDAGLegalize *DAGLegalize) {
316 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
317 "unaligned indexed stores not implemented!");
318 SDValue Chain = ST->getChain();
319 SDValue Ptr = ST->getBasePtr();
320 SDValue Val = ST->getValue();
321 EVT VT = Val.getValueType();
322 int Alignment = ST->getAlignment();
323 unsigned AS = ST->getAddressSpace();
326 if (ST->getMemoryVT().isFloatingPoint() ||
327 ST->getMemoryVT().isVector()) {
328 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
329 if (TLI.isTypeLegal(intVT)) {
330 // Expand to a bitconvert of the value to the integer type of the
331 // same size, then a (misaligned) int store.
332 // FIXME: Does not handle truncating floating point stores!
333 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
334 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
335 ST->isVolatile(), ST->isNonTemporal(), Alignment);
336 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
339 // Do a (aligned) store to a stack slot, then copy from the stack slot
340 // to the final destination using (unaligned) integer loads and stores.
341 EVT StoredVT = ST->getMemoryVT();
343 TLI.getRegisterType(*DAG.getContext(),
344 EVT::getIntegerVT(*DAG.getContext(),
345 StoredVT.getSizeInBits()));
346 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
347 unsigned RegBytes = RegVT.getSizeInBits() / 8;
348 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
350 // Make sure the stack slot is also aligned for the register type.
351 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
353 // Perform the original store, only redirected to the stack slot.
354 SDValue Store = DAG.getTruncStore(Chain, dl,
355 Val, StackPtr, MachinePointerInfo(),
356 StoredVT, false, false, 0);
357 SDValue Increment = DAG.getConstant(
358 RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout(), AS));
359 SmallVector<SDValue, 8> Stores;
362 // Do all but one copies using the full register width.
363 for (unsigned i = 1; i < NumRegs; i++) {
364 // Load one integer register's worth from the stack slot.
365 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
366 MachinePointerInfo(),
367 false, false, false, 0);
368 // Store it to the final location. Remember the store.
369 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
370 ST->getPointerInfo().getWithOffset(Offset),
371 ST->isVolatile(), ST->isNonTemporal(),
372 MinAlign(ST->getAlignment(), Offset)));
373 // Increment the pointers.
375 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
377 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
380 // The last store may be partial. Do a truncating store. On big-endian
381 // machines this requires an extending load from the stack slot to ensure
382 // that the bits are in the right place.
383 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
384 8 * (StoredBytes - Offset));
386 // Load from the stack slot.
387 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
388 MachinePointerInfo(),
389 MemVT, false, false, false, 0);
391 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
393 .getWithOffset(Offset),
394 MemVT, ST->isVolatile(),
396 MinAlign(ST->getAlignment(), Offset),
398 // The order of the stores doesn't matter - say it with a TokenFactor.
399 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
400 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
403 assert(ST->getMemoryVT().isInteger() &&
404 !ST->getMemoryVT().isVector() &&
405 "Unaligned store of unknown type.");
406 // Get the half-size VT
407 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
408 int NumBits = NewStoredVT.getSizeInBits();
409 int IncrementSize = NumBits / 8;
411 // Divide the stored value in two parts.
412 SDValue ShiftAmount =
413 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Val.getValueType(),
414 DAG.getDataLayout()));
416 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
418 // Store the two parts
419 SDValue Store1, Store2;
420 Store1 = DAG.getTruncStore(Chain, dl,
421 DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
422 Ptr, ST->getPointerInfo(), NewStoredVT,
423 ST->isVolatile(), ST->isNonTemporal(), Alignment);
425 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
426 DAG.getConstant(IncrementSize, dl,
427 TLI.getPointerTy(DAG.getDataLayout(), AS)));
428 Alignment = MinAlign(Alignment, IncrementSize);
429 Store2 = DAG.getTruncStore(
430 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
431 ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT,
432 ST->isVolatile(), ST->isNonTemporal(), Alignment, ST->getAAInfo());
435 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
436 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
439 /// Expands an unaligned load to 2 half-size loads.
441 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
442 const TargetLowering &TLI,
443 SDValue &ValResult, SDValue &ChainResult) {
444 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
445 "unaligned indexed loads not implemented!");
446 SDValue Chain = LD->getChain();
447 SDValue Ptr = LD->getBasePtr();
448 EVT VT = LD->getValueType(0);
449 EVT LoadedVT = LD->getMemoryVT();
451 if (VT.isFloatingPoint() || VT.isVector()) {
452 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
453 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
454 // Expand to a (misaligned) integer load of the same size,
455 // then bitconvert to floating point or vector.
456 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
457 LD->getMemOperand());
458 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
460 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
461 ISD::ANY_EXTEND, dl, VT, Result);
464 ChainResult = newLoad.getValue(1);
468 // Copy the value to a (aligned) stack slot using (unaligned) integer
469 // loads and stores, then do a (aligned) load from the stack slot.
470 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
471 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
472 unsigned RegBytes = RegVT.getSizeInBits() / 8;
473 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
475 // Make sure the stack slot is also aligned for the register type.
476 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
479 DAG.getConstant(RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout()));
480 SmallVector<SDValue, 8> Stores;
481 SDValue StackPtr = StackBase;
484 // Do all but one copies using the full register width.
485 for (unsigned i = 1; i < NumRegs; i++) {
486 // Load one integer register's worth from the original location.
487 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
488 LD->getPointerInfo().getWithOffset(Offset),
489 LD->isVolatile(), LD->isNonTemporal(),
491 MinAlign(LD->getAlignment(), Offset),
493 // Follow the load with a store to the stack slot. Remember the store.
494 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
495 MachinePointerInfo(), false, false, 0));
496 // Increment the pointers.
498 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
499 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
503 // The last copy may be partial. Do an extending load.
504 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
505 8 * (LoadedBytes - Offset));
506 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
507 LD->getPointerInfo().getWithOffset(Offset),
508 MemVT, LD->isVolatile(),
511 MinAlign(LD->getAlignment(), Offset),
513 // Follow the load with a store to the stack slot. Remember the store.
514 // On big-endian machines this requires a truncating store to ensure
515 // that the bits end up in the right place.
516 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
517 MachinePointerInfo(), MemVT,
520 // The order of the stores doesn't matter - say it with a TokenFactor.
521 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
523 // Finally, perform the original load only redirected to the stack slot.
524 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
525 MachinePointerInfo(), LoadedVT, false,false, false,
528 // Callers expect a MERGE_VALUES node.
533 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
534 "Unaligned load of unsupported type.");
536 // Compute the new VT that is half the size of the old one. This is an
538 unsigned NumBits = LoadedVT.getSizeInBits();
540 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
543 unsigned Alignment = LD->getAlignment();
544 unsigned IncrementSize = NumBits / 8;
545 ISD::LoadExtType HiExtType = LD->getExtensionType();
547 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
548 if (HiExtType == ISD::NON_EXTLOAD)
549 HiExtType = ISD::ZEXTLOAD;
551 // Load the value in two parts
553 if (DAG.getDataLayout().isLittleEndian()) {
554 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
555 NewLoadedVT, LD->isVolatile(),
556 LD->isNonTemporal(), LD->isInvariant(), Alignment,
558 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
559 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
560 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
561 LD->getPointerInfo().getWithOffset(IncrementSize),
562 NewLoadedVT, LD->isVolatile(),
563 LD->isNonTemporal(),LD->isInvariant(),
564 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
566 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
567 NewLoadedVT, LD->isVolatile(),
568 LD->isNonTemporal(), LD->isInvariant(), Alignment,
570 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
571 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
572 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
573 LD->getPointerInfo().getWithOffset(IncrementSize),
574 NewLoadedVT, LD->isVolatile(),
575 LD->isNonTemporal(), LD->isInvariant(),
576 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
579 // aggregate the two parts
580 SDValue ShiftAmount =
581 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Hi.getValueType(),
582 DAG.getDataLayout()));
583 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
584 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
586 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
593 /// Some target cannot handle a variable insertion index for the
594 /// INSERT_VECTOR_ELT instruction. In this case, it
595 /// is necessary to spill the vector being inserted into to memory, perform
596 /// the insert there, and then read the result back.
597 SDValue SelectionDAGLegalize::
598 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
604 // If the target doesn't support this, we have to spill the input vector
605 // to a temporary stack slot, update the element, then reload it. This is
606 // badness. We could also load the value into a vector register (either
607 // with a "move to register" or "extload into register" instruction, then
608 // permute it into place, if the idx is a constant and if the idx is
609 // supported by the target.
610 EVT VT = Tmp1.getValueType();
611 EVT EltVT = VT.getVectorElementType();
612 EVT IdxVT = Tmp3.getValueType();
613 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
614 SDValue StackPtr = DAG.CreateStackTemporary(VT);
616 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
619 SDValue Ch = DAG.getStore(
620 DAG.getEntryNode(), dl, Tmp1, StackPtr,
621 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI), false,
624 // Truncate or zero extend offset to target pointer type.
625 Tmp3 = DAG.getZExtOrTrunc(Tmp3, dl, PtrVT);
626 // Add the offset to the index.
627 unsigned EltSize = EltVT.getSizeInBits()/8;
628 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,
629 DAG.getConstant(EltSize, dl, IdxVT));
630 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
631 // Store the scalar value.
632 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
634 // Load the updated vector.
635 return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
636 DAG.getMachineFunction(), SPFI),
637 false, false, false, 0);
641 SDValue SelectionDAGLegalize::
642 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
643 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
644 // SCALAR_TO_VECTOR requires that the type of the value being inserted
645 // match the element type of the vector being created, except for
646 // integers in which case the inserted value can be over width.
647 EVT EltVT = Vec.getValueType().getVectorElementType();
648 if (Val.getValueType() == EltVT ||
649 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
650 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
651 Vec.getValueType(), Val);
653 unsigned NumElts = Vec.getValueType().getVectorNumElements();
654 // We generate a shuffle of InVec and ScVec, so the shuffle mask
655 // should be 0,1,2,3,4,5... with the appropriate element replaced with
657 SmallVector<int, 8> ShufOps;
658 for (unsigned i = 0; i != NumElts; ++i)
659 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
661 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
665 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
668 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
669 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
670 // FIXME: We shouldn't do this for TargetConstantFP's.
671 // FIXME: move this to the DAG Combiner! Note that we can't regress due
672 // to phase ordering between legalized code and the dag combiner. This
673 // probably means that we need to integrate dag combiner and legalizer
675 // We generally can't do this one for long doubles.
676 SDValue Chain = ST->getChain();
677 SDValue Ptr = ST->getBasePtr();
678 unsigned Alignment = ST->getAlignment();
679 bool isVolatile = ST->isVolatile();
680 bool isNonTemporal = ST->isNonTemporal();
681 AAMDNodes AAInfo = ST->getAAInfo();
683 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
684 if (CFP->getValueType(0) == MVT::f32 &&
685 TLI.isTypeLegal(MVT::i32)) {
686 SDValue Con = DAG.getConstant(CFP->getValueAPF().
687 bitcastToAPInt().zextOrTrunc(32),
688 SDLoc(CFP), MVT::i32);
689 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
690 isVolatile, isNonTemporal, Alignment, AAInfo);
693 if (CFP->getValueType(0) == MVT::f64) {
694 // If this target supports 64-bit registers, do a single 64-bit store.
695 if (TLI.isTypeLegal(MVT::i64)) {
696 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
697 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
698 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
699 isVolatile, isNonTemporal, Alignment, AAInfo);
702 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
703 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
704 // stores. If the target supports neither 32- nor 64-bits, this
705 // xform is certainly not worth it.
706 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
707 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
708 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
709 if (DAG.getDataLayout().isBigEndian())
712 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
713 isNonTemporal, Alignment, AAInfo);
714 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
715 DAG.getConstant(4, dl, Ptr.getValueType()));
716 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
717 ST->getPointerInfo().getWithOffset(4),
718 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
721 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
725 return SDValue(nullptr, 0);
728 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
729 StoreSDNode *ST = cast<StoreSDNode>(Node);
730 SDValue Chain = ST->getChain();
731 SDValue Ptr = ST->getBasePtr();
734 unsigned Alignment = ST->getAlignment();
735 bool isVolatile = ST->isVolatile();
736 bool isNonTemporal = ST->isNonTemporal();
737 AAMDNodes AAInfo = ST->getAAInfo();
739 if (!ST->isTruncatingStore()) {
740 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
741 ReplaceNode(ST, OptStore);
746 SDValue Value = ST->getValue();
747 MVT VT = Value.getSimpleValueType();
748 switch (TLI.getOperationAction(ISD::STORE, VT)) {
749 default: llvm_unreachable("This action is not supported yet!");
750 case TargetLowering::Legal: {
751 // If this is an unaligned store and the target doesn't support it,
753 EVT MemVT = ST->getMemoryVT();
754 unsigned AS = ST->getAddressSpace();
755 unsigned Align = ST->getAlignment();
756 const DataLayout &DL = DAG.getDataLayout();
757 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
758 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
761 case TargetLowering::Custom: {
762 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
763 if (Res && Res != SDValue(Node, 0))
764 ReplaceNode(SDValue(Node, 0), Res);
767 case TargetLowering::Promote: {
768 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
769 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
770 "Can only promote stores to same size type");
771 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
773 DAG.getStore(Chain, dl, Value, Ptr,
774 ST->getPointerInfo(), isVolatile,
775 isNonTemporal, Alignment, AAInfo);
776 ReplaceNode(SDValue(Node, 0), Result);
783 SDValue Value = ST->getValue();
785 EVT StVT = ST->getMemoryVT();
786 unsigned StWidth = StVT.getSizeInBits();
787 auto &DL = DAG.getDataLayout();
789 if (StWidth != StVT.getStoreSizeInBits()) {
790 // Promote to a byte-sized store with upper bits zero if not
791 // storing an integral number of bytes. For example, promote
792 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
793 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
794 StVT.getStoreSizeInBits());
795 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
797 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
798 NVT, isVolatile, isNonTemporal, Alignment, AAInfo);
799 ReplaceNode(SDValue(Node, 0), Result);
800 } else if (StWidth & (StWidth - 1)) {
801 // If not storing a power-of-2 number of bits, expand as two stores.
802 assert(!StVT.isVector() && "Unsupported truncstore!");
803 unsigned RoundWidth = 1 << Log2_32(StWidth);
804 assert(RoundWidth < StWidth);
805 unsigned ExtraWidth = StWidth - RoundWidth;
806 assert(ExtraWidth < RoundWidth);
807 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
808 "Store size not an integral number of bytes!");
809 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
810 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
812 unsigned IncrementSize;
814 if (DL.isLittleEndian()) {
815 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
816 // Store the bottom RoundWidth bits.
817 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
819 isVolatile, isNonTemporal, Alignment,
822 // Store the remaining ExtraWidth bits.
823 IncrementSize = RoundWidth / 8;
824 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
825 DAG.getConstant(IncrementSize, dl,
826 Ptr.getValueType()));
828 ISD::SRL, dl, Value.getValueType(), Value,
829 DAG.getConstant(RoundWidth, dl,
830 TLI.getShiftAmountTy(Value.getValueType(), DL)));
831 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
832 ST->getPointerInfo().getWithOffset(IncrementSize),
833 ExtraVT, isVolatile, isNonTemporal,
834 MinAlign(Alignment, IncrementSize), AAInfo);
836 // Big endian - avoid unaligned stores.
837 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
838 // Store the top RoundWidth bits.
840 ISD::SRL, dl, Value.getValueType(), Value,
841 DAG.getConstant(ExtraWidth, dl,
842 TLI.getShiftAmountTy(Value.getValueType(), DL)));
843 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
844 RoundVT, isVolatile, isNonTemporal, Alignment,
847 // Store the remaining ExtraWidth bits.
848 IncrementSize = RoundWidth / 8;
849 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
850 DAG.getConstant(IncrementSize, dl,
851 Ptr.getValueType()));
852 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
853 ST->getPointerInfo().getWithOffset(IncrementSize),
854 ExtraVT, isVolatile, isNonTemporal,
855 MinAlign(Alignment, IncrementSize), AAInfo);
858 // The order of the stores doesn't matter.
859 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
860 ReplaceNode(SDValue(Node, 0), Result);
862 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
863 default: llvm_unreachable("This action is not supported yet!");
864 case TargetLowering::Legal: {
865 EVT MemVT = ST->getMemoryVT();
866 unsigned AS = ST->getAddressSpace();
867 unsigned Align = ST->getAlignment();
868 // If this is an unaligned store and the target doesn't support it,
870 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
871 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
874 case TargetLowering::Custom: {
875 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
876 if (Res && Res != SDValue(Node, 0))
877 ReplaceNode(SDValue(Node, 0), Res);
880 case TargetLowering::Expand:
881 assert(!StVT.isVector() &&
882 "Vector Stores are handled in LegalizeVectorOps");
884 // TRUNCSTORE:i16 i32 -> STORE i16
885 assert(TLI.isTypeLegal(StVT) &&
886 "Do not know how to expand this store!");
887 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
889 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
890 isVolatile, isNonTemporal, Alignment, AAInfo);
891 ReplaceNode(SDValue(Node, 0), Result);
898 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
899 LoadSDNode *LD = cast<LoadSDNode>(Node);
900 SDValue Chain = LD->getChain(); // The chain.
901 SDValue Ptr = LD->getBasePtr(); // The base pointer.
902 SDValue Value; // The value returned by the load op.
905 ISD::LoadExtType ExtType = LD->getExtensionType();
906 if (ExtType == ISD::NON_EXTLOAD) {
907 MVT VT = Node->getSimpleValueType(0);
908 SDValue RVal = SDValue(Node, 0);
909 SDValue RChain = SDValue(Node, 1);
911 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
912 default: llvm_unreachable("This action is not supported yet!");
913 case TargetLowering::Legal: {
914 EVT MemVT = LD->getMemoryVT();
915 unsigned AS = LD->getAddressSpace();
916 unsigned Align = LD->getAlignment();
917 const DataLayout &DL = DAG.getDataLayout();
918 // If this is an unaligned load and the target doesn't support it,
920 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
921 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
924 case TargetLowering::Custom: {
925 SDValue Res = TLI.LowerOperation(RVal, DAG);
928 RChain = Res.getValue(1);
932 case TargetLowering::Promote: {
933 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
934 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
935 "Can only promote loads to same size type");
937 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
938 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
939 RChain = Res.getValue(1);
943 if (RChain.getNode() != Node) {
944 assert(RVal.getNode() != Node && "Load must be completely replaced");
945 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
946 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
948 UpdatedNodes->insert(RVal.getNode());
949 UpdatedNodes->insert(RChain.getNode());
956 EVT SrcVT = LD->getMemoryVT();
957 unsigned SrcWidth = SrcVT.getSizeInBits();
958 unsigned Alignment = LD->getAlignment();
959 bool isVolatile = LD->isVolatile();
960 bool isNonTemporal = LD->isNonTemporal();
961 bool isInvariant = LD->isInvariant();
962 AAMDNodes AAInfo = LD->getAAInfo();
964 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
965 // Some targets pretend to have an i1 loading operation, and actually
966 // load an i8. This trick is correct for ZEXTLOAD because the top 7
967 // bits are guaranteed to be zero; it helps the optimizers understand
968 // that these bits are zero. It is also useful for EXTLOAD, since it
969 // tells the optimizers that those bits are undefined. It would be
970 // nice to have an effective generic way of getting these benefits...
971 // Until such a way is found, don't insist on promoting i1 here.
973 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
974 TargetLowering::Promote)) {
975 // Promote to a byte-sized load if not loading an integral number of
976 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
977 unsigned NewWidth = SrcVT.getStoreSizeInBits();
978 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
981 // The extra bits are guaranteed to be zero, since we stored them that
982 // way. A zext load from NVT thus automatically gives zext from SrcVT.
984 ISD::LoadExtType NewExtType =
985 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
988 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
989 Chain, Ptr, LD->getPointerInfo(),
990 NVT, isVolatile, isNonTemporal, isInvariant, Alignment,
993 Ch = Result.getValue(1); // The chain.
995 if (ExtType == ISD::SEXTLOAD)
996 // Having the top bits zero doesn't help when sign extending.
997 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
998 Result.getValueType(),
999 Result, DAG.getValueType(SrcVT));
1000 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1001 // All the top bits are guaranteed to be zero - inform the optimizers.
1002 Result = DAG.getNode(ISD::AssertZext, dl,
1003 Result.getValueType(), Result,
1004 DAG.getValueType(SrcVT));
1008 } else if (SrcWidth & (SrcWidth - 1)) {
1009 // If not loading a power-of-2 number of bits, expand as two loads.
1010 assert(!SrcVT.isVector() && "Unsupported extload!");
1011 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1012 assert(RoundWidth < SrcWidth);
1013 unsigned ExtraWidth = SrcWidth - RoundWidth;
1014 assert(ExtraWidth < RoundWidth);
1015 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1016 "Load size not an integral number of bytes!");
1017 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1018 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1020 unsigned IncrementSize;
1021 auto &DL = DAG.getDataLayout();
1023 if (DL.isLittleEndian()) {
1024 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1025 // Load the bottom RoundWidth bits.
1026 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1028 LD->getPointerInfo(), RoundVT, isVolatile,
1029 isNonTemporal, isInvariant, Alignment, AAInfo);
1031 // Load the remaining ExtraWidth bits.
1032 IncrementSize = RoundWidth / 8;
1033 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1034 DAG.getConstant(IncrementSize, dl,
1035 Ptr.getValueType()));
1036 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1037 LD->getPointerInfo().getWithOffset(IncrementSize),
1038 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1039 MinAlign(Alignment, IncrementSize), AAInfo);
1041 // Build a factor node to remember that this load is independent of
1043 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1046 // Move the top bits to the right place.
1048 ISD::SHL, dl, Hi.getValueType(), Hi,
1049 DAG.getConstant(RoundWidth, dl,
1050 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1052 // Join the hi and lo parts.
1053 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1055 // Big endian - avoid unaligned loads.
1056 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1057 // Load the top RoundWidth bits.
1058 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1059 LD->getPointerInfo(), RoundVT, isVolatile,
1060 isNonTemporal, isInvariant, Alignment, AAInfo);
1062 // Load the remaining ExtraWidth bits.
1063 IncrementSize = RoundWidth / 8;
1064 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1065 DAG.getConstant(IncrementSize, dl,
1066 Ptr.getValueType()));
1067 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1068 dl, Node->getValueType(0), Chain, Ptr,
1069 LD->getPointerInfo().getWithOffset(IncrementSize),
1070 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1071 MinAlign(Alignment, IncrementSize), AAInfo);
1073 // Build a factor node to remember that this load is independent of
1075 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1078 // Move the top bits to the right place.
1080 ISD::SHL, dl, Hi.getValueType(), Hi,
1081 DAG.getConstant(ExtraWidth, dl,
1082 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1084 // Join the hi and lo parts.
1085 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1090 bool isCustom = false;
1091 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1092 SrcVT.getSimpleVT())) {
1093 default: llvm_unreachable("This action is not supported yet!");
1094 case TargetLowering::Custom:
1097 case TargetLowering::Legal: {
1098 Value = SDValue(Node, 0);
1099 Chain = SDValue(Node, 1);
1102 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1103 if (Res.getNode()) {
1105 Chain = Res.getValue(1);
1108 // If this is an unaligned load and the target doesn't support it,
1110 EVT MemVT = LD->getMemoryVT();
1111 unsigned AS = LD->getAddressSpace();
1112 unsigned Align = LD->getAlignment();
1113 const DataLayout &DL = DAG.getDataLayout();
1114 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
1115 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
1119 case TargetLowering::Expand:
1120 EVT DestVT = Node->getValueType(0);
1121 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
1122 // If the source type is not legal, see if there is a legal extload to
1123 // an intermediate type that we can then extend further.
1124 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
1125 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
1126 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
1127 // If we are loading a legal type, this is a non-extload followed by a
1129 ISD::LoadExtType MidExtType =
1130 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1132 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
1133 SrcVT, LD->getMemOperand());
1135 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1136 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1137 Chain = Load.getValue(1);
1141 // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
1142 // normal undefined upper bits behavior to allow using an in-reg extend
1143 // with the illegal FP type, so load as an integer and do the
1144 // from-integer conversion.
1145 if (SrcVT.getScalarType() == MVT::f16) {
1146 EVT ISrcVT = SrcVT.changeTypeToInteger();
1147 EVT IDestVT = DestVT.changeTypeToInteger();
1148 EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
1150 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
1152 LD->getMemOperand());
1153 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
1154 Chain = Result.getValue(1);
1159 assert(!SrcVT.isVector() &&
1160 "Vector Loads are handled in LegalizeVectorOps");
1162 // FIXME: This does not work for vectors on most targets. Sign-
1163 // and zero-extend operations are currently folded into extending
1164 // loads, whether they are legal or not, and then we end up here
1165 // without any support for legalizing them.
1166 assert(ExtType != ISD::EXTLOAD &&
1167 "EXTLOAD should always be supported!");
1168 // Turn the unsupported load into an EXTLOAD followed by an
1169 // explicit zero/sign extend inreg.
1170 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1171 Node->getValueType(0),
1173 LD->getMemOperand());
1175 if (ExtType == ISD::SEXTLOAD)
1176 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1177 Result.getValueType(),
1178 Result, DAG.getValueType(SrcVT));
1180 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1182 Chain = Result.getValue(1);
1187 // Since loads produce two values, make sure to remember that we legalized
1189 if (Chain.getNode() != Node) {
1190 assert(Value.getNode() != Node && "Load must be completely replaced");
1191 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1192 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1194 UpdatedNodes->insert(Value.getNode());
1195 UpdatedNodes->insert(Chain.getNode());
1201 /// Return a legal replacement for the given operation, with all legal operands.
1202 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1203 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
1205 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1209 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1210 assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1211 TargetLowering::TypeLegal ||
1212 TLI.isTypeLegal(Node->getValueType(i))) &&
1213 "Unexpected illegal type!");
1215 for (const SDValue &Op : Node->op_values())
1216 assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
1217 TargetLowering::TypeLegal ||
1218 TLI.isTypeLegal(Op.getValueType()) ||
1219 Op.getOpcode() == ISD::TargetConstant) &&
1220 "Unexpected illegal type!");
1223 // Figure out the correct action; the way to query this varies by opcode
1224 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1225 bool SimpleFinishLegalizing = true;
1226 switch (Node->getOpcode()) {
1227 case ISD::INTRINSIC_W_CHAIN:
1228 case ISD::INTRINSIC_WO_CHAIN:
1229 case ISD::INTRINSIC_VOID:
1230 case ISD::STACKSAVE:
1231 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1233 case ISD::GET_DYNAMIC_AREA_OFFSET:
1234 Action = TLI.getOperationAction(Node->getOpcode(),
1235 Node->getValueType(0));
1238 Action = TLI.getOperationAction(Node->getOpcode(),
1239 Node->getValueType(0));
1240 if (Action != TargetLowering::Promote)
1241 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1243 case ISD::FP_TO_FP16:
1244 case ISD::SINT_TO_FP:
1245 case ISD::UINT_TO_FP:
1246 case ISD::EXTRACT_VECTOR_ELT:
1247 Action = TLI.getOperationAction(Node->getOpcode(),
1248 Node->getOperand(0).getValueType());
1250 case ISD::FP_ROUND_INREG:
1251 case ISD::SIGN_EXTEND_INREG: {
1252 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1253 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1256 case ISD::ATOMIC_STORE: {
1257 Action = TLI.getOperationAction(Node->getOpcode(),
1258 Node->getOperand(2).getValueType());
1261 case ISD::SELECT_CC:
1264 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1265 Node->getOpcode() == ISD::SETCC ? 2 :
1266 Node->getOpcode() == ISD::SETCCE ? 3 : 1;
1267 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1268 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1269 ISD::CondCode CCCode =
1270 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1271 Action = TLI.getCondCodeAction(CCCode, OpVT);
1272 if (Action == TargetLowering::Legal) {
1273 if (Node->getOpcode() == ISD::SELECT_CC)
1274 Action = TLI.getOperationAction(Node->getOpcode(),
1275 Node->getValueType(0));
1277 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1283 // FIXME: Model these properly. LOAD and STORE are complicated, and
1284 // STORE expects the unlegalized operand in some cases.
1285 SimpleFinishLegalizing = false;
1287 case ISD::CALLSEQ_START:
1288 case ISD::CALLSEQ_END:
1289 // FIXME: This shouldn't be necessary. These nodes have special properties
1290 // dealing with the recursive nature of legalization. Removing this
1291 // special case should be done as part of making LegalizeDAG non-recursive.
1292 SimpleFinishLegalizing = false;
1294 case ISD::EXTRACT_ELEMENT:
1295 case ISD::FLT_ROUNDS_:
1297 case ISD::MERGE_VALUES:
1298 case ISD::EH_RETURN:
1299 case ISD::FRAME_TO_ARGS_OFFSET:
1300 case ISD::EH_SJLJ_SETJMP:
1301 case ISD::EH_SJLJ_LONGJMP:
1302 case ISD::EH_SJLJ_SETUP_DISPATCH:
1303 // These operations lie about being legal: when they claim to be legal,
1304 // they should actually be expanded.
1305 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1306 if (Action == TargetLowering::Legal)
1307 Action = TargetLowering::Expand;
1309 case ISD::INIT_TRAMPOLINE:
1310 case ISD::ADJUST_TRAMPOLINE:
1311 case ISD::FRAMEADDR:
1312 case ISD::RETURNADDR:
1313 // These operations lie about being legal: when they claim to be legal,
1314 // they should actually be custom-lowered.
1315 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1316 if (Action == TargetLowering::Legal)
1317 Action = TargetLowering::Custom;
1319 case ISD::READCYCLECOUNTER:
1320 // READCYCLECOUNTER returns an i64, even if type legalization might have
1321 // expanded that to several smaller types.
1322 Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1324 case ISD::READ_REGISTER:
1325 case ISD::WRITE_REGISTER:
1326 // Named register is legal in the DAG, but blocked by register name
1327 // selection if not implemented by target (to chose the correct register)
1328 // They'll be converted to Copy(To/From)Reg.
1329 Action = TargetLowering::Legal;
1331 case ISD::DEBUGTRAP:
1332 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1333 if (Action == TargetLowering::Expand) {
1334 // replace ISD::DEBUGTRAP with ISD::TRAP
1336 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1337 Node->getOperand(0));
1338 ReplaceNode(Node, NewVal.getNode());
1339 LegalizeOp(NewVal.getNode());
1345 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1346 Action = TargetLowering::Legal;
1348 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1353 if (SimpleFinishLegalizing) {
1354 SDNode *NewNode = Node;
1355 switch (Node->getOpcode()) {
1362 // Legalizing shifts/rotates requires adjusting the shift amount
1363 // to the appropriate width.
1364 if (!Node->getOperand(1).getValueType().isVector()) {
1366 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1367 Node->getOperand(1));
1368 HandleSDNode Handle(SAO);
1369 LegalizeOp(SAO.getNode());
1370 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1374 case ISD::SRL_PARTS:
1375 case ISD::SRA_PARTS:
1376 case ISD::SHL_PARTS:
1377 // Legalizing shifts/rotates requires adjusting the shift amount
1378 // to the appropriate width.
1379 if (!Node->getOperand(2).getValueType().isVector()) {
1381 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1382 Node->getOperand(2));
1383 HandleSDNode Handle(SAO);
1384 LegalizeOp(SAO.getNode());
1385 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1386 Node->getOperand(1),
1392 if (NewNode != Node) {
1393 ReplaceNode(Node, NewNode);
1397 case TargetLowering::Legal:
1399 case TargetLowering::Custom: {
1400 // FIXME: The handling for custom lowering with multiple results is
1402 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1403 if (Res.getNode()) {
1404 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1407 if (Node->getNumValues() == 1) {
1408 // We can just directly replace this node with the lowered value.
1409 ReplaceNode(SDValue(Node, 0), Res);
1413 SmallVector<SDValue, 8> ResultVals;
1414 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1415 ResultVals.push_back(Res.getValue(i));
1416 ReplaceNode(Node, ResultVals.data());
1421 case TargetLowering::Expand:
1422 if (ExpandNode(Node))
1425 case TargetLowering::LibCall:
1426 ConvertNodeToLibcall(Node);
1428 case TargetLowering::Promote:
1434 switch (Node->getOpcode()) {
1441 llvm_unreachable("Do not know how to legalize this operator!");
1443 case ISD::CALLSEQ_START:
1444 case ISD::CALLSEQ_END:
1447 return LegalizeLoadOps(Node);
1450 return LegalizeStoreOps(Node);
1455 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1456 SDValue Vec = Op.getOperand(0);
1457 SDValue Idx = Op.getOperand(1);
1460 // Before we generate a new store to a temporary stack slot, see if there is
1461 // already one that we can use. There often is because when we scalarize
1462 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1463 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1464 // the vector. If all are expanded here, we don't want one store per vector
1467 // Caches for hasPredecessorHelper
1468 SmallPtrSet<const SDNode *, 32> Visited;
1469 SmallVector<const SDNode *, 16> Worklist;
1471 SDValue StackPtr, Ch;
1472 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1473 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1475 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1476 if (ST->isIndexed() || ST->isTruncatingStore() ||
1477 ST->getValue() != Vec)
1480 // Make sure that nothing else could have stored into the destination of
1482 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1485 // If the index is dependent on the store we will introduce a cycle when
1486 // creating the load (the load uses the index, and by replacing the chain
1487 // we will make the index dependent on the load).
1488 if (Idx.getNode()->hasPredecessorHelper(ST, Visited, Worklist))
1491 StackPtr = ST->getBasePtr();
1492 Ch = SDValue(ST, 0);
1497 if (!Ch.getNode()) {
1498 // Store the value to a temporary stack slot, then LOAD the returned part.
1499 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1500 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1501 MachinePointerInfo(), false, false, 0);
1504 // Add the offset to the index.
1506 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1507 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1508 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1510 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1511 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1515 if (Op.getValueType().isVector())
1516 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,
1517 MachinePointerInfo(), false, false, false, 0);
1519 NewLoad = DAG.getExtLoad(
1520 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(),
1521 Vec.getValueType().getVectorElementType(), false, false, false, 0);
1523 // Replace the chain going out of the store, by the one out of the load.
1524 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1526 // We introduced a cycle though, so update the loads operands, making sure
1527 // to use the original store's chain as an incoming chain.
1528 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1530 NewLoadOperands[0] = Ch;
1532 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1536 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1537 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1539 SDValue Vec = Op.getOperand(0);
1540 SDValue Part = Op.getOperand(1);
1541 SDValue Idx = Op.getOperand(2);
1544 // Store the value to a temporary stack slot, then LOAD the returned part.
1546 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1547 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1548 MachinePointerInfo PtrInfo =
1549 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1551 // First store the whole vector.
1552 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1555 // Then store the inserted part.
1557 // Add the offset to the index.
1559 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1561 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1562 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1563 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1565 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1568 // Store the subvector.
1569 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr,
1570 MachinePointerInfo(), false, false, 0);
1572 // Finally, load the updated vector.
1573 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1574 false, false, false, 0);
1577 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1578 // We can't handle this case efficiently. Allocate a sufficiently
1579 // aligned object on the stack, store each element into it, then load
1580 // the result as a vector.
1581 // Create the stack frame object.
1582 EVT VT = Node->getValueType(0);
1583 EVT EltVT = VT.getVectorElementType();
1585 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1586 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1587 MachinePointerInfo PtrInfo =
1588 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1590 // Emit a store of each element to the stack slot.
1591 SmallVector<SDValue, 8> Stores;
1592 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1593 // Store (in the right endianness) the elements to memory.
1594 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1595 // Ignore undef elements.
1596 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1598 unsigned Offset = TypeByteSize*i;
1600 SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1601 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1603 // If the destination vector element type is narrower than the source
1604 // element type, only store the bits necessary.
1605 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1606 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1607 Node->getOperand(i), Idx,
1608 PtrInfo.getWithOffset(Offset),
1609 EltVT, false, false, 0));
1611 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1612 Node->getOperand(i), Idx,
1613 PtrInfo.getWithOffset(Offset),
1618 if (!Stores.empty()) // Not all undef elements?
1619 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1621 StoreChain = DAG.getEntryNode();
1623 // Result is a load from the stack slot.
1624 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1625 false, false, false, 0);
1629 /// Keeps track of state when getting the sign of a floating-point value as an
1631 struct FloatSignAsInt {
1636 MachinePointerInfo IntPointerInfo;
1637 MachinePointerInfo FloatPointerInfo;
1643 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1644 /// containing the sign bit if the target has no integer value capable of
1645 /// holding all bits of the floating-point value.
1646 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1647 SDLoc DL, SDValue Value) const {
1648 EVT FloatVT = Value.getValueType();
1649 unsigned NumBits = FloatVT.getSizeInBits();
1650 State.FloatVT = FloatVT;
1651 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1652 // Convert to an integer of the same size.
1653 if (TLI.isTypeLegal(IVT)) {
1654 State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1655 State.SignMask = APInt::getSignBit(NumBits);
1659 auto &DataLayout = DAG.getDataLayout();
1660 // Store the float to memory, then load the sign part out as an integer.
1661 MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1662 // First create a temporary that is aligned for both the load and store.
1663 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1664 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1665 // Then store the float to it.
1666 State.FloatPtr = StackPtr;
1667 MachineFunction &MF = DAG.getMachineFunction();
1668 State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1669 State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1670 State.FloatPointerInfo, false, false, 0);
1673 if (DataLayout.isBigEndian()) {
1674 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1675 // Load out a legal integer with the same sign bit as the float.
1677 State.IntPointerInfo = State.FloatPointerInfo;
1679 // Advance the pointer so that the loaded byte will contain the sign bit.
1680 unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1681 IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1682 DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1683 State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1687 State.IntPtr = IntPtr;
1688 State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain,
1689 IntPtr, State.IntPointerInfo, MVT::i8,
1690 false, false, false, 0);
1691 State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1694 /// Replace the integer value produced by getSignAsIntValue() with a new value
1695 /// and cast the result back to a floating-point type.
1696 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1697 SDLoc DL, SDValue NewIntValue) const {
1699 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1701 // Override the part containing the sign bit in the value stored on the stack.
1702 SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1703 State.IntPointerInfo, MVT::i8, false, false,
1705 return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1706 State.FloatPointerInfo, false, false, false, 0);
1709 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1711 SDValue Mag = Node->getOperand(0);
1712 SDValue Sign = Node->getOperand(1);
1714 // Get sign bit into an integer value.
1715 FloatSignAsInt SignAsInt;
1716 getSignAsIntValue(SignAsInt, DL, Sign);
1718 EVT IntVT = SignAsInt.IntValue.getValueType();
1719 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1720 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1723 // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1724 EVT FloatVT = Mag.getValueType();
1725 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1726 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1727 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1728 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1729 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1730 DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1731 return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1734 // Transform values to integer, copy the sign bit and transform back.
1735 FloatSignAsInt MagAsInt;
1736 getSignAsIntValue(MagAsInt, DL, Mag);
1737 assert(SignAsInt.SignMask == MagAsInt.SignMask);
1738 SDValue ClearSignMask = DAG.getConstant(~SignAsInt.SignMask, DL, IntVT);
1739 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, MagAsInt.IntValue,
1741 SDValue CopiedSign = DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit);
1743 return modifySignAsInt(MagAsInt, DL, CopiedSign);
1746 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1748 SDValue Value = Node->getOperand(0);
1750 // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1751 EVT FloatVT = Value.getValueType();
1752 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1753 SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1754 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1757 // Transform value to integer, clear the sign bit and transform back.
1758 FloatSignAsInt ValueAsInt;
1759 getSignAsIntValue(ValueAsInt, DL, Value);
1760 EVT IntVT = ValueAsInt.IntValue.getValueType();
1761 SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1762 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1764 return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1767 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1768 SmallVectorImpl<SDValue> &Results) {
1769 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1770 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1771 " not tell us which reg is the stack pointer!");
1773 EVT VT = Node->getValueType(0);
1774 SDValue Tmp1 = SDValue(Node, 0);
1775 SDValue Tmp2 = SDValue(Node, 1);
1776 SDValue Tmp3 = Node->getOperand(2);
1777 SDValue Chain = Tmp1.getOperand(0);
1779 // Chain the dynamic stack allocation so that it doesn't modify the stack
1780 // pointer when other instructions are using the stack.
1781 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1783 SDValue Size = Tmp2.getOperand(1);
1784 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1785 Chain = SP.getValue(1);
1786 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1787 unsigned StackAlign =
1788 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1789 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1790 if (Align > StackAlign)
1791 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1792 DAG.getConstant(-(uint64_t)Align, dl, VT));
1793 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1795 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1796 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1798 Results.push_back(Tmp1);
1799 Results.push_back(Tmp2);
1802 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1805 /// If the SETCC has been legalized using AND / OR, then the legalized node
1806 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1807 /// will be set to false.
1809 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1810 /// then the values of LHS and RHS will be swapped, CC will be set to the
1811 /// new condition, and NeedInvert will be set to false.
1813 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1814 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1815 /// will be set to true. The caller must invert the result of the SETCC with
1816 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1817 /// of a true/false result.
1819 /// \returns true if the SetCC has been legalized, false if it hasn't.
1820 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1821 SDValue &LHS, SDValue &RHS,
1825 MVT OpVT = LHS.getSimpleValueType();
1826 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1828 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1829 default: llvm_unreachable("Unknown condition code action!");
1830 case TargetLowering::Legal:
1833 case TargetLowering::Expand: {
1834 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1835 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1836 std::swap(LHS, RHS);
1837 CC = DAG.getCondCode(InvCC);
1840 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1843 default: llvm_unreachable("Don't know how to expand this condition!");
1845 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1846 == TargetLowering::Legal
1847 && "If SETO is expanded, SETOEQ must be legal!");
1848 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1850 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1851 == TargetLowering::Legal
1852 && "If SETUO is expanded, SETUNE must be legal!");
1853 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1866 // If we are floating point, assign and break, otherwise fall through.
1867 if (!OpVT.isInteger()) {
1868 // We can use the 4th bit to tell if we are the unordered
1869 // or ordered version of the opcode.
1870 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1871 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1872 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1875 // Fallthrough if we are unsigned integer.
1880 // We only support using the inverted operation, which is computed above
1881 // and not a different manner of supporting expanding these cases.
1882 llvm_unreachable("Don't know how to expand this condition!");
1885 // Try inverting the result of the inverse condition.
1886 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1887 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1888 CC = DAG.getCondCode(InvCC);
1892 // If inverting the condition didn't work then we have no means to expand
1894 llvm_unreachable("Don't know how to expand this condition!");
1897 SDValue SetCC1, SetCC2;
1898 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1899 // If we aren't the ordered or unorder operation,
1900 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1901 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1902 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1904 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1905 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1906 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1908 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1917 /// Emit a store/load combination to the stack. This stores
1918 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1919 /// a load from the stack slot to DestVT, extending it if needed.
1920 /// The resultant code need not be legal.
1921 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1925 // Create the stack frame object.
1926 unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1927 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1928 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1930 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1931 int SPFI = StackPtrFI->getIndex();
1932 MachinePointerInfo PtrInfo =
1933 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1935 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1936 unsigned SlotSize = SlotVT.getSizeInBits();
1937 unsigned DestSize = DestVT.getSizeInBits();
1938 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1939 unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1941 // Emit a store to the stack slot. Use a truncstore if the input value is
1942 // later than DestVT.
1945 if (SrcSize > SlotSize)
1946 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1947 PtrInfo, SlotVT, false, false, SrcAlign);
1949 assert(SrcSize == SlotSize && "Invalid store");
1950 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1951 PtrInfo, false, false, SrcAlign);
1954 // Result is a load from the stack slot.
1955 if (SlotSize == DestSize)
1956 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1957 false, false, false, DestAlign);
1959 assert(SlotSize < DestSize && "Unknown extension!");
1960 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1961 PtrInfo, SlotVT, false, false, false, DestAlign);
1964 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1966 // Create a vector sized/aligned stack slot, store the value to element #0,
1967 // then load the whole vector back out.
1968 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1970 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1971 int SPFI = StackPtrFI->getIndex();
1973 SDValue Ch = DAG.getTruncStore(
1974 DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1975 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1976 Node->getValueType(0).getVectorElementType(), false, false, 0);
1978 Node->getValueType(0), dl, Ch, StackPtr,
1979 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI), false,
1984 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1985 const TargetLowering &TLI, SDValue &Res) {
1986 unsigned NumElems = Node->getNumOperands();
1988 EVT VT = Node->getValueType(0);
1990 // Try to group the scalars into pairs, shuffle the pairs together, then
1991 // shuffle the pairs of pairs together, etc. until the vector has
1992 // been built. This will work only if all of the necessary shuffle masks
1995 // We do this in two phases; first to check the legality of the shuffles,
1996 // and next, assuming that all shuffles are legal, to create the new nodes.
1997 for (int Phase = 0; Phase < 2; ++Phase) {
1998 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
2000 for (unsigned i = 0; i < NumElems; ++i) {
2001 SDValue V = Node->getOperand(i);
2002 if (V.getOpcode() == ISD::UNDEF)
2007 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
2008 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
2011 while (IntermedVals.size() > 2) {
2012 NewIntermedVals.clear();
2013 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
2014 // This vector and the next vector are shuffled together (simply to
2015 // append the one to the other).
2016 SmallVector<int, 16> ShuffleVec(NumElems, -1);
2018 SmallVector<int, 16> FinalIndices;
2019 FinalIndices.reserve(IntermedVals[i].second.size() +
2020 IntermedVals[i+1].second.size());
2023 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
2026 FinalIndices.push_back(IntermedVals[i].second[j]);
2028 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
2030 ShuffleVec[k] = NumElems + j;
2031 FinalIndices.push_back(IntermedVals[i+1].second[j]);
2036 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
2037 IntermedVals[i+1].first,
2039 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
2041 NewIntermedVals.push_back(
2042 std::make_pair(Shuffle, std::move(FinalIndices)));
2045 // If we had an odd number of defined values, then append the last
2046 // element to the array of new vectors.
2047 if ((IntermedVals.size() & 1) != 0)
2048 NewIntermedVals.push_back(IntermedVals.back());
2050 IntermedVals.swap(NewIntermedVals);
2053 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
2054 "Invalid number of intermediate vectors");
2055 SDValue Vec1 = IntermedVals[0].first;
2057 if (IntermedVals.size() > 1)
2058 Vec2 = IntermedVals[1].first;
2060 Vec2 = DAG.getUNDEF(VT);
2062 SmallVector<int, 16> ShuffleVec(NumElems, -1);
2063 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
2064 ShuffleVec[IntermedVals[0].second[i]] = i;
2065 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
2066 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
2069 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2070 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
2077 /// Expand a BUILD_VECTOR node on targets that don't
2078 /// support the operation, but do support the resultant vector type.
2079 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
2080 unsigned NumElems = Node->getNumOperands();
2081 SDValue Value1, Value2;
2083 EVT VT = Node->getValueType(0);
2084 EVT OpVT = Node->getOperand(0).getValueType();
2085 EVT EltVT = VT.getVectorElementType();
2087 // If the only non-undef value is the low element, turn this into a
2088 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
2089 bool isOnlyLowElement = true;
2090 bool MoreThanTwoValues = false;
2091 bool isConstant = true;
2092 for (unsigned i = 0; i < NumElems; ++i) {
2093 SDValue V = Node->getOperand(i);
2094 if (V.getOpcode() == ISD::UNDEF)
2097 isOnlyLowElement = false;
2098 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
2101 if (!Value1.getNode()) {
2103 } else if (!Value2.getNode()) {
2106 } else if (V != Value1 && V != Value2) {
2107 MoreThanTwoValues = true;
2111 if (!Value1.getNode())
2112 return DAG.getUNDEF(VT);
2114 if (isOnlyLowElement)
2115 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
2117 // If all elements are constants, create a load from the constant pool.
2119 SmallVector<Constant*, 16> CV;
2120 for (unsigned i = 0, e = NumElems; i != e; ++i) {
2121 if (ConstantFPSDNode *V =
2122 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
2123 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
2124 } else if (ConstantSDNode *V =
2125 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
2127 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
2129 // If OpVT and EltVT don't match, EltVT is not legal and the
2130 // element values have been promoted/truncated earlier. Undo this;
2131 // we don't want a v16i8 to become a v16i32 for example.
2132 const ConstantInt *CI = V->getConstantIntValue();
2133 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
2134 CI->getZExtValue()));
2137 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
2138 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
2139 CV.push_back(UndefValue::get(OpNTy));
2142 Constant *CP = ConstantVector::get(CV);
2144 DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
2145 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2147 VT, dl, DAG.getEntryNode(), CPIdx,
2148 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2149 false, false, Alignment);
2152 SmallSet<SDValue, 16> DefinedValues;
2153 for (unsigned i = 0; i < NumElems; ++i) {
2154 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2156 DefinedValues.insert(Node->getOperand(i));
2159 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
2160 if (!MoreThanTwoValues) {
2161 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2162 for (unsigned i = 0; i < NumElems; ++i) {
2163 SDValue V = Node->getOperand(i);
2164 if (V.getOpcode() == ISD::UNDEF)
2166 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2168 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2169 // Get the splatted value into the low element of a vector register.
2170 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2172 if (Value2.getNode())
2173 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2175 Vec2 = DAG.getUNDEF(VT);
2177 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2178 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2182 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2187 // Otherwise, we can't handle this case efficiently.
2188 return ExpandVectorBuildThroughStack(Node);
2191 // Expand a node into a call to a libcall. If the result value
2192 // does not fit into a register, return the lo part and set the hi part to the
2193 // by-reg argument. If it does fit into a single register, return the result
2194 // and leave the Hi part unset.
2195 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2197 TargetLowering::ArgListTy Args;
2198 TargetLowering::ArgListEntry Entry;
2199 for (const SDValue &Op : Node->op_values()) {
2200 EVT ArgVT = Op.getValueType();
2201 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2204 Entry.isSExt = isSigned;
2205 Entry.isZExt = !isSigned;
2206 Args.push_back(Entry);
2208 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2209 TLI.getPointerTy(DAG.getDataLayout()));
2211 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2213 // By default, the input chain to this libcall is the entry node of the
2214 // function. If the libcall is going to be emitted as a tail call then
2215 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2216 // node which is being folded has a non-entry input chain.
2217 SDValue InChain = DAG.getEntryNode();
2219 // isTailCall may be true since the callee does not reference caller stack
2220 // frame. Check if it's in the right position.
2221 SDValue TCChain = InChain;
2222 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2226 TargetLowering::CallLoweringInfo CLI(DAG);
2227 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2228 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2229 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2231 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2233 if (!CallInfo.second.getNode())
2234 // It's a tailcall, return the chain (which is the DAG root).
2235 return DAG.getRoot();
2237 return CallInfo.first;
2240 /// Generate a libcall taking the given operands as arguments
2241 /// and returning a result of type RetVT.
2242 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2243 const SDValue *Ops, unsigned NumOps,
2244 bool isSigned, SDLoc dl) {
2245 TargetLowering::ArgListTy Args;
2246 Args.reserve(NumOps);
2248 TargetLowering::ArgListEntry Entry;
2249 for (unsigned i = 0; i != NumOps; ++i) {
2250 Entry.Node = Ops[i];
2251 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2252 Entry.isSExt = isSigned;
2253 Entry.isZExt = !isSigned;
2254 Args.push_back(Entry);
2256 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2257 TLI.getPointerTy(DAG.getDataLayout()));
2259 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2261 TargetLowering::CallLoweringInfo CLI(DAG);
2262 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2263 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2264 .setSExtResult(isSigned).setZExtResult(!isSigned);
2266 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2268 return CallInfo.first;
2271 // Expand a node into a call to a libcall. Similar to
2272 // ExpandLibCall except that the first operand is the in-chain.
2273 std::pair<SDValue, SDValue>
2274 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2277 SDValue InChain = Node->getOperand(0);
2279 TargetLowering::ArgListTy Args;
2280 TargetLowering::ArgListEntry Entry;
2281 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2282 EVT ArgVT = Node->getOperand(i).getValueType();
2283 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2284 Entry.Node = Node->getOperand(i);
2286 Entry.isSExt = isSigned;
2287 Entry.isZExt = !isSigned;
2288 Args.push_back(Entry);
2290 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2291 TLI.getPointerTy(DAG.getDataLayout()));
2293 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2295 TargetLowering::CallLoweringInfo CLI(DAG);
2296 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2297 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2298 .setSExtResult(isSigned).setZExtResult(!isSigned);
2300 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2305 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2306 RTLIB::Libcall Call_F32,
2307 RTLIB::Libcall Call_F64,
2308 RTLIB::Libcall Call_F80,
2309 RTLIB::Libcall Call_F128,
2310 RTLIB::Libcall Call_PPCF128) {
2312 switch (Node->getSimpleValueType(0).SimpleTy) {
2313 default: llvm_unreachable("Unexpected request for libcall!");
2314 case MVT::f32: LC = Call_F32; break;
2315 case MVT::f64: LC = Call_F64; break;
2316 case MVT::f80: LC = Call_F80; break;
2317 case MVT::f128: LC = Call_F128; break;
2318 case MVT::ppcf128: LC = Call_PPCF128; break;
2320 return ExpandLibCall(LC, Node, false);
2323 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2324 RTLIB::Libcall Call_I8,
2325 RTLIB::Libcall Call_I16,
2326 RTLIB::Libcall Call_I32,
2327 RTLIB::Libcall Call_I64,
2328 RTLIB::Libcall Call_I128) {
2330 switch (Node->getSimpleValueType(0).SimpleTy) {
2331 default: llvm_unreachable("Unexpected request for libcall!");
2332 case MVT::i8: LC = Call_I8; break;
2333 case MVT::i16: LC = Call_I16; break;
2334 case MVT::i32: LC = Call_I32; break;
2335 case MVT::i64: LC = Call_I64; break;
2336 case MVT::i128: LC = Call_I128; break;
2338 return ExpandLibCall(LC, Node, isSigned);
2341 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2343 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2344 SmallVectorImpl<SDValue> &Results) {
2345 unsigned Opcode = Node->getOpcode();
2346 bool isSigned = Opcode == ISD::SDIVREM;
2349 switch (Node->getSimpleValueType(0).SimpleTy) {
2350 default: llvm_unreachable("Unexpected request for libcall!");
2351 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2352 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2353 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2354 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2355 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2358 // The input chain to this libcall is the entry node of the function.
2359 // Legalizing the call will automatically add the previous call to the
2361 SDValue InChain = DAG.getEntryNode();
2363 EVT RetVT = Node->getValueType(0);
2364 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2366 TargetLowering::ArgListTy Args;
2367 TargetLowering::ArgListEntry Entry;
2368 for (const SDValue &Op : Node->op_values()) {
2369 EVT ArgVT = Op.getValueType();
2370 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2373 Entry.isSExt = isSigned;
2374 Entry.isZExt = !isSigned;
2375 Args.push_back(Entry);
2378 // Also pass the return address of the remainder.
2379 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2381 Entry.Ty = RetTy->getPointerTo();
2382 Entry.isSExt = isSigned;
2383 Entry.isZExt = !isSigned;
2384 Args.push_back(Entry);
2386 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2387 TLI.getPointerTy(DAG.getDataLayout()));
2390 TargetLowering::CallLoweringInfo CLI(DAG);
2391 CLI.setDebugLoc(dl).setChain(InChain)
2392 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2393 .setSExtResult(isSigned).setZExtResult(!isSigned);
2395 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2397 // Remainder is loaded back from the stack frame.
2398 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2399 MachinePointerInfo(), false, false, false, 0);
2400 Results.push_back(CallInfo.first);
2401 Results.push_back(Rem);
2404 /// Return true if sincos libcall is available.
2405 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2407 switch (Node->getSimpleValueType(0).SimpleTy) {
2408 default: llvm_unreachable("Unexpected request for libcall!");
2409 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2410 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2411 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2412 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2413 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2415 return TLI.getLibcallName(LC) != nullptr;
2418 /// Return true if sincos libcall is available and can be used to combine sin
2420 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2421 const TargetMachine &TM) {
2422 if (!isSinCosLibcallAvailable(Node, TLI))
2424 // GNU sin/cos functions set errno while sincos does not. Therefore
2425 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2426 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2427 if (isGNU && !TM.Options.UnsafeFPMath)
2432 /// Only issue sincos libcall if both sin and cos are needed.
2433 static bool useSinCos(SDNode *Node) {
2434 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2435 ? ISD::FCOS : ISD::FSIN;
2437 SDValue Op0 = Node->getOperand(0);
2438 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2439 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2443 // The other user might have been turned into sincos already.
2444 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2450 /// Issue libcalls to sincos to compute sin / cos pairs.
2452 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2453 SmallVectorImpl<SDValue> &Results) {
2455 switch (Node->getSimpleValueType(0).SimpleTy) {
2456 default: llvm_unreachable("Unexpected request for libcall!");
2457 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2458 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2459 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2460 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2461 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2464 // The input chain to this libcall is the entry node of the function.
2465 // Legalizing the call will automatically add the previous call to the
2467 SDValue InChain = DAG.getEntryNode();
2469 EVT RetVT = Node->getValueType(0);
2470 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2472 TargetLowering::ArgListTy Args;
2473 TargetLowering::ArgListEntry Entry;
2475 // Pass the argument.
2476 Entry.Node = Node->getOperand(0);
2478 Entry.isSExt = false;
2479 Entry.isZExt = false;
2480 Args.push_back(Entry);
2482 // Pass the return address of sin.
2483 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2484 Entry.Node = SinPtr;
2485 Entry.Ty = RetTy->getPointerTo();
2486 Entry.isSExt = false;
2487 Entry.isZExt = false;
2488 Args.push_back(Entry);
2490 // Also pass the return address of the cos.
2491 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2492 Entry.Node = CosPtr;
2493 Entry.Ty = RetTy->getPointerTo();
2494 Entry.isSExt = false;
2495 Entry.isZExt = false;
2496 Args.push_back(Entry);
2498 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2499 TLI.getPointerTy(DAG.getDataLayout()));
2502 TargetLowering::CallLoweringInfo CLI(DAG);
2503 CLI.setDebugLoc(dl).setChain(InChain)
2504 .setCallee(TLI.getLibcallCallingConv(LC),
2505 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2507 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2509 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2510 MachinePointerInfo(), false, false, false, 0));
2511 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2512 MachinePointerInfo(), false, false, false, 0));
2515 /// This function is responsible for legalizing a
2516 /// INT_TO_FP operation of the specified operand when the target requests that
2517 /// we expand it. At this point, we know that the result and operand types are
2518 /// legal for the target.
2519 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2523 // TODO: Should any fast-math-flags be set for the created nodes?
2525 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2526 // simple 32-bit [signed|unsigned] integer to float/double expansion
2528 // Get the stack frame index of a 8 byte buffer.
2529 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2531 // word offset constant for Hi/Lo address computation
2532 SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2533 StackSlot.getValueType());
2534 // set up Hi and Lo (into buffer) address based on endian
2535 SDValue Hi = StackSlot;
2536 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2537 StackSlot, WordOff);
2538 if (DAG.getDataLayout().isLittleEndian())
2541 // if signed map to unsigned space
2544 // constant used to invert sign bit (signed to unsigned mapping)
2545 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2546 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2550 // store the lo of the constructed double - based on integer input
2551 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2552 Op0Mapped, Lo, MachinePointerInfo(),
2554 // initial hi portion of constructed double
2555 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2556 // store the hi of the constructed double - biased exponent
2557 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2558 MachinePointerInfo(),
2560 // load the constructed double
2561 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2562 MachinePointerInfo(), false, false, false, 0);
2563 // FP constant to bias correct the final result
2564 SDValue Bias = DAG.getConstantFP(isSigned ?
2565 BitsToDouble(0x4330000080000000ULL) :
2566 BitsToDouble(0x4330000000000000ULL),
2568 // subtract the bias
2569 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2572 // handle final rounding
2573 if (DestVT == MVT::f64) {
2576 } else if (DestVT.bitsLT(MVT::f64)) {
2577 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2578 DAG.getIntPtrConstant(0, dl));
2579 } else if (DestVT.bitsGT(MVT::f64)) {
2580 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2584 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2585 // Code below here assumes !isSigned without checking again.
2587 // Implementation of unsigned i64 to f64 following the algorithm in
2588 // __floatundidf in compiler_rt. This implementation has the advantage
2589 // of performing rounding correctly, both in the default rounding mode
2590 // and in all alternate rounding modes.
2591 // TODO: Generalize this for use with other types.
2592 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2594 DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2595 SDValue TwoP84PlusTwoP52 =
2596 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2599 DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2601 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2602 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2603 DAG.getConstant(32, dl, MVT::i64));
2604 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2605 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2606 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2607 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2608 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2610 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2613 // Implementation of unsigned i64 to f32.
2614 // TODO: Generalize this for use with other types.
2615 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2616 // For unsigned conversions, convert them to signed conversions using the
2617 // algorithm from the x86_64 __floatundidf in compiler_rt.
2619 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2621 SDValue ShiftConst = DAG.getConstant(
2622 1, dl, TLI.getShiftAmountTy(Op0.getValueType(), DAG.getDataLayout()));
2623 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2624 SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2625 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2626 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2628 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2629 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2631 // TODO: This really should be implemented using a branch rather than a
2632 // select. We happen to get lucky and machinesink does the right
2633 // thing most of the time. This would be a good candidate for a
2634 //pseudo-op, or, even better, for whole-function isel.
2635 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2636 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2637 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2640 // Otherwise, implement the fully general conversion.
2642 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2643 DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2644 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2645 DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2646 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2647 DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2648 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2649 DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2651 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2652 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2653 DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2656 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2657 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType(), DAG.getDataLayout());
2659 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2660 DAG.getConstant(32, dl, SHVT));
2661 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2662 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2664 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2666 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2667 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2668 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2669 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2670 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2671 DAG.getIntPtrConstant(0, dl));
2674 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2676 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2678 DAG.getConstant(0, dl, Op0.getValueType()),
2680 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2681 Four = DAG.getIntPtrConstant(4, dl);
2682 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2683 SignSet, Four, Zero);
2685 // If the sign bit of the integer is set, the large number will be treated
2686 // as a negative number. To counteract this, the dynamic code adds an
2687 // offset depending on the data type.
2689 switch (Op0.getSimpleValueType().SimpleTy) {
2690 default: llvm_unreachable("Unsupported integer type!");
2691 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2692 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2693 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2694 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2696 if (DAG.getDataLayout().isLittleEndian())
2698 Constant *FudgeFactor = ConstantInt::get(
2699 Type::getInt64Ty(*DAG.getContext()), FF);
2702 DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2703 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2704 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2705 Alignment = std::min(Alignment, 4u);
2707 if (DestVT == MVT::f32)
2708 FudgeInReg = DAG.getLoad(
2709 MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2710 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2711 false, false, Alignment);
2713 SDValue Load = DAG.getExtLoad(
2714 ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2715 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2716 false, false, false, Alignment);
2717 HandleSDNode Handle(Load);
2718 LegalizeOp(Load.getNode());
2719 FudgeInReg = Handle.getValue();
2722 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2725 /// This function is responsible for legalizing a
2726 /// *INT_TO_FP operation of the specified operand when the target requests that
2727 /// we promote it. At this point, we know that the result and operand types are
2728 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2729 /// operation that takes a larger input.
2730 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2734 // First step, figure out the appropriate *INT_TO_FP operation to use.
2735 EVT NewInTy = LegalOp.getValueType();
2737 unsigned OpToUse = 0;
2739 // Scan for the appropriate larger type to use.
2741 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2742 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2744 // If the target supports SINT_TO_FP of this type, use it.
2745 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2746 OpToUse = ISD::SINT_TO_FP;
2749 if (isSigned) continue;
2751 // If the target supports UINT_TO_FP of this type, use it.
2752 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2753 OpToUse = ISD::UINT_TO_FP;
2757 // Otherwise, try a larger type.
2760 // Okay, we found the operation and type to use. Zero extend our input to the
2761 // desired type then run the operation on it.
2762 return DAG.getNode(OpToUse, dl, DestVT,
2763 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2764 dl, NewInTy, LegalOp));
2767 /// This function is responsible for legalizing a
2768 /// FP_TO_*INT operation of the specified operand when the target requests that
2769 /// we promote it. At this point, we know that the result and operand types are
2770 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2771 /// operation that returns a larger result.
2772 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2776 // First step, figure out the appropriate FP_TO*INT operation to use.
2777 EVT NewOutTy = DestVT;
2779 unsigned OpToUse = 0;
2781 // Scan for the appropriate larger type to use.
2783 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2784 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2786 // A larger signed type can hold all unsigned values of the requested type,
2787 // so using FP_TO_SINT is valid
2788 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2789 OpToUse = ISD::FP_TO_SINT;
2793 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2794 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2795 OpToUse = ISD::FP_TO_UINT;
2799 // Otherwise, try a larger type.
2803 // Okay, we found the operation and type to use.
2804 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2806 // Truncate the result of the extended FP_TO_*INT operation to the desired
2808 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2811 /// Open code the operations for BITREVERSE.
2812 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, SDLoc dl) {
2813 EVT VT = Op.getValueType();
2814 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2815 unsigned Sz = VT.getScalarSizeInBits();
2818 Tmp = DAG.getConstant(0, dl, VT);
2819 for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2822 DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2825 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2828 Shift = Shift.shl(J);
2829 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2830 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2836 /// Open code the operations for BSWAP of the specified operation.
2837 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2838 EVT VT = Op.getValueType();
2839 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2840 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2841 switch (VT.getSimpleVT().SimpleTy) {
2842 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2844 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2845 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2846 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2848 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2849 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2850 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2851 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2852 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2853 DAG.getConstant(0xFF0000, dl, VT));
2854 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2855 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2856 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2857 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2859 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2860 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2861 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2862 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2863 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2864 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2865 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2866 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2867 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2868 DAG.getConstant(255ULL<<48, dl, VT));
2869 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2870 DAG.getConstant(255ULL<<40, dl, VT));
2871 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2872 DAG.getConstant(255ULL<<32, dl, VT));
2873 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2874 DAG.getConstant(255ULL<<24, dl, VT));
2875 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2876 DAG.getConstant(255ULL<<16, dl, VT));
2877 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2878 DAG.getConstant(255ULL<<8 , dl, VT));
2879 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2880 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2881 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2882 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2883 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2884 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2885 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2889 /// Expand the specified bitcount instruction into operations.
2890 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2893 default: llvm_unreachable("Cannot expand this yet!");
2895 EVT VT = Op.getValueType();
2896 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2897 unsigned Len = VT.getSizeInBits();
2899 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2900 "CTPOP not implemented for this type.");
2902 // This is the "best" algorithm from
2903 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2905 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2907 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2909 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2911 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2914 // v = v - ((v >> 1) & 0x55555555...)
2915 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2916 DAG.getNode(ISD::AND, dl, VT,
2917 DAG.getNode(ISD::SRL, dl, VT, Op,
2918 DAG.getConstant(1, dl, ShVT)),
2920 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2921 Op = DAG.getNode(ISD::ADD, dl, VT,
2922 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2923 DAG.getNode(ISD::AND, dl, VT,
2924 DAG.getNode(ISD::SRL, dl, VT, Op,
2925 DAG.getConstant(2, dl, ShVT)),
2927 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2928 Op = DAG.getNode(ISD::AND, dl, VT,
2929 DAG.getNode(ISD::ADD, dl, VT, Op,
2930 DAG.getNode(ISD::SRL, dl, VT, Op,
2931 DAG.getConstant(4, dl, ShVT))),
2933 // v = (v * 0x01010101...) >> (Len - 8)
2934 Op = DAG.getNode(ISD::SRL, dl, VT,
2935 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2936 DAG.getConstant(Len - 8, dl, ShVT));
2940 case ISD::CTLZ_ZERO_UNDEF:
2941 // This trivially expands to CTLZ.
2942 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2944 EVT VT = Op.getValueType();
2945 unsigned len = VT.getSizeInBits();
2947 if (TLI.isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) {
2948 EVT SetCCVT = getSetCCResultType(VT);
2949 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
2950 SDValue Zero = DAG.getConstant(0, dl, VT);
2951 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
2952 return DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
2953 DAG.getConstant(len, dl, VT), CTLZ);
2956 // for now, we do this:
2957 // x = x | (x >> 1);
2958 // x = x | (x >> 2);
2960 // x = x | (x >>16);
2961 // x = x | (x >>32); // for 64-bit input
2962 // return popcount(~x);
2964 // Ref: "Hacker's Delight" by Henry Warren
2965 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2966 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2967 SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2968 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2969 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2971 Op = DAG.getNOT(dl, Op, VT);
2972 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2974 case ISD::CTTZ_ZERO_UNDEF:
2975 // This trivially expands to CTTZ.
2976 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2978 // for now, we use: { return popcount(~x & (x - 1)); }
2979 // unless the target has ctlz but not ctpop, in which case we use:
2980 // { return 32 - nlz(~x & (x-1)); }
2981 // Ref: "Hacker's Delight" by Henry Warren
2982 EVT VT = Op.getValueType();
2983 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2984 DAG.getNOT(dl, Op, VT),
2985 DAG.getNode(ISD::SUB, dl, VT, Op,
2986 DAG.getConstant(1, dl, VT)));
2987 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2988 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2989 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2990 return DAG.getNode(ISD::SUB, dl, VT,
2991 DAG.getConstant(VT.getSizeInBits(), dl, VT),
2992 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2993 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2998 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2999 SmallVector<SDValue, 8> Results;
3001 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3003 switch (Node->getOpcode()) {
3006 case ISD::CTLZ_ZERO_UNDEF:
3008 case ISD::CTTZ_ZERO_UNDEF:
3009 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
3010 Results.push_back(Tmp1);
3012 case ISD::BITREVERSE:
3013 Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
3016 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
3018 case ISD::FRAMEADDR:
3019 case ISD::RETURNADDR:
3020 case ISD::FRAME_TO_ARGS_OFFSET:
3021 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3023 case ISD::FLT_ROUNDS_:
3024 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
3026 case ISD::EH_RETURN:
3030 case ISD::EH_SJLJ_LONGJMP:
3031 // If the target didn't expand these, there's nothing to do, so just
3032 // preserve the chain and be done.
3033 Results.push_back(Node->getOperand(0));
3035 case ISD::READCYCLECOUNTER:
3036 // If the target didn't expand this, just return 'zero' and preserve the
3038 Results.append(Node->getNumValues() - 1,
3039 DAG.getConstant(0, dl, Node->getValueType(0)));
3040 Results.push_back(Node->getOperand(0));
3042 case ISD::EH_SJLJ_SETJMP:
3043 // If the target didn't expand this, just return 'zero' and preserve the
3045 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
3046 Results.push_back(Node->getOperand(0));
3048 case ISD::ATOMIC_LOAD: {
3049 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3050 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
3051 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3052 SDValue Swap = DAG.getAtomicCmpSwap(
3053 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3054 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
3055 cast<AtomicSDNode>(Node)->getMemOperand(),
3056 cast<AtomicSDNode>(Node)->getOrdering(),
3057 cast<AtomicSDNode>(Node)->getOrdering(),
3058 cast<AtomicSDNode>(Node)->getSynchScope());
3059 Results.push_back(Swap.getValue(0));
3060 Results.push_back(Swap.getValue(1));
3063 case ISD::ATOMIC_STORE: {
3064 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3065 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3066 cast<AtomicSDNode>(Node)->getMemoryVT(),
3067 Node->getOperand(0),
3068 Node->getOperand(1), Node->getOperand(2),
3069 cast<AtomicSDNode>(Node)->getMemOperand(),
3070 cast<AtomicSDNode>(Node)->getOrdering(),
3071 cast<AtomicSDNode>(Node)->getSynchScope());
3072 Results.push_back(Swap.getValue(1));
3075 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3076 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
3077 // splits out the success value as a comparison. Expanding the resulting
3078 // ATOMIC_CMP_SWAP will produce a libcall.
3079 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3080 SDValue Res = DAG.getAtomicCmpSwap(
3081 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3082 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
3083 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
3084 cast<AtomicSDNode>(Node)->getSuccessOrdering(),
3085 cast<AtomicSDNode>(Node)->getFailureOrdering(),
3086 cast<AtomicSDNode>(Node)->getSynchScope());
3088 SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
3089 Res, Node->getOperand(2), ISD::SETEQ);
3091 Results.push_back(Res.getValue(0));
3092 Results.push_back(Success);
3093 Results.push_back(Res.getValue(1));
3096 case ISD::DYNAMIC_STACKALLOC:
3097 ExpandDYNAMIC_STACKALLOC(Node, Results);
3099 case ISD::MERGE_VALUES:
3100 for (unsigned i = 0; i < Node->getNumValues(); i++)
3101 Results.push_back(Node->getOperand(i));
3104 EVT VT = Node->getValueType(0);
3106 Results.push_back(DAG.getConstant(0, dl, VT));
3108 assert(VT.isFloatingPoint() && "Unknown value type!");
3109 Results.push_back(DAG.getConstantFP(0, dl, VT));
3115 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3116 Node->getValueType(0), dl);
3117 Results.push_back(Tmp1);
3119 case ISD::FP_EXTEND:
3120 Tmp1 = EmitStackConvert(Node->getOperand(0),
3121 Node->getOperand(0).getValueType(),
3122 Node->getValueType(0), dl);
3123 Results.push_back(Tmp1);
3125 case ISD::SIGN_EXTEND_INREG: {
3126 // NOTE: we could fall back on load/store here too for targets without
3127 // SAR. However, it is doubtful that any exist.
3128 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3129 EVT VT = Node->getValueType(0);
3130 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3133 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3134 ExtraVT.getScalarType().getSizeInBits();
3135 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
3136 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3137 Node->getOperand(0), ShiftCst);
3138 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3139 Results.push_back(Tmp1);
3142 case ISD::FP_ROUND_INREG: {
3143 // The only way we can lower this is to turn it into a TRUNCSTORE,
3144 // EXTLOAD pair, targeting a temporary location (a stack slot).
3146 // NOTE: there is a choice here between constantly creating new stack
3147 // slots and always reusing the same one. We currently always create
3148 // new ones, as reuse may inhibit scheduling.
3149 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3150 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3151 Node->getValueType(0), dl);
3152 Results.push_back(Tmp1);
3155 case ISD::SINT_TO_FP:
3156 case ISD::UINT_TO_FP:
3157 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3158 Node->getOperand(0), Node->getValueType(0), dl);
3159 Results.push_back(Tmp1);
3161 case ISD::FP_TO_SINT:
3162 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3163 Results.push_back(Tmp1);
3165 case ISD::FP_TO_UINT: {
3166 SDValue True, False;
3167 EVT VT = Node->getOperand(0).getValueType();
3168 EVT NVT = Node->getValueType(0);
3169 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3170 APInt::getNullValue(VT.getSizeInBits()));
3171 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3172 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3173 Tmp1 = DAG.getConstantFP(apf, dl, VT);
3174 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3175 Node->getOperand(0),
3177 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3178 // TODO: Should any fast-math-flags be set for the FSUB?
3179 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3180 DAG.getNode(ISD::FSUB, dl, VT,
3181 Node->getOperand(0), Tmp1));
3182 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3183 DAG.getConstant(x, dl, NVT));
3184 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3185 Results.push_back(Tmp1);
3189 Results.push_back(DAG.expandVAArg(Node));
3190 Results.push_back(Results[0].getValue(1));
3193 Results.push_back(DAG.expandVACopy(Node));
3195 case ISD::EXTRACT_VECTOR_ELT:
3196 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3197 // This must be an access of the only element. Return it.
3198 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3199 Node->getOperand(0));
3201 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3202 Results.push_back(Tmp1);
3204 case ISD::EXTRACT_SUBVECTOR:
3205 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3207 case ISD::INSERT_SUBVECTOR:
3208 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3210 case ISD::CONCAT_VECTORS: {
3211 Results.push_back(ExpandVectorBuildThroughStack(Node));
3214 case ISD::SCALAR_TO_VECTOR:
3215 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3217 case ISD::INSERT_VECTOR_ELT:
3218 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3219 Node->getOperand(1),
3220 Node->getOperand(2), dl));
3222 case ISD::VECTOR_SHUFFLE: {
3223 SmallVector<int, 32> NewMask;
3224 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3226 EVT VT = Node->getValueType(0);
3227 EVT EltVT = VT.getVectorElementType();
3228 SDValue Op0 = Node->getOperand(0);
3229 SDValue Op1 = Node->getOperand(1);
3230 if (!TLI.isTypeLegal(EltVT)) {
3232 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3234 // BUILD_VECTOR operands are allowed to be wider than the element type.
3235 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3237 if (NewEltVT.bitsLT(EltVT)) {
3239 // Convert shuffle node.
3240 // If original node was v4i64 and the new EltVT is i32,
3241 // cast operands to v8i32 and re-build the mask.
3243 // Calculate new VT, the size of the new VT should be equal to original.
3245 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3246 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3247 assert(NewVT.bitsEq(VT));
3249 // cast operands to new VT
3250 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3251 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3253 // Convert the shuffle mask
3254 unsigned int factor =
3255 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3257 // EltVT gets smaller
3260 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3262 for (unsigned fi = 0; fi < factor; ++fi)
3263 NewMask.push_back(Mask[i]);
3266 for (unsigned fi = 0; fi < factor; ++fi)
3267 NewMask.push_back(Mask[i]*factor+fi);
3275 unsigned NumElems = VT.getVectorNumElements();
3276 SmallVector<SDValue, 16> Ops;
3277 for (unsigned i = 0; i != NumElems; ++i) {
3279 Ops.push_back(DAG.getUNDEF(EltVT));
3282 unsigned Idx = Mask[i];
3284 Ops.push_back(DAG.getNode(
3285 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3286 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3288 Ops.push_back(DAG.getNode(
3289 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3290 DAG.getConstant(Idx - NumElems, dl,
3291 TLI.getVectorIdxTy(DAG.getDataLayout()))));
3294 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3295 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3296 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3297 Results.push_back(Tmp1);
3300 case ISD::EXTRACT_ELEMENT: {
3301 EVT OpTy = Node->getOperand(0).getValueType();
3302 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3304 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3305 DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3306 TLI.getShiftAmountTy(
3307 Node->getOperand(0).getValueType(),
3308 DAG.getDataLayout())));
3309 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3312 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3313 Node->getOperand(0));
3315 Results.push_back(Tmp1);
3318 case ISD::STACKSAVE:
3319 // Expand to CopyFromReg if the target set
3320 // StackPointerRegisterToSaveRestore.
3321 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3322 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3323 Node->getValueType(0)));
3324 Results.push_back(Results[0].getValue(1));
3326 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3327 Results.push_back(Node->getOperand(0));
3330 case ISD::STACKRESTORE:
3331 // Expand to CopyToReg if the target set
3332 // StackPointerRegisterToSaveRestore.
3333 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3334 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3335 Node->getOperand(1)));
3337 Results.push_back(Node->getOperand(0));
3340 case ISD::GET_DYNAMIC_AREA_OFFSET:
3341 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3342 Results.push_back(Results[0].getValue(0));
3344 case ISD::FCOPYSIGN:
3345 Results.push_back(ExpandFCOPYSIGN(Node));
3348 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3349 Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3350 // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3351 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3352 Node->getOperand(0));
3353 Results.push_back(Tmp1);
3356 Results.push_back(ExpandFABS(Node));
3362 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3364 switch (Node->getOpcode()) {
3365 default: llvm_unreachable("How did we get here?");
3366 case ISD::SMAX: Pred = ISD::SETGT; break;
3367 case ISD::SMIN: Pred = ISD::SETLT; break;
3368 case ISD::UMAX: Pred = ISD::SETUGT; break;
3369 case ISD::UMIN: Pred = ISD::SETULT; break;
3371 Tmp1 = Node->getOperand(0);
3372 Tmp2 = Node->getOperand(1);
3373 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3374 Results.push_back(Tmp1);
3380 EVT VT = Node->getValueType(0);
3381 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3382 // fcos which share the same operand and both are used.
3383 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3384 canCombineSinCosLibcall(Node, TLI, TM))
3385 && useSinCos(Node)) {
3386 SDVTList VTs = DAG.getVTList(VT, VT);
3387 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3388 if (Node->getOpcode() == ISD::FCOS)
3389 Tmp1 = Tmp1.getValue(1);
3390 Results.push_back(Tmp1);
3395 llvm_unreachable("Illegal fmad should never be formed");
3397 case ISD::FP16_TO_FP:
3398 if (Node->getValueType(0) != MVT::f32) {
3399 // We can extend to types bigger than f32 in two steps without changing
3400 // the result. Since "f16 -> f32" is much more commonly available, give
3401 // CodeGen the option of emitting that before resorting to a libcall.
3403 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3405 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3408 case ISD::FP_TO_FP16:
3409 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3410 SDValue Op = Node->getOperand(0);
3411 MVT SVT = Op.getSimpleValueType();
3412 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3413 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3414 // Under fastmath, we can expand this node into a fround followed by
3415 // a float-half conversion.
3416 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3417 DAG.getIntPtrConstant(0, dl));
3419 DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3423 case ISD::ConstantFP: {
3424 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3425 // Check to see if this FP immediate is already legal.
3426 // If this is a legal constant, turn it into a TargetConstantFP node.
3427 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3428 Results.push_back(ExpandConstantFP(CFP, true));
3431 case ISD::Constant: {
3432 ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3433 Results.push_back(ExpandConstant(CP));
3437 EVT VT = Node->getValueType(0);
3438 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3439 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3440 const SDNodeFlags *Flags = &cast<BinaryWithFlagsSDNode>(Node)->Flags;
3441 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3442 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3443 Results.push_back(Tmp1);
3448 EVT VT = Node->getValueType(0);
3449 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3450 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3451 "Don't know how to expand this subtraction!");
3452 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3453 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3455 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3456 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3461 EVT VT = Node->getValueType(0);
3462 bool isSigned = Node->getOpcode() == ISD::SREM;
3463 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3464 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3465 Tmp2 = Node->getOperand(0);
3466 Tmp3 = Node->getOperand(1);
3467 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3468 SDVTList VTs = DAG.getVTList(VT, VT);
3469 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3470 Results.push_back(Tmp1);
3471 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3473 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3474 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3475 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3476 Results.push_back(Tmp1);
3482 bool isSigned = Node->getOpcode() == ISD::SDIV;
3483 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3484 EVT VT = Node->getValueType(0);
3485 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3486 SDVTList VTs = DAG.getVTList(VT, VT);
3487 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3488 Node->getOperand(1));
3489 Results.push_back(Tmp1);
3495 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3497 EVT VT = Node->getValueType(0);
3498 SDVTList VTs = DAG.getVTList(VT, VT);
3499 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3500 "If this wasn't legal, it shouldn't have been created!");
3501 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3502 Node->getOperand(1));
3503 Results.push_back(Tmp1.getValue(1));
3507 EVT VT = Node->getValueType(0);
3508 SDVTList VTs = DAG.getVTList(VT, VT);
3509 // See if multiply or divide can be lowered using two-result operations.
3510 // We just need the low half of the multiply; try both the signed
3511 // and unsigned forms. If the target supports both SMUL_LOHI and
3512 // UMUL_LOHI, form a preference by checking which forms of plain
3513 // MULH it supports.
3514 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3515 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3516 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3517 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3518 unsigned OpToUse = 0;
3519 if (HasSMUL_LOHI && !HasMULHS) {
3520 OpToUse = ISD::SMUL_LOHI;
3521 } else if (HasUMUL_LOHI && !HasMULHU) {
3522 OpToUse = ISD::UMUL_LOHI;
3523 } else if (HasSMUL_LOHI) {
3524 OpToUse = ISD::SMUL_LOHI;
3525 } else if (HasUMUL_LOHI) {
3526 OpToUse = ISD::UMUL_LOHI;
3529 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3530 Node->getOperand(1)));
3535 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3536 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3537 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3538 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3539 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3540 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3541 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3542 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3544 DAG.getConstant(HalfType.getSizeInBits(), dl,
3545 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3546 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3547 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3553 SDValue LHS = Node->getOperand(0);
3554 SDValue RHS = Node->getOperand(1);
3555 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3556 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3558 Results.push_back(Sum);
3559 EVT ResultType = Node->getValueType(1);
3560 EVT OType = getSetCCResultType(Node->getValueType(0));
3562 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3564 // LHSSign -> LHS >= 0
3565 // RHSSign -> RHS >= 0
3566 // SumSign -> Sum >= 0
3569 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3571 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3573 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3574 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3575 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3576 Node->getOpcode() == ISD::SADDO ?
3577 ISD::SETEQ : ISD::SETNE);
3579 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3580 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3582 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3583 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3588 SDValue LHS = Node->getOperand(0);
3589 SDValue RHS = Node->getOperand(1);
3590 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3591 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3593 Results.push_back(Sum);
3595 EVT ResultType = Node->getValueType(1);
3596 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3598 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3599 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3601 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3606 EVT VT = Node->getValueType(0);
3607 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3608 SDValue LHS = Node->getOperand(0);
3609 SDValue RHS = Node->getOperand(1);
3612 static const unsigned Ops[2][3] =
3613 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3614 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3615 bool isSigned = Node->getOpcode() == ISD::SMULO;
3616 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3617 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3618 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3619 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3620 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3622 TopHalf = BottomHalf.getValue(1);
3623 } else if (TLI.isTypeLegal(WideVT)) {
3624 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3625 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3626 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3627 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3628 DAG.getIntPtrConstant(0, dl));
3629 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3630 DAG.getIntPtrConstant(1, dl));
3632 // We can fall back to a libcall with an illegal type for the MUL if we
3633 // have a libcall big enough.
3634 // Also, we can fall back to a division in some cases, but that's a big
3635 // performance hit in the general case.
3636 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3637 if (WideVT == MVT::i16)
3638 LC = RTLIB::MUL_I16;
3639 else if (WideVT == MVT::i32)
3640 LC = RTLIB::MUL_I32;
3641 else if (WideVT == MVT::i64)
3642 LC = RTLIB::MUL_I64;
3643 else if (WideVT == MVT::i128)
3644 LC = RTLIB::MUL_I128;
3645 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3647 // The high part is obtained by SRA'ing all but one of the bits of low
3649 unsigned LoSize = VT.getSizeInBits();
3651 DAG.getNode(ISD::SRA, dl, VT, RHS,
3652 DAG.getConstant(LoSize - 1, dl,
3653 TLI.getPointerTy(DAG.getDataLayout())));
3655 DAG.getNode(ISD::SRA, dl, VT, LHS,
3656 DAG.getConstant(LoSize - 1, dl,
3657 TLI.getPointerTy(DAG.getDataLayout())));
3659 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3660 // pre-lowered to the correct types. This all depends upon WideVT not
3661 // being a legal type for the architecture and thus has to be split to
3663 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3664 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3665 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3666 DAG.getIntPtrConstant(0, dl));
3667 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3668 DAG.getIntPtrConstant(1, dl));
3669 // Ret is a node with an illegal type. Because such things are not
3670 // generally permitted during this phase of legalization, make sure the
3671 // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3673 assert(Ret->use_empty() &&
3674 "Unexpected uses of illegally type from expanded lib call.");
3678 Tmp1 = DAG.getConstant(
3679 VT.getSizeInBits() - 1, dl,
3680 TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
3681 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3682 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3685 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3686 DAG.getConstant(0, dl, VT), ISD::SETNE);
3688 Results.push_back(BottomHalf);
3689 Results.push_back(TopHalf);
3692 case ISD::BUILD_PAIR: {
3693 EVT PairTy = Node->getValueType(0);
3694 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3695 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3697 ISD::SHL, dl, PairTy, Tmp2,
3698 DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3699 TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3700 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3704 Tmp1 = Node->getOperand(0);
3705 Tmp2 = Node->getOperand(1);
3706 Tmp3 = Node->getOperand(2);
3707 if (Tmp1.getOpcode() == ISD::SETCC) {
3708 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3710 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3712 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3713 DAG.getConstant(0, dl, Tmp1.getValueType()),
3714 Tmp2, Tmp3, ISD::SETNE);
3716 Results.push_back(Tmp1);
3719 SDValue Chain = Node->getOperand(0);
3720 SDValue Table = Node->getOperand(1);
3721 SDValue Index = Node->getOperand(2);
3723 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
3725 const DataLayout &TD = DAG.getDataLayout();
3726 unsigned EntrySize =
3727 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3729 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3730 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3731 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3734 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3735 SDValue LD = DAG.getExtLoad(
3736 ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3737 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT,
3738 false, false, false, 0);
3740 if (TM.getRelocationModel() == Reloc::PIC_) {
3741 // For PIC, the sequence is:
3742 // BRIND(load(Jumptable + index) + RelocBase)
3743 // RelocBase can be JumpTable, GOT or some sort of global base.
3744 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3745 TLI.getPICJumpTableRelocBase(Table, DAG));
3747 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3748 Results.push_back(Tmp1);
3752 // Expand brcond's setcc into its constituent parts and create a BR_CC
3754 Tmp1 = Node->getOperand(0);
3755 Tmp2 = Node->getOperand(1);
3756 if (Tmp2.getOpcode() == ISD::SETCC) {
3757 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3758 Tmp1, Tmp2.getOperand(2),
3759 Tmp2.getOperand(0), Tmp2.getOperand(1),
3760 Node->getOperand(2));
3762 // We test only the i1 bit. Skip the AND if UNDEF.
3763 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3764 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3765 DAG.getConstant(1, dl, Tmp2.getValueType()));
3766 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3767 DAG.getCondCode(ISD::SETNE), Tmp3,
3768 DAG.getConstant(0, dl, Tmp3.getValueType()),
3769 Node->getOperand(2));
3771 Results.push_back(Tmp1);
3774 Tmp1 = Node->getOperand(0);
3775 Tmp2 = Node->getOperand(1);
3776 Tmp3 = Node->getOperand(2);
3777 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3778 Tmp3, NeedInvert, dl);
3781 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3782 // condition code, create a new SETCC node.
3784 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3787 // If we expanded the SETCC by inverting the condition code, then wrap
3788 // the existing SETCC in a NOT to restore the intended condition.
3790 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3792 Results.push_back(Tmp1);
3796 // Otherwise, SETCC for the given comparison type must be completely
3797 // illegal; expand it into a SELECT_CC.
3798 EVT VT = Node->getValueType(0);
3800 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3801 case TargetLowering::ZeroOrOneBooleanContent:
3802 case TargetLowering::UndefinedBooleanContent:
3805 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3809 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3810 DAG.getConstant(TrueValue, dl, VT),
3811 DAG.getConstant(0, dl, VT),
3813 Results.push_back(Tmp1);
3816 case ISD::SELECT_CC: {
3817 Tmp1 = Node->getOperand(0); // LHS
3818 Tmp2 = Node->getOperand(1); // RHS
3819 Tmp3 = Node->getOperand(2); // True
3820 Tmp4 = Node->getOperand(3); // False
3821 EVT VT = Node->getValueType(0);
3822 SDValue CC = Node->getOperand(4);
3823 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3825 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3826 // If the condition code is legal, then we need to expand this
3827 // node using SETCC and SELECT.
3828 EVT CmpVT = Tmp1.getValueType();
3829 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3830 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3833 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3834 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3835 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3839 // SELECT_CC is legal, so the condition code must not be.
3840 bool Legalized = false;
3841 // Try to legalize by inverting the condition. This is for targets that
3842 // might support an ordered version of a condition, but not the unordered
3843 // version (or vice versa).
3844 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3845 Tmp1.getValueType().isInteger());
3846 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3847 // Use the new condition code and swap true and false
3849 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3851 // If The inverse is not legal, then try to swap the arguments using
3852 // the inverse condition code.
3853 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3854 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3855 // The swapped inverse condition is legal, so swap true and false,
3858 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3863 Legalized = LegalizeSetCCCondCode(
3864 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3867 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3869 // If we expanded the SETCC by inverting the condition code, then swap
3870 // the True/False operands to match.
3872 std::swap(Tmp3, Tmp4);
3874 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3875 // condition code, create a new SELECT_CC node.
3877 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3878 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3880 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3881 CC = DAG.getCondCode(ISD::SETNE);
3882 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3883 Tmp2, Tmp3, Tmp4, CC);
3886 Results.push_back(Tmp1);
3890 Tmp1 = Node->getOperand(0); // Chain
3891 Tmp2 = Node->getOperand(2); // LHS
3892 Tmp3 = Node->getOperand(3); // RHS
3893 Tmp4 = Node->getOperand(1); // CC
3895 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3896 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3898 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3900 // If we expanded the SETCC by inverting the condition code, then wrap
3901 // the existing SETCC in a NOT to restore the intended condition.
3903 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3905 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3907 if (Tmp4.getNode()) {
3908 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3909 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3911 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3912 Tmp4 = DAG.getCondCode(ISD::SETNE);
3913 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3914 Tmp2, Tmp3, Node->getOperand(4));
3916 Results.push_back(Tmp1);
3919 case ISD::BUILD_VECTOR:
3920 Results.push_back(ExpandBUILD_VECTOR(Node));
3925 // Scalarize vector SRA/SRL/SHL.
3926 EVT VT = Node->getValueType(0);
3927 assert(VT.isVector() && "Unable to legalize non-vector shift");
3928 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3929 unsigned NumElem = VT.getVectorNumElements();
3931 SmallVector<SDValue, 8> Scalars;
3932 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3933 SDValue Ex = DAG.getNode(
3934 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3935 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3936 SDValue Sh = DAG.getNode(
3937 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3938 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3939 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3940 VT.getScalarType(), Ex, Sh));
3943 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
3944 ReplaceNode(SDValue(Node, 0), Result);
3947 case ISD::GLOBAL_OFFSET_TABLE:
3948 case ISD::GlobalAddress:
3949 case ISD::GlobalTLSAddress:
3950 case ISD::ExternalSymbol:
3951 case ISD::ConstantPool:
3952 case ISD::JumpTable:
3953 case ISD::INTRINSIC_W_CHAIN:
3954 case ISD::INTRINSIC_WO_CHAIN:
3955 case ISD::INTRINSIC_VOID:
3956 // FIXME: Custom lowering for these operations shouldn't return null!
3960 // Replace the original node with the legalized result.
3961 if (Results.empty())
3964 ReplaceNode(Node, Results.data());
3968 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3969 SmallVector<SDValue, 8> Results;
3971 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3972 unsigned Opc = Node->getOpcode();
3974 case ISD::ATOMIC_FENCE: {
3975 // If the target didn't lower this, lower it to '__sync_synchronize()' call
3976 // FIXME: handle "fence singlethread" more efficiently.
3977 TargetLowering::ArgListTy Args;
3979 TargetLowering::CallLoweringInfo CLI(DAG);
3981 .setChain(Node->getOperand(0))
3982 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3983 DAG.getExternalSymbol("__sync_synchronize",
3984 TLI.getPointerTy(DAG.getDataLayout())),
3985 std::move(Args), 0);
3987 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3989 Results.push_back(CallResult.second);
3992 // By default, atomic intrinsics are marked Legal and lowered. Targets
3993 // which don't support them directly, however, may want libcalls, in which
3994 // case they mark them Expand, and we get here.
3995 case ISD::ATOMIC_SWAP:
3996 case ISD::ATOMIC_LOAD_ADD:
3997 case ISD::ATOMIC_LOAD_SUB:
3998 case ISD::ATOMIC_LOAD_AND:
3999 case ISD::ATOMIC_LOAD_OR:
4000 case ISD::ATOMIC_LOAD_XOR:
4001 case ISD::ATOMIC_LOAD_NAND:
4002 case ISD::ATOMIC_LOAD_MIN:
4003 case ISD::ATOMIC_LOAD_MAX:
4004 case ISD::ATOMIC_LOAD_UMIN:
4005 case ISD::ATOMIC_LOAD_UMAX:
4006 case ISD::ATOMIC_CMP_SWAP: {
4007 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
4008 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
4009 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
4011 std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
4012 Results.push_back(Tmp.first);
4013 Results.push_back(Tmp.second);
4017 // If this operation is not supported, lower it to 'abort()' call
4018 TargetLowering::ArgListTy Args;
4019 TargetLowering::CallLoweringInfo CLI(DAG);
4021 .setChain(Node->getOperand(0))
4022 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
4023 DAG.getExternalSymbol("abort",
4024 TLI.getPointerTy(DAG.getDataLayout())),
4025 std::move(Args), 0);
4026 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
4028 Results.push_back(CallResult.second);
4032 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
4033 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
4034 RTLIB::FMIN_PPCF128));
4037 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
4038 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
4039 RTLIB::FMAX_PPCF128));
4042 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
4043 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
4044 RTLIB::SQRT_PPCF128));
4047 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
4048 RTLIB::SIN_F80, RTLIB::SIN_F128,
4049 RTLIB::SIN_PPCF128));
4052 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
4053 RTLIB::COS_F80, RTLIB::COS_F128,
4054 RTLIB::COS_PPCF128));
4057 // Expand into sincos libcall.
4058 ExpandSinCosLibCall(Node, Results);
4061 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
4062 RTLIB::LOG_F80, RTLIB::LOG_F128,
4063 RTLIB::LOG_PPCF128));
4066 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
4067 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
4068 RTLIB::LOG2_PPCF128));
4071 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
4072 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
4073 RTLIB::LOG10_PPCF128));
4076 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
4077 RTLIB::EXP_F80, RTLIB::EXP_F128,
4078 RTLIB::EXP_PPCF128));
4081 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
4082 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
4083 RTLIB::EXP2_PPCF128));
4086 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
4087 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
4088 RTLIB::TRUNC_PPCF128));
4091 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
4092 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
4093 RTLIB::FLOOR_PPCF128));
4096 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
4097 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
4098 RTLIB::CEIL_PPCF128));
4101 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
4102 RTLIB::RINT_F80, RTLIB::RINT_F128,
4103 RTLIB::RINT_PPCF128));
4105 case ISD::FNEARBYINT:
4106 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
4107 RTLIB::NEARBYINT_F64,
4108 RTLIB::NEARBYINT_F80,
4109 RTLIB::NEARBYINT_F128,
4110 RTLIB::NEARBYINT_PPCF128));
4113 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
4117 RTLIB::ROUND_PPCF128));
4120 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
4121 RTLIB::POWI_F80, RTLIB::POWI_F128,
4122 RTLIB::POWI_PPCF128));
4125 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
4126 RTLIB::POW_F80, RTLIB::POW_F128,
4127 RTLIB::POW_PPCF128));
4130 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
4131 RTLIB::DIV_F80, RTLIB::DIV_F128,
4132 RTLIB::DIV_PPCF128));
4135 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
4136 RTLIB::REM_F80, RTLIB::REM_F128,
4137 RTLIB::REM_PPCF128));
4140 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
4141 RTLIB::FMA_F80, RTLIB::FMA_F128,
4142 RTLIB::FMA_PPCF128));
4145 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
4146 RTLIB::ADD_F80, RTLIB::ADD_F128,
4147 RTLIB::ADD_PPCF128));
4150 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
4151 RTLIB::MUL_F80, RTLIB::MUL_F128,
4152 RTLIB::MUL_PPCF128));
4154 case ISD::FP16_TO_FP:
4155 if (Node->getValueType(0) == MVT::f32) {
4156 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
4159 case ISD::FP_TO_FP16: {
4161 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
4162 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4163 Results.push_back(ExpandLibCall(LC, Node, false));
4167 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4168 RTLIB::SUB_F80, RTLIB::SUB_F128,
4169 RTLIB::SUB_PPCF128));
4172 Results.push_back(ExpandIntLibCall(Node, true,
4174 RTLIB::SREM_I16, RTLIB::SREM_I32,
4175 RTLIB::SREM_I64, RTLIB::SREM_I128));
4178 Results.push_back(ExpandIntLibCall(Node, false,
4180 RTLIB::UREM_I16, RTLIB::UREM_I32,
4181 RTLIB::UREM_I64, RTLIB::UREM_I128));
4184 Results.push_back(ExpandIntLibCall(Node, true,
4186 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4187 RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4190 Results.push_back(ExpandIntLibCall(Node, false,
4192 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4193 RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4197 // Expand into divrem libcall
4198 ExpandDivRemLibCall(Node, Results);
4201 Results.push_back(ExpandIntLibCall(Node, false,
4203 RTLIB::MUL_I16, RTLIB::MUL_I32,
4204 RTLIB::MUL_I64, RTLIB::MUL_I128));
4208 // Replace the original node with the legalized result.
4209 if (!Results.empty())
4210 ReplaceNode(Node, Results.data());
4213 // Determine the vector type to use in place of an original scalar element when
4214 // promoting equally sized vectors.
4215 static MVT getPromotedVectorElementType(const TargetLowering &TLI,
4216 MVT EltVT, MVT NewEltVT) {
4217 unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4218 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4219 assert(TLI.isTypeLegal(MidVT) && "unexpected");
4223 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4224 SmallVector<SDValue, 8> Results;
4225 MVT OVT = Node->getSimpleValueType(0);
4226 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4227 Node->getOpcode() == ISD::SINT_TO_FP ||
4228 Node->getOpcode() == ISD::SETCC ||
4229 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4230 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4231 OVT = Node->getOperand(0).getSimpleValueType();
4233 if (Node->getOpcode() == ISD::BR_CC)
4234 OVT = Node->getOperand(2).getSimpleValueType();
4235 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4237 SDValue Tmp1, Tmp2, Tmp3;
4238 switch (Node->getOpcode()) {
4240 case ISD::CTTZ_ZERO_UNDEF:
4242 case ISD::CTLZ_ZERO_UNDEF:
4244 // Zero extend the argument.
4245 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4246 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4247 // already the correct result.
4248 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4249 if (Node->getOpcode() == ISD::CTTZ) {
4250 // FIXME: This should set a bit in the zero extended value instead.
4251 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4252 Tmp1, DAG.getConstant(NVT.getSizeInBits(), dl, NVT),
4254 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4255 DAG.getConstant(OVT.getSizeInBits(), dl, NVT), Tmp1);
4256 } else if (Node->getOpcode() == ISD::CTLZ ||
4257 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4258 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4259 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4260 DAG.getConstant(NVT.getSizeInBits() -
4261 OVT.getSizeInBits(), dl, NVT));
4263 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4266 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4267 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4268 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4270 ISD::SRL, dl, NVT, Tmp1,
4271 DAG.getConstant(DiffBits, dl,
4272 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4273 Results.push_back(Tmp1);
4276 case ISD::FP_TO_UINT:
4277 case ISD::FP_TO_SINT:
4278 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4279 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4280 Results.push_back(Tmp1);
4282 case ISD::UINT_TO_FP:
4283 case ISD::SINT_TO_FP:
4284 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4285 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4286 Results.push_back(Tmp1);
4289 SDValue Chain = Node->getOperand(0); // Get the chain.
4290 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4293 if (OVT.isVector()) {
4294 TruncOp = ISD::BITCAST;
4296 assert(OVT.isInteger()
4297 && "VAARG promotion is supported only for vectors or integer types");
4298 TruncOp = ISD::TRUNCATE;
4301 // Perform the larger operation, then convert back
4302 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4303 Node->getConstantOperandVal(3));
4304 Chain = Tmp1.getValue(1);
4306 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4308 // Modified the chain result - switch anything that used the old chain to
4310 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4311 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4313 UpdatedNodes->insert(Tmp2.getNode());
4314 UpdatedNodes->insert(Chain.getNode());
4322 unsigned ExtOp, TruncOp;
4323 if (OVT.isVector()) {
4324 ExtOp = ISD::BITCAST;
4325 TruncOp = ISD::BITCAST;
4327 assert(OVT.isInteger() && "Cannot promote logic operation");
4328 ExtOp = ISD::ANY_EXTEND;
4329 TruncOp = ISD::TRUNCATE;
4331 // Promote each of the values to the new type.
4332 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4333 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4334 // Perform the larger operation, then convert back
4335 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4336 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4340 unsigned ExtOp, TruncOp;
4341 if (Node->getValueType(0).isVector() ||
4342 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4343 ExtOp = ISD::BITCAST;
4344 TruncOp = ISD::BITCAST;
4345 } else if (Node->getValueType(0).isInteger()) {
4346 ExtOp = ISD::ANY_EXTEND;
4347 TruncOp = ISD::TRUNCATE;
4349 ExtOp = ISD::FP_EXTEND;
4350 TruncOp = ISD::FP_ROUND;
4352 Tmp1 = Node->getOperand(0);
4353 // Promote each of the values to the new type.
4354 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4355 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4356 // Perform the larger operation, then round down.
4357 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4358 if (TruncOp != ISD::FP_ROUND)
4359 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4361 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4362 DAG.getIntPtrConstant(0, dl));
4363 Results.push_back(Tmp1);
4366 case ISD::VECTOR_SHUFFLE: {
4367 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4369 // Cast the two input vectors.
4370 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4371 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4373 // Convert the shuffle mask to the right # elements.
4374 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4375 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4376 Results.push_back(Tmp1);
4380 unsigned ExtOp = ISD::FP_EXTEND;
4381 if (NVT.isInteger()) {
4382 ISD::CondCode CCCode =
4383 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4384 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4386 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4387 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4388 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4389 Tmp1, Tmp2, Node->getOperand(2)));
4393 unsigned ExtOp = ISD::FP_EXTEND;
4394 if (NVT.isInteger()) {
4395 ISD::CondCode CCCode =
4396 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4397 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4399 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4400 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4401 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4402 Node->getOperand(0), Node->getOperand(1),
4403 Tmp1, Tmp2, Node->getOperand(4)));
4414 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4415 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4416 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4418 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4419 Tmp3, DAG.getIntPtrConstant(0, dl)));
4423 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4424 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4425 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4427 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4428 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4429 DAG.getIntPtrConstant(0, dl)));
4432 case ISD::FCOPYSIGN:
4434 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4435 Tmp2 = Node->getOperand(1);
4436 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4438 // fcopysign doesn't change anything but the sign bit, so
4439 // (fp_round (fcopysign (fpext a), b))
4441 // (fp_round (fpext a))
4442 // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4443 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4444 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4445 Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4451 case ISD::FNEARBYINT:
4464 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4465 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4466 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4467 Tmp2, DAG.getIntPtrConstant(0, dl)));
4470 case ISD::BUILD_VECTOR: {
4471 MVT EltVT = OVT.getVectorElementType();
4472 MVT NewEltVT = NVT.getVectorElementType();
4474 // Handle bitcasts to a different vector type with the same total bit size
4476 // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4478 // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4480 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4481 "Invalid promote type for build_vector");
4482 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4484 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4486 SmallVector<SDValue, 8> NewOps;
4487 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4488 SDValue Op = Node->getOperand(I);
4489 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4493 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4494 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4495 Results.push_back(CvtVec);
4498 case ISD::EXTRACT_VECTOR_ELT: {
4499 MVT EltVT = OVT.getVectorElementType();
4500 MVT NewEltVT = NVT.getVectorElementType();
4502 // Handle bitcasts to a different vector type with the same total bit size.
4504 // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4506 // v4i32:castx = bitcast x:v2i64
4509 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4510 // (i32 (extract_vector_elt castx, (2 * y + 1)))
4513 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4514 "Invalid promote type for extract_vector_elt");
4515 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4517 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4518 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4520 SDValue Idx = Node->getOperand(1);
4521 EVT IdxVT = Idx.getValueType();
4523 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4524 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4526 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4528 SmallVector<SDValue, 8> NewOps;
4529 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4530 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4531 SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4533 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4535 NewOps.push_back(Elt);
4538 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, SL, MidVT, NewOps);
4540 Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4543 case ISD::INSERT_VECTOR_ELT: {
4544 MVT EltVT = OVT.getVectorElementType();
4545 MVT NewEltVT = NVT.getVectorElementType();
4547 // Handle bitcasts to a different vector type with the same total bit size
4549 // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4551 // v4i32:castx = bitcast x:v2i64
4552 // v2i32:casty = bitcast y:i64
4555 // (v4i32 insert_vector_elt
4556 // (v4i32 insert_vector_elt v4i32:castx,
4557 // (extract_vector_elt casty, 0), 2 * z),
4558 // (extract_vector_elt casty, 1), (2 * z + 1))
4560 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4561 "Invalid promote type for insert_vector_elt");
4562 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4564 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4565 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4567 SDValue Val = Node->getOperand(1);
4568 SDValue Idx = Node->getOperand(2);
4569 EVT IdxVT = Idx.getValueType();
4572 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4573 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4575 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4576 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4578 SDValue NewVec = CastVec;
4579 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4580 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4581 SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4583 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4584 CastVal, IdxOffset);
4586 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4587 NewVec, Elt, InEltIdx);
4590 Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4593 case ISD::SCALAR_TO_VECTOR: {
4594 MVT EltVT = OVT.getVectorElementType();
4595 MVT NewEltVT = NVT.getVectorElementType();
4597 // Handle bitcasts to different vector type with the smae total bit size.
4599 // e.g. v2i64 = scalar_to_vector x:i64
4601 // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4604 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4605 SDValue Val = Node->getOperand(0);
4608 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4609 SDValue Undef = DAG.getUNDEF(MidVT);
4611 SmallVector<SDValue, 8> NewElts;
4612 NewElts.push_back(CastVal);
4613 for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4614 NewElts.push_back(Undef);
4616 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4617 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4618 Results.push_back(CvtVec);
4623 // Replace the original node with the legalized result.
4624 if (!Results.empty())
4625 ReplaceNode(Node, Results.data());
4628 /// This is the entry point for the file.
4629 void SelectionDAG::Legalize() {
4630 AssignTopologicalOrder();
4632 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4633 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4635 // Visit all the nodes. We start in topological order, so that we see
4636 // nodes with their original operands intact. Legalization can produce
4637 // new nodes which may themselves need to be legalized. Iterate until all
4638 // nodes have been legalized.
4640 bool AnyLegalized = false;
4641 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4645 if (N->use_empty() && N != getRoot().getNode()) {
4651 if (LegalizedNodes.insert(N).second) {
4652 AnyLegalized = true;
4653 Legalizer.LegalizeOp(N);
4655 if (N->use_empty() && N != getRoot().getNode()) {
4666 // Remove dead nodes now.
4670 bool SelectionDAG::LegalizeOp(SDNode *N,
4671 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4672 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4673 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4675 // Directly insert the node in question, and legalize it. This will recurse
4676 // as needed through operands.
4677 LegalizedNodes.insert(N);
4678 Legalizer.LegalizeOp(N);
4680 return LegalizedNodes.count(N);