1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "instr-emitter"
17 #include "InstrEmitter.h"
18 #include "SDNodeDbgValue.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
33 /// MinRCSize - Smallest register class we allow when constraining virtual
34 /// registers. If satisfying all register class constraints would require
35 /// using a smaller register class, emit a COPY to a new virtual register
37 const unsigned MinRCSize = 4;
39 /// CountResults - The results of target nodes have register or immediate
40 /// operands first, then an optional chain, and optional glue operands (which do
41 /// not go into the resulting MachineInstr).
42 unsigned InstrEmitter::CountResults(SDNode *Node) {
43 unsigned N = Node->getNumValues();
44 while (N && Node->getValueType(N - 1) == MVT::Glue)
46 if (N && Node->getValueType(N - 1) == MVT::Other)
47 --N; // Skip over chain result.
51 /// countOperands - The inputs to target nodes have any actual inputs first,
52 /// followed by an optional chain operand, then an optional glue operand.
53 /// Compute the number of actual operands that will go into the resulting
56 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
57 /// the chain and glue. These operands may be implicit on the machine instr.
58 static unsigned countOperands(SDNode *Node, unsigned &NumImpUses) {
59 unsigned N = Node->getNumOperands();
60 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
62 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
63 --N; // Ignore chain if it exists.
65 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
66 for (unsigned I = N; I; --I) {
67 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
69 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
70 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
79 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
80 /// implicit physical register output.
82 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
83 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
85 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
86 // Just use the input register directly!
87 SDValue Op(Node, ResNo);
90 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
91 (void)isNew; // Silence compiler warning.
92 assert(isNew && "Node emitted out of order - early");
96 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
97 // the CopyToReg'd destination register instead of creating a new vreg.
99 const TargetRegisterClass *UseRC = NULL;
100 EVT VT = Node->getValueType(ResNo);
102 // Stick to the preferred register classes for legal types.
103 if (TLI->isTypeLegal(VT))
104 UseRC = TLI->getRegClassFor(VT);
106 if (!IsClone && !IsCloned)
107 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
111 if (User->getOpcode() == ISD::CopyToReg &&
112 User->getOperand(2).getNode() == Node &&
113 User->getOperand(2).getResNo() == ResNo) {
114 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
115 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
118 } else if (DestReg != SrcReg)
121 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
122 SDValue Op = User->getOperand(i);
123 if (Op.getNode() != Node || Op.getResNo() != ResNo)
125 EVT VT = Node->getValueType(Op.getResNo());
126 if (VT == MVT::Other || VT == MVT::Glue)
129 if (User->isMachineOpcode()) {
130 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
131 const TargetRegisterClass *RC = 0;
132 if (i+II.getNumDefs() < II.getNumOperands()) {
133 RC = TRI->getAllocatableClass(
134 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
139 const TargetRegisterClass *ComRC =
140 TRI->getCommonSubClass(UseRC, RC);
141 // If multiple uses expect disjoint register classes, we emit
142 // copies in AddRegisterOperand.
154 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
155 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
157 // Figure out the register class to create for the destreg.
159 DstRC = MRI->getRegClass(VRBase);
161 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
164 DstRC = TLI->getRegClassFor(VT);
167 // If all uses are reading from the src physical register and copying the
168 // register is either impossible or very expensive, then don't create a copy.
169 if (MatchReg && SrcRC->getCopyCost() < 0) {
172 // Create the reg, emit the copy.
173 VRBase = MRI->createVirtualRegister(DstRC);
174 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
175 VRBase).addReg(SrcReg);
178 SDValue Op(Node, ResNo);
181 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
182 (void)isNew; // Silence compiler warning.
183 assert(isNew && "Node emitted out of order - early");
186 /// getDstOfCopyToRegUse - If the only use of the specified result number of
187 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
188 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
189 unsigned ResNo) const {
190 if (!Node->hasOneUse())
193 SDNode *User = *Node->use_begin();
194 if (User->getOpcode() == ISD::CopyToReg &&
195 User->getOperand(2).getNode() == Node &&
196 User->getOperand(2).getResNo() == ResNo) {
197 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
198 if (TargetRegisterInfo::isVirtualRegister(Reg))
204 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
205 const MCInstrDesc &II,
206 bool IsClone, bool IsCloned,
207 DenseMap<SDValue, unsigned> &VRBaseMap) {
208 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
209 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
211 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
212 // If the specific node value is only used by a CopyToReg and the dest reg
213 // is a vreg in the same register class, use the CopyToReg'd destination
214 // register instead of creating a new vreg.
216 const TargetRegisterClass *RC =
217 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
218 if (II.OpInfo[i].isOptionalDef()) {
219 // Optional def must be a physical register.
220 unsigned NumResults = CountResults(Node);
221 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
222 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
223 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
226 if (!VRBase && !IsClone && !IsCloned)
227 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
230 if (User->getOpcode() == ISD::CopyToReg &&
231 User->getOperand(2).getNode() == Node &&
232 User->getOperand(2).getResNo() == i) {
233 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
234 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
235 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
238 MI->addOperand(MachineOperand::CreateReg(Reg, true));
245 // Create the result registers for this node and add the result regs to
246 // the machine instruction.
248 assert(RC && "Isn't a register operand!");
249 VRBase = MRI->createVirtualRegister(RC);
250 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
256 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
257 (void)isNew; // Silence compiler warning.
258 assert(isNew && "Node emitted out of order - early");
262 /// getVR - Return the virtual register corresponding to the specified result
263 /// of the specified node.
264 unsigned InstrEmitter::getVR(SDValue Op,
265 DenseMap<SDValue, unsigned> &VRBaseMap) {
266 if (Op.isMachineOpcode() &&
267 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
268 // Add an IMPLICIT_DEF instruction before every use.
269 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
270 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
271 // does not include operand register class info.
273 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
274 VReg = MRI->createVirtualRegister(RC);
276 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
277 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
281 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
282 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
287 /// AddRegisterOperand - Add the specified register as an operand to the
288 /// specified machine instr. Insert register copies if the register is
289 /// not in the required register class.
291 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
293 const MCInstrDesc *II,
294 DenseMap<SDValue, unsigned> &VRBaseMap,
295 bool IsDebug, bool IsClone, bool IsCloned) {
296 assert(Op.getValueType() != MVT::Other &&
297 Op.getValueType() != MVT::Glue &&
298 "Chain and glue operands should occur at end of operand list!");
299 // Get/emit the operand.
300 unsigned VReg = getVR(Op, VRBaseMap);
301 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
303 const MCInstrDesc &MCID = MI->getDesc();
304 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
305 MCID.OpInfo[IIOpNum].isOptionalDef();
307 // If the instruction requires a register in a different class, create
308 // a new virtual register and copy the value into it, but first attempt to
309 // shrink VReg's register class within reason. For example, if VReg == GR32
310 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
312 const TargetRegisterClass *DstRC = 0;
313 if (IIOpNum < II->getNumOperands())
314 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
315 assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
316 "Don't have operand info for this instruction!");
317 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
318 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
319 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
320 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
325 // If this value has only one use, that use is a kill. This is a
326 // conservative approximation. InstrEmitter does trivial coalescing
327 // with CopyFromReg nodes, so don't emit kill flags for them.
328 // Avoid kill flags on Schedule cloned nodes, since there will be
330 // Tied operands are never killed, so we need to check that. And that
331 // means we need to determine the index of the operand.
332 bool isKill = Op.hasOneUse() &&
333 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
335 !(IsClone || IsCloned);
337 unsigned Idx = MI->getNumOperands();
339 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
341 bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
346 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
347 false/*isImp*/, isKill,
348 false/*isDead*/, false/*isUndef*/,
349 false/*isEarlyClobber*/,
350 0/*SubReg*/, IsDebug));
353 /// AddOperand - Add the specified operand to the specified machine instr. II
354 /// specifies the instruction information for the node, and IIOpNum is the
355 /// operand number (in the II) that we are adding.
356 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
358 const MCInstrDesc *II,
359 DenseMap<SDValue, unsigned> &VRBaseMap,
360 bool IsDebug, bool IsClone, bool IsCloned) {
361 if (Op.isMachineOpcode()) {
362 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
363 IsDebug, IsClone, IsCloned);
364 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
365 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
366 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
367 const ConstantFP *CFP = F->getConstantFPValue();
368 MI->addOperand(MachineOperand::CreateFPImm(CFP));
369 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
370 // Turn additional physreg operands into implicit uses on non-variadic
371 // instructions. This is used by call and return instructions passing
372 // arguments in registers.
373 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
374 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, Imp));
375 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
376 MI->addOperand(MachineOperand::CreateRegMask(RM->getRegMask()));
377 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
378 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
379 TGA->getTargetFlags()));
380 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
381 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
382 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
383 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
384 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
385 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
386 JT->getTargetFlags()));
387 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
388 int Offset = CP->getOffset();
389 unsigned Align = CP->getAlignment();
390 Type *Type = CP->getType();
391 // MachineConstantPool wants an explicit alignment.
393 Align = TM->getTargetData()->getPrefTypeAlignment(Type);
395 // Alignment of vector types. FIXME!
396 Align = TM->getTargetData()->getTypeAllocSize(Type);
401 MachineConstantPool *MCP = MF->getConstantPool();
402 if (CP->isMachineConstantPoolEntry())
403 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
405 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
406 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
407 CP->getTargetFlags()));
408 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
409 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
410 ES->getTargetFlags()));
411 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
412 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
413 BA->getTargetFlags()));
415 assert(Op.getValueType() != MVT::Other &&
416 Op.getValueType() != MVT::Glue &&
417 "Chain and glue operands should occur at end of operand list!");
418 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
419 IsDebug, IsClone, IsCloned);
423 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
424 EVT VT, DebugLoc DL) {
425 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
426 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
428 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
431 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
433 // VReg has been adjusted. It can be used with SubIdx operands now.
437 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
439 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
440 assert(RC && "No legal register class for VT supports that SubIdx");
441 unsigned NewReg = MRI->createVirtualRegister(RC);
442 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
447 /// EmitSubregNode - Generate machine code for subreg nodes.
449 void InstrEmitter::EmitSubregNode(SDNode *Node,
450 DenseMap<SDValue, unsigned> &VRBaseMap,
451 bool IsClone, bool IsCloned) {
453 unsigned Opc = Node->getMachineOpcode();
455 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
456 // the CopyToReg'd destination register instead of creating a new vreg.
457 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
460 if (User->getOpcode() == ISD::CopyToReg &&
461 User->getOperand(2).getNode() == Node) {
462 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
463 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
470 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
471 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
472 // constraints on the %dst register, COPY can target all legal register
474 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
475 const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0));
477 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
478 MachineInstr *DefMI = MRI->getVRegDef(VReg);
479 unsigned SrcReg, DstReg, DefSubIdx;
481 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
482 SubIdx == DefSubIdx) {
484 // r1025 = s/zext r1024, 4
485 // r1026 = extract_subreg r1025, 4
487 // r1026 = copy r1024
488 VRBase = MRI->createVirtualRegister(TRC);
489 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
490 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
491 MRI->clearKillFlags(SrcReg);
493 // VReg may not support a SubIdx sub-register, and we may need to
494 // constrain its register class or issue a COPY to a compatible register
496 VReg = ConstrainForSubReg(VReg, SubIdx,
497 Node->getOperand(0).getValueType(),
498 Node->getDebugLoc());
500 // Create the destreg if it is missing.
502 VRBase = MRI->createVirtualRegister(TRC);
504 // Create the extract_subreg machine instruction.
505 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
506 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
508 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
509 Opc == TargetOpcode::SUBREG_TO_REG) {
510 SDValue N0 = Node->getOperand(0);
511 SDValue N1 = Node->getOperand(1);
512 SDValue N2 = Node->getOperand(2);
513 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
515 // Figure out the register class to create for the destreg. It should be
516 // the largest legal register class supporting SubIdx sub-registers.
517 // RegisterCoalescer will constrain it further if it decides to eliminate
518 // the INSERT_SUBREG instruction.
520 // %dst = INSERT_SUBREG %src, %sub, SubIdx
522 // is lowered by TwoAddressInstructionPass to:
525 // %dst:SubIdx = COPY %sub
527 // There is no constraint on the %src register class.
529 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0));
530 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
531 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
533 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
534 VRBase = MRI->createVirtualRegister(SRC);
536 // Create the insert_subreg or subreg_to_reg machine instruction.
537 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
538 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
540 // If creating a subreg_to_reg, then the first input operand
541 // is an implicit value immediate, otherwise it's a register
542 if (Opc == TargetOpcode::SUBREG_TO_REG) {
543 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
544 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
546 AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
548 // Add the subregster being inserted
549 AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
551 MI->addOperand(MachineOperand::CreateImm(SubIdx));
552 MBB->insert(InsertPos, MI);
554 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
557 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
558 (void)isNew; // Silence compiler warning.
559 assert(isNew && "Node emitted out of order - early");
562 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
563 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
564 /// register is constrained to be in a particular register class.
567 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
568 DenseMap<SDValue, unsigned> &VRBaseMap) {
569 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
571 // Create the new VReg in the destination class and emit a copy.
572 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
573 const TargetRegisterClass *DstRC =
574 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
575 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
576 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
577 NewVReg).addReg(VReg);
580 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
581 (void)isNew; // Silence compiler warning.
582 assert(isNew && "Node emitted out of order - early");
585 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
587 void InstrEmitter::EmitRegSequence(SDNode *Node,
588 DenseMap<SDValue, unsigned> &VRBaseMap,
589 bool IsClone, bool IsCloned) {
590 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
591 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
592 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
593 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
594 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
595 unsigned NumOps = Node->getNumOperands();
596 assert((NumOps & 1) == 1 &&
597 "REG_SEQUENCE must have an odd number of operands!");
598 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
599 for (unsigned i = 1; i != NumOps; ++i) {
600 SDValue Op = Node->getOperand(i);
602 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
603 // Skip physical registers as they don't have a vreg to get and we'll
604 // insert copies for them in TwoAddressInstructionPass anyway.
605 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
606 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
607 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
608 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
609 const TargetRegisterClass *SRC =
610 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
611 if (SRC && SRC != RC) {
612 MRI->setRegClass(NewVReg, SRC);
617 AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
621 MBB->insert(InsertPos, MI);
623 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
624 (void)isNew; // Silence compiler warning.
625 assert(isNew && "Node emitted out of order - early");
628 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
631 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
632 DenseMap<SDValue, unsigned> &VRBaseMap) {
633 uint64_t Offset = SD->getOffset();
634 MDNode* MDPtr = SD->getMDPtr();
635 DebugLoc DL = SD->getDebugLoc();
637 if (SD->getKind() == SDDbgValue::FRAMEIX) {
638 // Stack address; this needs to be lowered in target-dependent fashion.
639 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
640 unsigned FrameIx = SD->getFrameIx();
641 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
643 // Otherwise, we're going to create an instruction here.
644 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
645 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
646 if (SD->getKind() == SDDbgValue::SDNODE) {
647 SDNode *Node = SD->getSDNode();
648 SDValue Op = SDValue(Node, SD->getResNo());
649 // It's possible we replaced this SDNode with other(s) and therefore
650 // didn't generate code for it. It's better to catch these cases where
651 // they happen and transfer the debug info, but trying to guarantee that
652 // in all cases would be very fragile; this is a safeguard for any
654 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
655 if (I==VRBaseMap.end())
656 MIB.addReg(0U); // undef
658 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
659 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
660 } else if (SD->getKind() == SDDbgValue::CONST) {
661 const Value *V = SD->getConst();
662 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
663 if (CI->getBitWidth() > 64)
666 MIB.addImm(CI->getSExtValue());
667 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
670 // Could be an Undef. In any case insert an Undef so we can see what we
675 // Insert an Undef so we can see what we dropped.
679 MIB.addImm(Offset).addMetadata(MDPtr);
683 /// EmitMachineNode - Generate machine code for a target-specific node and
684 /// needed dependencies.
687 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
688 DenseMap<SDValue, unsigned> &VRBaseMap) {
689 unsigned Opc = Node->getMachineOpcode();
691 // Handle subreg insert/extract specially
692 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
693 Opc == TargetOpcode::INSERT_SUBREG ||
694 Opc == TargetOpcode::SUBREG_TO_REG) {
695 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
699 // Handle COPY_TO_REGCLASS specially.
700 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
701 EmitCopyToRegClassNode(Node, VRBaseMap);
705 // Handle REG_SEQUENCE specially.
706 if (Opc == TargetOpcode::REG_SEQUENCE) {
707 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
711 if (Opc == TargetOpcode::IMPLICIT_DEF)
712 // We want a unique VR for each IMPLICIT_DEF use.
715 const MCInstrDesc &II = TII->get(Opc);
716 unsigned NumResults = CountResults(Node);
717 unsigned NumImpUses = 0;
718 unsigned NodeOperands = countOperands(Node, NumImpUses);
719 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
721 unsigned NumMIOperands = NodeOperands + NumResults;
723 assert(NumMIOperands >= II.getNumOperands() &&
724 "Too few operands for a variadic node!");
726 assert(NumMIOperands >= II.getNumOperands() &&
727 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
729 "#operands for dag node doesn't match .td file!");
732 // Create the new machine instruction.
733 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
735 // Add result register values for things that are defined by this
738 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
740 // Emit all of the actual operands of this instruction, adding them to the
741 // instruction as appropriate.
742 bool HasOptPRefs = II.getNumDefs() > NumResults;
743 assert((!HasOptPRefs || !HasPhysRegOuts) &&
744 "Unable to cope with optional defs and phys regs defs!");
745 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
746 for (unsigned i = NumSkip; i != NodeOperands; ++i)
747 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
748 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
750 // Transfer all of the memory reference descriptions of this instruction.
751 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
752 cast<MachineSDNode>(Node)->memoperands_end());
754 // Insert the instruction into position in the block. This needs to
755 // happen before any custom inserter hook is called so that the
756 // hook knows where in the block to insert the replacement code.
757 MBB->insert(InsertPos, MI);
759 // The MachineInstr may also define physregs instead of virtregs. These
760 // physreg values can reach other instructions in different ways:
762 // 1. When there is a use of a Node value beyond the explicitly defined
763 // virtual registers, we emit a CopyFromReg for one of the implicitly
764 // defined physregs. This only happens when HasPhysRegOuts is true.
766 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
768 // 3. A glued instruction may implicitly use a physreg.
770 // 4. A glued instruction may use a RegisterSDNode operand.
772 // Collect all the used physreg defs, and make sure that any unused physreg
773 // defs are marked as dead.
774 SmallVector<unsigned, 8> UsedRegs;
776 // Additional results must be physical register defs.
777 if (HasPhysRegOuts) {
778 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
779 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
780 if (!Node->hasAnyUseOfValue(i))
782 // This implicitly defined physreg has a use.
783 UsedRegs.push_back(Reg);
784 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
788 // Scan the glue chain for any used physregs.
789 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
790 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
791 if (F->getOpcode() == ISD::CopyFromReg) {
792 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
794 } else if (F->getOpcode() == ISD::CopyToReg) {
795 // Skip CopyToReg nodes that are internal to the glue chain.
798 // Collect declared implicit uses.
799 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
800 UsedRegs.append(MCID.getImplicitUses(),
801 MCID.getImplicitUses() + MCID.getNumImplicitUses());
802 // In addition to declared implicit uses, we must also check for
803 // direct RegisterSDNode operands.
804 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
805 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
806 unsigned Reg = R->getReg();
807 if (TargetRegisterInfo::isPhysicalRegister(Reg))
808 UsedRegs.push_back(Reg);
813 // Finally mark unused registers as dead.
814 if (!UsedRegs.empty() || II.getImplicitDefs())
815 MI->setPhysRegsDeadExcept(UsedRegs, *TRI);
817 // Run post-isel target hook to adjust this instruction if needed.
819 if (II.hasPostISelHook())
821 TLI->AdjustInstrPostInstrSelection(MI, Node);
824 /// EmitSpecialNode - Generate machine code for a target-independent node and
825 /// needed dependencies.
827 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
828 DenseMap<SDValue, unsigned> &VRBaseMap) {
829 switch (Node->getOpcode()) {
834 llvm_unreachable("This target-independent node should have been selected!");
835 case ISD::EntryToken:
836 llvm_unreachable("EntryToken should have been excluded from the schedule!");
837 case ISD::MERGE_VALUES:
838 case ISD::TokenFactor: // fall thru
840 case ISD::CopyToReg: {
842 SDValue SrcVal = Node->getOperand(2);
843 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
844 SrcReg = R->getReg();
846 SrcReg = getVR(SrcVal, VRBaseMap);
848 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
849 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
852 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
853 DestReg).addReg(SrcReg);
856 case ISD::CopyFromReg: {
857 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
858 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
861 case ISD::EH_LABEL: {
862 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
863 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
864 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
868 case ISD::INLINEASM: {
869 unsigned NumOps = Node->getNumOperands();
870 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
871 --NumOps; // Ignore the glue operand.
873 // Create the inline asm machine instruction.
874 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
875 TII->get(TargetOpcode::INLINEASM));
877 // Add the asm string as an external symbol operand.
878 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
879 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
880 MI->addOperand(MachineOperand::CreateES(AsmStr));
882 // Add the HasSideEffect and isAlignStack bits.
884 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
886 MI->addOperand(MachineOperand::CreateImm(ExtraInfo));
888 // Add all of the operand registers to the instruction.
889 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
891 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
892 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
894 MI->addOperand(MachineOperand::CreateImm(Flags));
895 ++i; // Skip the ID value.
897 switch (InlineAsm::getKind(Flags)) {
898 default: llvm_unreachable("Bad flags!");
899 case InlineAsm::Kind_RegDef:
900 for (; NumVals; --NumVals, ++i) {
901 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
902 // FIXME: Add dead flags for physical and virtual registers defined.
903 // For now, mark physical register defs as implicit to help fast
904 // regalloc. This makes inline asm look a lot like calls.
905 MI->addOperand(MachineOperand::CreateReg(Reg, true,
906 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg)));
909 case InlineAsm::Kind_RegDefEarlyClobber:
910 case InlineAsm::Kind_Clobber:
911 for (; NumVals; --NumVals, ++i) {
912 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
913 MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true,
914 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg),
918 /*isEarlyClobber=*/ true));
921 case InlineAsm::Kind_RegUse: // Use of register.
922 case InlineAsm::Kind_Imm: // Immediate.
923 case InlineAsm::Kind_Mem: // Addressing mode.
924 // The addressing mode has been selected, just add all of the
925 // operands to the machine instruction.
926 for (; NumVals; --NumVals, ++i)
927 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
928 /*IsDebug=*/false, IsClone, IsCloned);
933 // Get the mdnode from the asm if it exists and add it to the instruction.
934 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
935 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
937 MI->addOperand(MachineOperand::CreateMetadata(MD));
939 MBB->insert(InsertPos, MI);
945 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
946 /// at the given position in the given block.
947 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
948 MachineBasicBlock::iterator insertpos)
949 : MF(mbb->getParent()),
950 MRI(&MF->getRegInfo()),
951 TM(&MF->getTarget()),
952 TII(TM->getInstrInfo()),
953 TRI(TM->getRegisterInfo()),
954 TLI(TM->getTargetLowering()),
955 MBB(mbb), InsertPos(insertpos) {