1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating functions from LLVM IR into
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/FunctionLoweringInfo.h"
16 #include "llvm/ADT/PostOrderIterator.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/WinEHFuncInfo.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/IntrinsicInst.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "function-lowering-info"
47 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
48 /// PHI nodes or outside of the basic block that defines it, or used by a
49 /// switch or atomic instruction, which may expand to multiple basic blocks.
50 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
51 if (I->use_empty()) return false;
52 if (isa<PHINode>(I)) return true;
53 const BasicBlock *BB = I->getParent();
54 for (const User *U : I->users())
55 if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
61 static ISD::NodeType getPreferredExtendForValue(const Value *V) {
62 // For the users of the source value being used for compare instruction, if
63 // the number of signed predicate is greater than unsigned predicate, we
64 // prefer to use SIGN_EXTEND.
66 // With this optimization, we would be able to reduce some redundant sign or
67 // zero extension instruction, and eventually more machine CSE opportunities
69 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
70 unsigned NumOfSigned = 0, NumOfUnsigned = 0;
71 for (const User *U : V->users()) {
72 if (const auto *CI = dyn_cast<CmpInst>(U)) {
73 NumOfSigned += CI->isSigned();
74 NumOfUnsigned += CI->isUnsigned();
77 if (NumOfSigned > NumOfUnsigned)
78 ExtendKind = ISD::SIGN_EXTEND;
83 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
87 TLI = MF->getSubtarget().getTargetLowering();
88 RegInfo = &MF->getRegInfo();
89 MachineModuleInfo &MMI = MF->getMMI();
91 // Check whether the function can return without sret-demotion.
92 SmallVector<ISD::OutputArg, 4> Outs;
93 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
95 CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
96 Fn->isVarArg(), Outs, Fn->getContext());
98 // Initialize the mapping of values to registers. This is only set up for
99 // instruction values that are used outside of the block that defines
101 Function::const_iterator BB = Fn->begin(), EB = Fn->end();
102 for (; BB != EB; ++BB)
103 for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
105 if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
106 // Static allocas can be folded into the initial stack frame adjustment.
107 if (AI->isStaticAlloca()) {
108 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
109 Type *Ty = AI->getAllocatedType();
110 uint64_t TySize = MF->getDataLayout().getTypeAllocSize(Ty);
112 std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(Ty),
115 TySize *= CUI->getZExtValue(); // Get total allocated size.
116 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
118 StaticAllocaMap[AI] =
119 MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
123 std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(
124 AI->getAllocatedType()),
126 unsigned StackAlign =
127 MF->getSubtarget().getFrameLowering()->getStackAlignment();
128 if (Align <= StackAlign)
130 // Inform the Frame Information that we have variable-sized objects.
131 MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
135 // Look for inline asm that clobbers the SP register.
136 if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
137 ImmutableCallSite CS(I);
138 if (isa<InlineAsm>(CS.getCalledValue())) {
139 unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
140 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
141 std::vector<TargetLowering::AsmOperandInfo> Ops =
142 TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, CS);
143 for (size_t I = 0, E = Ops.size(); I != E; ++I) {
144 TargetLowering::AsmOperandInfo &Op = Ops[I];
145 if (Op.Type == InlineAsm::isClobber) {
146 // Clobbers don't have SDValue operands, hence SDValue().
147 TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
148 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
149 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
151 if (PhysReg.first == SP)
152 MF->getFrameInfo()->setHasOpaqueSPAdjustment(true);
158 // Look for calls to the @llvm.va_start intrinsic. We can omit some
159 // prologue boilerplate for variadic functions that don't examine their
161 if (const auto *II = dyn_cast<IntrinsicInst>(I)) {
162 if (II->getIntrinsicID() == Intrinsic::vastart)
163 MF->getFrameInfo()->setHasVAStart(true);
166 // If we have a musttail call in a variadic funciton, we need to ensure we
167 // forward implicit register parameters.
168 if (const auto *CI = dyn_cast<CallInst>(I)) {
169 if (CI->isMustTailCall() && Fn->isVarArg())
170 MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
173 // Mark values used outside their block as exported, by allocating
174 // a virtual register for them.
175 if (isUsedOutsideOfDefiningBlock(I))
176 if (!isa<AllocaInst>(I) ||
177 !StaticAllocaMap.count(cast<AllocaInst>(I)))
178 InitializeRegForValue(I);
180 // Collect llvm.dbg.declare information. This is done now instead of
181 // during the initial isel pass through the IR so that it is done
182 // in a predictable order.
183 if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
184 assert(DI->getVariable() && "Missing variable");
185 assert(DI->getDebugLoc() && "Missing location");
186 if (MMI.hasDebugInfo()) {
187 // Don't handle byval struct arguments or VLAs, for example.
188 // Non-byval arguments are handled here (they refer to the stack
189 // temporary alloca at this point).
190 const Value *Address = DI->getAddress();
192 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
193 Address = BCI->getOperand(0);
194 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
195 DenseMap<const AllocaInst *, int>::iterator SI =
196 StaticAllocaMap.find(AI);
197 if (SI != StaticAllocaMap.end()) { // Check for VLAs.
199 MMI.setVariableDbgInfo(DI->getVariable(), DI->getExpression(),
200 FI, DI->getDebugLoc());
207 // Decide the preferred extend type for a value.
208 PreferredExtendType[I] = getPreferredExtendForValue(I);
211 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
212 // also creates the initial PHI MachineInstrs, though none of the input
213 // operands are populated.
214 for (BB = Fn->begin(); BB != EB; ++BB) {
215 // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
216 // are really data, and no instructions can live here.
218 const Instruction *I = BB->getFirstNonPHI();
219 if (!isa<LandingPadInst>(I))
220 MMI.setHasEHFunclets(true);
221 if (isa<CatchPadInst>(I) || isa<CatchEndPadInst>(I) ||
222 isa<CleanupEndPadInst>(I)) {
223 assert(&*BB->begin() == I &&
224 "WinEHPrepare failed to remove PHIs from imaginary BBs");
226 } else if (!isa<LandingPadInst>(I)) {
227 llvm_unreachable("unhandled EH pad in MBB graph");
231 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
235 // Transfer the address-taken flag. This is necessary because there could
236 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
237 // the first one should be marked.
238 if (BB->hasAddressTaken())
239 MBB->setHasAddressTaken();
241 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
243 for (BasicBlock::const_iterator I = BB->begin();
244 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
245 if (PN->use_empty()) continue;
248 if (PN->getType()->isEmptyTy())
251 DebugLoc DL = PN->getDebugLoc();
252 unsigned PHIReg = ValueMap[PN];
253 assert(PHIReg && "PHI node does not have an assigned virtual register!");
255 SmallVector<EVT, 4> ValueVTs;
256 ComputeValueVTs(*TLI, MF->getDataLayout(), PN->getType(), ValueVTs);
257 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
258 EVT VT = ValueVTs[vti];
259 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
260 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
261 for (unsigned i = 0; i != NumRegisters; ++i)
262 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
263 PHIReg += NumRegisters;
268 // Mark landing pad blocks.
269 SmallVector<const LandingPadInst *, 4> LPads;
270 for (BB = Fn->begin(); BB != EB; ++BB) {
271 const Instruction *FNP = BB->getFirstNonPHI();
272 if (BB->isEHPad() && !isa<CatchPadInst>(FNP) && !isa<CatchEndPadInst>(FNP))
273 MBBMap[BB]->setIsEHPad();
274 if (const auto *LPI = dyn_cast<LandingPadInst>(FNP))
275 LPads.push_back(LPI);
278 // If this is an MSVC EH personality, we need to do a bit more work.
279 if (!Fn->hasPersonalityFn())
281 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
282 if (!isMSVCEHPersonality(Personality))
285 if (Personality == EHPersonality::MSVC_Win64SEH ||
286 Personality == EHPersonality::MSVC_X86SEH) {
287 addSEHHandlersForLPads(LPads);
290 // Calculate state numbers if we haven't already.
291 WinEHFuncInfo &EHInfo = MMI.getWinEHFuncInfo(&fn);
292 if (Personality == EHPersonality::MSVC_CXX) {
293 const Function *WinEHParentFn = MMI.getWinEHParent(&fn);
294 calculateWinCXXEHStateNumbers(WinEHParentFn, EHInfo);
296 const Function *WinEHParentFn = MMI.getWinEHParent(&fn);
297 calculateSEHStateNumbers(WinEHParentFn, EHInfo);
300 // Map all BB references in the EH data to MBBs.
301 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap)
302 for (WinEHHandlerType &H : TBME.HandlerArray)
304 dyn_cast<BasicBlock>(H.Handler.get<const Value *>()))
305 H.Handler = MBBMap[BB];
306 for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
307 const BasicBlock *BB = UME.Handler.get<const BasicBlock *>();
308 UME.Handler = MBBMap[BB];
310 // If there's an explicit EH registration node on the stack, record its
312 if (EHInfo.EHRegNode && EHInfo.EHRegNode->getParent()->getParent() == Fn) {
313 assert(StaticAllocaMap.count(EHInfo.EHRegNode));
314 EHInfo.EHRegNodeFrameIndex = StaticAllocaMap[EHInfo.EHRegNode];
317 // Copy the state numbers to LandingPadInfo for the current function, which
318 // could be a handler or the parent. This should happen for 32-bit SEH and
320 if (Personality == EHPersonality::MSVC_CXX ||
321 Personality == EHPersonality::MSVC_X86SEH) {
322 for (const LandingPadInst *LP : LPads) {
323 MachineBasicBlock *LPadMBB = MBBMap[LP->getParent()];
324 MMI.addWinEHState(LPadMBB, EHInfo.EHPadStateMap[LP]);
329 void FunctionLoweringInfo::addSEHHandlersForLPads(
330 ArrayRef<const LandingPadInst *> LPads) {
331 MachineModuleInfo &MMI = MF->getMMI();
333 // Iterate over all landing pads with llvm.eh.actions calls.
334 for (const LandingPadInst *LP : LPads) {
335 const IntrinsicInst *ActionsCall =
336 dyn_cast<IntrinsicInst>(LP->getNextNode());
338 ActionsCall->getIntrinsicID() != Intrinsic::eh_actions)
341 // Parse the llvm.eh.actions call we found.
342 MachineBasicBlock *LPadMBB = MBBMap[LP->getParent()];
343 SmallVector<std::unique_ptr<ActionHandler>, 4> Actions;
344 parseEHActions(ActionsCall, Actions);
346 // Iterate EH actions from most to least precedence, which means
347 // iterating in reverse.
348 for (auto I = Actions.rbegin(), E = Actions.rend(); I != E; ++I) {
349 ActionHandler *Action = I->get();
350 if (auto *CH = dyn_cast<CatchHandler>(Action)) {
352 dyn_cast<Function>(CH->getSelector()->stripPointerCasts());
353 assert((Filter || CH->getSelector()->isNullValue()) &&
354 "expected function or catch-all");
355 const auto *RecoverBA =
356 cast<BlockAddress>(CH->getHandlerBlockOrFunc());
357 MMI.addSEHCatchHandler(LPadMBB, Filter, RecoverBA);
359 assert(isa<CleanupHandler>(Action));
360 const auto *Fini = cast<Function>(Action->getHandlerBlockOrFunc());
361 MMI.addSEHCleanupHandler(LPadMBB, Fini);
367 /// clear - Clear out all the function-specific state. This returns this
368 /// FunctionLoweringInfo to an empty state, ready to be used for a
369 /// different function.
370 void FunctionLoweringInfo::clear() {
371 assert(CatchInfoFound.size() == CatchInfoLost.size() &&
372 "Not all catch info was assigned to a landing pad!");
376 StaticAllocaMap.clear();
378 CatchInfoLost.clear();
379 CatchInfoFound.clear();
381 LiveOutRegInfo.clear();
383 ArgDbgValues.clear();
384 ByValArgFrameIndexMap.clear();
386 StatepointStackSlots.clear();
387 StatepointRelocatedValues.clear();
388 PreferredExtendType.clear();
391 /// CreateReg - Allocate a single virtual register for the given type.
392 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
393 return RegInfo->createVirtualRegister(
394 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
397 /// CreateRegs - Allocate the appropriate number of virtual registers of
398 /// the correctly promoted or expanded types. Assign these registers
399 /// consecutive vreg numbers and return the first assigned number.
401 /// In the case that the given value has struct or array type, this function
402 /// will assign registers for each member or element.
404 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
405 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
407 SmallVector<EVT, 4> ValueVTs;
408 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
410 unsigned FirstReg = 0;
411 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
412 EVT ValueVT = ValueVTs[Value];
413 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
415 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
416 for (unsigned i = 0; i != NumRegs; ++i) {
417 unsigned R = CreateReg(RegisterVT);
418 if (!FirstReg) FirstReg = R;
424 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
425 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
426 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
427 /// the larger bit width by zero extension. The bit width must be no smaller
428 /// than the LiveOutInfo's existing bit width.
429 const FunctionLoweringInfo::LiveOutInfo *
430 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
431 if (!LiveOutRegInfo.inBounds(Reg))
434 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
438 if (BitWidth > LOI->KnownZero.getBitWidth()) {
439 LOI->NumSignBits = 1;
440 LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
441 LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
447 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
448 /// register based on the LiveOutInfo of its operands.
449 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
450 Type *Ty = PN->getType();
451 if (!Ty->isIntegerTy() || Ty->isVectorTy())
454 SmallVector<EVT, 1> ValueVTs;
455 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
456 assert(ValueVTs.size() == 1 &&
457 "PHIs with non-vector integer types should have a single VT.");
458 EVT IntVT = ValueVTs[0];
460 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
462 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
463 unsigned BitWidth = IntVT.getSizeInBits();
465 unsigned DestReg = ValueMap[PN];
466 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
468 LiveOutRegInfo.grow(DestReg);
469 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
471 Value *V = PN->getIncomingValue(0);
472 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
473 DestLOI.NumSignBits = 1;
474 APInt Zero(BitWidth, 0);
475 DestLOI.KnownZero = Zero;
476 DestLOI.KnownOne = Zero;
480 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
481 APInt Val = CI->getValue().zextOrTrunc(BitWidth);
482 DestLOI.NumSignBits = Val.getNumSignBits();
483 DestLOI.KnownZero = ~Val;
484 DestLOI.KnownOne = Val;
486 assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
487 "CopyToReg node was created.");
488 unsigned SrcReg = ValueMap[V];
489 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
490 DestLOI.IsValid = false;
493 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
495 DestLOI.IsValid = false;
501 assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
502 DestLOI.KnownOne.getBitWidth() == BitWidth &&
503 "Masks should have the same bit width as the type.");
505 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
506 Value *V = PN->getIncomingValue(i);
507 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
508 DestLOI.NumSignBits = 1;
509 APInt Zero(BitWidth, 0);
510 DestLOI.KnownZero = Zero;
511 DestLOI.KnownOne = Zero;
515 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
516 APInt Val = CI->getValue().zextOrTrunc(BitWidth);
517 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
518 DestLOI.KnownZero &= ~Val;
519 DestLOI.KnownOne &= Val;
523 assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
524 "its CopyToReg node was created.");
525 unsigned SrcReg = ValueMap[V];
526 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
527 DestLOI.IsValid = false;
530 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
532 DestLOI.IsValid = false;
535 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
536 DestLOI.KnownZero &= SrcLOI->KnownZero;
537 DestLOI.KnownOne &= SrcLOI->KnownOne;
541 /// setArgumentFrameIndex - Record frame index for the byval
542 /// argument. This overrides previous frame index entry for this argument,
544 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
546 ByValArgFrameIndexMap[A] = FI;
549 /// getArgumentFrameIndex - Get frame index for the byval argument.
550 /// If the argument does not have any assigned frame index then 0 is
552 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
553 DenseMap<const Argument *, int>::iterator I =
554 ByValArgFrameIndexMap.find(A);
555 if (I != ByValArgFrameIndexMap.end())
557 DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
561 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
562 /// being passed to this variadic function, and set the MachineModuleInfo's
563 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
564 /// reference to _fltused on Windows, which will link in MSVCRT's
565 /// floating-point support.
566 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
567 MachineModuleInfo *MMI)
569 FunctionType *FT = cast<FunctionType>(
570 I.getCalledValue()->getType()->getContainedType(0));
571 if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
572 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
573 Type* T = I.getArgOperand(i)->getType();
574 for (auto i : post_order(T)) {
575 if (i->isFloatingPointTy()) {
576 MMI->setUsesVAFloatArgument(true);
584 /// AddLandingPadInfo - Extract the exception handling information from the
585 /// landingpad instruction and add them to the specified machine module info.
586 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
587 MachineBasicBlock *MBB) {
588 if (const auto *PF = dyn_cast<Function>(
589 I.getParent()->getParent()->getPersonalityFn()->stripPointerCasts()))
590 MMI.addPersonality(PF);
595 // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
596 // but we need to do it this way because of how the DWARF EH emitter
597 // processes the clauses.
598 for (unsigned i = I.getNumClauses(); i != 0; --i) {
599 Value *Val = I.getClause(i - 1);
600 if (I.isCatch(i - 1)) {
601 MMI.addCatchTypeInfo(MBB,
602 dyn_cast<GlobalValue>(Val->stripPointerCasts()));
604 // Add filters in a list.
605 Constant *CVal = cast<Constant>(Val);
606 SmallVector<const GlobalValue*, 4> FilterList;
607 for (User::op_iterator
608 II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
609 FilterList.push_back(cast<GlobalValue>((*II)->stripPointerCasts()));
611 MMI.addFilterTypeInfo(MBB, FilterList);