1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "SelectionDAGBuild.h"
59 unsigned FastISel::getRegForValue(Value *V) {
60 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
62 // Ignore illegal types. We must do this before looking up the value
63 // in ValueMap because Arguments are given virtual registers regardless
64 // of whether FastISel can handle them.
65 if (!TLI.isTypeLegal(VT)) {
66 // Promote MVT::i1 to a legal type though, because it's common and easy.
68 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
73 // Look up the value to see if we already have a register for it. We
74 // cache values defined by Instructions across blocks, and other values
75 // only locally. This is because Instructions already have the SSA
76 // def-dominatess-use requirement enforced.
77 if (ValueMap.count(V))
79 unsigned Reg = LocalValueMap[V];
83 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
84 if (CI->getValue().getActiveBits() <= 64)
85 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
86 } else if (isa<AllocaInst>(V)) {
87 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
88 } else if (isa<ConstantPointerNull>(V)) {
89 // Translate this as an integer zero so that it can be
90 // local-CSE'd with actual integer zeros.
91 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
92 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
93 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
96 const APFloat &Flt = CF->getValueAPF();
97 MVT IntVT = TLI.getPointerTy();
100 uint32_t IntBitWidth = IntVT.getSizeInBits();
102 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
103 APFloat::rmTowardZero, &isExact);
105 APInt IntVal(IntBitWidth, 2, x);
107 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
109 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
112 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
113 if (!SelectOperator(CE, CE->getOpcode())) return 0;
114 Reg = LocalValueMap[CE];
115 } else if (isa<UndefValue>(V)) {
116 Reg = createResultReg(TLI.getRegClassFor(VT));
117 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
120 // If target-independent code couldn't handle the value, give target-specific
122 if (!Reg && isa<Constant>(V))
123 Reg = TargetMaterializeConstant(cast<Constant>(V));
125 // Don't cache constant materializations in the general ValueMap.
126 // To do so would require tracking what uses they dominate.
128 LocalValueMap[V] = Reg;
132 unsigned FastISel::lookUpRegForValue(Value *V) {
133 // Look up the value to see if we already have a register for it. We
134 // cache values defined by Instructions across blocks, and other values
135 // only locally. This is because Instructions already have the SSA
136 // def-dominatess-use requirement enforced.
137 if (ValueMap.count(V))
139 return LocalValueMap[V];
142 /// UpdateValueMap - Update the value map to include the new mapping for this
143 /// instruction, or insert an extra copy to get the result in a previous
144 /// determined register.
145 /// NOTE: This is only necessary because we might select a block that uses
146 /// a value before we select the block that defines the value. It might be
147 /// possible to fix this by selecting blocks in reverse postorder.
148 void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
149 if (!isa<Instruction>(I)) {
150 LocalValueMap[I] = Reg;
153 if (!ValueMap.count(I))
156 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
157 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
160 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
161 unsigned IdxN = getRegForValue(Idx);
163 // Unhandled operand. Halt "fast" selection and bail.
166 // If the index is smaller or larger than intptr_t, truncate or extend it.
167 MVT PtrVT = TLI.getPointerTy();
168 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
169 if (IdxVT.bitsLT(PtrVT))
170 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
171 ISD::SIGN_EXTEND, IdxN);
172 else if (IdxVT.bitsGT(PtrVT))
173 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
174 ISD::TRUNCATE, IdxN);
178 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
179 /// which has an opcode which directly corresponds to the given ISD opcode.
181 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
182 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
183 if (VT == MVT::Other || !VT.isSimple())
184 // Unhandled type. Halt "fast" selection and bail.
187 // We only handle legal types. For example, on x86-32 the instruction
188 // selector contains all of the 64-bit instructions from x86-64,
189 // under the assumption that i64 won't be used if the target doesn't
191 if (!TLI.isTypeLegal(VT)) {
192 // MVT::i1 is special. Allow AND, OR, or XOR because they
193 // don't require additional zeroing, which makes them easy.
195 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
196 ISDOpcode == ISD::XOR))
197 VT = TLI.getTypeToTransformTo(VT);
202 unsigned Op0 = getRegForValue(I->getOperand(0));
204 // Unhandled operand. Halt "fast" selection and bail.
207 // Check if the second operand is a constant and handle it appropriately.
208 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
209 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
210 ISDOpcode, Op0, CI->getZExtValue());
211 if (ResultReg != 0) {
212 // We successfully emitted code for the given LLVM Instruction.
213 UpdateValueMap(I, ResultReg);
218 // Check if the second operand is a constant float.
219 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
220 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
222 if (ResultReg != 0) {
223 // We successfully emitted code for the given LLVM Instruction.
224 UpdateValueMap(I, ResultReg);
229 unsigned Op1 = getRegForValue(I->getOperand(1));
231 // Unhandled operand. Halt "fast" selection and bail.
234 // Now we have both operands in registers. Emit the instruction.
235 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
236 ISDOpcode, Op0, Op1);
238 // Target-specific code wasn't able to find a machine opcode for
239 // the given ISD opcode and type. Halt "fast" selection and bail.
242 // We successfully emitted code for the given LLVM Instruction.
243 UpdateValueMap(I, ResultReg);
247 bool FastISel::SelectGetElementPtr(User *I) {
248 unsigned N = getRegForValue(I->getOperand(0));
250 // Unhandled operand. Halt "fast" selection and bail.
253 const Type *Ty = I->getOperand(0)->getType();
254 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
255 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
258 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
259 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
262 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
263 // FIXME: This can be optimized by combining the add with a
265 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
267 // Unhandled operand. Halt "fast" selection and bail.
270 Ty = StTy->getElementType(Field);
272 Ty = cast<SequentialType>(Ty)->getElementType();
274 // If this is a constant subscript, handle it quickly.
275 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
276 if (CI->getZExtValue() == 0) continue;
278 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
279 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
281 // Unhandled operand. Halt "fast" selection and bail.
286 // N = N + Idx * ElementSize;
287 uint64_t ElementSize = TD.getTypePaddedSize(Ty);
288 unsigned IdxN = getRegForGEPIndex(Idx);
290 // Unhandled operand. Halt "fast" selection and bail.
293 if (ElementSize != 1) {
294 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
296 // Unhandled operand. Halt "fast" selection and bail.
299 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
301 // Unhandled operand. Halt "fast" selection and bail.
306 // We successfully emitted code for the given LLVM Instruction.
307 UpdateValueMap(I, N);
311 bool FastISel::SelectCall(User *I) {
312 Function *F = cast<CallInst>(I)->getCalledFunction();
313 if (!F) return false;
315 unsigned IID = F->getIntrinsicID();
318 case Intrinsic::dbg_stoppoint: {
319 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
320 if (DW && DW->ValidDebugInfo(SPI->getContext())) {
321 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
322 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
324 unsigned Line = SPI->getLine();
325 unsigned Col = SPI->getColumn();
326 unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col);
327 setCurDebugLoc(DebugLoc::get(Idx));
331 case Intrinsic::dbg_region_start: {
332 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
333 if (DW && DW->ValidDebugInfo(RSI->getContext()))
334 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
337 case Intrinsic::dbg_region_end: {
338 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
339 if (DW && DW->ValidDebugInfo(REI->getContext()))
340 DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
343 case Intrinsic::dbg_func_start: {
344 if (!DW) return true;
345 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
346 Value *SP = FSI->getSubprogram();
348 if (DW->ValidDebugInfo(SP)) {
349 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
350 // (most?) gdb expects.
351 DISubprogram Subprogram(cast<GlobalVariable>(SP));
352 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
353 unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(),
354 CompileUnit.getFilename());
356 // Record the source line but does not create a label for the normal
357 // function start. It will be emitted at asm emission time. However,
358 // create a label if this is a beginning of inlined function.
359 unsigned Line = Subprogram.getLineNumber();
360 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
365 case Intrinsic::dbg_declare:
366 // FIXME: Do something correct here when declare stuff is working again.
368 case Intrinsic::eh_exception: {
369 MVT VT = TLI.getValueType(I->getType());
370 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
372 case TargetLowering::Expand: {
373 if (!MBB->isLandingPad()) {
374 // FIXME: Mark exception register as live in. Hack for PR1508.
375 unsigned Reg = TLI.getExceptionAddressRegister();
376 if (Reg) MBB->addLiveIn(Reg);
378 unsigned Reg = TLI.getExceptionAddressRegister();
379 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
380 unsigned ResultReg = createResultReg(RC);
381 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
383 assert(InsertedCopy && "Can't copy address registers!");
384 InsertedCopy = InsertedCopy;
385 UpdateValueMap(I, ResultReg);
391 case Intrinsic::eh_selector_i32:
392 case Intrinsic::eh_selector_i64: {
393 MVT VT = TLI.getValueType(I->getType());
394 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
396 case TargetLowering::Expand: {
397 MVT VT = (IID == Intrinsic::eh_selector_i32 ?
398 MVT::i32 : MVT::i64);
401 if (MBB->isLandingPad())
402 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
405 CatchInfoLost.insert(cast<CallInst>(I));
407 // FIXME: Mark exception selector register as live in. Hack for PR1508.
408 unsigned Reg = TLI.getExceptionSelectorRegister();
409 if (Reg) MBB->addLiveIn(Reg);
412 unsigned Reg = TLI.getExceptionSelectorRegister();
413 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
414 unsigned ResultReg = createResultReg(RC);
415 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
417 assert(InsertedCopy && "Can't copy address registers!");
418 InsertedCopy = InsertedCopy;
419 UpdateValueMap(I, ResultReg);
422 getRegForValue(Constant::getNullValue(I->getType()));
423 UpdateValueMap(I, ResultReg);
434 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
435 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
436 MVT DstVT = TLI.getValueType(I->getType());
438 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
439 DstVT == MVT::Other || !DstVT.isSimple() ||
440 !TLI.isTypeLegal(DstVT))
441 // Unhandled type. Halt "fast" selection and bail.
444 // Check if the source operand is legal. Or as a special case,
445 // it may be i1 if we're doing zero-extension because that's
446 // trivially easy and somewhat common.
447 if (!TLI.isTypeLegal(SrcVT)) {
448 if (SrcVT == MVT::i1 && Opcode == ISD::ZERO_EXTEND)
449 SrcVT = TLI.getTypeToTransformTo(SrcVT);
451 // Unhandled type. Halt "fast" selection and bail.
455 unsigned InputReg = getRegForValue(I->getOperand(0));
457 // Unhandled operand. Halt "fast" selection and bail.
460 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
467 UpdateValueMap(I, ResultReg);
471 bool FastISel::SelectBitCast(User *I) {
472 // If the bitcast doesn't change the type, just use the operand value.
473 if (I->getType() == I->getOperand(0)->getType()) {
474 unsigned Reg = getRegForValue(I->getOperand(0));
477 UpdateValueMap(I, Reg);
481 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
482 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
483 MVT DstVT = TLI.getValueType(I->getType());
485 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
486 DstVT == MVT::Other || !DstVT.isSimple() ||
487 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
488 // Unhandled type. Halt "fast" selection and bail.
491 unsigned Op0 = getRegForValue(I->getOperand(0));
493 // Unhandled operand. Halt "fast" selection and bail.
496 // First, try to perform the bitcast by inserting a reg-reg copy.
497 unsigned ResultReg = 0;
498 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
499 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
500 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
501 ResultReg = createResultReg(DstClass);
503 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
504 Op0, DstClass, SrcClass);
509 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
511 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
512 ISD::BIT_CONVERT, Op0);
517 UpdateValueMap(I, ResultReg);
522 FastISel::SelectInstruction(Instruction *I) {
523 return SelectOperator(I, I->getOpcode());
526 /// FastEmitBranch - Emit an unconditional branch to the given block,
527 /// unless it is the immediate (fall-through) successor, and update
530 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
531 MachineFunction::iterator NextMBB =
532 next(MachineFunction::iterator(MBB));
534 if (MBB->isLayoutSuccessor(MSucc)) {
535 // The unconditional fall-through case, which needs no instructions.
537 // The unconditional branch case.
538 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
540 MBB->addSuccessor(MSucc);
544 FastISel::SelectOperator(User *I, unsigned Opcode) {
546 case Instruction::Add: {
547 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
548 return SelectBinaryOp(I, Opc);
550 case Instruction::Sub: {
551 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
552 return SelectBinaryOp(I, Opc);
554 case Instruction::Mul: {
555 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
556 return SelectBinaryOp(I, Opc);
558 case Instruction::SDiv:
559 return SelectBinaryOp(I, ISD::SDIV);
560 case Instruction::UDiv:
561 return SelectBinaryOp(I, ISD::UDIV);
562 case Instruction::FDiv:
563 return SelectBinaryOp(I, ISD::FDIV);
564 case Instruction::SRem:
565 return SelectBinaryOp(I, ISD::SREM);
566 case Instruction::URem:
567 return SelectBinaryOp(I, ISD::UREM);
568 case Instruction::FRem:
569 return SelectBinaryOp(I, ISD::FREM);
570 case Instruction::Shl:
571 return SelectBinaryOp(I, ISD::SHL);
572 case Instruction::LShr:
573 return SelectBinaryOp(I, ISD::SRL);
574 case Instruction::AShr:
575 return SelectBinaryOp(I, ISD::SRA);
576 case Instruction::And:
577 return SelectBinaryOp(I, ISD::AND);
578 case Instruction::Or:
579 return SelectBinaryOp(I, ISD::OR);
580 case Instruction::Xor:
581 return SelectBinaryOp(I, ISD::XOR);
583 case Instruction::GetElementPtr:
584 return SelectGetElementPtr(I);
586 case Instruction::Br: {
587 BranchInst *BI = cast<BranchInst>(I);
589 if (BI->isUnconditional()) {
590 BasicBlock *LLVMSucc = BI->getSuccessor(0);
591 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
592 FastEmitBranch(MSucc);
596 // Conditional branches are not handed yet.
597 // Halt "fast" selection and bail.
601 case Instruction::Unreachable:
605 case Instruction::PHI:
606 // PHI nodes are already emitted.
609 case Instruction::Alloca:
610 // FunctionLowering has the static-sized case covered.
611 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
614 // Dynamic-sized alloca is not handled yet.
617 case Instruction::Call:
618 return SelectCall(I);
620 case Instruction::BitCast:
621 return SelectBitCast(I);
623 case Instruction::FPToSI:
624 return SelectCast(I, ISD::FP_TO_SINT);
625 case Instruction::ZExt:
626 return SelectCast(I, ISD::ZERO_EXTEND);
627 case Instruction::SExt:
628 return SelectCast(I, ISD::SIGN_EXTEND);
629 case Instruction::Trunc:
630 return SelectCast(I, ISD::TRUNCATE);
631 case Instruction::SIToFP:
632 return SelectCast(I, ISD::SINT_TO_FP);
634 case Instruction::IntToPtr: // Deliberate fall-through.
635 case Instruction::PtrToInt: {
636 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
637 MVT DstVT = TLI.getValueType(I->getType());
638 if (DstVT.bitsGT(SrcVT))
639 return SelectCast(I, ISD::ZERO_EXTEND);
640 if (DstVT.bitsLT(SrcVT))
641 return SelectCast(I, ISD::TRUNCATE);
642 unsigned Reg = getRegForValue(I->getOperand(0));
643 if (Reg == 0) return false;
644 UpdateValueMap(I, Reg);
649 // Unhandled instruction. Halt "fast" selection and bail.
654 FastISel::FastISel(MachineFunction &mf,
655 MachineModuleInfo *mmi,
657 DenseMap<const Value *, unsigned> &vm,
658 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
659 DenseMap<const AllocaInst *, int> &am
661 , SmallSet<Instruction*, 8> &cil
674 MRI(MF.getRegInfo()),
675 MFI(*MF.getFrameInfo()),
676 MCP(*MF.getConstantPool()),
678 TD(*TM.getTargetData()),
679 TII(*TM.getInstrInfo()),
680 TLI(*TM.getTargetLowering()) {
683 FastISel::~FastISel() {}
685 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
690 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
691 ISD::NodeType, unsigned /*Op0*/) {
695 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
696 ISD::NodeType, unsigned /*Op0*/,
701 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
702 ISD::NodeType, uint64_t /*Imm*/) {
706 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
707 ISD::NodeType, ConstantFP * /*FPImm*/) {
711 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
712 ISD::NodeType, unsigned /*Op0*/,
717 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
718 ISD::NodeType, unsigned /*Op0*/,
719 ConstantFP * /*FPImm*/) {
723 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
725 unsigned /*Op0*/, unsigned /*Op1*/,
730 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
731 /// to emit an instruction with an immediate operand using FastEmit_ri.
732 /// If that fails, it materializes the immediate into a register and try
733 /// FastEmit_rr instead.
734 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
735 unsigned Op0, uint64_t Imm,
736 MVT::SimpleValueType ImmType) {
737 // First check if immediate type is legal. If not, we can't use the ri form.
738 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
741 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
742 if (MaterialReg == 0)
744 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
747 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
748 /// to emit an instruction with a floating-point immediate operand using
749 /// FastEmit_rf. If that fails, it materializes the immediate into a register
750 /// and try FastEmit_rr instead.
751 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
752 unsigned Op0, ConstantFP *FPImm,
753 MVT::SimpleValueType ImmType) {
754 // First check if immediate type is legal. If not, we can't use the rf form.
755 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
759 // Materialize the constant in a register.
760 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
761 if (MaterialReg == 0) {
762 // If the target doesn't have a way to directly enter a floating-point
763 // value into a register, use an alternate approach.
764 // TODO: The current approach only supports floating-point constants
765 // that can be constructed by conversion from integer values. This should
766 // be replaced by code that creates a load from a constant-pool entry,
767 // which will require some target-specific work.
768 const APFloat &Flt = FPImm->getValueAPF();
769 MVT IntVT = TLI.getPointerTy();
772 uint32_t IntBitWidth = IntVT.getSizeInBits();
774 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
775 APFloat::rmTowardZero, &isExact);
778 APInt IntVal(IntBitWidth, 2, x);
780 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
781 ISD::Constant, IntVal.getZExtValue());
784 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
785 ISD::SINT_TO_FP, IntegerReg);
786 if (MaterialReg == 0)
789 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
792 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
793 return MRI.createVirtualRegister(RC);
796 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
797 const TargetRegisterClass* RC) {
798 unsigned ResultReg = createResultReg(RC);
799 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
801 BuildMI(MBB, DL, II, ResultReg);
805 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
806 const TargetRegisterClass *RC,
808 unsigned ResultReg = createResultReg(RC);
809 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
811 if (II.getNumDefs() >= 1)
812 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
814 BuildMI(MBB, DL, II).addReg(Op0);
815 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
816 II.ImplicitDefs[0], RC, RC);
824 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
825 const TargetRegisterClass *RC,
826 unsigned Op0, unsigned Op1) {
827 unsigned ResultReg = createResultReg(RC);
828 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
830 if (II.getNumDefs() >= 1)
831 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
833 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
834 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
835 II.ImplicitDefs[0], RC, RC);
842 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
843 const TargetRegisterClass *RC,
844 unsigned Op0, uint64_t Imm) {
845 unsigned ResultReg = createResultReg(RC);
846 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
848 if (II.getNumDefs() >= 1)
849 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
851 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
852 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
853 II.ImplicitDefs[0], RC, RC);
860 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
861 const TargetRegisterClass *RC,
862 unsigned Op0, ConstantFP *FPImm) {
863 unsigned ResultReg = createResultReg(RC);
864 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
866 if (II.getNumDefs() >= 1)
867 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
869 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
870 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
871 II.ImplicitDefs[0], RC, RC);
878 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
879 const TargetRegisterClass *RC,
880 unsigned Op0, unsigned Op1, uint64_t Imm) {
881 unsigned ResultReg = createResultReg(RC);
882 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
884 if (II.getNumDefs() >= 1)
885 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
887 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
888 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
889 II.ImplicitDefs[0], RC, RC);
896 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
897 const TargetRegisterClass *RC,
899 unsigned ResultReg = createResultReg(RC);
900 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
902 if (II.getNumDefs() >= 1)
903 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
905 BuildMI(MBB, DL, II).addImm(Imm);
906 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
907 II.ImplicitDefs[0], RC, RC);
914 unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
915 unsigned Op0, uint32_t Idx) {
916 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
918 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
919 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
921 if (II.getNumDefs() >= 1)
922 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
924 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
925 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
926 II.ImplicitDefs[0], RC, RC);