1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Function.h"
15 #include "llvm/GlobalVariable.h"
16 #include "llvm/Instructions.h"
17 #include "llvm/IntrinsicInst.h"
18 #include "llvm/CodeGen/FastISel.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetMachine.h"
28 unsigned FastISel::getRegForValue(Value *V) {
29 // Look up the value to see if we already have a register for it. We
30 // cache values defined by Instructions across blocks, and other values
31 // only locally. This is because Instructions already have the SSA
32 // def-dominatess-use requirement enforced.
33 if (ValueMap.count(V))
35 unsigned Reg = LocalValueMap[V];
39 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
41 // Ignore illegal types.
42 if (!TLI.isTypeLegal(VT)) {
43 // Promote MVT::i1 to a legal type though, because it's common and easy.
45 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
50 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
51 if (CI->getValue().getActiveBits() <= 64)
52 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
53 } else if (isa<AllocaInst>(V)) {
54 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
55 } else if (isa<ConstantPointerNull>(V)) {
56 Reg = FastEmit_i(VT, VT, ISD::Constant, 0);
57 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
58 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
61 const APFloat &Flt = CF->getValueAPF();
62 MVT IntVT = TLI.getPointerTy();
65 uint32_t IntBitWidth = IntVT.getSizeInBits();
66 if (!Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
67 APFloat::rmTowardZero) != APFloat::opOK) {
68 APInt IntVal(IntBitWidth, 2, x);
70 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
71 ISD::Constant, IntVal.getZExtValue());
73 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
76 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
77 if (!SelectOperator(CE, CE->getOpcode())) return 0;
78 Reg = LocalValueMap[CE];
79 } else if (isa<UndefValue>(V)) {
80 Reg = createResultReg(TLI.getRegClassFor(VT));
81 BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
84 // If target-independent code couldn't handle the value, give target-specific
86 if (!Reg && isa<Constant>(V))
87 Reg = TargetMaterializeConstant(cast<Constant>(V));
89 // Don't cache constant materializations in the general ValueMap.
90 // To do so would require tracking what uses they dominate.
92 LocalValueMap[V] = Reg;
96 unsigned FastISel::lookUpRegForValue(Value *V) {
97 // Look up the value to see if we already have a register for it. We
98 // cache values defined by Instructions across blocks, and other values
99 // only locally. This is because Instructions already have the SSA
100 // def-dominatess-use requirement enforced.
101 if (ValueMap.count(V))
103 return LocalValueMap[V];
106 /// UpdateValueMap - Update the value map to include the new mapping for this
107 /// instruction, or insert an extra copy to get the result in a previous
108 /// determined register.
109 /// NOTE: This is only necessary because we might select a block that uses
110 /// a value before we select the block that defines the value. It might be
111 /// possible to fix this by selecting blocks in reverse postorder.
112 void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
113 if (!isa<Instruction>(I)) {
114 LocalValueMap[I] = Reg;
117 if (!ValueMap.count(I))
120 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
121 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
124 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
125 /// which has an opcode which directly corresponds to the given ISD opcode.
127 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
128 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
129 if (VT == MVT::Other || !VT.isSimple())
130 // Unhandled type. Halt "fast" selection and bail.
133 // We only handle legal types. For example, on x86-32 the instruction
134 // selector contains all of the 64-bit instructions from x86-64,
135 // under the assumption that i64 won't be used if the target doesn't
137 if (!TLI.isTypeLegal(VT)) {
138 // MVT::i1 is special. Allow AND and OR (but not XOR) because they
139 // don't require additional zeroing, which makes them easy.
141 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR))
142 VT = TLI.getTypeToTransformTo(VT);
147 unsigned Op0 = getRegForValue(I->getOperand(0));
149 // Unhandled operand. Halt "fast" selection and bail.
152 // Check if the second operand is a constant and handle it appropriately.
153 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
154 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
155 ISDOpcode, Op0, CI->getZExtValue());
156 if (ResultReg != 0) {
157 // We successfully emitted code for the given LLVM Instruction.
158 UpdateValueMap(I, ResultReg);
163 // Check if the second operand is a constant float.
164 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
165 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
167 if (ResultReg != 0) {
168 // We successfully emitted code for the given LLVM Instruction.
169 UpdateValueMap(I, ResultReg);
174 unsigned Op1 = getRegForValue(I->getOperand(1));
176 // Unhandled operand. Halt "fast" selection and bail.
179 // Now we have both operands in registers. Emit the instruction.
180 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
181 ISDOpcode, Op0, Op1);
183 // Target-specific code wasn't able to find a machine opcode for
184 // the given ISD opcode and type. Halt "fast" selection and bail.
187 // We successfully emitted code for the given LLVM Instruction.
188 UpdateValueMap(I, ResultReg);
192 bool FastISel::SelectGetElementPtr(User *I) {
193 unsigned N = getRegForValue(I->getOperand(0));
195 // Unhandled operand. Halt "fast" selection and bail.
198 const Type *Ty = I->getOperand(0)->getType();
199 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
200 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
203 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
204 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
207 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
208 // FIXME: This can be optimized by combining the add with a
210 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
212 // Unhandled operand. Halt "fast" selection and bail.
215 Ty = StTy->getElementType(Field);
217 Ty = cast<SequentialType>(Ty)->getElementType();
219 // If this is a constant subscript, handle it quickly.
220 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
221 if (CI->getZExtValue() == 0) continue;
223 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
224 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
226 // Unhandled operand. Halt "fast" selection and bail.
231 // N = N + Idx * ElementSize;
232 uint64_t ElementSize = TD.getABITypeSize(Ty);
233 unsigned IdxN = getRegForValue(Idx);
235 // Unhandled operand. Halt "fast" selection and bail.
238 // If the index is smaller or larger than intptr_t, truncate or extend
240 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
241 if (IdxVT.bitsLT(VT))
242 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
243 else if (IdxVT.bitsGT(VT))
244 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
246 // Unhandled operand. Halt "fast" selection and bail.
249 if (ElementSize != 1) {
250 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
252 // Unhandled operand. Halt "fast" selection and bail.
255 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
257 // Unhandled operand. Halt "fast" selection and bail.
262 // We successfully emitted code for the given LLVM Instruction.
263 UpdateValueMap(I, N);
267 bool FastISel::SelectCall(User *I) {
268 Function *F = cast<CallInst>(I)->getCalledFunction();
269 if (!F) return false;
271 unsigned IID = F->getIntrinsicID();
274 case Intrinsic::dbg_stoppoint: {
275 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
276 if (MMI && SPI->getContext() && MMI->Verify(SPI->getContext())) {
277 DebugInfoDesc *DD = MMI->getDescFor(SPI->getContext());
278 assert(DD && "Not a debug information descriptor");
279 const CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
280 unsigned SrcFile = MMI->RecordSource(CompileUnit);
281 unsigned Line = SPI->getLine();
282 unsigned Col = SPI->getColumn();
283 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
284 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
285 BuildMI(MBB, II).addImm(ID);
289 case Intrinsic::dbg_region_start: {
290 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
291 if (MMI && RSI->getContext() && MMI->Verify(RSI->getContext())) {
292 unsigned ID = MMI->RecordRegionStart(RSI->getContext());
293 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
294 BuildMI(MBB, II).addImm(ID);
298 case Intrinsic::dbg_region_end: {
299 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
300 if (MMI && REI->getContext() && MMI->Verify(REI->getContext())) {
301 unsigned ID = MMI->RecordRegionEnd(REI->getContext());
302 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
303 BuildMI(MBB, II).addImm(ID);
307 case Intrinsic::dbg_func_start: {
308 if (!MMI) return true;
309 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
310 Value *SP = FSI->getSubprogram();
311 if (SP && MMI->Verify(SP)) {
312 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
313 // what (most?) gdb expects.
314 DebugInfoDesc *DD = MMI->getDescFor(SP);
315 assert(DD && "Not a debug information descriptor");
316 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
317 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
318 unsigned SrcFile = MMI->RecordSource(CompileUnit);
319 // Record the source line but does create a label. It will be emitted
320 // at asm emission time.
321 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
325 case Intrinsic::dbg_declare: {
326 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
327 Value *Variable = DI->getVariable();
328 if (MMI && Variable && MMI->Verify(Variable)) {
329 // Determine the address of the declared object.
330 Value *Address = DI->getAddress();
331 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
332 Address = BCI->getOperand(0);
333 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
334 // Don't handle byval struct arguments, for example.
336 DenseMap<const AllocaInst*, int>::iterator SI =
337 StaticAllocaMap.find(AI);
338 assert(SI != StaticAllocaMap.end() && "Invalid dbg.declare!");
341 // Determine the debug globalvariable.
342 GlobalValue *GV = cast<GlobalVariable>(Variable);
344 // Build the DECLARE instruction.
345 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
346 BuildMI(MBB, II).addFrameIndex(FI).addGlobalAddress(GV);
354 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
355 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
356 MVT DstVT = TLI.getValueType(I->getType());
358 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
359 DstVT == MVT::Other || !DstVT.isSimple() ||
360 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
361 // Unhandled type. Halt "fast" selection and bail.
364 unsigned InputReg = getRegForValue(I->getOperand(0));
366 // Unhandled operand. Halt "fast" selection and bail.
369 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
376 UpdateValueMap(I, ResultReg);
380 bool FastISel::SelectBitCast(User *I) {
381 // If the bitcast doesn't change the type, just use the operand value.
382 if (I->getType() == I->getOperand(0)->getType()) {
383 unsigned Reg = getRegForValue(I->getOperand(0));
386 UpdateValueMap(I, Reg);
390 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
391 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
392 MVT DstVT = TLI.getValueType(I->getType());
394 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
395 DstVT == MVT::Other || !DstVT.isSimple() ||
396 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
397 // Unhandled type. Halt "fast" selection and bail.
400 unsigned Op0 = getRegForValue(I->getOperand(0));
402 // Unhandled operand. Halt "fast" selection and bail.
405 // First, try to perform the bitcast by inserting a reg-reg copy.
406 unsigned ResultReg = 0;
407 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
408 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
409 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
410 ResultReg = createResultReg(DstClass);
412 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
413 Op0, DstClass, SrcClass);
418 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
420 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
421 ISD::BIT_CONVERT, Op0);
426 UpdateValueMap(I, ResultReg);
431 FastISel::SelectInstruction(Instruction *I) {
432 return SelectOperator(I, I->getOpcode());
436 FastISel::SelectOperator(User *I, unsigned Opcode) {
438 case Instruction::Add: {
439 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
440 return SelectBinaryOp(I, Opc);
442 case Instruction::Sub: {
443 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
444 return SelectBinaryOp(I, Opc);
446 case Instruction::Mul: {
447 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
448 return SelectBinaryOp(I, Opc);
450 case Instruction::SDiv:
451 return SelectBinaryOp(I, ISD::SDIV);
452 case Instruction::UDiv:
453 return SelectBinaryOp(I, ISD::UDIV);
454 case Instruction::FDiv:
455 return SelectBinaryOp(I, ISD::FDIV);
456 case Instruction::SRem:
457 return SelectBinaryOp(I, ISD::SREM);
458 case Instruction::URem:
459 return SelectBinaryOp(I, ISD::UREM);
460 case Instruction::FRem:
461 return SelectBinaryOp(I, ISD::FREM);
462 case Instruction::Shl:
463 return SelectBinaryOp(I, ISD::SHL);
464 case Instruction::LShr:
465 return SelectBinaryOp(I, ISD::SRL);
466 case Instruction::AShr:
467 return SelectBinaryOp(I, ISD::SRA);
468 case Instruction::And:
469 return SelectBinaryOp(I, ISD::AND);
470 case Instruction::Or:
471 return SelectBinaryOp(I, ISD::OR);
472 case Instruction::Xor:
473 return SelectBinaryOp(I, ISD::XOR);
475 case Instruction::GetElementPtr:
476 return SelectGetElementPtr(I);
478 case Instruction::Br: {
479 BranchInst *BI = cast<BranchInst>(I);
481 if (BI->isUnconditional()) {
482 MachineFunction::iterator NextMBB =
483 next(MachineFunction::iterator(MBB));
484 BasicBlock *LLVMSucc = BI->getSuccessor(0);
485 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
487 if (NextMBB != MF.end() && MSucc == NextMBB) {
488 // The unconditional fall-through case, which needs no instructions.
490 // The unconditional branch case.
491 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
493 MBB->addSuccessor(MSucc);
497 // Conditional branches are not handed yet.
498 // Halt "fast" selection and bail.
502 case Instruction::Unreachable:
506 case Instruction::PHI:
507 // PHI nodes are already emitted.
510 case Instruction::Alloca:
511 // FunctionLowering has the static-sized case covered.
512 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
515 // Dynamic-sized alloca is not handled yet.
518 case Instruction::Call:
519 return SelectCall(I);
521 case Instruction::BitCast:
522 return SelectBitCast(I);
524 case Instruction::FPToSI:
525 return SelectCast(I, ISD::FP_TO_SINT);
526 case Instruction::ZExt:
527 return SelectCast(I, ISD::ZERO_EXTEND);
528 case Instruction::SExt:
529 return SelectCast(I, ISD::SIGN_EXTEND);
530 case Instruction::Trunc:
531 return SelectCast(I, ISD::TRUNCATE);
532 case Instruction::SIToFP:
533 return SelectCast(I, ISD::SINT_TO_FP);
535 case Instruction::IntToPtr: // Deliberate fall-through.
536 case Instruction::PtrToInt: {
537 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
538 MVT DstVT = TLI.getValueType(I->getType());
539 if (DstVT.bitsGT(SrcVT))
540 return SelectCast(I, ISD::ZERO_EXTEND);
541 if (DstVT.bitsLT(SrcVT))
542 return SelectCast(I, ISD::TRUNCATE);
543 unsigned Reg = getRegForValue(I->getOperand(0));
544 if (Reg == 0) return false;
545 UpdateValueMap(I, Reg);
550 // Unhandled instruction. Halt "fast" selection and bail.
555 FastISel::FastISel(MachineFunction &mf,
556 MachineModuleInfo *mmi,
557 DenseMap<const Value *, unsigned> &vm,
558 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
559 DenseMap<const AllocaInst *, int> &am)
566 MRI(MF.getRegInfo()),
567 MFI(*MF.getFrameInfo()),
568 MCP(*MF.getConstantPool()),
570 TD(*TM.getTargetData()),
571 TII(*TM.getInstrInfo()),
572 TLI(*TM.getTargetLowering()) {
575 FastISel::~FastISel() {}
577 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
582 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
583 ISD::NodeType, unsigned /*Op0*/) {
587 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
588 ISD::NodeType, unsigned /*Op0*/,
593 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
594 ISD::NodeType, uint64_t /*Imm*/) {
598 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
599 ISD::NodeType, ConstantFP * /*FPImm*/) {
603 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
604 ISD::NodeType, unsigned /*Op0*/,
609 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
610 ISD::NodeType, unsigned /*Op0*/,
611 ConstantFP * /*FPImm*/) {
615 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
617 unsigned /*Op0*/, unsigned /*Op1*/,
622 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
623 /// to emit an instruction with an immediate operand using FastEmit_ri.
624 /// If that fails, it materializes the immediate into a register and try
625 /// FastEmit_rr instead.
626 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
627 unsigned Op0, uint64_t Imm,
628 MVT::SimpleValueType ImmType) {
629 // First check if immediate type is legal. If not, we can't use the ri form.
630 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
633 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
634 if (MaterialReg == 0)
636 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
639 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
640 /// to emit an instruction with a floating-point immediate operand using
641 /// FastEmit_rf. If that fails, it materializes the immediate into a register
642 /// and try FastEmit_rr instead.
643 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
644 unsigned Op0, ConstantFP *FPImm,
645 MVT::SimpleValueType ImmType) {
646 // First check if immediate type is legal. If not, we can't use the rf form.
647 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
651 // Materialize the constant in a register.
652 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
653 if (MaterialReg == 0) {
654 // If the target doesn't have a way to directly enter a floating-point
655 // value into a register, use an alternate approach.
656 // TODO: The current approach only supports floating-point constants
657 // that can be constructed by conversion from integer values. This should
658 // be replaced by code that creates a load from a constant-pool entry,
659 // which will require some target-specific work.
660 const APFloat &Flt = FPImm->getValueAPF();
661 MVT IntVT = TLI.getPointerTy();
664 uint32_t IntBitWidth = IntVT.getSizeInBits();
665 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
666 APFloat::rmTowardZero) != APFloat::opOK)
668 APInt IntVal(IntBitWidth, 2, x);
670 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
671 ISD::Constant, IntVal.getZExtValue());
674 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
675 ISD::SINT_TO_FP, IntegerReg);
676 if (MaterialReg == 0)
679 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
682 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
683 return MRI.createVirtualRegister(RC);
686 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
687 const TargetRegisterClass* RC) {
688 unsigned ResultReg = createResultReg(RC);
689 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
691 BuildMI(MBB, II, ResultReg);
695 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
696 const TargetRegisterClass *RC,
698 unsigned ResultReg = createResultReg(RC);
699 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
701 if (II.getNumDefs() >= 1)
702 BuildMI(MBB, II, ResultReg).addReg(Op0);
704 BuildMI(MBB, II).addReg(Op0);
705 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
706 II.ImplicitDefs[0], RC, RC);
714 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
715 const TargetRegisterClass *RC,
716 unsigned Op0, unsigned Op1) {
717 unsigned ResultReg = createResultReg(RC);
718 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
720 if (II.getNumDefs() >= 1)
721 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
723 BuildMI(MBB, II).addReg(Op0).addReg(Op1);
724 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
725 II.ImplicitDefs[0], RC, RC);
732 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
733 const TargetRegisterClass *RC,
734 unsigned Op0, uint64_t Imm) {
735 unsigned ResultReg = createResultReg(RC);
736 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
738 if (II.getNumDefs() >= 1)
739 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
741 BuildMI(MBB, II).addReg(Op0).addImm(Imm);
742 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
743 II.ImplicitDefs[0], RC, RC);
750 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
751 const TargetRegisterClass *RC,
752 unsigned Op0, ConstantFP *FPImm) {
753 unsigned ResultReg = createResultReg(RC);
754 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
756 if (II.getNumDefs() >= 1)
757 BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
759 BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm);
760 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
761 II.ImplicitDefs[0], RC, RC);
768 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
769 const TargetRegisterClass *RC,
770 unsigned Op0, unsigned Op1, uint64_t Imm) {
771 unsigned ResultReg = createResultReg(RC);
772 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
774 if (II.getNumDefs() >= 1)
775 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
777 BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm);
778 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
779 II.ImplicitDefs[0], RC, RC);
786 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
787 const TargetRegisterClass *RC,
789 unsigned ResultReg = createResultReg(RC);
790 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
792 if (II.getNumDefs() >= 1)
793 BuildMI(MBB, II, ResultReg).addImm(Imm);
795 BuildMI(MBB, II).addImm(Imm);
796 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
797 II.ImplicitDefs[0], RC, RC);
804 unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
805 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
806 const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
808 unsigned ResultReg = createResultReg(SRC);
809 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
811 if (II.getNumDefs() >= 1)
812 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
814 BuildMI(MBB, II).addReg(Op0).addImm(Idx);
815 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
816 II.ImplicitDefs[0], RC, RC);