1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: make truncate see through SIGN_EXTEND and AND
26 // FIXME: divide by zero is currently left unfolded. do we want to turn this
28 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "dagcombine"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
51 // Worklist of all of the nodes that need to be simplified.
52 std::vector<SDNode*> WorkList;
54 /// AddUsersToWorkList - When an instruction is simplified, add all users of
55 /// the instruction to the work lists because they might get more simplified
58 void AddUsersToWorkList(SDNode *N) {
59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
61 WorkList.push_back(*UI);
64 /// removeFromWorkList - remove all instances of N from the worklist.
66 void removeFromWorkList(SDNode *N) {
67 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
72 void AddToWorkList(SDNode *N) {
73 WorkList.push_back(N);
76 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
78 DEBUG(std::cerr << "\nReplacing "; N->dump();
79 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
80 std::cerr << " and " << To.size()-1 << " other values\n");
81 std::vector<SDNode*> NowDead;
82 DAG.ReplaceAllUsesWith(N, To, &NowDead);
84 // Push the new nodes and any users onto the worklist
85 for (unsigned i = 0, e = To.size(); i != e; ++i) {
86 WorkList.push_back(To[i].Val);
87 AddUsersToWorkList(To[i].Val);
90 // Nodes can end up on the worklist more than once. Make sure we do
91 // not process a node that has been replaced.
92 removeFromWorkList(N);
93 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
94 removeFromWorkList(NowDead[i]);
96 // Finally, since the node is now dead, remove it from the graph.
98 return SDOperand(N, 0);
101 SDOperand CombineTo(SDNode *N, SDOperand Res) {
102 std::vector<SDOperand> To;
104 return CombineTo(N, To);
107 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
108 std::vector<SDOperand> To;
111 return CombineTo(N, To);
115 /// SimplifyDemandedBits - Check the specified integer node value to see if
116 /// it can be simplified or if things it uses can be simplified by bit
117 /// propagation. If so, return true.
118 bool SimplifyDemandedBits(SDOperand Op) {
119 TargetLowering::TargetLoweringOpt TLO(DAG);
120 uint64_t KnownZero, KnownOne;
121 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
122 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
126 WorkList.push_back(Op.Val);
128 // Replace the old value with the new one.
130 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
131 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG));
133 std::vector<SDNode*> NowDead;
134 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
136 // Push the new node and any (possibly new) users onto the worklist.
137 WorkList.push_back(TLO.New.Val);
138 AddUsersToWorkList(TLO.New.Val);
140 // Nodes can end up on the worklist more than once. Make sure we do
141 // not process a node that has been replaced.
142 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
143 removeFromWorkList(NowDead[i]);
145 // Finally, if the node is now dead, remove it from the graph. The node
146 // may not be dead if the replacement process recursively simplified to
147 // something else needing this node.
148 if (TLO.Old.Val->use_empty()) {
149 removeFromWorkList(TLO.Old.Val);
150 DAG.DeleteNode(TLO.Old.Val);
155 /// visit - call the node-specific routine that knows how to fold each
156 /// particular type of node.
157 SDOperand visit(SDNode *N);
159 // Visitation implementation - Implement dag node combining for different
160 // node types. The semantics are as follows:
162 // SDOperand.Val == 0 - No change was made
163 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
164 // otherwise - N should be replaced by the returned Operand.
166 SDOperand visitTokenFactor(SDNode *N);
167 SDOperand visitADD(SDNode *N);
168 SDOperand visitSUB(SDNode *N);
169 SDOperand visitMUL(SDNode *N);
170 SDOperand visitSDIV(SDNode *N);
171 SDOperand visitUDIV(SDNode *N);
172 SDOperand visitSREM(SDNode *N);
173 SDOperand visitUREM(SDNode *N);
174 SDOperand visitMULHU(SDNode *N);
175 SDOperand visitMULHS(SDNode *N);
176 SDOperand visitAND(SDNode *N);
177 SDOperand visitOR(SDNode *N);
178 SDOperand visitXOR(SDNode *N);
179 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
180 SDOperand visitSHL(SDNode *N);
181 SDOperand visitSRA(SDNode *N);
182 SDOperand visitSRL(SDNode *N);
183 SDOperand visitCTLZ(SDNode *N);
184 SDOperand visitCTTZ(SDNode *N);
185 SDOperand visitCTPOP(SDNode *N);
186 SDOperand visitSELECT(SDNode *N);
187 SDOperand visitSELECT_CC(SDNode *N);
188 SDOperand visitSETCC(SDNode *N);
189 SDOperand visitSIGN_EXTEND(SDNode *N);
190 SDOperand visitZERO_EXTEND(SDNode *N);
191 SDOperand visitANY_EXTEND(SDNode *N);
192 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
193 SDOperand visitTRUNCATE(SDNode *N);
194 SDOperand visitBIT_CONVERT(SDNode *N);
195 SDOperand visitVBIT_CONVERT(SDNode *N);
196 SDOperand visitFADD(SDNode *N);
197 SDOperand visitFSUB(SDNode *N);
198 SDOperand visitFMUL(SDNode *N);
199 SDOperand visitFDIV(SDNode *N);
200 SDOperand visitFREM(SDNode *N);
201 SDOperand visitFCOPYSIGN(SDNode *N);
202 SDOperand visitSINT_TO_FP(SDNode *N);
203 SDOperand visitUINT_TO_FP(SDNode *N);
204 SDOperand visitFP_TO_SINT(SDNode *N);
205 SDOperand visitFP_TO_UINT(SDNode *N);
206 SDOperand visitFP_ROUND(SDNode *N);
207 SDOperand visitFP_ROUND_INREG(SDNode *N);
208 SDOperand visitFP_EXTEND(SDNode *N);
209 SDOperand visitFNEG(SDNode *N);
210 SDOperand visitFABS(SDNode *N);
211 SDOperand visitBRCOND(SDNode *N);
212 SDOperand visitBR_CC(SDNode *N);
213 SDOperand visitLOAD(SDNode *N);
214 SDOperand visitXEXTLOAD(SDNode *N);
215 SDOperand visitSTORE(SDNode *N);
216 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
217 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
218 SDOperand visitVBUILD_VECTOR(SDNode *N);
219 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
220 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
222 SDOperand XformToShuffleWithZero(SDNode *N);
223 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
225 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
226 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
227 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
228 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
229 SDOperand N3, ISD::CondCode CC);
230 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
231 ISD::CondCode Cond, bool foldBooleans = true);
232 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
233 SDOperand BuildSDIV(SDNode *N);
234 SDOperand BuildUDIV(SDNode *N);
236 DAGCombiner(SelectionDAG &D)
237 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
239 /// Run - runs the dag combiner on all nodes in the work list
240 void Run(bool RunningAfterLegalize);
244 //===----------------------------------------------------------------------===//
245 // TargetLowering::DAGCombinerInfo implementation
246 //===----------------------------------------------------------------------===//
248 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
249 ((DAGCombiner*)DC)->AddToWorkList(N);
252 SDOperand TargetLowering::DAGCombinerInfo::
253 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
254 return ((DAGCombiner*)DC)->CombineTo(N, To);
257 SDOperand TargetLowering::DAGCombinerInfo::
258 CombineTo(SDNode *N, SDOperand Res) {
259 return ((DAGCombiner*)DC)->CombineTo(N, Res);
263 SDOperand TargetLowering::DAGCombinerInfo::
264 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
265 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
271 //===----------------------------------------------------------------------===//
275 int64_t m; // magic number
276 int64_t s; // shift amount
280 uint64_t m; // magic number
281 int64_t a; // add indicator
282 int64_t s; // shift amount
285 /// magic - calculate the magic numbers required to codegen an integer sdiv as
286 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
288 static ms magic32(int32_t d) {
290 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
291 const uint32_t two31 = 0x80000000U;
295 t = two31 + ((uint32_t)d >> 31);
296 anc = t - 1 - t%ad; // absolute value of nc
297 p = 31; // initialize p
298 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
299 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
300 q2 = two31/ad; // initialize q2 = 2p/abs(d)
301 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
304 q1 = 2*q1; // update q1 = 2p/abs(nc)
305 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
306 if (r1 >= anc) { // must be unsigned comparison
310 q2 = 2*q2; // update q2 = 2p/abs(d)
311 r2 = 2*r2; // update r2 = rem(2p/abs(d))
312 if (r2 >= ad) { // must be unsigned comparison
317 } while (q1 < delta || (q1 == delta && r1 == 0));
319 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
320 if (d < 0) mag.m = -mag.m; // resulting magic number
321 mag.s = p - 32; // resulting shift
325 /// magicu - calculate the magic numbers required to codegen an integer udiv as
326 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
327 static mu magicu32(uint32_t d) {
329 uint32_t nc, delta, q1, r1, q2, r2;
331 magu.a = 0; // initialize "add" indicator
333 p = 31; // initialize p
334 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
335 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
336 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
337 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
340 if (r1 >= nc - r1 ) {
341 q1 = 2*q1 + 1; // update q1
342 r1 = 2*r1 - nc; // update r1
345 q1 = 2*q1; // update q1
346 r1 = 2*r1; // update r1
348 if (r2 + 1 >= d - r2) {
349 if (q2 >= 0x7FFFFFFF) magu.a = 1;
350 q2 = 2*q2 + 1; // update q2
351 r2 = 2*r2 + 1 - d; // update r2
354 if (q2 >= 0x80000000) magu.a = 1;
355 q2 = 2*q2; // update q2
356 r2 = 2*r2 + 1; // update r2
359 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
360 magu.m = q2 + 1; // resulting magic number
361 magu.s = p - 32; // resulting shift
365 /// magic - calculate the magic numbers required to codegen an integer sdiv as
366 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
368 static ms magic64(int64_t d) {
370 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
371 const uint64_t two63 = 9223372036854775808ULL; // 2^63
374 ad = d >= 0 ? d : -d;
375 t = two63 + ((uint64_t)d >> 63);
376 anc = t - 1 - t%ad; // absolute value of nc
377 p = 63; // initialize p
378 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
379 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
380 q2 = two63/ad; // initialize q2 = 2p/abs(d)
381 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
384 q1 = 2*q1; // update q1 = 2p/abs(nc)
385 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
386 if (r1 >= anc) { // must be unsigned comparison
390 q2 = 2*q2; // update q2 = 2p/abs(d)
391 r2 = 2*r2; // update r2 = rem(2p/abs(d))
392 if (r2 >= ad) { // must be unsigned comparison
397 } while (q1 < delta || (q1 == delta && r1 == 0));
400 if (d < 0) mag.m = -mag.m; // resulting magic number
401 mag.s = p - 64; // resulting shift
405 /// magicu - calculate the magic numbers required to codegen an integer udiv as
406 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
407 static mu magicu64(uint64_t d)
410 uint64_t nc, delta, q1, r1, q2, r2;
412 magu.a = 0; // initialize "add" indicator
414 p = 63; // initialize p
415 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
416 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
417 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
418 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
421 if (r1 >= nc - r1 ) {
422 q1 = 2*q1 + 1; // update q1
423 r1 = 2*r1 - nc; // update r1
426 q1 = 2*q1; // update q1
427 r1 = 2*r1; // update r1
429 if (r2 + 1 >= d - r2) {
430 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
431 q2 = 2*q2 + 1; // update q2
432 r2 = 2*r2 + 1 - d; // update r2
435 if (q2 >= 0x8000000000000000ull) magu.a = 1;
436 q2 = 2*q2; // update q2
437 r2 = 2*r2 + 1; // update r2
440 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
441 magu.m = q2 + 1; // resulting magic number
442 magu.s = p - 64; // resulting shift
446 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
447 // that selects between the values 1 and 0, making it equivalent to a setcc.
448 // Also, set the incoming LHS, RHS, and CC references to the appropriate
449 // nodes based on the type of node we are checking. This simplifies life a
450 // bit for the callers.
451 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
453 if (N.getOpcode() == ISD::SETCC) {
454 LHS = N.getOperand(0);
455 RHS = N.getOperand(1);
456 CC = N.getOperand(2);
459 if (N.getOpcode() == ISD::SELECT_CC &&
460 N.getOperand(2).getOpcode() == ISD::Constant &&
461 N.getOperand(3).getOpcode() == ISD::Constant &&
462 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
463 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
464 LHS = N.getOperand(0);
465 RHS = N.getOperand(1);
466 CC = N.getOperand(4);
472 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
473 // one use. If this is true, it allows the users to invert the operation for
474 // free when it is profitable to do so.
475 static bool isOneUseSetCC(SDOperand N) {
476 SDOperand N0, N1, N2;
477 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
482 // FIXME: This should probably go in the ISD class rather than being duplicated
484 static bool isCommutativeBinOp(unsigned Opcode) {
490 case ISD::XOR: return true;
491 default: return false; // FIXME: Need commutative info for user ops!
495 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
496 MVT::ValueType VT = N0.getValueType();
497 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
498 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
499 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
500 if (isa<ConstantSDNode>(N1)) {
501 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
502 AddToWorkList(OpNode.Val);
503 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
504 } else if (N0.hasOneUse()) {
505 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
506 AddToWorkList(OpNode.Val);
507 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
510 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
511 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
512 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
513 if (isa<ConstantSDNode>(N0)) {
514 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
515 AddToWorkList(OpNode.Val);
516 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
517 } else if (N1.hasOneUse()) {
518 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
519 AddToWorkList(OpNode.Val);
520 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
526 void DAGCombiner::Run(bool RunningAfterLegalize) {
527 // set the instance variable, so that the various visit routines may use it.
528 AfterLegalize = RunningAfterLegalize;
530 // Add all the dag nodes to the worklist.
531 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
532 E = DAG.allnodes_end(); I != E; ++I)
533 WorkList.push_back(I);
535 // Create a dummy node (which is not added to allnodes), that adds a reference
536 // to the root node, preventing it from being deleted, and tracking any
537 // changes of the root.
538 HandleSDNode Dummy(DAG.getRoot());
541 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
542 TargetLowering::DAGCombinerInfo
543 DagCombineInfo(DAG, !RunningAfterLegalize, this);
545 // while the worklist isn't empty, inspect the node on the end of it and
546 // try and combine it.
547 while (!WorkList.empty()) {
548 SDNode *N = WorkList.back();
551 // If N has no uses, it is dead. Make sure to revisit all N's operands once
552 // N is deleted from the DAG, since they too may now be dead or may have a
553 // reduced number of uses, allowing other xforms.
554 if (N->use_empty() && N != &Dummy) {
555 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
556 WorkList.push_back(N->getOperand(i).Val);
558 removeFromWorkList(N);
563 SDOperand RV = visit(N);
565 // If nothing happened, try a target-specific DAG combine.
567 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
568 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
569 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
574 // If we get back the same node we passed in, rather than a new node or
575 // zero, we know that the node must have defined multiple values and
576 // CombineTo was used. Since CombineTo takes care of the worklist
577 // mechanics for us, we have no work to do in this case.
579 DEBUG(std::cerr << "\nReplacing "; N->dump();
580 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
582 std::vector<SDNode*> NowDead;
583 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
585 // Push the new node and any users onto the worklist
586 WorkList.push_back(RV.Val);
587 AddUsersToWorkList(RV.Val);
589 // Nodes can end up on the worklist more than once. Make sure we do
590 // not process a node that has been replaced.
591 removeFromWorkList(N);
592 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
593 removeFromWorkList(NowDead[i]);
595 // Finally, since the node is now dead, remove it from the graph.
601 // If the root changed (e.g. it was a dead load, update the root).
602 DAG.setRoot(Dummy.getValue());
605 SDOperand DAGCombiner::visit(SDNode *N) {
606 switch(N->getOpcode()) {
608 case ISD::TokenFactor: return visitTokenFactor(N);
609 case ISD::ADD: return visitADD(N);
610 case ISD::SUB: return visitSUB(N);
611 case ISD::MUL: return visitMUL(N);
612 case ISD::SDIV: return visitSDIV(N);
613 case ISD::UDIV: return visitUDIV(N);
614 case ISD::SREM: return visitSREM(N);
615 case ISD::UREM: return visitUREM(N);
616 case ISD::MULHU: return visitMULHU(N);
617 case ISD::MULHS: return visitMULHS(N);
618 case ISD::AND: return visitAND(N);
619 case ISD::OR: return visitOR(N);
620 case ISD::XOR: return visitXOR(N);
621 case ISD::SHL: return visitSHL(N);
622 case ISD::SRA: return visitSRA(N);
623 case ISD::SRL: return visitSRL(N);
624 case ISD::CTLZ: return visitCTLZ(N);
625 case ISD::CTTZ: return visitCTTZ(N);
626 case ISD::CTPOP: return visitCTPOP(N);
627 case ISD::SELECT: return visitSELECT(N);
628 case ISD::SELECT_CC: return visitSELECT_CC(N);
629 case ISD::SETCC: return visitSETCC(N);
630 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
631 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
632 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
633 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
634 case ISD::TRUNCATE: return visitTRUNCATE(N);
635 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
636 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
637 case ISD::FADD: return visitFADD(N);
638 case ISD::FSUB: return visitFSUB(N);
639 case ISD::FMUL: return visitFMUL(N);
640 case ISD::FDIV: return visitFDIV(N);
641 case ISD::FREM: return visitFREM(N);
642 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
643 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
644 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
645 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
646 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
647 case ISD::FP_ROUND: return visitFP_ROUND(N);
648 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
649 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
650 case ISD::FNEG: return visitFNEG(N);
651 case ISD::FABS: return visitFABS(N);
652 case ISD::BRCOND: return visitBRCOND(N);
653 case ISD::BR_CC: return visitBR_CC(N);
654 case ISD::LOAD: return visitLOAD(N);
657 case ISD::ZEXTLOAD: return visitXEXTLOAD(N);
658 case ISD::STORE: return visitSTORE(N);
659 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
660 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
661 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
662 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
663 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
664 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
665 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
666 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
667 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
668 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
669 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
670 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
671 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
676 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
677 std::vector<SDOperand> Ops;
678 bool Changed = false;
680 // If the token factor has two operands and one is the entry token, replace
681 // the token factor with the other operand.
682 if (N->getNumOperands() == 2) {
683 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
684 return N->getOperand(1);
685 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
686 return N->getOperand(0);
689 // fold (tokenfactor (tokenfactor)) -> tokenfactor
690 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
691 SDOperand Op = N->getOperand(i);
692 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
693 AddToWorkList(Op.Val); // Remove dead node.
695 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
696 Ops.push_back(Op.getOperand(j));
702 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
706 SDOperand DAGCombiner::visitADD(SDNode *N) {
707 SDOperand N0 = N->getOperand(0);
708 SDOperand N1 = N->getOperand(1);
709 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
710 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
711 MVT::ValueType VT = N0.getValueType();
713 // fold (add c1, c2) -> c1+c2
715 return DAG.getNode(ISD::ADD, VT, N0, N1);
716 // canonicalize constant to RHS
718 return DAG.getNode(ISD::ADD, VT, N1, N0);
719 // fold (add x, 0) -> x
720 if (N1C && N1C->isNullValue())
722 // fold ((c1-A)+c2) -> (c1+c2)-A
723 if (N1C && N0.getOpcode() == ISD::SUB)
724 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
725 return DAG.getNode(ISD::SUB, VT,
726 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
729 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
732 // fold ((0-A) + B) -> B-A
733 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
734 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
735 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
736 // fold (A + (0-B)) -> A-B
737 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
738 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
739 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
740 // fold (A+(B-A)) -> B
741 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
742 return N1.getOperand(0);
744 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
745 return SDOperand(N, 0);
747 // fold (a+b) -> (a|b) iff a and b share no bits.
748 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
749 uint64_t LHSZero, LHSOne;
750 uint64_t RHSZero, RHSOne;
751 uint64_t Mask = MVT::getIntVTBitMask(VT);
752 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
754 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
756 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
757 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
758 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
759 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
760 return DAG.getNode(ISD::OR, VT, N0, N1);
767 SDOperand DAGCombiner::visitSUB(SDNode *N) {
768 SDOperand N0 = N->getOperand(0);
769 SDOperand N1 = N->getOperand(1);
770 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
771 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
772 MVT::ValueType VT = N0.getValueType();
774 // fold (sub x, x) -> 0
776 return DAG.getConstant(0, N->getValueType(0));
777 // fold (sub c1, c2) -> c1-c2
779 return DAG.getNode(ISD::SUB, VT, N0, N1);
780 // fold (sub x, c) -> (add x, -c)
782 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
784 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
785 return N0.getOperand(1);
787 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
788 return N0.getOperand(0);
792 SDOperand DAGCombiner::visitMUL(SDNode *N) {
793 SDOperand N0 = N->getOperand(0);
794 SDOperand N1 = N->getOperand(1);
795 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
796 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
797 MVT::ValueType VT = N0.getValueType();
799 // fold (mul c1, c2) -> c1*c2
801 return DAG.getNode(ISD::MUL, VT, N0, N1);
802 // canonicalize constant to RHS
804 return DAG.getNode(ISD::MUL, VT, N1, N0);
805 // fold (mul x, 0) -> 0
806 if (N1C && N1C->isNullValue())
808 // fold (mul x, -1) -> 0-x
809 if (N1C && N1C->isAllOnesValue())
810 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
811 // fold (mul x, (1 << c)) -> x << c
812 if (N1C && isPowerOf2_64(N1C->getValue()))
813 return DAG.getNode(ISD::SHL, VT, N0,
814 DAG.getConstant(Log2_64(N1C->getValue()),
815 TLI.getShiftAmountTy()));
816 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
817 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
818 // FIXME: If the input is something that is easily negated (e.g. a
819 // single-use add), we should put the negate there.
820 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
821 DAG.getNode(ISD::SHL, VT, N0,
822 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
823 TLI.getShiftAmountTy())));
826 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
827 if (N1C && N0.getOpcode() == ISD::SHL &&
828 isa<ConstantSDNode>(N0.getOperand(1))) {
829 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
830 AddToWorkList(C3.Val);
831 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
834 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
837 SDOperand Sh(0,0), Y(0,0);
838 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
839 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
840 N0.Val->hasOneUse()) {
842 } else if (N1.getOpcode() == ISD::SHL &&
843 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
847 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
848 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
851 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
852 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
853 isa<ConstantSDNode>(N0.getOperand(1))) {
854 return DAG.getNode(ISD::ADD, VT,
855 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
856 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
860 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
866 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
867 SDOperand N0 = N->getOperand(0);
868 SDOperand N1 = N->getOperand(1);
869 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
870 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
871 MVT::ValueType VT = N->getValueType(0);
873 // fold (sdiv c1, c2) -> c1/c2
874 if (N0C && N1C && !N1C->isNullValue())
875 return DAG.getNode(ISD::SDIV, VT, N0, N1);
876 // fold (sdiv X, 1) -> X
877 if (N1C && N1C->getSignExtended() == 1LL)
879 // fold (sdiv X, -1) -> 0-X
880 if (N1C && N1C->isAllOnesValue())
881 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
882 // If we know the sign bits of both operands are zero, strength reduce to a
883 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
884 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
885 if (TLI.MaskedValueIsZero(N1, SignBit) &&
886 TLI.MaskedValueIsZero(N0, SignBit))
887 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
888 // fold (sdiv X, pow2) -> simple ops after legalize
889 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
890 (isPowerOf2_64(N1C->getSignExtended()) ||
891 isPowerOf2_64(-N1C->getSignExtended()))) {
892 // If dividing by powers of two is cheap, then don't perform the following
894 if (TLI.isPow2DivCheap())
896 int64_t pow2 = N1C->getSignExtended();
897 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
898 unsigned lg2 = Log2_64(abs2);
899 // Splat the sign bit into the register
900 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
901 DAG.getConstant(MVT::getSizeInBits(VT)-1,
902 TLI.getShiftAmountTy()));
903 AddToWorkList(SGN.Val);
904 // Add (N0 < 0) ? abs2 - 1 : 0;
905 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
906 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
907 TLI.getShiftAmountTy()));
908 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
909 AddToWorkList(SRL.Val);
910 AddToWorkList(ADD.Val); // Divide by pow2
911 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
912 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
913 // If we're dividing by a positive value, we're done. Otherwise, we must
914 // negate the result.
917 AddToWorkList(SRA.Val);
918 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
920 // if integer divide is expensive and we satisfy the requirements, emit an
921 // alternate sequence.
922 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
923 !TLI.isIntDivCheap()) {
924 SDOperand Op = BuildSDIV(N);
925 if (Op.Val) return Op;
930 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
931 SDOperand N0 = N->getOperand(0);
932 SDOperand N1 = N->getOperand(1);
933 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
934 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
935 MVT::ValueType VT = N->getValueType(0);
937 // fold (udiv c1, c2) -> c1/c2
938 if (N0C && N1C && !N1C->isNullValue())
939 return DAG.getNode(ISD::UDIV, VT, N0, N1);
940 // fold (udiv x, (1 << c)) -> x >>u c
941 if (N1C && isPowerOf2_64(N1C->getValue()))
942 return DAG.getNode(ISD::SRL, VT, N0,
943 DAG.getConstant(Log2_64(N1C->getValue()),
944 TLI.getShiftAmountTy()));
945 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
946 if (N1.getOpcode() == ISD::SHL) {
947 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
948 if (isPowerOf2_64(SHC->getValue())) {
949 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
950 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
951 DAG.getConstant(Log2_64(SHC->getValue()),
953 AddToWorkList(Add.Val);
954 return DAG.getNode(ISD::SRL, VT, N0, Add);
958 // fold (udiv x, c) -> alternate
959 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
960 SDOperand Op = BuildUDIV(N);
961 if (Op.Val) return Op;
966 SDOperand DAGCombiner::visitSREM(SDNode *N) {
967 SDOperand N0 = N->getOperand(0);
968 SDOperand N1 = N->getOperand(1);
969 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
970 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
971 MVT::ValueType VT = N->getValueType(0);
973 // fold (srem c1, c2) -> c1%c2
974 if (N0C && N1C && !N1C->isNullValue())
975 return DAG.getNode(ISD::SREM, VT, N0, N1);
976 // If we know the sign bits of both operands are zero, strength reduce to a
977 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
978 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
979 if (TLI.MaskedValueIsZero(N1, SignBit) &&
980 TLI.MaskedValueIsZero(N0, SignBit))
981 return DAG.getNode(ISD::UREM, VT, N0, N1);
985 SDOperand DAGCombiner::visitUREM(SDNode *N) {
986 SDOperand N0 = N->getOperand(0);
987 SDOperand N1 = N->getOperand(1);
988 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
989 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
990 MVT::ValueType VT = N->getValueType(0);
992 // fold (urem c1, c2) -> c1%c2
993 if (N0C && N1C && !N1C->isNullValue())
994 return DAG.getNode(ISD::UREM, VT, N0, N1);
995 // fold (urem x, pow2) -> (and x, pow2-1)
996 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
997 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
998 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
999 if (N1.getOpcode() == ISD::SHL) {
1000 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1001 if (isPowerOf2_64(SHC->getValue())) {
1002 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1003 AddToWorkList(Add.Val);
1004 return DAG.getNode(ISD::AND, VT, N0, Add);
1011 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1012 SDOperand N0 = N->getOperand(0);
1013 SDOperand N1 = N->getOperand(1);
1014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1016 // fold (mulhs x, 0) -> 0
1017 if (N1C && N1C->isNullValue())
1019 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1020 if (N1C && N1C->getValue() == 1)
1021 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1022 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1023 TLI.getShiftAmountTy()));
1027 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1028 SDOperand N0 = N->getOperand(0);
1029 SDOperand N1 = N->getOperand(1);
1030 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1032 // fold (mulhu x, 0) -> 0
1033 if (N1C && N1C->isNullValue())
1035 // fold (mulhu x, 1) -> 0
1036 if (N1C && N1C->getValue() == 1)
1037 return DAG.getConstant(0, N0.getValueType());
1041 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1042 /// two operands of the same opcode, try to simplify it.
1043 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1044 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1045 MVT::ValueType VT = N0.getValueType();
1046 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1048 // For each of OP in AND/OR/XOR:
1049 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1050 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1051 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1052 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1053 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1054 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1055 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1056 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1057 N0.getOperand(0).getValueType(),
1058 N0.getOperand(0), N1.getOperand(0));
1059 AddToWorkList(ORNode.Val);
1060 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1063 // For each of OP in SHL/SRL/SRA/AND...
1064 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1065 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1066 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1067 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1068 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1069 N0.getOperand(1) == N1.getOperand(1)) {
1070 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1071 N0.getOperand(0).getValueType(),
1072 N0.getOperand(0), N1.getOperand(0));
1073 AddToWorkList(ORNode.Val);
1074 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1080 SDOperand DAGCombiner::visitAND(SDNode *N) {
1081 SDOperand N0 = N->getOperand(0);
1082 SDOperand N1 = N->getOperand(1);
1083 SDOperand LL, LR, RL, RR, CC0, CC1;
1084 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1085 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1086 MVT::ValueType VT = N1.getValueType();
1087 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1089 // fold (and c1, c2) -> c1&c2
1091 return DAG.getNode(ISD::AND, VT, N0, N1);
1092 // canonicalize constant to RHS
1094 return DAG.getNode(ISD::AND, VT, N1, N0);
1095 // fold (and x, -1) -> x
1096 if (N1C && N1C->isAllOnesValue())
1098 // if (and x, c) is known to be zero, return 0
1099 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1100 return DAG.getConstant(0, VT);
1102 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1105 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1106 if (N1C && N0.getOpcode() == ISD::OR)
1107 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1108 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1110 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1111 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1112 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1113 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1114 ~N1C->getValue() & InMask)) {
1115 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1118 // Replace uses of the AND with uses of the Zero extend node.
1121 // We actually want to replace all uses of the any_extend with the
1122 // zero_extend, to avoid duplicating things. This will later cause this
1123 // AND to be folded.
1124 CombineTo(N0.Val, Zext);
1125 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1128 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1129 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1130 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1131 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1133 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1134 MVT::isInteger(LL.getValueType())) {
1135 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1136 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1137 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1138 AddToWorkList(ORNode.Val);
1139 return DAG.getSetCC(VT, ORNode, LR, Op1);
1141 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1142 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1143 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1144 AddToWorkList(ANDNode.Val);
1145 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1147 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1148 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1149 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1150 AddToWorkList(ORNode.Val);
1151 return DAG.getSetCC(VT, ORNode, LR, Op1);
1154 // canonicalize equivalent to ll == rl
1155 if (LL == RR && LR == RL) {
1156 Op1 = ISD::getSetCCSwappedOperands(Op1);
1159 if (LL == RL && LR == RR) {
1160 bool isInteger = MVT::isInteger(LL.getValueType());
1161 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1162 if (Result != ISD::SETCC_INVALID)
1163 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1167 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1168 if (N0.getOpcode() == N1.getOpcode()) {
1169 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1170 if (Tmp.Val) return Tmp;
1173 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1174 // fold (and (sra)) -> (and (srl)) when possible.
1175 if (!MVT::isVector(VT) &&
1176 SimplifyDemandedBits(SDOperand(N, 0)))
1177 return SDOperand(N, 0);
1178 // fold (zext_inreg (extload x)) -> (zextload x)
1179 if (N0.getOpcode() == ISD::EXTLOAD) {
1180 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1181 // If we zero all the possible extended bits, then we can turn this into
1182 // a zextload if we are running before legalize or the operation is legal.
1183 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1184 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1185 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1186 N0.getOperand(1), N0.getOperand(2),
1189 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1190 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1193 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1194 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1195 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1196 // If we zero all the possible extended bits, then we can turn this into
1197 // a zextload if we are running before legalize or the operation is legal.
1198 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1199 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1200 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1201 N0.getOperand(1), N0.getOperand(2),
1204 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1205 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1209 // fold (and (load x), 255) -> (zextload x, i8)
1210 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1212 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
1213 N0.getOpcode() == ISD::ZEXTLOAD) &&
1215 MVT::ValueType EVT, LoadedVT;
1216 if (N1C->getValue() == 255)
1218 else if (N1C->getValue() == 65535)
1220 else if (N1C->getValue() == ~0U)
1225 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
1226 cast<VTSDNode>(N0.getOperand(3))->getVT();
1227 if (EVT != MVT::Other && LoadedVT > EVT &&
1228 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1229 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1230 // For big endian targets, we need to add an offset to the pointer to load
1231 // the correct bytes. For little endian systems, we merely need to read
1232 // fewer bytes from the same pointer.
1234 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1235 SDOperand NewPtr = N0.getOperand(1);
1236 if (!TLI.isLittleEndian())
1237 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1238 DAG.getConstant(PtrOff, PtrType));
1239 AddToWorkList(NewPtr.Val);
1241 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr,
1242 N0.getOperand(2), EVT);
1244 CombineTo(N0.Val, Load, Load.getValue(1));
1245 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1252 SDOperand DAGCombiner::visitOR(SDNode *N) {
1253 SDOperand N0 = N->getOperand(0);
1254 SDOperand N1 = N->getOperand(1);
1255 SDOperand LL, LR, RL, RR, CC0, CC1;
1256 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1257 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1258 MVT::ValueType VT = N1.getValueType();
1259 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1261 // fold (or c1, c2) -> c1|c2
1263 return DAG.getNode(ISD::OR, VT, N0, N1);
1264 // canonicalize constant to RHS
1266 return DAG.getNode(ISD::OR, VT, N1, N0);
1267 // fold (or x, 0) -> x
1268 if (N1C && N1C->isNullValue())
1270 // fold (or x, -1) -> -1
1271 if (N1C && N1C->isAllOnesValue())
1273 // fold (or x, c) -> c iff (x & ~c) == 0
1275 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1278 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1281 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1282 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1283 isa<ConstantSDNode>(N0.getOperand(1))) {
1284 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1285 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1287 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1289 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1290 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1291 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1292 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1294 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1295 MVT::isInteger(LL.getValueType())) {
1296 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1297 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1298 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1299 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1300 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1301 AddToWorkList(ORNode.Val);
1302 return DAG.getSetCC(VT, ORNode, LR, Op1);
1304 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1305 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1306 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1307 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1308 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1309 AddToWorkList(ANDNode.Val);
1310 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1313 // canonicalize equivalent to ll == rl
1314 if (LL == RR && LR == RL) {
1315 Op1 = ISD::getSetCCSwappedOperands(Op1);
1318 if (LL == RL && LR == RR) {
1319 bool isInteger = MVT::isInteger(LL.getValueType());
1320 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1321 if (Result != ISD::SETCC_INVALID)
1322 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1326 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1327 if (N0.getOpcode() == N1.getOpcode()) {
1328 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1329 if (Tmp.Val) return Tmp;
1332 // canonicalize shl to left side in a shl/srl pair, to match rotate
1333 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1335 // check for rotl, rotr
1336 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1337 N0.getOperand(0) == N1.getOperand(0) &&
1338 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1339 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1340 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1341 N1.getOperand(1).getOpcode() == ISD::Constant) {
1342 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1343 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1344 if ((c1val + c2val) == OpSizeInBits)
1345 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1347 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1348 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1349 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1350 if (ConstantSDNode *SUBC =
1351 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1352 if (SUBC->getValue() == OpSizeInBits)
1353 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1354 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1355 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1356 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1357 if (ConstantSDNode *SUBC =
1358 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1359 if (SUBC->getValue() == OpSizeInBits) {
1360 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1361 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1364 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1371 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1372 SDOperand N0 = N->getOperand(0);
1373 SDOperand N1 = N->getOperand(1);
1374 SDOperand LHS, RHS, CC;
1375 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1376 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1377 MVT::ValueType VT = N0.getValueType();
1379 // fold (xor c1, c2) -> c1^c2
1381 return DAG.getNode(ISD::XOR, VT, N0, N1);
1382 // canonicalize constant to RHS
1384 return DAG.getNode(ISD::XOR, VT, N1, N0);
1385 // fold (xor x, 0) -> x
1386 if (N1C && N1C->isNullValue())
1389 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1392 // fold !(x cc y) -> (x !cc y)
1393 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1394 bool isInt = MVT::isInteger(LHS.getValueType());
1395 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1397 if (N0.getOpcode() == ISD::SETCC)
1398 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1399 if (N0.getOpcode() == ISD::SELECT_CC)
1400 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1401 assert(0 && "Unhandled SetCC Equivalent!");
1404 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1405 if (N1C && N1C->getValue() == 1 &&
1406 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1407 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1408 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1409 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1410 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1411 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1412 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1413 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1416 // fold !(x or y) -> (!x and !y) iff x or y are constants
1417 if (N1C && N1C->isAllOnesValue() &&
1418 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1419 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1420 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1421 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1422 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1423 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1424 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1425 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1428 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1429 if (N1C && N0.getOpcode() == ISD::XOR) {
1430 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1431 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1433 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1434 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1436 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1437 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1439 // fold (xor x, x) -> 0
1441 if (!MVT::isVector(VT)) {
1442 return DAG.getConstant(0, VT);
1443 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1444 // Produce a vector of zeros.
1445 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1446 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1447 return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
1451 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1452 if (N0.getOpcode() == N1.getOpcode()) {
1453 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1454 if (Tmp.Val) return Tmp;
1457 // Simplify the expression using non-local knowledge.
1458 if (!MVT::isVector(VT) &&
1459 SimplifyDemandedBits(SDOperand(N, 0)))
1460 return SDOperand(N, 0);
1465 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1466 SDOperand N0 = N->getOperand(0);
1467 SDOperand N1 = N->getOperand(1);
1468 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1469 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1470 MVT::ValueType VT = N0.getValueType();
1471 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1473 // fold (shl c1, c2) -> c1<<c2
1475 return DAG.getNode(ISD::SHL, VT, N0, N1);
1476 // fold (shl 0, x) -> 0
1477 if (N0C && N0C->isNullValue())
1479 // fold (shl x, c >= size(x)) -> undef
1480 if (N1C && N1C->getValue() >= OpSizeInBits)
1481 return DAG.getNode(ISD::UNDEF, VT);
1482 // fold (shl x, 0) -> x
1483 if (N1C && N1C->isNullValue())
1485 // if (shl x, c) is known to be zero, return 0
1486 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1487 return DAG.getConstant(0, VT);
1488 if (SimplifyDemandedBits(SDOperand(N, 0)))
1489 return SDOperand(N, 0);
1490 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1491 if (N1C && N0.getOpcode() == ISD::SHL &&
1492 N0.getOperand(1).getOpcode() == ISD::Constant) {
1493 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1494 uint64_t c2 = N1C->getValue();
1495 if (c1 + c2 > OpSizeInBits)
1496 return DAG.getConstant(0, VT);
1497 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1498 DAG.getConstant(c1 + c2, N1.getValueType()));
1500 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1501 // (srl (and x, -1 << c1), c1-c2)
1502 if (N1C && N0.getOpcode() == ISD::SRL &&
1503 N0.getOperand(1).getOpcode() == ISD::Constant) {
1504 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1505 uint64_t c2 = N1C->getValue();
1506 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1507 DAG.getConstant(~0ULL << c1, VT));
1509 return DAG.getNode(ISD::SHL, VT, Mask,
1510 DAG.getConstant(c2-c1, N1.getValueType()));
1512 return DAG.getNode(ISD::SRL, VT, Mask,
1513 DAG.getConstant(c1-c2, N1.getValueType()));
1515 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1516 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1517 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1518 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1519 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1520 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1521 isa<ConstantSDNode>(N0.getOperand(1))) {
1522 return DAG.getNode(ISD::ADD, VT,
1523 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1524 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1529 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1530 SDOperand N0 = N->getOperand(0);
1531 SDOperand N1 = N->getOperand(1);
1532 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1533 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1534 MVT::ValueType VT = N0.getValueType();
1536 // fold (sra c1, c2) -> c1>>c2
1538 return DAG.getNode(ISD::SRA, VT, N0, N1);
1539 // fold (sra 0, x) -> 0
1540 if (N0C && N0C->isNullValue())
1542 // fold (sra -1, x) -> -1
1543 if (N0C && N0C->isAllOnesValue())
1545 // fold (sra x, c >= size(x)) -> undef
1546 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1547 return DAG.getNode(ISD::UNDEF, VT);
1548 // fold (sra x, 0) -> x
1549 if (N1C && N1C->isNullValue())
1551 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1553 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1554 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1557 default: EVT = MVT::Other; break;
1558 case 1: EVT = MVT::i1; break;
1559 case 8: EVT = MVT::i8; break;
1560 case 16: EVT = MVT::i16; break;
1561 case 32: EVT = MVT::i32; break;
1563 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1564 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1565 DAG.getValueType(EVT));
1568 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1569 if (N1C && N0.getOpcode() == ISD::SRA) {
1570 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1571 unsigned Sum = N1C->getValue() + C1->getValue();
1572 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1573 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1574 DAG.getConstant(Sum, N1C->getValueType(0)));
1578 // Simplify, based on bits shifted out of the LHS.
1579 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1580 return SDOperand(N, 0);
1583 // If the sign bit is known to be zero, switch this to a SRL.
1584 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1585 return DAG.getNode(ISD::SRL, VT, N0, N1);
1589 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1590 SDOperand N0 = N->getOperand(0);
1591 SDOperand N1 = N->getOperand(1);
1592 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1593 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1594 MVT::ValueType VT = N0.getValueType();
1595 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1597 // fold (srl c1, c2) -> c1 >>u c2
1599 return DAG.getNode(ISD::SRL, VT, N0, N1);
1600 // fold (srl 0, x) -> 0
1601 if (N0C && N0C->isNullValue())
1603 // fold (srl x, c >= size(x)) -> undef
1604 if (N1C && N1C->getValue() >= OpSizeInBits)
1605 return DAG.getNode(ISD::UNDEF, VT);
1606 // fold (srl x, 0) -> x
1607 if (N1C && N1C->isNullValue())
1609 // if (srl x, c) is known to be zero, return 0
1610 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1611 return DAG.getConstant(0, VT);
1612 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1613 if (N1C && N0.getOpcode() == ISD::SRL &&
1614 N0.getOperand(1).getOpcode() == ISD::Constant) {
1615 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1616 uint64_t c2 = N1C->getValue();
1617 if (c1 + c2 > OpSizeInBits)
1618 return DAG.getConstant(0, VT);
1619 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1620 DAG.getConstant(c1 + c2, N1.getValueType()));
1623 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1624 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1625 // Shifting in all undef bits?
1626 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1627 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1628 return DAG.getNode(ISD::UNDEF, VT);
1630 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1631 AddToWorkList(SmallShift.Val);
1632 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1635 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1636 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1637 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1638 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1639 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1641 // If any of the input bits are KnownOne, then the input couldn't be all
1642 // zeros, thus the result of the srl will always be zero.
1643 if (KnownOne) return DAG.getConstant(0, VT);
1645 // If all of the bits input the to ctlz node are known to be zero, then
1646 // the result of the ctlz is "32" and the result of the shift is one.
1647 uint64_t UnknownBits = ~KnownZero & Mask;
1648 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1650 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1651 if ((UnknownBits & (UnknownBits-1)) == 0) {
1652 // Okay, we know that only that the single bit specified by UnknownBits
1653 // could be set on input to the CTLZ node. If this bit is set, the SRL
1654 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1655 // to an SRL,XOR pair, which is likely to simplify more.
1656 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1657 SDOperand Op = N0.getOperand(0);
1659 Op = DAG.getNode(ISD::SRL, VT, Op,
1660 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1661 AddToWorkList(Op.Val);
1663 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1670 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1671 SDOperand N0 = N->getOperand(0);
1672 MVT::ValueType VT = N->getValueType(0);
1674 // fold (ctlz c1) -> c2
1675 if (isa<ConstantSDNode>(N0))
1676 return DAG.getNode(ISD::CTLZ, VT, N0);
1680 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1681 SDOperand N0 = N->getOperand(0);
1682 MVT::ValueType VT = N->getValueType(0);
1684 // fold (cttz c1) -> c2
1685 if (isa<ConstantSDNode>(N0))
1686 return DAG.getNode(ISD::CTTZ, VT, N0);
1690 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1691 SDOperand N0 = N->getOperand(0);
1692 MVT::ValueType VT = N->getValueType(0);
1694 // fold (ctpop c1) -> c2
1695 if (isa<ConstantSDNode>(N0))
1696 return DAG.getNode(ISD::CTPOP, VT, N0);
1700 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1701 SDOperand N0 = N->getOperand(0);
1702 SDOperand N1 = N->getOperand(1);
1703 SDOperand N2 = N->getOperand(2);
1704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1706 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1707 MVT::ValueType VT = N->getValueType(0);
1709 // fold select C, X, X -> X
1712 // fold select true, X, Y -> X
1713 if (N0C && !N0C->isNullValue())
1715 // fold select false, X, Y -> Y
1716 if (N0C && N0C->isNullValue())
1718 // fold select C, 1, X -> C | X
1719 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1720 return DAG.getNode(ISD::OR, VT, N0, N2);
1721 // fold select C, 0, X -> ~C & X
1722 // FIXME: this should check for C type == X type, not i1?
1723 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1724 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1725 AddToWorkList(XORNode.Val);
1726 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1728 // fold select C, X, 1 -> ~C | X
1729 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1730 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1731 AddToWorkList(XORNode.Val);
1732 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1734 // fold select C, X, 0 -> C & X
1735 // FIXME: this should check for C type == X type, not i1?
1736 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1737 return DAG.getNode(ISD::AND, VT, N0, N1);
1738 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1739 if (MVT::i1 == VT && N0 == N1)
1740 return DAG.getNode(ISD::OR, VT, N0, N2);
1741 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1742 if (MVT::i1 == VT && N0 == N2)
1743 return DAG.getNode(ISD::AND, VT, N0, N1);
1744 // If we can fold this based on the true/false value, do so.
1745 if (SimplifySelectOps(N, N1, N2))
1747 // fold selects based on a setcc into other things, such as min/max/abs
1748 if (N0.getOpcode() == ISD::SETCC)
1750 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1751 // having to say they don't support SELECT_CC on every type the DAG knows
1752 // about, since there is no way to mark an opcode illegal at all value types
1753 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1754 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1755 N1, N2, N0.getOperand(2));
1757 return SimplifySelect(N0, N1, N2);
1761 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1762 SDOperand N0 = N->getOperand(0);
1763 SDOperand N1 = N->getOperand(1);
1764 SDOperand N2 = N->getOperand(2);
1765 SDOperand N3 = N->getOperand(3);
1766 SDOperand N4 = N->getOperand(4);
1767 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1768 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1769 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1770 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1772 // Determine if the condition we're dealing with is constant
1773 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1774 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1776 // fold select_cc lhs, rhs, x, x, cc -> x
1780 // If we can fold this based on the true/false value, do so.
1781 if (SimplifySelectOps(N, N2, N3))
1784 // fold select_cc into other things, such as min/max/abs
1785 return SimplifySelectCC(N0, N1, N2, N3, CC);
1788 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1789 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1790 cast<CondCodeSDNode>(N->getOperand(2))->get());
1793 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1794 SDOperand N0 = N->getOperand(0);
1795 MVT::ValueType VT = N->getValueType(0);
1797 // fold (sext c1) -> c1
1798 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1799 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1801 // fold (sext (sext x)) -> (sext x)
1802 // fold (sext (aext x)) -> (sext x)
1803 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1804 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1806 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1807 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1809 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1810 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1811 DAG.getValueType(N0.getValueType()));
1813 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1814 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1815 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1816 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1817 N0.getOperand(1), N0.getOperand(2),
1819 CombineTo(N, ExtLoad);
1820 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1821 ExtLoad.getValue(1));
1822 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1825 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1826 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1827 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1829 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1830 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1831 N0.getOperand(1), N0.getOperand(2), EVT);
1832 CombineTo(N, ExtLoad);
1833 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1834 ExtLoad.getValue(1));
1835 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1841 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1842 SDOperand N0 = N->getOperand(0);
1843 MVT::ValueType VT = N->getValueType(0);
1845 // fold (zext c1) -> c1
1846 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1847 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1848 // fold (zext (zext x)) -> (zext x)
1849 // fold (zext (aext x)) -> (zext x)
1850 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1851 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1852 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1853 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1854 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1855 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1856 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1857 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1858 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1859 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1860 N0.getOperand(1), N0.getOperand(2),
1862 CombineTo(N, ExtLoad);
1863 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1864 ExtLoad.getValue(1));
1865 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1868 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1869 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1870 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1872 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1873 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1874 N0.getOperand(1), N0.getOperand(2), EVT);
1875 CombineTo(N, ExtLoad);
1876 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1877 ExtLoad.getValue(1));
1878 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1883 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
1884 SDOperand N0 = N->getOperand(0);
1885 MVT::ValueType VT = N->getValueType(0);
1887 // fold (aext c1) -> c1
1888 if (isa<ConstantSDNode>(N0))
1889 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
1890 // fold (aext (aext x)) -> (aext x)
1891 // fold (aext (zext x)) -> (zext x)
1892 // fold (aext (sext x)) -> (sext x)
1893 if (N0.getOpcode() == ISD::ANY_EXTEND ||
1894 N0.getOpcode() == ISD::ZERO_EXTEND ||
1895 N0.getOpcode() == ISD::SIGN_EXTEND)
1896 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1898 // fold (aext (truncate x)) -> x iff x size == zext size.
1899 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT)
1900 return N0.getOperand(0);
1901 // fold (aext (load x)) -> (aext (truncate (extload x)))
1902 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1903 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) {
1904 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
1905 N0.getOperand(1), N0.getOperand(2),
1907 CombineTo(N, ExtLoad);
1908 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1909 ExtLoad.getValue(1));
1910 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1913 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
1914 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
1915 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
1916 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD ||
1917 N0.getOpcode() == ISD::SEXTLOAD) &&
1919 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1920 SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0),
1921 N0.getOperand(1), N0.getOperand(2), EVT);
1922 CombineTo(N, ExtLoad);
1923 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1924 ExtLoad.getValue(1));
1925 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1931 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1932 SDOperand N0 = N->getOperand(0);
1933 SDOperand N1 = N->getOperand(1);
1934 MVT::ValueType VT = N->getValueType(0);
1935 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1936 unsigned EVTBits = MVT::getSizeInBits(EVT);
1938 // fold (sext_in_reg c1) -> c1
1939 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
1940 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
1942 // If the input is already sign extended, just drop the extension.
1943 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
1946 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1947 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1948 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1949 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1952 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1953 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
1954 return DAG.getZeroExtendInReg(N0, EVT);
1956 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
1957 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
1958 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
1959 if (N0.getOpcode() == ISD::SRL) {
1960 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1961 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
1962 // We can turn this into an SRA iff the input to the SRL is already sign
1964 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
1965 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
1966 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
1970 // fold (sext_inreg (extload x)) -> (sextload x)
1971 if (N0.getOpcode() == ISD::EXTLOAD &&
1972 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1973 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1974 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1975 N0.getOperand(1), N0.getOperand(2),
1977 CombineTo(N, ExtLoad);
1978 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1979 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1981 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1982 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1983 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1984 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1985 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1986 N0.getOperand(1), N0.getOperand(2),
1988 CombineTo(N, ExtLoad);
1989 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1990 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1995 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1996 SDOperand N0 = N->getOperand(0);
1997 MVT::ValueType VT = N->getValueType(0);
2000 if (N0.getValueType() == N->getValueType(0))
2002 // fold (truncate c1) -> c1
2003 if (isa<ConstantSDNode>(N0))
2004 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2005 // fold (truncate (truncate x)) -> (truncate x)
2006 if (N0.getOpcode() == ISD::TRUNCATE)
2007 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2008 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2009 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2010 N0.getOpcode() == ISD::ANY_EXTEND) {
2011 if (N0.getValueType() < VT)
2012 // if the source is smaller than the dest, we still need an extend
2013 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2014 else if (N0.getValueType() > VT)
2015 // if the source is larger than the dest, than we just need the truncate
2016 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2018 // if the source and dest are the same type, we can drop both the extend
2020 return N0.getOperand(0);
2022 // fold (truncate (load x)) -> (smaller load x)
2023 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
2024 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2025 "Cannot truncate to larger type!");
2026 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2027 // For big endian targets, we need to add an offset to the pointer to load
2028 // the correct bytes. For little endian systems, we merely need to read
2029 // fewer bytes from the same pointer.
2031 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2032 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
2033 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
2034 DAG.getConstant(PtrOff, PtrType));
2035 AddToWorkList(NewPtr.Val);
2036 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
2038 CombineTo(N0.Val, Load, Load.getValue(1));
2039 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2044 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2045 SDOperand N0 = N->getOperand(0);
2046 MVT::ValueType VT = N->getValueType(0);
2048 // If the input is a constant, let getNode() fold it.
2049 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2050 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2051 if (Res.Val != N) return Res;
2054 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2055 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2057 // fold (conv (load x)) -> (load (conv*)x)
2058 // FIXME: These xforms need to know that the resultant load doesn't need a
2059 // higher alignment than the original!
2060 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
2061 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
2064 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2072 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2073 SDOperand N0 = N->getOperand(0);
2074 MVT::ValueType VT = N->getValueType(0);
2076 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2077 // First check to see if this is all constant.
2078 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2079 VT == MVT::Vector) {
2080 bool isSimple = true;
2081 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2082 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2083 N0.getOperand(i).getOpcode() != ISD::Constant &&
2084 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2089 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2090 if (isSimple && !MVT::isVector(DestEltVT)) {
2091 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2098 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2099 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2100 /// destination element value type.
2101 SDOperand DAGCombiner::
2102 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2103 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2105 // If this is already the right type, we're done.
2106 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2108 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2109 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2111 // If this is a conversion of N elements of one type to N elements of another
2112 // type, convert each element. This handles FP<->INT cases.
2113 if (SrcBitSize == DstBitSize) {
2114 std::vector<SDOperand> Ops;
2115 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2116 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2117 AddToWorkList(Ops.back().Val);
2119 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2120 Ops.push_back(DAG.getValueType(DstEltVT));
2121 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2124 // Otherwise, we're growing or shrinking the elements. To avoid having to
2125 // handle annoying details of growing/shrinking FP values, we convert them to
2127 if (MVT::isFloatingPoint(SrcEltVT)) {
2128 // Convert the input float vector to a int vector where the elements are the
2130 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2131 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2132 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2136 // Now we know the input is an integer vector. If the output is a FP type,
2137 // convert to integer first, then to FP of the right size.
2138 if (MVT::isFloatingPoint(DstEltVT)) {
2139 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2140 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2141 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2143 // Next, convert to FP elements of the same size.
2144 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2147 // Okay, we know the src/dst types are both integers of differing types.
2148 // Handling growing first.
2149 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2150 if (SrcBitSize < DstBitSize) {
2151 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2153 std::vector<SDOperand> Ops;
2154 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2155 i += NumInputsPerOutput) {
2156 bool isLE = TLI.isLittleEndian();
2157 uint64_t NewBits = 0;
2158 bool EltIsUndef = true;
2159 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2160 // Shift the previously computed bits over.
2161 NewBits <<= SrcBitSize;
2162 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2163 if (Op.getOpcode() == ISD::UNDEF) continue;
2166 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2170 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2172 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2175 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2176 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2177 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2180 // Finally, this must be the case where we are shrinking elements: each input
2181 // turns into multiple outputs.
2182 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2183 std::vector<SDOperand> Ops;
2184 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2185 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2186 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2187 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2190 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2192 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2193 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2194 OpVal >>= DstBitSize;
2195 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2198 // For big endian targets, swap the order of the pieces of each element.
2199 if (!TLI.isLittleEndian())
2200 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2202 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2203 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2204 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2209 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2210 SDOperand N0 = N->getOperand(0);
2211 SDOperand N1 = N->getOperand(1);
2212 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2213 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2214 MVT::ValueType VT = N->getValueType(0);
2216 // fold (fadd c1, c2) -> c1+c2
2218 return DAG.getNode(ISD::FADD, VT, N0, N1);
2219 // canonicalize constant to RHS
2220 if (N0CFP && !N1CFP)
2221 return DAG.getNode(ISD::FADD, VT, N1, N0);
2222 // fold (A + (-B)) -> A-B
2223 if (N1.getOpcode() == ISD::FNEG)
2224 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2225 // fold ((-A) + B) -> B-A
2226 if (N0.getOpcode() == ISD::FNEG)
2227 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2231 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2232 SDOperand N0 = N->getOperand(0);
2233 SDOperand N1 = N->getOperand(1);
2234 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2235 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2236 MVT::ValueType VT = N->getValueType(0);
2238 // fold (fsub c1, c2) -> c1-c2
2240 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2241 // fold (A-(-B)) -> A+B
2242 if (N1.getOpcode() == ISD::FNEG)
2243 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2247 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2248 SDOperand N0 = N->getOperand(0);
2249 SDOperand N1 = N->getOperand(1);
2250 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2251 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2252 MVT::ValueType VT = N->getValueType(0);
2254 // fold (fmul c1, c2) -> c1*c2
2256 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2257 // canonicalize constant to RHS
2258 if (N0CFP && !N1CFP)
2259 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2260 // fold (fmul X, 2.0) -> (fadd X, X)
2261 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2262 return DAG.getNode(ISD::FADD, VT, N0, N0);
2266 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2267 SDOperand N0 = N->getOperand(0);
2268 SDOperand N1 = N->getOperand(1);
2269 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2270 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2271 MVT::ValueType VT = N->getValueType(0);
2273 // fold (fdiv c1, c2) -> c1/c2
2275 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2279 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2280 SDOperand N0 = N->getOperand(0);
2281 SDOperand N1 = N->getOperand(1);
2282 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2283 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2284 MVT::ValueType VT = N->getValueType(0);
2286 // fold (frem c1, c2) -> fmod(c1,c2)
2288 return DAG.getNode(ISD::FREM, VT, N0, N1);
2292 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2293 SDOperand N0 = N->getOperand(0);
2294 SDOperand N1 = N->getOperand(1);
2295 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2296 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2297 MVT::ValueType VT = N->getValueType(0);
2299 if (N0CFP && N1CFP) // Constant fold
2300 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2303 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2304 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2309 u.d = N1CFP->getValue();
2311 return DAG.getNode(ISD::FABS, VT, N0);
2313 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2316 // copysign(fabs(x), y) -> copysign(x, y)
2317 // copysign(fneg(x), y) -> copysign(x, y)
2318 // copysign(copysign(x,z), y) -> copysign(x, y)
2319 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2320 N0.getOpcode() == ISD::FCOPYSIGN)
2321 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2323 // copysign(x, abs(y)) -> abs(x)
2324 if (N1.getOpcode() == ISD::FABS)
2325 return DAG.getNode(ISD::FABS, VT, N0);
2327 // copysign(x, copysign(y,z)) -> copysign(x, z)
2328 if (N1.getOpcode() == ISD::FCOPYSIGN)
2329 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2331 // copysign(x, fp_extend(y)) -> copysign(x, y)
2332 // copysign(x, fp_round(y)) -> copysign(x, y)
2333 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2334 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2341 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2342 SDOperand N0 = N->getOperand(0);
2343 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2344 MVT::ValueType VT = N->getValueType(0);
2346 // fold (sint_to_fp c1) -> c1fp
2348 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2352 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2353 SDOperand N0 = N->getOperand(0);
2354 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2355 MVT::ValueType VT = N->getValueType(0);
2357 // fold (uint_to_fp c1) -> c1fp
2359 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2363 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2364 SDOperand N0 = N->getOperand(0);
2365 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2366 MVT::ValueType VT = N->getValueType(0);
2368 // fold (fp_to_sint c1fp) -> c1
2370 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2374 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2375 SDOperand N0 = N->getOperand(0);
2376 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2377 MVT::ValueType VT = N->getValueType(0);
2379 // fold (fp_to_uint c1fp) -> c1
2381 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2385 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2386 SDOperand N0 = N->getOperand(0);
2387 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2388 MVT::ValueType VT = N->getValueType(0);
2390 // fold (fp_round c1fp) -> c1fp
2392 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2394 // fold (fp_round (fp_extend x)) -> x
2395 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2396 return N0.getOperand(0);
2398 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2399 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2400 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2401 AddToWorkList(Tmp.Val);
2402 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2408 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2409 SDOperand N0 = N->getOperand(0);
2410 MVT::ValueType VT = N->getValueType(0);
2411 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2412 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2414 // fold (fp_round_inreg c1fp) -> c1fp
2416 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2417 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2422 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2423 SDOperand N0 = N->getOperand(0);
2424 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2425 MVT::ValueType VT = N->getValueType(0);
2427 // fold (fp_extend c1fp) -> c1fp
2429 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2431 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2432 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
2433 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) {
2434 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
2435 N0.getOperand(1), N0.getOperand(2),
2437 CombineTo(N, ExtLoad);
2438 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2439 ExtLoad.getValue(1));
2440 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2447 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2448 SDOperand N0 = N->getOperand(0);
2449 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2450 MVT::ValueType VT = N->getValueType(0);
2452 // fold (fneg c1) -> -c1
2454 return DAG.getNode(ISD::FNEG, VT, N0);
2455 // fold (fneg (sub x, y)) -> (sub y, x)
2456 if (N0.getOpcode() == ISD::SUB)
2457 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2458 // fold (fneg (fneg x)) -> x
2459 if (N0.getOpcode() == ISD::FNEG)
2460 return N0.getOperand(0);
2464 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2465 SDOperand N0 = N->getOperand(0);
2466 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2467 MVT::ValueType VT = N->getValueType(0);
2469 // fold (fabs c1) -> fabs(c1)
2471 return DAG.getNode(ISD::FABS, VT, N0);
2472 // fold (fabs (fabs x)) -> (fabs x)
2473 if (N0.getOpcode() == ISD::FABS)
2474 return N->getOperand(0);
2475 // fold (fabs (fneg x)) -> (fabs x)
2476 // fold (fabs (fcopysign x, y)) -> (fabs x)
2477 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2478 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2483 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2484 SDOperand Chain = N->getOperand(0);
2485 SDOperand N1 = N->getOperand(1);
2486 SDOperand N2 = N->getOperand(2);
2487 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2489 // never taken branch, fold to chain
2490 if (N1C && N1C->isNullValue())
2492 // unconditional branch
2493 if (N1C && N1C->getValue() == 1)
2494 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2495 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2497 if (N1.getOpcode() == ISD::SETCC &&
2498 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2499 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2500 N1.getOperand(0), N1.getOperand(1), N2);
2505 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2507 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2508 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2509 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2511 // Use SimplifySetCC to simplify SETCC's.
2512 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2513 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2515 // fold br_cc true, dest -> br dest (unconditional branch)
2516 if (SCCC && SCCC->getValue())
2517 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2519 // fold br_cc false, dest -> unconditional fall through
2520 if (SCCC && SCCC->isNullValue())
2521 return N->getOperand(0);
2522 // fold to a simpler setcc
2523 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2524 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2525 Simp.getOperand(2), Simp.getOperand(0),
2526 Simp.getOperand(1), N->getOperand(4));
2530 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2531 SDOperand Chain = N->getOperand(0);
2532 SDOperand Ptr = N->getOperand(1);
2533 SDOperand SrcValue = N->getOperand(2);
2535 // If there are no uses of the loaded value, change uses of the chain value
2536 // into uses of the chain input (i.e. delete the dead load).
2537 if (N->hasNUsesOfValue(0, 0))
2538 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2540 // If this load is directly stored, replace the load value with the stored
2542 // TODO: Handle store large -> read small portion.
2543 // TODO: Handle TRUNCSTORE/EXTLOAD
2544 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2545 Chain.getOperand(1).getValueType() == N->getValueType(0))
2546 return CombineTo(N, Chain.getOperand(1), Chain);
2551 /// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD.
2552 SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) {
2553 SDOperand Chain = N->getOperand(0);
2554 SDOperand Ptr = N->getOperand(1);
2555 SDOperand SrcValue = N->getOperand(2);
2556 SDOperand EVT = N->getOperand(3);
2558 // If there are no uses of the loaded value, change uses of the chain value
2559 // into uses of the chain input (i.e. delete the dead load).
2560 if (N->hasNUsesOfValue(0, 0))
2561 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2566 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2567 SDOperand Chain = N->getOperand(0);
2568 SDOperand Value = N->getOperand(1);
2569 SDOperand Ptr = N->getOperand(2);
2570 SDOperand SrcValue = N->getOperand(3);
2572 // If this is a store that kills a previous store, remove the previous store.
2573 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2574 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2575 // Make sure that these stores are the same value type:
2576 // FIXME: we really care that the second store is >= size of the first.
2577 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2578 // Create a new store of Value that replaces both stores.
2579 SDNode *PrevStore = Chain.Val;
2580 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2582 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2583 PrevStore->getOperand(0), Value, Ptr,
2585 CombineTo(N, NewStore); // Nuke this store.
2586 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2587 return SDOperand(N, 0);
2590 // If this is a store of a bit convert, store the input value.
2591 // FIXME: This needs to know that the resultant store does not need a
2592 // higher alignment than the original.
2593 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2594 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2600 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2601 SDOperand InVec = N->getOperand(0);
2602 SDOperand InVal = N->getOperand(1);
2603 SDOperand EltNo = N->getOperand(2);
2605 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2606 // vector with the inserted element.
2607 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2608 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2609 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2610 if (Elt < Ops.size())
2612 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops);
2618 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2619 SDOperand InVec = N->getOperand(0);
2620 SDOperand InVal = N->getOperand(1);
2621 SDOperand EltNo = N->getOperand(2);
2622 SDOperand NumElts = N->getOperand(3);
2623 SDOperand EltType = N->getOperand(4);
2625 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2626 // vector with the inserted element.
2627 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2628 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2629 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2630 if (Elt < Ops.size()-2)
2632 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops);
2638 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2639 unsigned NumInScalars = N->getNumOperands()-2;
2640 SDOperand NumElts = N->getOperand(NumInScalars);
2641 SDOperand EltType = N->getOperand(NumInScalars+1);
2643 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2644 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2645 // two distinct vectors, turn this into a shuffle node.
2646 SDOperand VecIn1, VecIn2;
2647 for (unsigned i = 0; i != NumInScalars; ++i) {
2648 // Ignore undef inputs.
2649 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2651 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2652 // constant index, bail out.
2653 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2654 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2655 VecIn1 = VecIn2 = SDOperand(0, 0);
2659 // If the input vector type disagrees with the result of the vbuild_vector,
2660 // we can't make a shuffle.
2661 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2662 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2663 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2664 VecIn1 = VecIn2 = SDOperand(0, 0);
2668 // Otherwise, remember this. We allow up to two distinct input vectors.
2669 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2672 if (VecIn1.Val == 0) {
2673 VecIn1 = ExtractedFromVec;
2674 } else if (VecIn2.Val == 0) {
2675 VecIn2 = ExtractedFromVec;
2678 VecIn1 = VecIn2 = SDOperand(0, 0);
2683 // If everything is good, we can make a shuffle operation.
2685 std::vector<SDOperand> BuildVecIndices;
2686 for (unsigned i = 0; i != NumInScalars; ++i) {
2687 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2688 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2692 SDOperand Extract = N->getOperand(i);
2694 // If extracting from the first vector, just use the index directly.
2695 if (Extract.getOperand(0) == VecIn1) {
2696 BuildVecIndices.push_back(Extract.getOperand(1));
2700 // Otherwise, use InIdx + VecSize
2701 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2702 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2705 // Add count and size info.
2706 BuildVecIndices.push_back(NumElts);
2707 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2709 // Return the new VVECTOR_SHUFFLE node.
2710 std::vector<SDOperand> Ops;
2711 Ops.push_back(VecIn1);
2713 Ops.push_back(VecIn2);
2715 // Use an undef vbuild_vector as input for the second operand.
2716 std::vector<SDOperand> UnOps(NumInScalars,
2717 DAG.getNode(ISD::UNDEF,
2718 cast<VTSDNode>(EltType)->getVT()));
2719 UnOps.push_back(NumElts);
2720 UnOps.push_back(EltType);
2721 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
2722 AddToWorkList(Ops.back().Val);
2724 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
2725 Ops.push_back(NumElts);
2726 Ops.push_back(EltType);
2727 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
2733 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2734 SDOperand ShufMask = N->getOperand(2);
2735 unsigned NumElts = ShufMask.getNumOperands();
2737 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2738 bool isIdentity = true;
2739 for (unsigned i = 0; i != NumElts; ++i) {
2740 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2741 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2746 if (isIdentity) return N->getOperand(0);
2748 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2750 for (unsigned i = 0; i != NumElts; ++i) {
2751 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2752 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2757 if (isIdentity) return N->getOperand(1);
2759 // If the LHS and the RHS are the same node, turn the RHS into an undef.
2760 if (N->getOperand(0) == N->getOperand(1)) {
2761 if (N->getOperand(0).getOpcode() == ISD::UNDEF)
2762 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
2763 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
2765 std::vector<SDOperand> MappedOps;
2766 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
2767 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
2768 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
2769 MappedOps.push_back(ShufMask.getOperand(i));
2772 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
2773 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
2776 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
2778 AddToWorkList(ShufMask.Val);
2779 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
2781 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
2788 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
2789 SDOperand ShufMask = N->getOperand(2);
2790 unsigned NumElts = ShufMask.getNumOperands()-2;
2792 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2793 bool isIdentity = true;
2794 for (unsigned i = 0; i != NumElts; ++i) {
2795 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2796 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2801 if (isIdentity) return N->getOperand(0);
2803 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2805 for (unsigned i = 0; i != NumElts; ++i) {
2806 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2807 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2812 if (isIdentity) return N->getOperand(1);
2814 // If the LHS and the RHS are the same node, turn the RHS into an undef.
2815 if (N->getOperand(0) == N->getOperand(1)) {
2816 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
2818 std::vector<SDOperand> MappedOps;
2819 for (unsigned i = 0; i != NumElts; ++i) {
2820 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
2821 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
2822 MappedOps.push_back(ShufMask.getOperand(i));
2825 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
2826 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
2829 // Add the type/#elts values.
2830 MappedOps.push_back(ShufMask.getOperand(NumElts));
2831 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
2833 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
2835 AddToWorkList(ShufMask.Val);
2837 // Build the undef vector.
2838 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
2839 for (unsigned i = 0; i != NumElts; ++i)
2840 MappedOps[i] = UDVal;
2841 MappedOps[NumElts ] = *(N->getOperand(0).Val->op_end()-2);
2842 MappedOps[NumElts+1] = *(N->getOperand(0).Val->op_end()-1);
2843 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps);
2845 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
2846 N->getOperand(0), UDVal, ShufMask,
2847 MappedOps[NumElts], MappedOps[NumElts+1]);
2853 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
2854 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
2855 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
2856 /// vector_shuffle V, Zero, <0, 4, 2, 4>
2857 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
2858 SDOperand LHS = N->getOperand(0);
2859 SDOperand RHS = N->getOperand(1);
2860 if (N->getOpcode() == ISD::VAND) {
2861 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
2862 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
2863 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
2864 RHS = RHS.getOperand(0);
2865 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
2866 std::vector<SDOperand> IdxOps;
2867 unsigned NumOps = RHS.getNumOperands();
2868 unsigned NumElts = NumOps-2;
2869 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
2870 for (unsigned i = 0; i != NumElts; ++i) {
2871 SDOperand Elt = RHS.getOperand(i);
2872 if (!isa<ConstantSDNode>(Elt))
2874 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
2875 IdxOps.push_back(DAG.getConstant(i, EVT));
2876 else if (cast<ConstantSDNode>(Elt)->isNullValue())
2877 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
2882 // Let's see if the target supports this vector_shuffle.
2883 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
2886 // Return the new VVECTOR_SHUFFLE node.
2887 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
2888 SDOperand EVTNode = DAG.getValueType(EVT);
2889 std::vector<SDOperand> Ops;
2890 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, EVTNode);
2892 AddToWorkList(LHS.Val);
2893 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
2894 ZeroOps.push_back(NumEltsNode);
2895 ZeroOps.push_back(EVTNode);
2896 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps));
2897 IdxOps.push_back(NumEltsNode);
2898 IdxOps.push_back(EVTNode);
2899 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps));
2900 Ops.push_back(NumEltsNode);
2901 Ops.push_back(EVTNode);
2902 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
2903 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
2904 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
2905 DstVecSize, DstVecEVT);
2913 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
2914 /// the scalar operation of the vop if it is operating on an integer vector
2915 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
2916 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
2917 ISD::NodeType FPOp) {
2918 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
2919 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
2920 SDOperand LHS = N->getOperand(0);
2921 SDOperand RHS = N->getOperand(1);
2922 SDOperand Shuffle = XformToShuffleWithZero(N);
2923 if (Shuffle.Val) return Shuffle;
2925 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
2927 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
2928 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
2929 std::vector<SDOperand> Ops;
2930 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
2931 SDOperand LHSOp = LHS.getOperand(i);
2932 SDOperand RHSOp = RHS.getOperand(i);
2933 // If these two elements can't be folded, bail out.
2934 if ((LHSOp.getOpcode() != ISD::UNDEF &&
2935 LHSOp.getOpcode() != ISD::Constant &&
2936 LHSOp.getOpcode() != ISD::ConstantFP) ||
2937 (RHSOp.getOpcode() != ISD::UNDEF &&
2938 RHSOp.getOpcode() != ISD::Constant &&
2939 RHSOp.getOpcode() != ISD::ConstantFP))
2941 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
2942 AddToWorkList(Ops.back().Val);
2943 assert((Ops.back().getOpcode() == ISD::UNDEF ||
2944 Ops.back().getOpcode() == ISD::Constant ||
2945 Ops.back().getOpcode() == ISD::ConstantFP) &&
2946 "Scalar binop didn't fold!");
2949 if (Ops.size() == LHS.getNumOperands()-2) {
2950 Ops.push_back(*(LHS.Val->op_end()-2));
2951 Ops.push_back(*(LHS.Val->op_end()-1));
2952 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2959 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2960 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2962 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2963 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2964 // If we got a simplified select_cc node back from SimplifySelectCC, then
2965 // break it down into a new SETCC node, and a new SELECT node, and then return
2966 // the SELECT node, since we were called with a SELECT node.
2968 // Check to see if we got a select_cc back (to turn into setcc/select).
2969 // Otherwise, just return whatever node we got back, like fabs.
2970 if (SCC.getOpcode() == ISD::SELECT_CC) {
2971 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2972 SCC.getOperand(0), SCC.getOperand(1),
2974 AddToWorkList(SETCC.Val);
2975 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2976 SCC.getOperand(3), SETCC);
2983 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2984 /// are the two values being selected between, see if we can simplify the
2987 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2990 // If this is a select from two identical things, try to pull the operation
2991 // through the select.
2992 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2994 std::cerr << "SELECT: ["; LHS.Val->dump();
2995 std::cerr << "] ["; RHS.Val->dump();
2999 // If this is a load and the token chain is identical, replace the select
3000 // of two loads with a load through a select of the address to load from.
3001 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3002 // constants have been dropped into the constant pool.
3003 if ((LHS.getOpcode() == ISD::LOAD ||
3004 LHS.getOpcode() == ISD::EXTLOAD ||
3005 LHS.getOpcode() == ISD::ZEXTLOAD ||
3006 LHS.getOpcode() == ISD::SEXTLOAD) &&
3007 // Token chains must be identical.
3008 LHS.getOperand(0) == RHS.getOperand(0) &&
3009 // If this is an EXTLOAD, the VT's must match.
3010 (LHS.getOpcode() == ISD::LOAD ||
3011 LHS.getOperand(3) == RHS.getOperand(3))) {
3012 // FIXME: this conflates two src values, discarding one. This is not
3013 // the right thing to do, but nothing uses srcvalues now. When they do,
3014 // turn SrcValue into a list of locations.
3016 if (TheSelect->getOpcode() == ISD::SELECT)
3017 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
3018 TheSelect->getOperand(0), LHS.getOperand(1),
3021 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
3022 TheSelect->getOperand(0),
3023 TheSelect->getOperand(1),
3024 LHS.getOperand(1), RHS.getOperand(1),
3025 TheSelect->getOperand(4));
3028 if (LHS.getOpcode() == ISD::LOAD)
3029 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
3030 Addr, LHS.getOperand(2));
3032 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
3033 LHS.getOperand(0), Addr, LHS.getOperand(2),
3034 cast<VTSDNode>(LHS.getOperand(3))->getVT());
3035 // Users of the select now use the result of the load.
3036 CombineTo(TheSelect, Load);
3038 // Users of the old loads now use the new load's chain. We know the
3039 // old-load value is dead now.
3040 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3041 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3049 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3050 SDOperand N2, SDOperand N3,
3053 MVT::ValueType VT = N2.getValueType();
3054 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
3055 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3056 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3057 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3059 // Determine if the condition we're dealing with is constant
3060 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3061 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3063 // fold select_cc true, x, y -> x
3064 if (SCCC && SCCC->getValue())
3066 // fold select_cc false, x, y -> y
3067 if (SCCC && SCCC->getValue() == 0)
3070 // Check to see if we can simplify the select into an fabs node
3071 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3072 // Allow either -0.0 or 0.0
3073 if (CFP->getValue() == 0.0) {
3074 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3075 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3076 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3077 N2 == N3.getOperand(0))
3078 return DAG.getNode(ISD::FABS, VT, N0);
3080 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3081 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3082 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3083 N2.getOperand(0) == N3)
3084 return DAG.getNode(ISD::FABS, VT, N3);
3088 // Check to see if we can perform the "gzip trick", transforming
3089 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3090 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
3091 MVT::isInteger(N0.getValueType()) &&
3092 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
3093 MVT::ValueType XType = N0.getValueType();
3094 MVT::ValueType AType = N2.getValueType();
3095 if (XType >= AType) {
3096 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3097 // single-bit constant.
3098 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3099 unsigned ShCtV = Log2_64(N2C->getValue());
3100 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3101 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3102 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3103 AddToWorkList(Shift.Val);
3104 if (XType > AType) {
3105 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3106 AddToWorkList(Shift.Val);
3108 return DAG.getNode(ISD::AND, AType, Shift, N2);
3110 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3111 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3112 TLI.getShiftAmountTy()));
3113 AddToWorkList(Shift.Val);
3114 if (XType > AType) {
3115 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3116 AddToWorkList(Shift.Val);
3118 return DAG.getNode(ISD::AND, AType, Shift, N2);
3122 // fold select C, 16, 0 -> shl C, 4
3123 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3124 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3125 // Get a SetCC of the condition
3126 // FIXME: Should probably make sure that setcc is legal if we ever have a
3127 // target where it isn't.
3128 SDOperand Temp, SCC;
3129 // cast from setcc result type to select result type
3130 if (AfterLegalize) {
3131 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3132 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3134 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3135 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3137 AddToWorkList(SCC.Val);
3138 AddToWorkList(Temp.Val);
3139 // shl setcc result by log2 n2c
3140 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3141 DAG.getConstant(Log2_64(N2C->getValue()),
3142 TLI.getShiftAmountTy()));
3145 // Check to see if this is the equivalent of setcc
3146 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3147 // otherwise, go ahead with the folds.
3148 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3149 MVT::ValueType XType = N0.getValueType();
3150 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3151 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3152 if (Res.getValueType() != VT)
3153 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3157 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3158 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3159 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3160 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3161 return DAG.getNode(ISD::SRL, XType, Ctlz,
3162 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3163 TLI.getShiftAmountTy()));
3165 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3166 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3167 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3169 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3170 DAG.getConstant(~0ULL, XType));
3171 return DAG.getNode(ISD::SRL, XType,
3172 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3173 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3174 TLI.getShiftAmountTy()));
3176 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3177 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3178 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3179 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3180 TLI.getShiftAmountTy()));
3181 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3185 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3186 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3187 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3188 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3189 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3190 MVT::ValueType XType = N0.getValueType();
3191 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3192 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3193 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3194 TLI.getShiftAmountTy()));
3195 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3196 AddToWorkList(Shift.Val);
3197 AddToWorkList(Add.Val);
3198 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3206 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3207 SDOperand N1, ISD::CondCode Cond,
3208 bool foldBooleans) {
3209 // These setcc operations always fold.
3213 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3215 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3218 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3219 uint64_t C1 = N1C->getValue();
3220 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3221 uint64_t C0 = N0C->getValue();
3223 // Sign extend the operands if required
3224 if (ISD::isSignedIntSetCC(Cond)) {
3225 C0 = N0C->getSignExtended();
3226 C1 = N1C->getSignExtended();
3230 default: assert(0 && "Unknown integer setcc!");
3231 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3232 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3233 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
3234 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
3235 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
3236 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
3237 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
3238 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
3239 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
3240 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
3243 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3244 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3245 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3247 // If the comparison constant has bits in the upper part, the
3248 // zero-extended value could never match.
3249 if (C1 & (~0ULL << InSize)) {
3250 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3254 case ISD::SETEQ: return DAG.getConstant(0, VT);
3257 case ISD::SETNE: return DAG.getConstant(1, VT);
3260 // True if the sign bit of C1 is set.
3261 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3264 // True if the sign bit of C1 isn't set.
3265 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3271 // Otherwise, we can perform the comparison with the low bits.
3279 return DAG.getSetCC(VT, N0.getOperand(0),
3280 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3283 break; // todo, be more careful with signed comparisons
3285 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3286 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3287 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3288 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3289 MVT::ValueType ExtDstTy = N0.getValueType();
3290 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3292 // If the extended part has any inconsistent bits, it cannot ever
3293 // compare equal. In other words, they have to be all ones or all
3296 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3297 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3298 return DAG.getConstant(Cond == ISD::SETNE, VT);
3301 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3302 if (Op0Ty == ExtSrcTy) {
3303 ZextOp = N0.getOperand(0);
3305 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3306 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3307 DAG.getConstant(Imm, Op0Ty));
3309 AddToWorkList(ZextOp.Val);
3310 // Otherwise, make this a use of a zext.
3311 return DAG.getSetCC(VT, ZextOp,
3312 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3315 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3316 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3317 (N0.getOpcode() == ISD::XOR ||
3318 (N0.getOpcode() == ISD::AND &&
3319 N0.getOperand(0).getOpcode() == ISD::XOR &&
3320 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3321 isa<ConstantSDNode>(N0.getOperand(1)) &&
3322 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3323 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
3324 // only do this if the top bits are known zero.
3325 if (TLI.MaskedValueIsZero(N1,
3326 MVT::getIntVTBitMask(N0.getValueType())-1)) {
3327 // Okay, get the un-inverted input value.
3329 if (N0.getOpcode() == ISD::XOR)
3330 Val = N0.getOperand(0);
3332 assert(N0.getOpcode() == ISD::AND &&
3333 N0.getOperand(0).getOpcode() == ISD::XOR);
3334 // ((X^1)&1)^1 -> X & 1
3335 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3336 N0.getOperand(0).getOperand(0), N0.getOperand(1));
3338 return DAG.getSetCC(VT, Val, N1,
3339 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3343 uint64_t MinVal, MaxVal;
3344 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3345 if (ISD::isSignedIntSetCC(Cond)) {
3346 MinVal = 1ULL << (OperandBitSize-1);
3347 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3348 MaxVal = ~0ULL >> (65-OperandBitSize);
3353 MaxVal = ~0ULL >> (64-OperandBitSize);
3356 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3357 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3358 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3359 --C1; // X >= C0 --> X > (C0-1)
3360 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3361 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3364 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3365 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3366 ++C1; // X <= C0 --> X < (C0+1)
3367 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3368 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3371 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3372 return DAG.getConstant(0, VT); // X < MIN --> false
3374 // Canonicalize setgt X, Min --> setne X, Min
3375 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3376 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3377 // Canonicalize setlt X, Max --> setne X, Max
3378 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3379 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3381 // If we have setult X, 1, turn it into seteq X, 0
3382 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3383 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3385 // If we have setugt X, Max-1, turn it into seteq X, Max
3386 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3387 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3390 // If we have "setcc X, C0", check to see if we can shrink the immediate
3393 // SETUGT X, SINTMAX -> SETLT X, 0
3394 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3395 C1 == (~0ULL >> (65-OperandBitSize)))
3396 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3399 // FIXME: Implement the rest of these.
3401 // Fold bit comparisons when we can.
3402 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3403 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3404 if (ConstantSDNode *AndRHS =
3405 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3406 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3407 // Perform the xform if the AND RHS is a single bit.
3408 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
3409 return DAG.getNode(ISD::SRL, VT, N0,
3410 DAG.getConstant(Log2_64(AndRHS->getValue()),
3411 TLI.getShiftAmountTy()));
3413 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3414 // (X & 8) == 8 --> (X & 8) >> 3
3415 // Perform the xform if C1 is a single bit.
3416 if ((C1 & (C1-1)) == 0) {
3417 return DAG.getNode(ISD::SRL, VT, N0,
3418 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3423 } else if (isa<ConstantSDNode>(N0.Val)) {
3424 // Ensure that the constant occurs on the RHS.
3425 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3428 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
3429 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
3430 double C0 = N0C->getValue(), C1 = N1C->getValue();
3433 default: break; // FIXME: Implement the rest of these!
3434 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3435 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3436 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
3437 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
3438 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
3439 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
3442 // Ensure that the constant occurs on the RHS.
3443 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3447 // We can always fold X == Y for integer setcc's.
3448 if (MVT::isInteger(N0.getValueType()))
3449 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3450 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3451 if (UOF == 2) // FP operators that are undefined on NaNs.
3452 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3453 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3454 return DAG.getConstant(UOF, VT);
3455 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3456 // if it is not already.
3457 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3458 if (NewCond != Cond)
3459 return DAG.getSetCC(VT, N0, N1, NewCond);
3462 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3463 MVT::isInteger(N0.getValueType())) {
3464 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3465 N0.getOpcode() == ISD::XOR) {
3466 // Simplify (X+Y) == (X+Z) --> Y == Z
3467 if (N0.getOpcode() == N1.getOpcode()) {
3468 if (N0.getOperand(0) == N1.getOperand(0))
3469 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3470 if (N0.getOperand(1) == N1.getOperand(1))
3471 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3472 if (isCommutativeBinOp(N0.getOpcode())) {
3473 // If X op Y == Y op X, try other combinations.
3474 if (N0.getOperand(0) == N1.getOperand(1))
3475 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3476 if (N0.getOperand(1) == N1.getOperand(0))
3477 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3481 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3482 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3483 // Turn (X+C1) == C2 --> X == C2-C1
3484 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3485 return DAG.getSetCC(VT, N0.getOperand(0),
3486 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3487 N0.getValueType()), Cond);
3490 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3491 if (N0.getOpcode() == ISD::XOR)
3492 // If we know that all of the inverted bits are zero, don't bother
3493 // performing the inversion.
3494 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3495 return DAG.getSetCC(VT, N0.getOperand(0),
3496 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3497 N0.getValueType()), Cond);
3500 // Turn (C1-X) == C2 --> X == C1-C2
3501 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3502 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3503 return DAG.getSetCC(VT, N0.getOperand(1),
3504 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3505 N0.getValueType()), Cond);
3510 // Simplify (X+Z) == X --> Z == 0
3511 if (N0.getOperand(0) == N1)
3512 return DAG.getSetCC(VT, N0.getOperand(1),
3513 DAG.getConstant(0, N0.getValueType()), Cond);
3514 if (N0.getOperand(1) == N1) {
3515 if (isCommutativeBinOp(N0.getOpcode()))
3516 return DAG.getSetCC(VT, N0.getOperand(0),
3517 DAG.getConstant(0, N0.getValueType()), Cond);
3519 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3520 // (Z-X) == X --> Z == X<<1
3521 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3523 DAG.getConstant(1,TLI.getShiftAmountTy()));
3524 AddToWorkList(SH.Val);
3525 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3530 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3531 N1.getOpcode() == ISD::XOR) {
3532 // Simplify X == (X+Z) --> Z == 0
3533 if (N1.getOperand(0) == N0) {
3534 return DAG.getSetCC(VT, N1.getOperand(1),
3535 DAG.getConstant(0, N1.getValueType()), Cond);
3536 } else if (N1.getOperand(1) == N0) {
3537 if (isCommutativeBinOp(N1.getOpcode())) {
3538 return DAG.getSetCC(VT, N1.getOperand(0),
3539 DAG.getConstant(0, N1.getValueType()), Cond);
3541 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3542 // X == (Z-X) --> X<<1 == Z
3543 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3544 DAG.getConstant(1,TLI.getShiftAmountTy()));
3545 AddToWorkList(SH.Val);
3546 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3552 // Fold away ALL boolean setcc's.
3554 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3556 default: assert(0 && "Unknown integer setcc!");
3557 case ISD::SETEQ: // X == Y -> (X^Y)^1
3558 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3559 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3560 AddToWorkList(Temp.Val);
3562 case ISD::SETNE: // X != Y --> (X^Y)
3563 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3565 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3566 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3567 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3568 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3569 AddToWorkList(Temp.Val);
3571 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3572 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3573 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3574 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3575 AddToWorkList(Temp.Val);
3577 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3578 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3579 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3580 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3581 AddToWorkList(Temp.Val);
3583 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3584 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3585 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3586 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3589 if (VT != MVT::i1) {
3590 AddToWorkList(N0.Val);
3591 // FIXME: If running after legalize, we probably can't do this.
3592 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3597 // Could not fold it.
3601 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3602 /// return a DAG expression to select that will generate the same value by
3603 /// multiplying by a magic number. See:
3604 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3605 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3606 MVT::ValueType VT = N->getValueType(0);
3608 // Check to see if we can do this.
3609 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
3610 return SDOperand(); // BuildSDIV only operates on i32 or i64
3611 if (!TLI.isOperationLegal(ISD::MULHS, VT))
3612 return SDOperand(); // Make sure the target supports MULHS.
3614 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
3615 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
3617 // Multiply the numerator (operand 0) by the magic value
3618 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
3619 DAG.getConstant(magics.m, VT));
3620 // If d > 0 and m < 0, add the numerator
3621 if (d > 0 && magics.m < 0) {
3622 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
3623 AddToWorkList(Q.Val);
3625 // If d < 0 and m > 0, subtract the numerator.
3626 if (d < 0 && magics.m > 0) {
3627 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
3628 AddToWorkList(Q.Val);
3630 // Shift right algebraic if shift value is nonzero
3632 Q = DAG.getNode(ISD::SRA, VT, Q,
3633 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
3634 AddToWorkList(Q.Val);
3636 // Extract the sign bit and add it to the quotient
3638 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
3639 TLI.getShiftAmountTy()));
3640 AddToWorkList(T.Val);
3641 return DAG.getNode(ISD::ADD, VT, Q, T);
3644 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3645 /// return a DAG expression to select that will generate the same value by
3646 /// multiplying by a magic number. See:
3647 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3648 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3649 MVT::ValueType VT = N->getValueType(0);
3651 // Check to see if we can do this.
3652 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
3653 return SDOperand(); // BuildUDIV only operates on i32 or i64
3654 if (!TLI.isOperationLegal(ISD::MULHU, VT))
3655 return SDOperand(); // Make sure the target supports MULHU.
3657 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
3658 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
3660 // Multiply the numerator (operand 0) by the magic value
3661 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
3662 DAG.getConstant(magics.m, VT));
3663 AddToWorkList(Q.Val);
3665 if (magics.a == 0) {
3666 return DAG.getNode(ISD::SRL, VT, Q,
3667 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
3669 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
3670 AddToWorkList(NPQ.Val);
3671 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
3672 DAG.getConstant(1, TLI.getShiftAmountTy()));
3673 AddToWorkList(NPQ.Val);
3674 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
3675 AddToWorkList(NPQ.Val);
3676 return DAG.getNode(ISD::SRL, VT, NPQ,
3677 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
3681 // SelectionDAG::Combine - This is the entry point for the file.
3683 void SelectionDAG::Combine(bool RunningAfterLegalize) {
3684 /// run - This is the main entry point to this class.
3686 DAGCombiner(*this).Run(RunningAfterLegalize);