1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
41 STATISTIC(NodesCombined , "Number of dag nodes combined");
42 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
43 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
44 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
45 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
136 SDValue PromoteIntBinOp(SDValue Op);
137 SDValue PromoteIntShiftOp(SDValue Op);
138 SDValue PromoteExtend(SDValue Op);
139 bool PromoteLoad(SDValue Op);
141 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
142 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
143 ISD::NodeType ExtType);
145 /// combine - call the node-specific routine that knows how to fold each
146 /// particular type of node. If that doesn't do anything, try the
147 /// target-specific DAG combines.
148 SDValue combine(SDNode *N);
150 // Visitation implementation - Implement dag node combining for different
151 // node types. The semantics are as follows:
153 // SDValue.getNode() == 0 - No change was made
154 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
155 // otherwise - N should be replaced by the returned Operand.
157 SDValue visitTokenFactor(SDNode *N);
158 SDValue visitMERGE_VALUES(SDNode *N);
159 SDValue visitADD(SDNode *N);
160 SDValue visitSUB(SDNode *N);
161 SDValue visitADDC(SDNode *N);
162 SDValue visitADDE(SDNode *N);
163 SDValue visitMUL(SDNode *N);
164 SDValue visitSDIV(SDNode *N);
165 SDValue visitUDIV(SDNode *N);
166 SDValue visitSREM(SDNode *N);
167 SDValue visitUREM(SDNode *N);
168 SDValue visitMULHU(SDNode *N);
169 SDValue visitMULHS(SDNode *N);
170 SDValue visitSMUL_LOHI(SDNode *N);
171 SDValue visitUMUL_LOHI(SDNode *N);
172 SDValue visitSMULO(SDNode *N);
173 SDValue visitUMULO(SDNode *N);
174 SDValue visitSDIVREM(SDNode *N);
175 SDValue visitUDIVREM(SDNode *N);
176 SDValue visitAND(SDNode *N);
177 SDValue visitOR(SDNode *N);
178 SDValue visitXOR(SDNode *N);
179 SDValue SimplifyVBinOp(SDNode *N);
180 SDValue visitSHL(SDNode *N);
181 SDValue visitSRA(SDNode *N);
182 SDValue visitSRL(SDNode *N);
183 SDValue visitCTLZ(SDNode *N);
184 SDValue visitCTTZ(SDNode *N);
185 SDValue visitCTPOP(SDNode *N);
186 SDValue visitSELECT(SDNode *N);
187 SDValue visitSELECT_CC(SDNode *N);
188 SDValue visitSETCC(SDNode *N);
189 SDValue visitSIGN_EXTEND(SDNode *N);
190 SDValue visitZERO_EXTEND(SDNode *N);
191 SDValue visitANY_EXTEND(SDNode *N);
192 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
193 SDValue visitTRUNCATE(SDNode *N);
194 SDValue visitBITCAST(SDNode *N);
195 SDValue visitBUILD_PAIR(SDNode *N);
196 SDValue visitFADD(SDNode *N);
197 SDValue visitFSUB(SDNode *N);
198 SDValue visitFMUL(SDNode *N);
199 SDValue visitFDIV(SDNode *N);
200 SDValue visitFREM(SDNode *N);
201 SDValue visitFCOPYSIGN(SDNode *N);
202 SDValue visitSINT_TO_FP(SDNode *N);
203 SDValue visitUINT_TO_FP(SDNode *N);
204 SDValue visitFP_TO_SINT(SDNode *N);
205 SDValue visitFP_TO_UINT(SDNode *N);
206 SDValue visitFP_ROUND(SDNode *N);
207 SDValue visitFP_ROUND_INREG(SDNode *N);
208 SDValue visitFP_EXTEND(SDNode *N);
209 SDValue visitFNEG(SDNode *N);
210 SDValue visitFABS(SDNode *N);
211 SDValue visitBRCOND(SDNode *N);
212 SDValue visitBR_CC(SDNode *N);
213 SDValue visitLOAD(SDNode *N);
214 SDValue visitSTORE(SDNode *N);
215 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
216 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
217 SDValue visitBUILD_VECTOR(SDNode *N);
218 SDValue visitCONCAT_VECTORS(SDNode *N);
219 SDValue visitVECTOR_SHUFFLE(SDNode *N);
220 SDValue visitMEMBARRIER(SDNode *N);
222 SDValue XformToShuffleWithZero(SDNode *N);
223 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
225 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
227 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
228 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
229 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
230 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
231 SDValue N3, ISD::CondCode CC,
232 bool NotExtCompare = false);
233 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
234 DebugLoc DL, bool foldBooleans = true);
235 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
237 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
238 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
239 SDValue BuildSDIV(SDNode *N);
240 SDValue BuildUDIV(SDNode *N);
241 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
242 bool DemandHighBits = true);
243 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
244 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
245 SDValue ReduceLoadWidth(SDNode *N);
246 SDValue ReduceLoadOpStoreWidth(SDNode *N);
247 SDValue TransformFPLoadStorePair(SDNode *N);
249 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
251 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
252 /// looking for aliasing nodes and adding them to the Aliases vector.
253 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
254 SmallVector<SDValue, 8> &Aliases);
256 /// isAlias - Return true if there is any possibility that the two addresses
258 bool isAlias(SDValue Ptr1, int64_t Size1,
259 const Value *SrcValue1, int SrcValueOffset1,
260 unsigned SrcValueAlign1,
261 const MDNode *TBAAInfo1,
262 SDValue Ptr2, int64_t Size2,
263 const Value *SrcValue2, int SrcValueOffset2,
264 unsigned SrcValueAlign2,
265 const MDNode *TBAAInfo2) const;
267 /// FindAliasInfo - Extracts the relevant alias information from the memory
268 /// node. Returns true if the operand was a load.
269 bool FindAliasInfo(SDNode *N,
270 SDValue &Ptr, int64_t &Size,
271 const Value *&SrcValue, int &SrcValueOffset,
272 unsigned &SrcValueAlignment,
273 const MDNode *&TBAAInfo) const;
275 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
276 /// looking for a better chain (aliasing node.)
277 SDValue FindBetterChain(SDNode *N, SDValue Chain);
280 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
281 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
282 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
284 /// Run - runs the dag combiner on all nodes in the work list
285 void Run(CombineLevel AtLevel);
287 SelectionDAG &getDAG() const { return DAG; }
289 /// getShiftAmountTy - Returns a type large enough to hold any valid
290 /// shift amount - before type legalization these can be huge.
291 EVT getShiftAmountTy(EVT LHSTy) {
292 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
295 /// isTypeLegal - This method returns true if we are running before type
296 /// legalization or if the specified VT is legal.
297 bool isTypeLegal(const EVT &VT) {
298 if (!LegalTypes) return true;
299 return TLI.isTypeLegal(VT);
306 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
307 /// nodes from the worklist.
308 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
311 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
313 virtual void NodeDeleted(SDNode *N, SDNode *E) {
314 DC.removeFromWorkList(N);
317 virtual void NodeUpdated(SDNode *N) {
323 //===----------------------------------------------------------------------===//
324 // TargetLowering::DAGCombinerInfo implementation
325 //===----------------------------------------------------------------------===//
327 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
328 ((DAGCombiner*)DC)->AddToWorkList(N);
331 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
332 ((DAGCombiner*)DC)->removeFromWorkList(N);
335 SDValue TargetLowering::DAGCombinerInfo::
336 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
337 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
340 SDValue TargetLowering::DAGCombinerInfo::
341 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
342 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
346 SDValue TargetLowering::DAGCombinerInfo::
347 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
348 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
351 void TargetLowering::DAGCombinerInfo::
352 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
353 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
356 //===----------------------------------------------------------------------===//
358 //===----------------------------------------------------------------------===//
360 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
361 /// specified expression for the same cost as the expression itself, or 2 if we
362 /// can compute the negated form more cheaply than the expression itself.
363 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
364 unsigned Depth = 0) {
365 // No compile time optimizations on this type.
366 if (Op.getValueType() == MVT::ppcf128)
369 // fneg is removable even if it has multiple uses.
370 if (Op.getOpcode() == ISD::FNEG) return 2;
372 // Don't allow anything with multiple uses.
373 if (!Op.hasOneUse()) return 0;
375 // Don't recurse exponentially.
376 if (Depth > 6) return 0;
378 switch (Op.getOpcode()) {
379 default: return false;
380 case ISD::ConstantFP:
381 // Don't invert constant FP values after legalize. The negated constant
382 // isn't necessarily legal.
383 return LegalOperations ? 0 : 1;
385 // FIXME: determine better conditions for this xform.
386 if (!UnsafeFPMath) return 0;
388 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
389 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
391 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
392 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
394 // We can't turn -(A-B) into B-A when we honor signed zeros.
395 if (!UnsafeFPMath) return 0;
397 // fold (fneg (fsub A, B)) -> (fsub B, A)
402 if (HonorSignDependentRoundingFPMath()) return 0;
404 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
405 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
408 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
413 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
417 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
418 /// returns the newly negated expression.
419 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
420 bool LegalOperations, unsigned Depth = 0) {
421 // fneg is removable even if it has multiple uses.
422 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
424 // Don't allow anything with multiple uses.
425 assert(Op.hasOneUse() && "Unknown reuse!");
427 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
428 switch (Op.getOpcode()) {
429 default: llvm_unreachable("Unknown code");
430 case ISD::ConstantFP: {
431 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
433 return DAG.getConstantFP(V, Op.getValueType());
436 // FIXME: determine better conditions for this xform.
437 assert(UnsafeFPMath);
439 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
440 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
441 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
442 GetNegatedExpression(Op.getOperand(0), DAG,
443 LegalOperations, Depth+1),
445 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
446 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
447 GetNegatedExpression(Op.getOperand(1), DAG,
448 LegalOperations, Depth+1),
451 // We can't turn -(A-B) into B-A when we honor signed zeros.
452 assert(UnsafeFPMath);
454 // fold (fneg (fsub 0, B)) -> B
455 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
456 if (N0CFP->getValueAPF().isZero())
457 return Op.getOperand(1);
459 // fold (fneg (fsub A, B)) -> (fsub B, A)
460 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
461 Op.getOperand(1), Op.getOperand(0));
465 assert(!HonorSignDependentRoundingFPMath());
467 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
468 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
469 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
470 GetNegatedExpression(Op.getOperand(0), DAG,
471 LegalOperations, Depth+1),
474 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
475 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
477 GetNegatedExpression(Op.getOperand(1), DAG,
478 LegalOperations, Depth+1));
482 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
483 GetNegatedExpression(Op.getOperand(0), DAG,
484 LegalOperations, Depth+1));
486 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
487 GetNegatedExpression(Op.getOperand(0), DAG,
488 LegalOperations, Depth+1),
494 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
495 // that selects between the values 1 and 0, making it equivalent to a setcc.
496 // Also, set the incoming LHS, RHS, and CC references to the appropriate
497 // nodes based on the type of node we are checking. This simplifies life a
498 // bit for the callers.
499 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
501 if (N.getOpcode() == ISD::SETCC) {
502 LHS = N.getOperand(0);
503 RHS = N.getOperand(1);
504 CC = N.getOperand(2);
507 if (N.getOpcode() == ISD::SELECT_CC &&
508 N.getOperand(2).getOpcode() == ISD::Constant &&
509 N.getOperand(3).getOpcode() == ISD::Constant &&
510 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
511 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
512 LHS = N.getOperand(0);
513 RHS = N.getOperand(1);
514 CC = N.getOperand(4);
520 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
521 // one use. If this is true, it allows the users to invert the operation for
522 // free when it is profitable to do so.
523 static bool isOneUseSetCC(SDValue N) {
525 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
530 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
531 SDValue N0, SDValue N1) {
532 EVT VT = N0.getValueType();
533 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
534 if (isa<ConstantSDNode>(N1)) {
535 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
537 DAG.FoldConstantArithmetic(Opc, VT,
538 cast<ConstantSDNode>(N0.getOperand(1)),
539 cast<ConstantSDNode>(N1));
540 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
542 if (N0.hasOneUse()) {
543 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
544 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
545 N0.getOperand(0), N1);
546 AddToWorkList(OpNode.getNode());
547 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
551 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
552 if (isa<ConstantSDNode>(N0)) {
553 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
555 DAG.FoldConstantArithmetic(Opc, VT,
556 cast<ConstantSDNode>(N1.getOperand(1)),
557 cast<ConstantSDNode>(N0));
558 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
560 if (N1.hasOneUse()) {
561 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
562 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
563 N1.getOperand(0), N0);
564 AddToWorkList(OpNode.getNode());
565 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
572 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
574 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
576 DEBUG(dbgs() << "\nReplacing.1 ";
578 dbgs() << "\nWith: ";
579 To[0].getNode()->dump(&DAG);
580 dbgs() << " and " << NumTo-1 << " other values\n";
581 for (unsigned i = 0, e = NumTo; i != e; ++i)
582 assert((!To[i].getNode() ||
583 N->getValueType(i) == To[i].getValueType()) &&
584 "Cannot combine value to value of different type!"));
585 WorkListRemover DeadNodes(*this);
586 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
589 // Push the new nodes and any users onto the worklist
590 for (unsigned i = 0, e = NumTo; i != e; ++i) {
591 if (To[i].getNode()) {
592 AddToWorkList(To[i].getNode());
593 AddUsersToWorkList(To[i].getNode());
598 // Finally, if the node is now dead, remove it from the graph. The node
599 // may not be dead if the replacement process recursively simplified to
600 // something else needing this node.
601 if (N->use_empty()) {
602 // Nodes can be reintroduced into the worklist. Make sure we do not
603 // process a node that has been replaced.
604 removeFromWorkList(N);
606 // Finally, since the node is now dead, remove it from the graph.
609 return SDValue(N, 0);
613 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
614 // Replace all uses. If any nodes become isomorphic to other nodes and
615 // are deleted, make sure to remove them from our worklist.
616 WorkListRemover DeadNodes(*this);
617 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
619 // Push the new node and any (possibly new) users onto the worklist.
620 AddToWorkList(TLO.New.getNode());
621 AddUsersToWorkList(TLO.New.getNode());
623 // Finally, if the node is now dead, remove it from the graph. The node
624 // may not be dead if the replacement process recursively simplified to
625 // something else needing this node.
626 if (TLO.Old.getNode()->use_empty()) {
627 removeFromWorkList(TLO.Old.getNode());
629 // If the operands of this node are only used by the node, they will now
630 // be dead. Make sure to visit them first to delete dead nodes early.
631 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
632 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
633 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
635 DAG.DeleteNode(TLO.Old.getNode());
639 /// SimplifyDemandedBits - Check the specified integer node value to see if
640 /// it can be simplified or if things it uses can be simplified by bit
641 /// propagation. If so, return true.
642 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
643 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
644 APInt KnownZero, KnownOne;
645 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
649 AddToWorkList(Op.getNode());
651 // Replace the old value with the new one.
653 DEBUG(dbgs() << "\nReplacing.2 ";
654 TLO.Old.getNode()->dump(&DAG);
655 dbgs() << "\nWith: ";
656 TLO.New.getNode()->dump(&DAG);
659 CommitTargetLoweringOpt(TLO);
663 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
664 DebugLoc dl = Load->getDebugLoc();
665 EVT VT = Load->getValueType(0);
666 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
668 DEBUG(dbgs() << "\nReplacing.9 ";
670 dbgs() << "\nWith: ";
671 Trunc.getNode()->dump(&DAG);
673 WorkListRemover DeadNodes(*this);
674 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
675 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
677 removeFromWorkList(Load);
678 DAG.DeleteNode(Load);
679 AddToWorkList(Trunc.getNode());
682 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
684 DebugLoc dl = Op.getDebugLoc();
685 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
686 EVT MemVT = LD->getMemoryVT();
687 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
688 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
690 : LD->getExtensionType();
692 return DAG.getExtLoad(ExtType, dl, PVT,
693 LD->getChain(), LD->getBasePtr(),
694 LD->getPointerInfo(),
695 MemVT, LD->isVolatile(),
696 LD->isNonTemporal(), LD->getAlignment());
699 unsigned Opc = Op.getOpcode();
702 case ISD::AssertSext:
703 return DAG.getNode(ISD::AssertSext, dl, PVT,
704 SExtPromoteOperand(Op.getOperand(0), PVT),
706 case ISD::AssertZext:
707 return DAG.getNode(ISD::AssertZext, dl, PVT,
708 ZExtPromoteOperand(Op.getOperand(0), PVT),
710 case ISD::Constant: {
712 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
713 return DAG.getNode(ExtOpc, dl, PVT, Op);
717 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
719 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
722 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
723 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
725 EVT OldVT = Op.getValueType();
726 DebugLoc dl = Op.getDebugLoc();
727 bool Replace = false;
728 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
729 if (NewOp.getNode() == 0)
731 AddToWorkList(NewOp.getNode());
734 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
735 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
736 DAG.getValueType(OldVT));
739 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
740 EVT OldVT = Op.getValueType();
741 DebugLoc dl = Op.getDebugLoc();
742 bool Replace = false;
743 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
744 if (NewOp.getNode() == 0)
746 AddToWorkList(NewOp.getNode());
749 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
750 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
753 /// PromoteIntBinOp - Promote the specified integer binary operation if the
754 /// target indicates it is beneficial. e.g. On x86, it's usually better to
755 /// promote i16 operations to i32 since i16 instructions are longer.
756 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
757 if (!LegalOperations)
760 EVT VT = Op.getValueType();
761 if (VT.isVector() || !VT.isInteger())
764 // If operation type is 'undesirable', e.g. i16 on x86, consider
766 unsigned Opc = Op.getOpcode();
767 if (TLI.isTypeDesirableForOp(Opc, VT))
771 // Consult target whether it is a good idea to promote this operation and
772 // what's the right type to promote it to.
773 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
774 assert(PVT != VT && "Don't know what type to promote to!");
776 bool Replace0 = false;
777 SDValue N0 = Op.getOperand(0);
778 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
779 if (NN0.getNode() == 0)
782 bool Replace1 = false;
783 SDValue N1 = Op.getOperand(1);
788 NN1 = PromoteOperand(N1, PVT, Replace1);
789 if (NN1.getNode() == 0)
793 AddToWorkList(NN0.getNode());
795 AddToWorkList(NN1.getNode());
798 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
800 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
802 DEBUG(dbgs() << "\nPromoting ";
803 Op.getNode()->dump(&DAG));
804 DebugLoc dl = Op.getDebugLoc();
805 return DAG.getNode(ISD::TRUNCATE, dl, VT,
806 DAG.getNode(Opc, dl, PVT, NN0, NN1));
811 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
812 /// target indicates it is beneficial. e.g. On x86, it's usually better to
813 /// promote i16 operations to i32 since i16 instructions are longer.
814 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
815 if (!LegalOperations)
818 EVT VT = Op.getValueType();
819 if (VT.isVector() || !VT.isInteger())
822 // If operation type is 'undesirable', e.g. i16 on x86, consider
824 unsigned Opc = Op.getOpcode();
825 if (TLI.isTypeDesirableForOp(Opc, VT))
829 // Consult target whether it is a good idea to promote this operation and
830 // what's the right type to promote it to.
831 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
832 assert(PVT != VT && "Don't know what type to promote to!");
834 bool Replace = false;
835 SDValue N0 = Op.getOperand(0);
837 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
838 else if (Opc == ISD::SRL)
839 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
841 N0 = PromoteOperand(N0, PVT, Replace);
842 if (N0.getNode() == 0)
845 AddToWorkList(N0.getNode());
847 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
849 DEBUG(dbgs() << "\nPromoting ";
850 Op.getNode()->dump(&DAG));
851 DebugLoc dl = Op.getDebugLoc();
852 return DAG.getNode(ISD::TRUNCATE, dl, VT,
853 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
858 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
859 if (!LegalOperations)
862 EVT VT = Op.getValueType();
863 if (VT.isVector() || !VT.isInteger())
866 // If operation type is 'undesirable', e.g. i16 on x86, consider
868 unsigned Opc = Op.getOpcode();
869 if (TLI.isTypeDesirableForOp(Opc, VT))
873 // Consult target whether it is a good idea to promote this operation and
874 // what's the right type to promote it to.
875 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
876 assert(PVT != VT && "Don't know what type to promote to!");
877 // fold (aext (aext x)) -> (aext x)
878 // fold (aext (zext x)) -> (zext x)
879 // fold (aext (sext x)) -> (sext x)
880 DEBUG(dbgs() << "\nPromoting ";
881 Op.getNode()->dump(&DAG));
882 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
887 bool DAGCombiner::PromoteLoad(SDValue Op) {
888 if (!LegalOperations)
891 EVT VT = Op.getValueType();
892 if (VT.isVector() || !VT.isInteger())
895 // If operation type is 'undesirable', e.g. i16 on x86, consider
897 unsigned Opc = Op.getOpcode();
898 if (TLI.isTypeDesirableForOp(Opc, VT))
902 // Consult target whether it is a good idea to promote this operation and
903 // what's the right type to promote it to.
904 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
905 assert(PVT != VT && "Don't know what type to promote to!");
907 DebugLoc dl = Op.getDebugLoc();
908 SDNode *N = Op.getNode();
909 LoadSDNode *LD = cast<LoadSDNode>(N);
910 EVT MemVT = LD->getMemoryVT();
911 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
912 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
914 : LD->getExtensionType();
915 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
916 LD->getChain(), LD->getBasePtr(),
917 LD->getPointerInfo(),
918 MemVT, LD->isVolatile(),
919 LD->isNonTemporal(), LD->getAlignment());
920 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
922 DEBUG(dbgs() << "\nPromoting ";
925 Result.getNode()->dump(&DAG);
927 WorkListRemover DeadNodes(*this);
928 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
929 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
930 removeFromWorkList(N);
932 AddToWorkList(Result.getNode());
939 //===----------------------------------------------------------------------===//
940 // Main DAG Combiner implementation
941 //===----------------------------------------------------------------------===//
943 void DAGCombiner::Run(CombineLevel AtLevel) {
944 // set the instance variables, so that the various visit routines may use it.
946 LegalOperations = Level >= NoIllegalOperations;
947 LegalTypes = Level >= NoIllegalTypes;
949 // Add all the dag nodes to the worklist.
950 WorkList.reserve(DAG.allnodes_size());
951 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
952 E = DAG.allnodes_end(); I != E; ++I)
953 WorkList.push_back(I);
955 // Create a dummy node (which is not added to allnodes), that adds a reference
956 // to the root node, preventing it from being deleted, and tracking any
957 // changes of the root.
958 HandleSDNode Dummy(DAG.getRoot());
960 // The root of the dag may dangle to deleted nodes until the dag combiner is
961 // done. Set it to null to avoid confusion.
962 DAG.setRoot(SDValue());
964 // while the worklist isn't empty, inspect the node on the end of it and
965 // try and combine it.
966 while (!WorkList.empty()) {
967 SDNode *N = WorkList.back();
970 // If N has no uses, it is dead. Make sure to revisit all N's operands once
971 // N is deleted from the DAG, since they too may now be dead or may have a
972 // reduced number of uses, allowing other xforms.
973 if (N->use_empty() && N != &Dummy) {
974 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
975 AddToWorkList(N->getOperand(i).getNode());
981 SDValue RV = combine(N);
983 if (RV.getNode() == 0)
988 // If we get back the same node we passed in, rather than a new node or
989 // zero, we know that the node must have defined multiple values and
990 // CombineTo was used. Since CombineTo takes care of the worklist
991 // mechanics for us, we have no work to do in this case.
992 if (RV.getNode() == N)
995 assert(N->getOpcode() != ISD::DELETED_NODE &&
996 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
997 "Node was deleted but visit returned new node!");
999 DEBUG(dbgs() << "\nReplacing.3 ";
1001 dbgs() << "\nWith: ";
1002 RV.getNode()->dump(&DAG);
1005 // Transfer debug value.
1006 DAG.TransferDbgValues(SDValue(N, 0), RV);
1007 WorkListRemover DeadNodes(*this);
1008 if (N->getNumValues() == RV.getNode()->getNumValues())
1009 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
1011 assert(N->getValueType(0) == RV.getValueType() &&
1012 N->getNumValues() == 1 && "Type mismatch");
1014 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
1017 // Push the new node and any users onto the worklist
1018 AddToWorkList(RV.getNode());
1019 AddUsersToWorkList(RV.getNode());
1021 // Add any uses of the old node to the worklist in case this node is the
1022 // last one that uses them. They may become dead after this node is
1024 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1025 AddToWorkList(N->getOperand(i).getNode());
1027 // Finally, if the node is now dead, remove it from the graph. The node
1028 // may not be dead if the replacement process recursively simplified to
1029 // something else needing this node.
1030 if (N->use_empty()) {
1031 // Nodes can be reintroduced into the worklist. Make sure we do not
1032 // process a node that has been replaced.
1033 removeFromWorkList(N);
1035 // Finally, since the node is now dead, remove it from the graph.
1040 // If the root changed (e.g. it was a dead load, update the root).
1041 DAG.setRoot(Dummy.getValue());
1044 SDValue DAGCombiner::visit(SDNode *N) {
1045 switch (N->getOpcode()) {
1047 case ISD::TokenFactor: return visitTokenFactor(N);
1048 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1049 case ISD::ADD: return visitADD(N);
1050 case ISD::SUB: return visitSUB(N);
1051 case ISD::ADDC: return visitADDC(N);
1052 case ISD::ADDE: return visitADDE(N);
1053 case ISD::MUL: return visitMUL(N);
1054 case ISD::SDIV: return visitSDIV(N);
1055 case ISD::UDIV: return visitUDIV(N);
1056 case ISD::SREM: return visitSREM(N);
1057 case ISD::UREM: return visitUREM(N);
1058 case ISD::MULHU: return visitMULHU(N);
1059 case ISD::MULHS: return visitMULHS(N);
1060 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1061 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1062 case ISD::SMULO: return visitSMULO(N);
1063 case ISD::UMULO: return visitUMULO(N);
1064 case ISD::SDIVREM: return visitSDIVREM(N);
1065 case ISD::UDIVREM: return visitUDIVREM(N);
1066 case ISD::AND: return visitAND(N);
1067 case ISD::OR: return visitOR(N);
1068 case ISD::XOR: return visitXOR(N);
1069 case ISD::SHL: return visitSHL(N);
1070 case ISD::SRA: return visitSRA(N);
1071 case ISD::SRL: return visitSRL(N);
1072 case ISD::CTLZ: return visitCTLZ(N);
1073 case ISD::CTTZ: return visitCTTZ(N);
1074 case ISD::CTPOP: return visitCTPOP(N);
1075 case ISD::SELECT: return visitSELECT(N);
1076 case ISD::SELECT_CC: return visitSELECT_CC(N);
1077 case ISD::SETCC: return visitSETCC(N);
1078 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1079 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1080 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1081 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1082 case ISD::TRUNCATE: return visitTRUNCATE(N);
1083 case ISD::BITCAST: return visitBITCAST(N);
1084 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1085 case ISD::FADD: return visitFADD(N);
1086 case ISD::FSUB: return visitFSUB(N);
1087 case ISD::FMUL: return visitFMUL(N);
1088 case ISD::FDIV: return visitFDIV(N);
1089 case ISD::FREM: return visitFREM(N);
1090 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1091 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1092 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1093 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1094 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1095 case ISD::FP_ROUND: return visitFP_ROUND(N);
1096 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1097 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1098 case ISD::FNEG: return visitFNEG(N);
1099 case ISD::FABS: return visitFABS(N);
1100 case ISD::BRCOND: return visitBRCOND(N);
1101 case ISD::BR_CC: return visitBR_CC(N);
1102 case ISD::LOAD: return visitLOAD(N);
1103 case ISD::STORE: return visitSTORE(N);
1104 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1105 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1106 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1107 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1108 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1109 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1114 SDValue DAGCombiner::combine(SDNode *N) {
1115 SDValue RV = visit(N);
1117 // If nothing happened, try a target-specific DAG combine.
1118 if (RV.getNode() == 0) {
1119 assert(N->getOpcode() != ISD::DELETED_NODE &&
1120 "Node was deleted but visit returned NULL!");
1122 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1123 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1125 // Expose the DAG combiner to the target combiner impls.
1126 TargetLowering::DAGCombinerInfo
1127 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1129 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1133 // If nothing happened still, try promoting the operation.
1134 if (RV.getNode() == 0) {
1135 switch (N->getOpcode()) {
1143 RV = PromoteIntBinOp(SDValue(N, 0));
1148 RV = PromoteIntShiftOp(SDValue(N, 0));
1150 case ISD::SIGN_EXTEND:
1151 case ISD::ZERO_EXTEND:
1152 case ISD::ANY_EXTEND:
1153 RV = PromoteExtend(SDValue(N, 0));
1156 if (PromoteLoad(SDValue(N, 0)))
1162 // If N is a commutative binary node, try commuting it to enable more
1164 if (RV.getNode() == 0 &&
1165 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1166 N->getNumValues() == 1) {
1167 SDValue N0 = N->getOperand(0);
1168 SDValue N1 = N->getOperand(1);
1170 // Constant operands are canonicalized to RHS.
1171 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1172 SDValue Ops[] = { N1, N0 };
1173 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1176 return SDValue(CSENode, 0);
1183 /// getInputChainForNode - Given a node, return its input chain if it has one,
1184 /// otherwise return a null sd operand.
1185 static SDValue getInputChainForNode(SDNode *N) {
1186 if (unsigned NumOps = N->getNumOperands()) {
1187 if (N->getOperand(0).getValueType() == MVT::Other)
1188 return N->getOperand(0);
1189 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1190 return N->getOperand(NumOps-1);
1191 for (unsigned i = 1; i < NumOps-1; ++i)
1192 if (N->getOperand(i).getValueType() == MVT::Other)
1193 return N->getOperand(i);
1198 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1199 // If N has two operands, where one has an input chain equal to the other,
1200 // the 'other' chain is redundant.
1201 if (N->getNumOperands() == 2) {
1202 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1203 return N->getOperand(0);
1204 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1205 return N->getOperand(1);
1208 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1209 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1210 SmallPtrSet<SDNode*, 16> SeenOps;
1211 bool Changed = false; // If we should replace this token factor.
1213 // Start out with this token factor.
1216 // Iterate through token factors. The TFs grows when new token factors are
1218 for (unsigned i = 0; i < TFs.size(); ++i) {
1219 SDNode *TF = TFs[i];
1221 // Check each of the operands.
1222 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1223 SDValue Op = TF->getOperand(i);
1225 switch (Op.getOpcode()) {
1226 case ISD::EntryToken:
1227 // Entry tokens don't need to be added to the list. They are
1232 case ISD::TokenFactor:
1233 if (Op.hasOneUse() &&
1234 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1235 // Queue up for processing.
1236 TFs.push_back(Op.getNode());
1237 // Clean up in case the token factor is removed.
1238 AddToWorkList(Op.getNode());
1245 // Only add if it isn't already in the list.
1246 if (SeenOps.insert(Op.getNode()))
1257 // If we've change things around then replace token factor.
1260 // The entry token is the only possible outcome.
1261 Result = DAG.getEntryNode();
1263 // New and improved token factor.
1264 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1265 MVT::Other, &Ops[0], Ops.size());
1268 // Don't add users to work list.
1269 return CombineTo(N, Result, false);
1275 /// MERGE_VALUES can always be eliminated.
1276 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1277 WorkListRemover DeadNodes(*this);
1278 // Replacing results may cause a different MERGE_VALUES to suddenly
1279 // be CSE'd with N, and carry its uses with it. Iterate until no
1280 // uses remain, to ensure that the node can be safely deleted.
1282 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1283 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1285 } while (!N->use_empty());
1286 removeFromWorkList(N);
1288 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1292 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1293 SelectionDAG &DAG) {
1294 EVT VT = N0.getValueType();
1295 SDValue N00 = N0.getOperand(0);
1296 SDValue N01 = N0.getOperand(1);
1297 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1299 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1300 isa<ConstantSDNode>(N00.getOperand(1))) {
1301 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1302 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1303 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1304 N00.getOperand(0), N01),
1305 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1306 N00.getOperand(1), N01));
1307 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1313 SDValue DAGCombiner::visitADD(SDNode *N) {
1314 SDValue N0 = N->getOperand(0);
1315 SDValue N1 = N->getOperand(1);
1316 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1317 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1318 EVT VT = N0.getValueType();
1321 if (VT.isVector()) {
1322 SDValue FoldedVOp = SimplifyVBinOp(N);
1323 if (FoldedVOp.getNode()) return FoldedVOp;
1326 // fold (add x, undef) -> undef
1327 if (N0.getOpcode() == ISD::UNDEF)
1329 if (N1.getOpcode() == ISD::UNDEF)
1331 // fold (add c1, c2) -> c1+c2
1333 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1334 // canonicalize constant to RHS
1336 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1337 // fold (add x, 0) -> x
1338 if (N1C && N1C->isNullValue())
1340 // fold (add Sym, c) -> Sym+c
1341 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1342 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1343 GA->getOpcode() == ISD::GlobalAddress)
1344 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1346 (uint64_t)N1C->getSExtValue());
1347 // fold ((c1-A)+c2) -> (c1+c2)-A
1348 if (N1C && N0.getOpcode() == ISD::SUB)
1349 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1350 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1351 DAG.getConstant(N1C->getAPIntValue()+
1352 N0C->getAPIntValue(), VT),
1355 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1356 if (RADD.getNode() != 0)
1358 // fold ((0-A) + B) -> B-A
1359 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1360 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1361 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1362 // fold (A + (0-B)) -> A-B
1363 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1364 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1365 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1366 // fold (A+(B-A)) -> B
1367 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1368 return N1.getOperand(0);
1369 // fold ((B-A)+A) -> B
1370 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1371 return N0.getOperand(0);
1372 // fold (A+(B-(A+C))) to (B-C)
1373 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1374 N0 == N1.getOperand(1).getOperand(0))
1375 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1376 N1.getOperand(1).getOperand(1));
1377 // fold (A+(B-(C+A))) to (B-C)
1378 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1379 N0 == N1.getOperand(1).getOperand(1))
1380 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1381 N1.getOperand(1).getOperand(0));
1382 // fold (A+((B-A)+or-C)) to (B+or-C)
1383 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1384 N1.getOperand(0).getOpcode() == ISD::SUB &&
1385 N0 == N1.getOperand(0).getOperand(1))
1386 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1387 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1389 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1390 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1391 SDValue N00 = N0.getOperand(0);
1392 SDValue N01 = N0.getOperand(1);
1393 SDValue N10 = N1.getOperand(0);
1394 SDValue N11 = N1.getOperand(1);
1396 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1397 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1398 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1399 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1402 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1403 return SDValue(N, 0);
1405 // fold (a+b) -> (a|b) iff a and b share no bits.
1406 if (VT.isInteger() && !VT.isVector()) {
1407 APInt LHSZero, LHSOne;
1408 APInt RHSZero, RHSOne;
1409 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1410 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1412 if (LHSZero.getBoolValue()) {
1413 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1415 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1416 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1417 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1418 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1419 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1423 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1424 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1425 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1426 if (Result.getNode()) return Result;
1428 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1429 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1430 if (Result.getNode()) return Result;
1433 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1434 if (N1.getOpcode() == ISD::SHL &&
1435 N1.getOperand(0).getOpcode() == ISD::SUB)
1436 if (ConstantSDNode *C =
1437 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1438 if (C->getAPIntValue() == 0)
1439 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1440 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1441 N1.getOperand(0).getOperand(1),
1443 if (N0.getOpcode() == ISD::SHL &&
1444 N0.getOperand(0).getOpcode() == ISD::SUB)
1445 if (ConstantSDNode *C =
1446 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1447 if (C->getAPIntValue() == 0)
1448 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1449 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1450 N0.getOperand(0).getOperand(1),
1453 if (N1.getOpcode() == ISD::AND) {
1454 SDValue AndOp0 = N1.getOperand(0);
1455 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1456 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1457 unsigned DestBits = VT.getScalarType().getSizeInBits();
1459 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1460 // and similar xforms where the inner op is either ~0 or 0.
1461 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1462 DebugLoc DL = N->getDebugLoc();
1463 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1467 // add (sext i1), X -> sub X, (zext i1)
1468 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1469 N0.getOperand(0).getValueType() == MVT::i1 &&
1470 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1471 DebugLoc DL = N->getDebugLoc();
1472 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1473 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1479 SDValue DAGCombiner::visitADDC(SDNode *N) {
1480 SDValue N0 = N->getOperand(0);
1481 SDValue N1 = N->getOperand(1);
1482 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1483 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1484 EVT VT = N0.getValueType();
1486 // If the flag result is dead, turn this into an ADD.
1487 if (N->hasNUsesOfValue(0, 1))
1488 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1489 DAG.getNode(ISD::CARRY_FALSE,
1490 N->getDebugLoc(), MVT::Glue));
1492 // canonicalize constant to RHS.
1494 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1496 // fold (addc x, 0) -> x + no carry out
1497 if (N1C && N1C->isNullValue())
1498 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1499 N->getDebugLoc(), MVT::Glue));
1501 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1502 APInt LHSZero, LHSOne;
1503 APInt RHSZero, RHSOne;
1504 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1505 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1507 if (LHSZero.getBoolValue()) {
1508 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1510 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1511 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1512 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1513 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1514 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1515 DAG.getNode(ISD::CARRY_FALSE,
1516 N->getDebugLoc(), MVT::Glue));
1522 SDValue DAGCombiner::visitADDE(SDNode *N) {
1523 SDValue N0 = N->getOperand(0);
1524 SDValue N1 = N->getOperand(1);
1525 SDValue CarryIn = N->getOperand(2);
1526 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1527 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1529 // canonicalize constant to RHS
1531 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1534 // fold (adde x, y, false) -> (addc x, y)
1535 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1536 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1541 // Since it may not be valid to emit a fold to zero for vector initializers
1542 // check if we can before folding.
1543 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1544 SelectionDAG &DAG, bool LegalOperations) {
1545 if (!VT.isVector()) {
1546 return DAG.getConstant(0, VT);
1548 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1549 // Produce a vector of zeros.
1550 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1551 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1552 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1553 &Ops[0], Ops.size());
1558 SDValue DAGCombiner::visitSUB(SDNode *N) {
1559 SDValue N0 = N->getOperand(0);
1560 SDValue N1 = N->getOperand(1);
1561 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1562 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1563 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1564 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1565 EVT VT = N0.getValueType();
1568 if (VT.isVector()) {
1569 SDValue FoldedVOp = SimplifyVBinOp(N);
1570 if (FoldedVOp.getNode()) return FoldedVOp;
1573 // fold (sub x, x) -> 0
1574 // FIXME: Refactor this and xor and other similar operations together.
1576 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1577 // fold (sub c1, c2) -> c1-c2
1579 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1580 // fold (sub x, c) -> (add x, -c)
1582 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1583 DAG.getConstant(-N1C->getAPIntValue(), VT));
1584 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1585 if (N0C && N0C->isAllOnesValue())
1586 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1587 // fold A-(A-B) -> B
1588 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1589 return N1.getOperand(1);
1590 // fold (A+B)-A -> B
1591 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1592 return N0.getOperand(1);
1593 // fold (A+B)-B -> A
1594 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1595 return N0.getOperand(0);
1596 // fold C2-(A+C1) -> (C2-C1)-A
1597 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1598 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
1599 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1602 // fold ((A+(B+or-C))-B) -> A+or-C
1603 if (N0.getOpcode() == ISD::ADD &&
1604 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1605 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1606 N0.getOperand(1).getOperand(0) == N1)
1607 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1608 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1609 // fold ((A+(C+B))-B) -> A+C
1610 if (N0.getOpcode() == ISD::ADD &&
1611 N0.getOperand(1).getOpcode() == ISD::ADD &&
1612 N0.getOperand(1).getOperand(1) == N1)
1613 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1614 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1615 // fold ((A-(B-C))-C) -> A-B
1616 if (N0.getOpcode() == ISD::SUB &&
1617 N0.getOperand(1).getOpcode() == ISD::SUB &&
1618 N0.getOperand(1).getOperand(1) == N1)
1619 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1620 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1622 // If either operand of a sub is undef, the result is undef
1623 if (N0.getOpcode() == ISD::UNDEF)
1625 if (N1.getOpcode() == ISD::UNDEF)
1628 // If the relocation model supports it, consider symbol offsets.
1629 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1630 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1631 // fold (sub Sym, c) -> Sym-c
1632 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1633 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1635 (uint64_t)N1C->getSExtValue());
1636 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1637 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1638 if (GA->getGlobal() == GB->getGlobal())
1639 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1646 SDValue DAGCombiner::visitMUL(SDNode *N) {
1647 SDValue N0 = N->getOperand(0);
1648 SDValue N1 = N->getOperand(1);
1649 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1650 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1651 EVT VT = N0.getValueType();
1654 if (VT.isVector()) {
1655 SDValue FoldedVOp = SimplifyVBinOp(N);
1656 if (FoldedVOp.getNode()) return FoldedVOp;
1659 // fold (mul x, undef) -> 0
1660 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1661 return DAG.getConstant(0, VT);
1662 // fold (mul c1, c2) -> c1*c2
1664 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1665 // canonicalize constant to RHS
1667 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1668 // fold (mul x, 0) -> 0
1669 if (N1C && N1C->isNullValue())
1671 // fold (mul x, -1) -> 0-x
1672 if (N1C && N1C->isAllOnesValue())
1673 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1674 DAG.getConstant(0, VT), N0);
1675 // fold (mul x, (1 << c)) -> x << c
1676 if (N1C && N1C->getAPIntValue().isPowerOf2())
1677 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1678 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1679 getShiftAmountTy(N0.getValueType())));
1680 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1681 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1682 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1683 // FIXME: If the input is something that is easily negated (e.g. a
1684 // single-use add), we should put the negate there.
1685 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1686 DAG.getConstant(0, VT),
1687 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1688 DAG.getConstant(Log2Val,
1689 getShiftAmountTy(N0.getValueType()))));
1691 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1692 if (N1C && N0.getOpcode() == ISD::SHL &&
1693 isa<ConstantSDNode>(N0.getOperand(1))) {
1694 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1695 N1, N0.getOperand(1));
1696 AddToWorkList(C3.getNode());
1697 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1698 N0.getOperand(0), C3);
1701 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1704 SDValue Sh(0,0), Y(0,0);
1705 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1706 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1707 N0.getNode()->hasOneUse()) {
1709 } else if (N1.getOpcode() == ISD::SHL &&
1710 isa<ConstantSDNode>(N1.getOperand(1)) &&
1711 N1.getNode()->hasOneUse()) {
1716 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1717 Sh.getOperand(0), Y);
1718 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1719 Mul, Sh.getOperand(1));
1723 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1724 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1725 isa<ConstantSDNode>(N0.getOperand(1)))
1726 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1727 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1728 N0.getOperand(0), N1),
1729 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1730 N0.getOperand(1), N1));
1733 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1734 if (RMUL.getNode() != 0)
1740 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1741 SDValue N0 = N->getOperand(0);
1742 SDValue N1 = N->getOperand(1);
1743 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1744 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1745 EVT VT = N->getValueType(0);
1748 if (VT.isVector()) {
1749 SDValue FoldedVOp = SimplifyVBinOp(N);
1750 if (FoldedVOp.getNode()) return FoldedVOp;
1753 // fold (sdiv c1, c2) -> c1/c2
1754 if (N0C && N1C && !N1C->isNullValue())
1755 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1756 // fold (sdiv X, 1) -> X
1757 if (N1C && N1C->getSExtValue() == 1LL)
1759 // fold (sdiv X, -1) -> 0-X
1760 if (N1C && N1C->isAllOnesValue())
1761 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1762 DAG.getConstant(0, VT), N0);
1763 // If we know the sign bits of both operands are zero, strength reduce to a
1764 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1765 if (!VT.isVector()) {
1766 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1767 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1770 // fold (sdiv X, pow2) -> simple ops after legalize
1771 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1772 (isPowerOf2_64(N1C->getSExtValue()) ||
1773 isPowerOf2_64(-N1C->getSExtValue()))) {
1774 // If dividing by powers of two is cheap, then don't perform the following
1776 if (TLI.isPow2DivCheap())
1779 int64_t pow2 = N1C->getSExtValue();
1780 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1781 unsigned lg2 = Log2_64(abs2);
1783 // Splat the sign bit into the register
1784 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1785 DAG.getConstant(VT.getSizeInBits()-1,
1786 getShiftAmountTy(N0.getValueType())));
1787 AddToWorkList(SGN.getNode());
1789 // Add (N0 < 0) ? abs2 - 1 : 0;
1790 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1791 DAG.getConstant(VT.getSizeInBits() - lg2,
1792 getShiftAmountTy(SGN.getValueType())));
1793 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1794 AddToWorkList(SRL.getNode());
1795 AddToWorkList(ADD.getNode()); // Divide by pow2
1796 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1797 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1799 // If we're dividing by a positive value, we're done. Otherwise, we must
1800 // negate the result.
1804 AddToWorkList(SRA.getNode());
1805 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1806 DAG.getConstant(0, VT), SRA);
1809 // if integer divide is expensive and we satisfy the requirements, emit an
1810 // alternate sequence.
1811 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1812 !TLI.isIntDivCheap()) {
1813 SDValue Op = BuildSDIV(N);
1814 if (Op.getNode()) return Op;
1818 if (N0.getOpcode() == ISD::UNDEF)
1819 return DAG.getConstant(0, VT);
1820 // X / undef -> undef
1821 if (N1.getOpcode() == ISD::UNDEF)
1827 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1828 SDValue N0 = N->getOperand(0);
1829 SDValue N1 = N->getOperand(1);
1830 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1831 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1832 EVT VT = N->getValueType(0);
1835 if (VT.isVector()) {
1836 SDValue FoldedVOp = SimplifyVBinOp(N);
1837 if (FoldedVOp.getNode()) return FoldedVOp;
1840 // fold (udiv c1, c2) -> c1/c2
1841 if (N0C && N1C && !N1C->isNullValue())
1842 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1843 // fold (udiv x, (1 << c)) -> x >>u c
1844 if (N1C && N1C->getAPIntValue().isPowerOf2())
1845 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1846 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1847 getShiftAmountTy(N0.getValueType())));
1848 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1849 if (N1.getOpcode() == ISD::SHL) {
1850 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1851 if (SHC->getAPIntValue().isPowerOf2()) {
1852 EVT ADDVT = N1.getOperand(1).getValueType();
1853 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1855 DAG.getConstant(SHC->getAPIntValue()
1858 AddToWorkList(Add.getNode());
1859 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1863 // fold (udiv x, c) -> alternate
1864 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1865 SDValue Op = BuildUDIV(N);
1866 if (Op.getNode()) return Op;
1870 if (N0.getOpcode() == ISD::UNDEF)
1871 return DAG.getConstant(0, VT);
1872 // X / undef -> undef
1873 if (N1.getOpcode() == ISD::UNDEF)
1879 SDValue DAGCombiner::visitSREM(SDNode *N) {
1880 SDValue N0 = N->getOperand(0);
1881 SDValue N1 = N->getOperand(1);
1882 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1883 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1884 EVT VT = N->getValueType(0);
1886 // fold (srem c1, c2) -> c1%c2
1887 if (N0C && N1C && !N1C->isNullValue())
1888 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1889 // If we know the sign bits of both operands are zero, strength reduce to a
1890 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1891 if (!VT.isVector()) {
1892 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1893 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1896 // If X/C can be simplified by the division-by-constant logic, lower
1897 // X%C to the equivalent of X-X/C*C.
1898 if (N1C && !N1C->isNullValue()) {
1899 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1900 AddToWorkList(Div.getNode());
1901 SDValue OptimizedDiv = combine(Div.getNode());
1902 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1903 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1905 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1906 AddToWorkList(Mul.getNode());
1912 if (N0.getOpcode() == ISD::UNDEF)
1913 return DAG.getConstant(0, VT);
1914 // X % undef -> undef
1915 if (N1.getOpcode() == ISD::UNDEF)
1921 SDValue DAGCombiner::visitUREM(SDNode *N) {
1922 SDValue N0 = N->getOperand(0);
1923 SDValue N1 = N->getOperand(1);
1924 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1925 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1926 EVT VT = N->getValueType(0);
1928 // fold (urem c1, c2) -> c1%c2
1929 if (N0C && N1C && !N1C->isNullValue())
1930 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1931 // fold (urem x, pow2) -> (and x, pow2-1)
1932 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1933 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1934 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1935 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1936 if (N1.getOpcode() == ISD::SHL) {
1937 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1938 if (SHC->getAPIntValue().isPowerOf2()) {
1940 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1941 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1943 AddToWorkList(Add.getNode());
1944 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1949 // If X/C can be simplified by the division-by-constant logic, lower
1950 // X%C to the equivalent of X-X/C*C.
1951 if (N1C && !N1C->isNullValue()) {
1952 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1953 AddToWorkList(Div.getNode());
1954 SDValue OptimizedDiv = combine(Div.getNode());
1955 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1956 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1958 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1959 AddToWorkList(Mul.getNode());
1965 if (N0.getOpcode() == ISD::UNDEF)
1966 return DAG.getConstant(0, VT);
1967 // X % undef -> undef
1968 if (N1.getOpcode() == ISD::UNDEF)
1974 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1975 SDValue N0 = N->getOperand(0);
1976 SDValue N1 = N->getOperand(1);
1977 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1978 EVT VT = N->getValueType(0);
1979 DebugLoc DL = N->getDebugLoc();
1981 // fold (mulhs x, 0) -> 0
1982 if (N1C && N1C->isNullValue())
1984 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1985 if (N1C && N1C->getAPIntValue() == 1)
1986 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1987 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1988 getShiftAmountTy(N0.getValueType())));
1989 // fold (mulhs x, undef) -> 0
1990 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1991 return DAG.getConstant(0, VT);
1993 // If the type twice as wide is legal, transform the mulhs to a wider multiply
1995 if (VT.isSimple() && !VT.isVector()) {
1996 MVT Simple = VT.getSimpleVT();
1997 unsigned SimpleSize = Simple.getSizeInBits();
1998 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
1999 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2000 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2001 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2002 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2003 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2004 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2005 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2012 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2013 SDValue N0 = N->getOperand(0);
2014 SDValue N1 = N->getOperand(1);
2015 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2016 EVT VT = N->getValueType(0);
2017 DebugLoc DL = N->getDebugLoc();
2019 // fold (mulhu x, 0) -> 0
2020 if (N1C && N1C->isNullValue())
2022 // fold (mulhu x, 1) -> 0
2023 if (N1C && N1C->getAPIntValue() == 1)
2024 return DAG.getConstant(0, N0.getValueType());
2025 // fold (mulhu x, undef) -> 0
2026 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2027 return DAG.getConstant(0, VT);
2029 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2031 if (VT.isSimple() && !VT.isVector()) {
2032 MVT Simple = VT.getSimpleVT();
2033 unsigned SimpleSize = Simple.getSizeInBits();
2034 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2035 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2036 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2037 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2038 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2039 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2040 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2041 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2048 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2049 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2050 /// that are being performed. Return true if a simplification was made.
2052 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2054 // If the high half is not needed, just compute the low half.
2055 bool HiExists = N->hasAnyUseOfValue(1);
2057 (!LegalOperations ||
2058 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2059 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2060 N->op_begin(), N->getNumOperands());
2061 return CombineTo(N, Res, Res);
2064 // If the low half is not needed, just compute the high half.
2065 bool LoExists = N->hasAnyUseOfValue(0);
2067 (!LegalOperations ||
2068 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2069 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2070 N->op_begin(), N->getNumOperands());
2071 return CombineTo(N, Res, Res);
2074 // If both halves are used, return as it is.
2075 if (LoExists && HiExists)
2078 // If the two computed results can be simplified separately, separate them.
2080 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2081 N->op_begin(), N->getNumOperands());
2082 AddToWorkList(Lo.getNode());
2083 SDValue LoOpt = combine(Lo.getNode());
2084 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2085 (!LegalOperations ||
2086 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2087 return CombineTo(N, LoOpt, LoOpt);
2091 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2092 N->op_begin(), N->getNumOperands());
2093 AddToWorkList(Hi.getNode());
2094 SDValue HiOpt = combine(Hi.getNode());
2095 if (HiOpt.getNode() && HiOpt != Hi &&
2096 (!LegalOperations ||
2097 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2098 return CombineTo(N, HiOpt, HiOpt);
2104 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2105 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2106 if (Res.getNode()) return Res;
2108 EVT VT = N->getValueType(0);
2109 DebugLoc DL = N->getDebugLoc();
2111 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2113 if (VT.isSimple() && !VT.isVector()) {
2114 MVT Simple = VT.getSimpleVT();
2115 unsigned SimpleSize = Simple.getSizeInBits();
2116 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2117 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2118 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2119 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2120 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2121 // Compute the high part as N1.
2122 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2123 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2124 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2125 // Compute the low part as N0.
2126 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2127 return CombineTo(N, Lo, Hi);
2134 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2135 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2136 if (Res.getNode()) return Res;
2138 EVT VT = N->getValueType(0);
2139 DebugLoc DL = N->getDebugLoc();
2141 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2143 if (VT.isSimple() && !VT.isVector()) {
2144 MVT Simple = VT.getSimpleVT();
2145 unsigned SimpleSize = Simple.getSizeInBits();
2146 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2147 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2148 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2149 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2150 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2151 // Compute the high part as N1.
2152 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2153 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2154 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2155 // Compute the low part as N0.
2156 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2157 return CombineTo(N, Lo, Hi);
2164 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2165 // (smulo x, 2) -> (saddo x, x)
2166 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2167 if (C2->getAPIntValue() == 2)
2168 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2169 N->getOperand(0), N->getOperand(0));
2174 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2175 // (umulo x, 2) -> (uaddo x, x)
2176 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2177 if (C2->getAPIntValue() == 2)
2178 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2179 N->getOperand(0), N->getOperand(0));
2184 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2185 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2186 if (Res.getNode()) return Res;
2191 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2192 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2193 if (Res.getNode()) return Res;
2198 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2199 /// two operands of the same opcode, try to simplify it.
2200 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2201 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2202 EVT VT = N0.getValueType();
2203 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2205 // Bail early if none of these transforms apply.
2206 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2208 // For each of OP in AND/OR/XOR:
2209 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2210 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2211 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2212 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2214 // do not sink logical op inside of a vector extend, since it may combine
2216 EVT Op0VT = N0.getOperand(0).getValueType();
2217 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2218 N0.getOpcode() == ISD::SIGN_EXTEND ||
2219 // Avoid infinite looping with PromoteIntBinOp.
2220 (N0.getOpcode() == ISD::ANY_EXTEND &&
2221 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2222 (N0.getOpcode() == ISD::TRUNCATE &&
2223 (!TLI.isZExtFree(VT, Op0VT) ||
2224 !TLI.isTruncateFree(Op0VT, VT)) &&
2225 TLI.isTypeLegal(Op0VT))) &&
2227 Op0VT == N1.getOperand(0).getValueType() &&
2228 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2229 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2230 N0.getOperand(0).getValueType(),
2231 N0.getOperand(0), N1.getOperand(0));
2232 AddToWorkList(ORNode.getNode());
2233 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2236 // For each of OP in SHL/SRL/SRA/AND...
2237 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2238 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2239 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2240 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2241 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2242 N0.getOperand(1) == N1.getOperand(1)) {
2243 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2244 N0.getOperand(0).getValueType(),
2245 N0.getOperand(0), N1.getOperand(0));
2246 AddToWorkList(ORNode.getNode());
2247 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2248 ORNode, N0.getOperand(1));
2254 SDValue DAGCombiner::visitAND(SDNode *N) {
2255 SDValue N0 = N->getOperand(0);
2256 SDValue N1 = N->getOperand(1);
2257 SDValue LL, LR, RL, RR, CC0, CC1;
2258 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2259 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2260 EVT VT = N1.getValueType();
2261 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2264 if (VT.isVector()) {
2265 SDValue FoldedVOp = SimplifyVBinOp(N);
2266 if (FoldedVOp.getNode()) return FoldedVOp;
2269 // fold (and x, undef) -> 0
2270 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2271 return DAG.getConstant(0, VT);
2272 // fold (and c1, c2) -> c1&c2
2274 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2275 // canonicalize constant to RHS
2277 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2278 // fold (and x, -1) -> x
2279 if (N1C && N1C->isAllOnesValue())
2281 // if (and x, c) is known to be zero, return 0
2282 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2283 APInt::getAllOnesValue(BitWidth)))
2284 return DAG.getConstant(0, VT);
2286 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2287 if (RAND.getNode() != 0)
2289 // fold (and (or x, C), D) -> D if (C & D) == D
2290 if (N1C && N0.getOpcode() == ISD::OR)
2291 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2292 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2294 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2295 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2296 SDValue N0Op0 = N0.getOperand(0);
2297 APInt Mask = ~N1C->getAPIntValue();
2298 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2299 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2300 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2301 N0.getValueType(), N0Op0);
2303 // Replace uses of the AND with uses of the Zero extend node.
2306 // We actually want to replace all uses of the any_extend with the
2307 // zero_extend, to avoid duplicating things. This will later cause this
2308 // AND to be folded.
2309 CombineTo(N0.getNode(), Zext);
2310 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2313 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2314 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2315 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2316 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2318 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2319 LL.getValueType().isInteger()) {
2320 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2321 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2322 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2323 LR.getValueType(), LL, RL);
2324 AddToWorkList(ORNode.getNode());
2325 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2327 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2328 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2329 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2330 LR.getValueType(), LL, RL);
2331 AddToWorkList(ANDNode.getNode());
2332 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2334 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2335 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2336 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2337 LR.getValueType(), LL, RL);
2338 AddToWorkList(ORNode.getNode());
2339 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2342 // canonicalize equivalent to ll == rl
2343 if (LL == RR && LR == RL) {
2344 Op1 = ISD::getSetCCSwappedOperands(Op1);
2347 if (LL == RL && LR == RR) {
2348 bool isInteger = LL.getValueType().isInteger();
2349 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2350 if (Result != ISD::SETCC_INVALID &&
2351 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2352 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2357 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2358 if (N0.getOpcode() == N1.getOpcode()) {
2359 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2360 if (Tmp.getNode()) return Tmp;
2363 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2364 // fold (and (sra)) -> (and (srl)) when possible.
2365 if (!VT.isVector() &&
2366 SimplifyDemandedBits(SDValue(N, 0)))
2367 return SDValue(N, 0);
2369 // fold (zext_inreg (extload x)) -> (zextload x)
2370 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2371 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2372 EVT MemVT = LN0->getMemoryVT();
2373 // If we zero all the possible extended bits, then we can turn this into
2374 // a zextload if we are running before legalize or the operation is legal.
2375 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2376 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2377 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2378 ((!LegalOperations && !LN0->isVolatile()) ||
2379 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2380 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2381 LN0->getChain(), LN0->getBasePtr(),
2382 LN0->getPointerInfo(), MemVT,
2383 LN0->isVolatile(), LN0->isNonTemporal(),
2384 LN0->getAlignment());
2386 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2387 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2390 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2391 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2393 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2394 EVT MemVT = LN0->getMemoryVT();
2395 // If we zero all the possible extended bits, then we can turn this into
2396 // a zextload if we are running before legalize or the operation is legal.
2397 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2398 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2399 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2400 ((!LegalOperations && !LN0->isVolatile()) ||
2401 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2402 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2404 LN0->getBasePtr(), LN0->getPointerInfo(),
2406 LN0->isVolatile(), LN0->isNonTemporal(),
2407 LN0->getAlignment());
2409 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2410 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2414 // fold (and (load x), 255) -> (zextload x, i8)
2415 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2416 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2417 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2418 (N0.getOpcode() == ISD::ANY_EXTEND &&
2419 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2420 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2421 LoadSDNode *LN0 = HasAnyExt
2422 ? cast<LoadSDNode>(N0.getOperand(0))
2423 : cast<LoadSDNode>(N0);
2424 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2425 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2426 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2427 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2428 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2429 EVT LoadedVT = LN0->getMemoryVT();
2431 if (ExtVT == LoadedVT &&
2432 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2433 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2436 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2437 LN0->getChain(), LN0->getBasePtr(),
2438 LN0->getPointerInfo(),
2439 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2440 LN0->getAlignment());
2442 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2443 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2446 // Do not change the width of a volatile load.
2447 // Do not generate loads of non-round integer types since these can
2448 // be expensive (and would be wrong if the type is not byte sized).
2449 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2450 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2451 EVT PtrType = LN0->getOperand(1).getValueType();
2453 unsigned Alignment = LN0->getAlignment();
2454 SDValue NewPtr = LN0->getBasePtr();
2456 // For big endian targets, we need to add an offset to the pointer
2457 // to load the correct bytes. For little endian systems, we merely
2458 // need to read fewer bytes from the same pointer.
2459 if (TLI.isBigEndian()) {
2460 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2461 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2462 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2463 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2464 NewPtr, DAG.getConstant(PtrOff, PtrType));
2465 Alignment = MinAlign(Alignment, PtrOff);
2468 AddToWorkList(NewPtr.getNode());
2470 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2472 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2473 LN0->getChain(), NewPtr,
2474 LN0->getPointerInfo(),
2475 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2478 CombineTo(LN0, Load, Load.getValue(1));
2479 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2488 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2490 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2491 bool DemandHighBits) {
2492 if (!LegalOperations)
2495 EVT VT = N->getValueType(0);
2496 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2498 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2501 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2502 bool LookPassAnd0 = false;
2503 bool LookPassAnd1 = false;
2504 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2506 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2508 if (N0.getOpcode() == ISD::AND) {
2509 if (!N0.getNode()->hasOneUse())
2511 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2512 if (!N01C || N01C->getZExtValue() != 0xFF00)
2514 N0 = N0.getOperand(0);
2515 LookPassAnd0 = true;
2518 if (N1.getOpcode() == ISD::AND) {
2519 if (!N1.getNode()->hasOneUse())
2521 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2522 if (!N11C || N11C->getZExtValue() != 0xFF)
2524 N1 = N1.getOperand(0);
2525 LookPassAnd1 = true;
2528 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2530 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2532 if (!N0.getNode()->hasOneUse() ||
2533 !N1.getNode()->hasOneUse())
2536 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2537 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2540 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2543 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2544 SDValue N00 = N0->getOperand(0);
2545 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2546 if (!N00.getNode()->hasOneUse())
2548 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2549 if (!N001C || N001C->getZExtValue() != 0xFF)
2551 N00 = N00.getOperand(0);
2552 LookPassAnd0 = true;
2555 SDValue N10 = N1->getOperand(0);
2556 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2557 if (!N10.getNode()->hasOneUse())
2559 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2560 if (!N101C || N101C->getZExtValue() != 0xFF00)
2562 N10 = N10.getOperand(0);
2563 LookPassAnd1 = true;
2569 // Make sure everything beyond the low halfword is zero since the SRL 16
2570 // will clear the top bits.
2571 unsigned OpSizeInBits = VT.getSizeInBits();
2572 if (DemandHighBits && OpSizeInBits > 16 &&
2573 (!LookPassAnd0 || !LookPassAnd1) &&
2574 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2577 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2578 if (OpSizeInBits > 16)
2579 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2580 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2584 /// isBSwapHWordElement - Return true if the specified node is an element
2585 /// that makes up a 32-bit packed halfword byteswap. i.e.
2586 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2587 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2588 if (!N.getNode()->hasOneUse())
2591 unsigned Opc = N.getOpcode();
2592 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2595 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2600 switch (N1C->getZExtValue()) {
2603 case 0xFF: Num = 0; break;
2604 case 0xFF00: Num = 1; break;
2605 case 0xFF0000: Num = 2; break;
2606 case 0xFF000000: Num = 3; break;
2609 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2610 SDValue N0 = N.getOperand(0);
2611 if (Opc == ISD::AND) {
2612 if (Num == 0 || Num == 2) {
2614 // (x >> 8) & 0xff0000
2615 if (N0.getOpcode() != ISD::SRL)
2617 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2618 if (!C || C->getZExtValue() != 8)
2621 // (x << 8) & 0xff00
2622 // (x << 8) & 0xff000000
2623 if (N0.getOpcode() != ISD::SHL)
2625 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2626 if (!C || C->getZExtValue() != 8)
2629 } else if (Opc == ISD::SHL) {
2631 // (x & 0xff0000) << 8
2632 if (Num != 0 && Num != 2)
2634 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2635 if (!C || C->getZExtValue() != 8)
2637 } else { // Opc == ISD::SRL
2638 // (x & 0xff00) >> 8
2639 // (x & 0xff000000) >> 8
2640 if (Num != 1 && Num != 3)
2642 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2643 if (!C || C->getZExtValue() != 8)
2650 Parts[Num] = N0.getOperand(0).getNode();
2654 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2655 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2656 /// => (rotl (bswap x), 16)
2657 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2658 if (!LegalOperations)
2661 EVT VT = N->getValueType(0);
2664 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2667 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2669 // (or (or (and), (and)), (or (and), (and)))
2670 // (or (or (or (and), (and)), (and)), (and))
2671 if (N0.getOpcode() != ISD::OR)
2673 SDValue N00 = N0.getOperand(0);
2674 SDValue N01 = N0.getOperand(1);
2676 if (N1.getOpcode() == ISD::OR) {
2677 // (or (or (and), (and)), (or (and), (and)))
2678 SDValue N000 = N00.getOperand(0);
2679 if (!isBSwapHWordElement(N000, Parts))
2682 SDValue N001 = N00.getOperand(1);
2683 if (!isBSwapHWordElement(N001, Parts))
2685 SDValue N010 = N01.getOperand(0);
2686 if (!isBSwapHWordElement(N010, Parts))
2688 SDValue N011 = N01.getOperand(1);
2689 if (!isBSwapHWordElement(N011, Parts))
2692 // (or (or (or (and), (and)), (and)), (and))
2693 if (!isBSwapHWordElement(N1, Parts))
2695 if (!isBSwapHWordElement(N01, Parts))
2697 if (N00.getOpcode() != ISD::OR)
2699 SDValue N000 = N00.getOperand(0);
2700 if (!isBSwapHWordElement(N000, Parts))
2702 SDValue N001 = N00.getOperand(1);
2703 if (!isBSwapHWordElement(N001, Parts))
2707 // Make sure the parts are all coming from the same node.
2708 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2711 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2712 SDValue(Parts[0],0));
2714 // Result of the bswap should be rotated by 16. If it's not legal, than
2715 // do (x << 16) | (x >> 16).
2716 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
2717 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2718 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2719 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2720 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
2721 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
2722 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
2723 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2726 SDValue DAGCombiner::visitOR(SDNode *N) {
2727 SDValue N0 = N->getOperand(0);
2728 SDValue N1 = N->getOperand(1);
2729 SDValue LL, LR, RL, RR, CC0, CC1;
2730 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2731 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2732 EVT VT = N1.getValueType();
2735 if (VT.isVector()) {
2736 SDValue FoldedVOp = SimplifyVBinOp(N);
2737 if (FoldedVOp.getNode()) return FoldedVOp;
2740 // fold (or x, undef) -> -1
2741 if (!LegalOperations &&
2742 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2743 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2744 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2746 // fold (or c1, c2) -> c1|c2
2748 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2749 // canonicalize constant to RHS
2751 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2752 // fold (or x, 0) -> x
2753 if (N1C && N1C->isNullValue())
2755 // fold (or x, -1) -> -1
2756 if (N1C && N1C->isAllOnesValue())
2758 // fold (or x, c) -> c iff (x & ~c) == 0
2759 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2762 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
2763 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
2764 if (BSwap.getNode() != 0)
2766 BSwap = MatchBSwapHWordLow(N, N0, N1);
2767 if (BSwap.getNode() != 0)
2771 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2772 if (ROR.getNode() != 0)
2774 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2775 // iff (c1 & c2) == 0.
2776 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2777 isa<ConstantSDNode>(N0.getOperand(1))) {
2778 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2779 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2780 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2781 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2782 N0.getOperand(0), N1),
2783 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2785 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2786 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2787 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2788 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2790 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2791 LL.getValueType().isInteger()) {
2792 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2793 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2794 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2795 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2796 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2797 LR.getValueType(), LL, RL);
2798 AddToWorkList(ORNode.getNode());
2799 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2801 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2802 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2803 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2804 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2805 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2806 LR.getValueType(), LL, RL);
2807 AddToWorkList(ANDNode.getNode());
2808 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2811 // canonicalize equivalent to ll == rl
2812 if (LL == RR && LR == RL) {
2813 Op1 = ISD::getSetCCSwappedOperands(Op1);
2816 if (LL == RL && LR == RR) {
2817 bool isInteger = LL.getValueType().isInteger();
2818 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2819 if (Result != ISD::SETCC_INVALID &&
2820 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2821 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2826 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2827 if (N0.getOpcode() == N1.getOpcode()) {
2828 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2829 if (Tmp.getNode()) return Tmp;
2832 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2833 if (N0.getOpcode() == ISD::AND &&
2834 N1.getOpcode() == ISD::AND &&
2835 N0.getOperand(1).getOpcode() == ISD::Constant &&
2836 N1.getOperand(1).getOpcode() == ISD::Constant &&
2837 // Don't increase # computations.
2838 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2839 // We can only do this xform if we know that bits from X that are set in C2
2840 // but not in C1 are already zero. Likewise for Y.
2841 const APInt &LHSMask =
2842 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2843 const APInt &RHSMask =
2844 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2846 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2847 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2848 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2849 N0.getOperand(0), N1.getOperand(0));
2850 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2851 DAG.getConstant(LHSMask | RHSMask, VT));
2855 // See if this is some rotate idiom.
2856 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2857 return SDValue(Rot, 0);
2859 // Simplify the operands using demanded-bits information.
2860 if (!VT.isVector() &&
2861 SimplifyDemandedBits(SDValue(N, 0)))
2862 return SDValue(N, 0);
2867 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2868 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2869 if (Op.getOpcode() == ISD::AND) {
2870 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2871 Mask = Op.getOperand(1);
2872 Op = Op.getOperand(0);
2878 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2886 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2887 // idioms for rotate, and if the target supports rotation instructions, generate
2889 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2890 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2891 EVT VT = LHS.getValueType();
2892 if (!TLI.isTypeLegal(VT)) return 0;
2894 // The target must have at least one rotate flavor.
2895 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2896 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2897 if (!HasROTL && !HasROTR) return 0;
2899 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2900 SDValue LHSShift; // The shift.
2901 SDValue LHSMask; // AND value if any.
2902 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2903 return 0; // Not part of a rotate.
2905 SDValue RHSShift; // The shift.
2906 SDValue RHSMask; // AND value if any.
2907 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2908 return 0; // Not part of a rotate.
2910 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2911 return 0; // Not shifting the same value.
2913 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2914 return 0; // Shifts must disagree.
2916 // Canonicalize shl to left side in a shl/srl pair.
2917 if (RHSShift.getOpcode() == ISD::SHL) {
2918 std::swap(LHS, RHS);
2919 std::swap(LHSShift, RHSShift);
2920 std::swap(LHSMask , RHSMask );
2923 unsigned OpSizeInBits = VT.getSizeInBits();
2924 SDValue LHSShiftArg = LHSShift.getOperand(0);
2925 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2926 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2928 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2929 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2930 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2931 RHSShiftAmt.getOpcode() == ISD::Constant) {
2932 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2933 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2934 if ((LShVal + RShVal) != OpSizeInBits)
2939 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2941 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2943 // If there is an AND of either shifted operand, apply it to the result.
2944 if (LHSMask.getNode() || RHSMask.getNode()) {
2945 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2947 if (LHSMask.getNode()) {
2948 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2949 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2951 if (RHSMask.getNode()) {
2952 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2953 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2956 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2959 return Rot.getNode();
2962 // If there is a mask here, and we have a variable shift, we can't be sure
2963 // that we're masking out the right stuff.
2964 if (LHSMask.getNode() || RHSMask.getNode())
2967 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2968 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2969 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2970 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2971 if (ConstantSDNode *SUBC =
2972 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2973 if (SUBC->getAPIntValue() == OpSizeInBits) {
2975 return DAG.getNode(ISD::ROTL, DL, VT,
2976 LHSShiftArg, LHSShiftAmt).getNode();
2978 return DAG.getNode(ISD::ROTR, DL, VT,
2979 LHSShiftArg, RHSShiftAmt).getNode();
2984 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2985 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2986 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2987 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2988 if (ConstantSDNode *SUBC =
2989 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2990 if (SUBC->getAPIntValue() == OpSizeInBits) {
2992 return DAG.getNode(ISD::ROTR, DL, VT,
2993 LHSShiftArg, RHSShiftAmt).getNode();
2995 return DAG.getNode(ISD::ROTL, DL, VT,
2996 LHSShiftArg, LHSShiftAmt).getNode();
3001 // Look for sign/zext/any-extended or truncate cases:
3002 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3003 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3004 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3005 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3006 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3007 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3008 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3009 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3010 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3011 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3012 if (RExtOp0.getOpcode() == ISD::SUB &&
3013 RExtOp0.getOperand(1) == LExtOp0) {
3014 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3016 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3017 // (rotr x, (sub 32, y))
3018 if (ConstantSDNode *SUBC =
3019 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3020 if (SUBC->getAPIntValue() == OpSizeInBits) {
3021 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3023 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3026 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3027 RExtOp0 == LExtOp0.getOperand(1)) {
3028 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3030 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3031 // (rotl x, (sub 32, y))
3032 if (ConstantSDNode *SUBC =
3033 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3034 if (SUBC->getAPIntValue() == OpSizeInBits) {
3035 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3037 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3046 SDValue DAGCombiner::visitXOR(SDNode *N) {
3047 SDValue N0 = N->getOperand(0);
3048 SDValue N1 = N->getOperand(1);
3049 SDValue LHS, RHS, CC;
3050 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3051 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3052 EVT VT = N0.getValueType();
3055 if (VT.isVector()) {
3056 SDValue FoldedVOp = SimplifyVBinOp(N);
3057 if (FoldedVOp.getNode()) return FoldedVOp;
3060 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3061 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3062 return DAG.getConstant(0, VT);
3063 // fold (xor x, undef) -> undef
3064 if (N0.getOpcode() == ISD::UNDEF)
3066 if (N1.getOpcode() == ISD::UNDEF)
3068 // fold (xor c1, c2) -> c1^c2
3070 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3071 // canonicalize constant to RHS
3073 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3074 // fold (xor x, 0) -> x
3075 if (N1C && N1C->isNullValue())
3078 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3079 if (RXOR.getNode() != 0)
3082 // fold !(x cc y) -> (x !cc y)
3083 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3084 bool isInt = LHS.getValueType().isInteger();
3085 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3088 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3089 switch (N0.getOpcode()) {
3091 llvm_unreachable("Unhandled SetCC Equivalent!");
3093 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3094 case ISD::SELECT_CC:
3095 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3096 N0.getOperand(3), NotCC);
3101 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3102 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3103 N0.getNode()->hasOneUse() &&
3104 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3105 SDValue V = N0.getOperand(0);
3106 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3107 DAG.getConstant(1, V.getValueType()));
3108 AddToWorkList(V.getNode());
3109 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3112 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3113 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3114 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3115 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3116 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3117 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3118 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3119 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3120 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3121 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3124 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3125 if (N1C && N1C->isAllOnesValue() &&
3126 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3127 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3128 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3129 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3130 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3131 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3132 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3133 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3136 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3137 if (N1C && N0.getOpcode() == ISD::XOR) {
3138 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3139 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3141 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3142 DAG.getConstant(N1C->getAPIntValue() ^
3143 N00C->getAPIntValue(), VT));
3145 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3146 DAG.getConstant(N1C->getAPIntValue() ^
3147 N01C->getAPIntValue(), VT));
3149 // fold (xor x, x) -> 0
3151 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3153 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3154 if (N0.getOpcode() == N1.getOpcode()) {
3155 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3156 if (Tmp.getNode()) return Tmp;
3159 // Simplify the expression using non-local knowledge.
3160 if (!VT.isVector() &&
3161 SimplifyDemandedBits(SDValue(N, 0)))
3162 return SDValue(N, 0);
3167 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3168 /// the shift amount is a constant.
3169 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3170 SDNode *LHS = N->getOperand(0).getNode();
3171 if (!LHS->hasOneUse()) return SDValue();
3173 // We want to pull some binops through shifts, so that we have (and (shift))
3174 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3175 // thing happens with address calculations, so it's important to canonicalize
3177 bool HighBitSet = false; // Can we transform this if the high bit is set?
3179 switch (LHS->getOpcode()) {
3180 default: return SDValue();
3183 HighBitSet = false; // We can only transform sra if the high bit is clear.
3186 HighBitSet = true; // We can only transform sra if the high bit is set.
3189 if (N->getOpcode() != ISD::SHL)
3190 return SDValue(); // only shl(add) not sr[al](add).
3191 HighBitSet = false; // We can only transform sra if the high bit is clear.
3195 // We require the RHS of the binop to be a constant as well.
3196 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3197 if (!BinOpCst) return SDValue();
3199 // FIXME: disable this unless the input to the binop is a shift by a constant.
3200 // If it is not a shift, it pessimizes some common cases like:
3202 // void foo(int *X, int i) { X[i & 1235] = 1; }
3203 // int bar(int *X, int i) { return X[i & 255]; }
3204 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3205 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3206 BinOpLHSVal->getOpcode() != ISD::SRA &&
3207 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3208 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3211 EVT VT = N->getValueType(0);
3213 // If this is a signed shift right, and the high bit is modified by the
3214 // logical operation, do not perform the transformation. The highBitSet
3215 // boolean indicates the value of the high bit of the constant which would
3216 // cause it to be modified for this operation.
3217 if (N->getOpcode() == ISD::SRA) {
3218 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3219 if (BinOpRHSSignSet != HighBitSet)
3223 // Fold the constants, shifting the binop RHS by the shift amount.
3224 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3226 LHS->getOperand(1), N->getOperand(1));
3228 // Create the new shift.
3229 SDValue NewShift = DAG.getNode(N->getOpcode(),
3230 LHS->getOperand(0).getDebugLoc(),
3231 VT, LHS->getOperand(0), N->getOperand(1));
3233 // Create the new binop.
3234 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3237 SDValue DAGCombiner::visitSHL(SDNode *N) {
3238 SDValue N0 = N->getOperand(0);
3239 SDValue N1 = N->getOperand(1);
3240 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3241 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3242 EVT VT = N0.getValueType();
3243 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3245 // fold (shl c1, c2) -> c1<<c2
3247 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3248 // fold (shl 0, x) -> 0
3249 if (N0C && N0C->isNullValue())
3251 // fold (shl x, c >= size(x)) -> undef
3252 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3253 return DAG.getUNDEF(VT);
3254 // fold (shl x, 0) -> x
3255 if (N1C && N1C->isNullValue())
3257 // fold (shl undef, x) -> 0
3258 if (N0.getOpcode() == ISD::UNDEF)
3259 return DAG.getConstant(0, VT);
3260 // if (shl x, c) is known to be zero, return 0
3261 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3262 APInt::getAllOnesValue(OpSizeInBits)))
3263 return DAG.getConstant(0, VT);
3264 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3265 if (N1.getOpcode() == ISD::TRUNCATE &&
3266 N1.getOperand(0).getOpcode() == ISD::AND &&
3267 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3268 SDValue N101 = N1.getOperand(0).getOperand(1);
3269 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3270 EVT TruncVT = N1.getValueType();
3271 SDValue N100 = N1.getOperand(0).getOperand(0);
3272 APInt TruncC = N101C->getAPIntValue();
3273 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3274 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3275 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3276 DAG.getNode(ISD::TRUNCATE,
3279 DAG.getConstant(TruncC, TruncVT)));
3283 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3284 return SDValue(N, 0);
3286 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3287 if (N1C && N0.getOpcode() == ISD::SHL &&
3288 N0.getOperand(1).getOpcode() == ISD::Constant) {
3289 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3290 uint64_t c2 = N1C->getZExtValue();
3291 if (c1 + c2 >= OpSizeInBits)
3292 return DAG.getConstant(0, VT);
3293 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3294 DAG.getConstant(c1 + c2, N1.getValueType()));
3297 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3298 // For this to be valid, the second form must not preserve any of the bits
3299 // that are shifted out by the inner shift in the first form. This means
3300 // the outer shift size must be >= the number of bits added by the ext.
3301 // As a corollary, we don't care what kind of ext it is.
3302 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3303 N0.getOpcode() == ISD::ANY_EXTEND ||
3304 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3305 N0.getOperand(0).getOpcode() == ISD::SHL &&
3306 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3308 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3309 uint64_t c2 = N1C->getZExtValue();
3310 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3311 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3312 if (c2 >= OpSizeInBits - InnerShiftSize) {
3313 if (c1 + c2 >= OpSizeInBits)
3314 return DAG.getConstant(0, VT);
3315 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3316 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3317 N0.getOperand(0)->getOperand(0)),
3318 DAG.getConstant(c1 + c2, N1.getValueType()));
3322 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3323 // (and (srl x, (sub c1, c2), MASK)
3324 if (N1C && N0.getOpcode() == ISD::SRL &&
3325 N0.getOperand(1).getOpcode() == ISD::Constant) {
3326 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3327 if (c1 < VT.getSizeInBits()) {
3328 uint64_t c2 = N1C->getZExtValue();
3329 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3330 VT.getSizeInBits() - c1);
3333 Mask = Mask.shl(c2-c1);
3334 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3335 DAG.getConstant(c2-c1, N1.getValueType()));
3337 Mask = Mask.lshr(c1-c2);
3338 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3339 DAG.getConstant(c1-c2, N1.getValueType()));
3341 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3342 DAG.getConstant(Mask, VT));
3345 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3346 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3347 SDValue HiBitsMask =
3348 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3349 VT.getSizeInBits() -
3350 N1C->getZExtValue()),
3352 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3357 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3358 if (NewSHL.getNode())
3365 SDValue DAGCombiner::visitSRA(SDNode *N) {
3366 SDValue N0 = N->getOperand(0);
3367 SDValue N1 = N->getOperand(1);
3368 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3369 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3370 EVT VT = N0.getValueType();
3371 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3373 // fold (sra c1, c2) -> (sra c1, c2)
3375 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3376 // fold (sra 0, x) -> 0
3377 if (N0C && N0C->isNullValue())
3379 // fold (sra -1, x) -> -1
3380 if (N0C && N0C->isAllOnesValue())
3382 // fold (sra x, (setge c, size(x))) -> undef
3383 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3384 return DAG.getUNDEF(VT);
3385 // fold (sra x, 0) -> x
3386 if (N1C && N1C->isNullValue())
3388 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3390 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3391 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3392 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3394 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3395 ExtVT, VT.getVectorNumElements());
3396 if ((!LegalOperations ||
3397 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3398 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3399 N0.getOperand(0), DAG.getValueType(ExtVT));
3402 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3403 if (N1C && N0.getOpcode() == ISD::SRA) {
3404 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3405 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3406 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3407 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3408 DAG.getConstant(Sum, N1C->getValueType(0)));
3412 // fold (sra (shl X, m), (sub result_size, n))
3413 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3414 // result_size - n != m.
3415 // If truncate is free for the target sext(shl) is likely to result in better
3417 if (N0.getOpcode() == ISD::SHL) {
3418 // Get the two constanst of the shifts, CN0 = m, CN = n.
3419 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3421 // Determine what the truncate's result bitsize and type would be.
3423 EVT::getIntegerVT(*DAG.getContext(),
3424 OpSizeInBits - N1C->getZExtValue());
3425 // Determine the residual right-shift amount.
3426 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3428 // If the shift is not a no-op (in which case this should be just a sign
3429 // extend already), the truncated to type is legal, sign_extend is legal
3430 // on that type, and the truncate to that type is both legal and free,
3431 // perform the transform.
3432 if ((ShiftAmt > 0) &&
3433 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3434 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3435 TLI.isTruncateFree(VT, TruncVT)) {
3437 SDValue Amt = DAG.getConstant(ShiftAmt,
3438 getShiftAmountTy(N0.getOperand(0).getValueType()));
3439 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3440 N0.getOperand(0), Amt);
3441 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3443 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3444 N->getValueType(0), Trunc);
3449 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3450 if (N1.getOpcode() == ISD::TRUNCATE &&
3451 N1.getOperand(0).getOpcode() == ISD::AND &&
3452 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3453 SDValue N101 = N1.getOperand(0).getOperand(1);
3454 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3455 EVT TruncVT = N1.getValueType();
3456 SDValue N100 = N1.getOperand(0).getOperand(0);
3457 APInt TruncC = N101C->getAPIntValue();
3458 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3459 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3460 DAG.getNode(ISD::AND, N->getDebugLoc(),
3462 DAG.getNode(ISD::TRUNCATE,
3465 DAG.getConstant(TruncC, TruncVT)));
3469 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3470 // if c1 is equal to the number of bits the trunc removes
3471 if (N0.getOpcode() == ISD::TRUNCATE &&
3472 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3473 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3474 N0.getOperand(0).hasOneUse() &&
3475 N0.getOperand(0).getOperand(1).hasOneUse() &&
3476 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3477 EVT LargeVT = N0.getOperand(0).getValueType();
3478 ConstantSDNode *LargeShiftAmt =
3479 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3481 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3482 LargeShiftAmt->getZExtValue()) {
3484 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3485 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3486 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3487 N0.getOperand(0).getOperand(0), Amt);
3488 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3492 // Simplify, based on bits shifted out of the LHS.
3493 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3494 return SDValue(N, 0);
3497 // If the sign bit is known to be zero, switch this to a SRL.
3498 if (DAG.SignBitIsZero(N0))
3499 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3502 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3503 if (NewSRA.getNode())
3510 SDValue DAGCombiner::visitSRL(SDNode *N) {
3511 SDValue N0 = N->getOperand(0);
3512 SDValue N1 = N->getOperand(1);
3513 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3514 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3515 EVT VT = N0.getValueType();
3516 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3518 // fold (srl c1, c2) -> c1 >>u c2
3520 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3521 // fold (srl 0, x) -> 0
3522 if (N0C && N0C->isNullValue())
3524 // fold (srl x, c >= size(x)) -> undef
3525 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3526 return DAG.getUNDEF(VT);
3527 // fold (srl x, 0) -> x
3528 if (N1C && N1C->isNullValue())
3530 // if (srl x, c) is known to be zero, return 0
3531 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3532 APInt::getAllOnesValue(OpSizeInBits)))
3533 return DAG.getConstant(0, VT);
3535 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3536 if (N1C && N0.getOpcode() == ISD::SRL &&
3537 N0.getOperand(1).getOpcode() == ISD::Constant) {
3538 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3539 uint64_t c2 = N1C->getZExtValue();
3540 if (c1 + c2 >= OpSizeInBits)
3541 return DAG.getConstant(0, VT);
3542 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3543 DAG.getConstant(c1 + c2, N1.getValueType()));
3546 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3547 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3548 N0.getOperand(0).getOpcode() == ISD::SRL &&
3549 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3551 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3552 uint64_t c2 = N1C->getZExtValue();
3553 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3554 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3555 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3556 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3557 if (c1 + OpSizeInBits == InnerShiftSize) {
3558 if (c1 + c2 >= InnerShiftSize)
3559 return DAG.getConstant(0, VT);
3560 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3561 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3562 N0.getOperand(0)->getOperand(0),
3563 DAG.getConstant(c1 + c2, ShiftCountVT)));
3567 // fold (srl (shl x, c), c) -> (and x, cst2)
3568 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3569 N0.getValueSizeInBits() <= 64) {
3570 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3571 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3572 DAG.getConstant(~0ULL >> ShAmt, VT));
3576 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3577 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3578 // Shifting in all undef bits?
3579 EVT SmallVT = N0.getOperand(0).getValueType();
3580 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3581 return DAG.getUNDEF(VT);
3583 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3584 uint64_t ShiftAmt = N1C->getZExtValue();
3585 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3587 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3588 AddToWorkList(SmallShift.getNode());
3589 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3593 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3594 // bit, which is unmodified by sra.
3595 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3596 if (N0.getOpcode() == ISD::SRA)
3597 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3600 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3601 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3602 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3603 APInt KnownZero, KnownOne;
3604 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3605 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3607 // If any of the input bits are KnownOne, then the input couldn't be all
3608 // zeros, thus the result of the srl will always be zero.
3609 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3611 // If all of the bits input the to ctlz node are known to be zero, then
3612 // the result of the ctlz is "32" and the result of the shift is one.
3613 APInt UnknownBits = ~KnownZero & Mask;
3614 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3616 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3617 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3618 // Okay, we know that only that the single bit specified by UnknownBits
3619 // could be set on input to the CTLZ node. If this bit is set, the SRL
3620 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3621 // to an SRL/XOR pair, which is likely to simplify more.
3622 unsigned ShAmt = UnknownBits.countTrailingZeros();
3623 SDValue Op = N0.getOperand(0);
3626 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3627 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3628 AddToWorkList(Op.getNode());
3631 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3632 Op, DAG.getConstant(1, VT));
3636 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3637 if (N1.getOpcode() == ISD::TRUNCATE &&
3638 N1.getOperand(0).getOpcode() == ISD::AND &&
3639 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3640 SDValue N101 = N1.getOperand(0).getOperand(1);
3641 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3642 EVT TruncVT = N1.getValueType();
3643 SDValue N100 = N1.getOperand(0).getOperand(0);
3644 APInt TruncC = N101C->getAPIntValue();
3645 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3646 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3647 DAG.getNode(ISD::AND, N->getDebugLoc(),
3649 DAG.getNode(ISD::TRUNCATE,
3652 DAG.getConstant(TruncC, TruncVT)));
3656 // fold operands of srl based on knowledge that the low bits are not
3658 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3659 return SDValue(N, 0);
3662 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3663 if (NewSRL.getNode())
3667 // Attempt to convert a srl of a load into a narrower zero-extending load.
3668 SDValue NarrowLoad = ReduceLoadWidth(N);
3669 if (NarrowLoad.getNode())
3672 // Here is a common situation. We want to optimize:
3675 // %b = and i32 %a, 2
3676 // %c = srl i32 %b, 1
3677 // brcond i32 %c ...
3683 // %c = setcc eq %b, 0
3686 // However when after the source operand of SRL is optimized into AND, the SRL
3687 // itself may not be optimized further. Look for it and add the BRCOND into
3689 if (N->hasOneUse()) {
3690 SDNode *Use = *N->use_begin();
3691 if (Use->getOpcode() == ISD::BRCOND)
3693 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3694 // Also look pass the truncate.
3695 Use = *Use->use_begin();
3696 if (Use->getOpcode() == ISD::BRCOND)
3704 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3705 SDValue N0 = N->getOperand(0);
3706 EVT VT = N->getValueType(0);
3708 // fold (ctlz c1) -> c2
3709 if (isa<ConstantSDNode>(N0))
3710 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3714 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3715 SDValue N0 = N->getOperand(0);
3716 EVT VT = N->getValueType(0);
3718 // fold (cttz c1) -> c2
3719 if (isa<ConstantSDNode>(N0))
3720 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3724 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3725 SDValue N0 = N->getOperand(0);
3726 EVT VT = N->getValueType(0);
3728 // fold (ctpop c1) -> c2
3729 if (isa<ConstantSDNode>(N0))
3730 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3734 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3735 SDValue N0 = N->getOperand(0);
3736 SDValue N1 = N->getOperand(1);
3737 SDValue N2 = N->getOperand(2);
3738 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3739 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3740 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3741 EVT VT = N->getValueType(0);
3742 EVT VT0 = N0.getValueType();
3744 // fold (select C, X, X) -> X
3747 // fold (select true, X, Y) -> X
3748 if (N0C && !N0C->isNullValue())
3750 // fold (select false, X, Y) -> Y
3751 if (N0C && N0C->isNullValue())
3753 // fold (select C, 1, X) -> (or C, X)
3754 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3755 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3756 // fold (select C, 0, 1) -> (xor C, 1)
3757 if (VT.isInteger() &&
3760 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
3761 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3764 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3765 N0, DAG.getConstant(1, VT0));
3766 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3767 N0, DAG.getConstant(1, VT0));
3768 AddToWorkList(XORNode.getNode());
3770 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3771 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3773 // fold (select C, 0, X) -> (and (not C), X)
3774 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3775 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3776 AddToWorkList(NOTNode.getNode());
3777 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3779 // fold (select C, X, 1) -> (or (not C), X)
3780 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3781 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3782 AddToWorkList(NOTNode.getNode());
3783 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3785 // fold (select C, X, 0) -> (and C, X)
3786 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3787 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3788 // fold (select X, X, Y) -> (or X, Y)
3789 // fold (select X, 1, Y) -> (or X, Y)
3790 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3791 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3792 // fold (select X, Y, X) -> (and X, Y)
3793 // fold (select X, Y, 0) -> (and X, Y)
3794 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3795 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3797 // If we can fold this based on the true/false value, do so.
3798 if (SimplifySelectOps(N, N1, N2))
3799 return SDValue(N, 0); // Don't revisit N.
3801 // fold selects based on a setcc into other things, such as min/max/abs
3802 if (N0.getOpcode() == ISD::SETCC) {
3804 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3805 // having to say they don't support SELECT_CC on every type the DAG knows
3806 // about, since there is no way to mark an opcode illegal at all value types
3807 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3808 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3809 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3810 N0.getOperand(0), N0.getOperand(1),
3811 N1, N2, N0.getOperand(2));
3812 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3818 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3819 SDValue N0 = N->getOperand(0);
3820 SDValue N1 = N->getOperand(1);
3821 SDValue N2 = N->getOperand(2);
3822 SDValue N3 = N->getOperand(3);
3823 SDValue N4 = N->getOperand(4);
3824 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3826 // fold select_cc lhs, rhs, x, x, cc -> x
3830 // Determine if the condition we're dealing with is constant
3831 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3832 N0, N1, CC, N->getDebugLoc(), false);
3833 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3835 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3836 if (!SCCC->isNullValue())
3837 return N2; // cond always true -> true val
3839 return N3; // cond always false -> false val
3842 // Fold to a simpler select_cc
3843 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3844 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3845 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3848 // If we can fold this based on the true/false value, do so.
3849 if (SimplifySelectOps(N, N2, N3))
3850 return SDValue(N, 0); // Don't revisit N.
3852 // fold select_cc into other things, such as min/max/abs
3853 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3856 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3857 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3858 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3862 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3863 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3864 // transformation. Returns true if extension are possible and the above
3865 // mentioned transformation is profitable.
3866 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3868 SmallVector<SDNode*, 4> &ExtendNodes,
3869 const TargetLowering &TLI) {
3870 bool HasCopyToRegUses = false;
3871 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3872 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3873 UE = N0.getNode()->use_end();
3878 if (UI.getUse().getResNo() != N0.getResNo())
3880 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3881 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3882 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3883 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3884 // Sign bits will be lost after a zext.
3887 for (unsigned i = 0; i != 2; ++i) {
3888 SDValue UseOp = User->getOperand(i);
3891 if (!isa<ConstantSDNode>(UseOp))
3896 ExtendNodes.push_back(User);
3899 // If truncates aren't free and there are users we can't
3900 // extend, it isn't worthwhile.
3903 // Remember if this value is live-out.
3904 if (User->getOpcode() == ISD::CopyToReg)
3905 HasCopyToRegUses = true;
3908 if (HasCopyToRegUses) {
3909 bool BothLiveOut = false;
3910 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3912 SDUse &Use = UI.getUse();
3913 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3919 // Both unextended and extended values are live out. There had better be
3920 // a good reason for the transformation.
3921 return ExtendNodes.size();
3926 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
3927 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
3928 ISD::NodeType ExtType) {
3929 // Extend SetCC uses if necessary.
3930 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3931 SDNode *SetCC = SetCCs[i];
3932 SmallVector<SDValue, 4> Ops;
3934 for (unsigned j = 0; j != 2; ++j) {
3935 SDValue SOp = SetCC->getOperand(j);
3937 Ops.push_back(ExtLoad);
3939 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
3942 Ops.push_back(SetCC->getOperand(2));
3943 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
3944 &Ops[0], Ops.size()));
3948 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3949 SDValue N0 = N->getOperand(0);
3950 EVT VT = N->getValueType(0);
3952 // fold (sext c1) -> c1
3953 if (isa<ConstantSDNode>(N0))
3954 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3956 // fold (sext (sext x)) -> (sext x)
3957 // fold (sext (aext x)) -> (sext x)
3958 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3959 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3962 if (N0.getOpcode() == ISD::TRUNCATE) {
3963 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3964 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3965 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3966 if (NarrowLoad.getNode()) {
3967 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3968 if (NarrowLoad.getNode() != N0.getNode()) {
3969 CombineTo(N0.getNode(), NarrowLoad);
3970 // CombineTo deleted the truncate, if needed, but not what's under it.
3973 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3976 // See if the value being truncated is already sign extended. If so, just
3977 // eliminate the trunc/sext pair.
3978 SDValue Op = N0.getOperand(0);
3979 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3980 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3981 unsigned DestBits = VT.getScalarType().getSizeInBits();
3982 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3984 if (OpBits == DestBits) {
3985 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3986 // bits, it is already ready.
3987 if (NumSignBits > DestBits-MidBits)
3989 } else if (OpBits < DestBits) {
3990 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3991 // bits, just sext from i32.
3992 if (NumSignBits > OpBits-MidBits)
3993 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3995 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3996 // bits, just truncate to i32.
3997 if (NumSignBits > OpBits-MidBits)
3998 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4001 // fold (sext (truncate x)) -> (sextinreg x).
4002 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4003 N0.getValueType())) {
4004 if (OpBits < DestBits)
4005 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4006 else if (OpBits > DestBits)
4007 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4008 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4009 DAG.getValueType(N0.getValueType()));
4013 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4014 // None of the supported targets knows how to perform load and sign extend
4015 // on vectors in one instruction. We only perform this transformation on
4017 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4018 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4019 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4020 bool DoXform = true;
4021 SmallVector<SDNode*, 4> SetCCs;
4022 if (!N0.hasOneUse())
4023 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4025 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4026 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4028 LN0->getBasePtr(), LN0->getPointerInfo(),
4030 LN0->isVolatile(), LN0->isNonTemporal(),
4031 LN0->getAlignment());
4032 CombineTo(N, ExtLoad);
4033 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4034 N0.getValueType(), ExtLoad);
4035 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4036 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4038 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4042 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4043 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4044 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4045 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4046 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4047 EVT MemVT = LN0->getMemoryVT();
4048 if ((!LegalOperations && !LN0->isVolatile()) ||
4049 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4050 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4052 LN0->getBasePtr(), LN0->getPointerInfo(),
4054 LN0->isVolatile(), LN0->isNonTemporal(),
4055 LN0->getAlignment());
4056 CombineTo(N, ExtLoad);
4057 CombineTo(N0.getNode(),
4058 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4059 N0.getValueType(), ExtLoad),
4060 ExtLoad.getValue(1));
4061 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4065 // fold (sext (and/or/xor (load x), cst)) ->
4066 // (and/or/xor (sextload x), (sext cst))
4067 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4068 N0.getOpcode() == ISD::XOR) &&
4069 isa<LoadSDNode>(N0.getOperand(0)) &&
4070 N0.getOperand(1).getOpcode() == ISD::Constant &&
4071 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4072 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4073 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4074 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4075 bool DoXform = true;
4076 SmallVector<SDNode*, 4> SetCCs;
4077 if (!N0.hasOneUse())
4078 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4081 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4082 LN0->getChain(), LN0->getBasePtr(),
4083 LN0->getPointerInfo(),
4086 LN0->isNonTemporal(),
4087 LN0->getAlignment());
4088 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4089 Mask = Mask.sext(VT.getSizeInBits());
4090 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4091 ExtLoad, DAG.getConstant(Mask, VT));
4092 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4093 N0.getOperand(0).getDebugLoc(),
4094 N0.getOperand(0).getValueType(), ExtLoad);
4096 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4097 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4099 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4104 if (N0.getOpcode() == ISD::SETCC) {
4105 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4106 // Only do this before legalize for now.
4107 if (VT.isVector() && !LegalOperations) {
4108 EVT N0VT = N0.getOperand(0).getValueType();
4109 // We know that the # elements of the results is the same as the
4110 // # elements of the compare (and the # elements of the compare result
4111 // for that matter). Check to see that they are the same size. If so,
4112 // we know that the element size of the sext'd result matches the
4113 // element size of the compare operands.
4114 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4115 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4117 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4118 // If the desired elements are smaller or larger than the source
4119 // elements we can use a matching integer vector type and then
4120 // truncate/sign extend
4122 EVT MatchingElementType =
4123 EVT::getIntegerVT(*DAG.getContext(),
4124 N0VT.getScalarType().getSizeInBits());
4125 EVT MatchingVectorType =
4126 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4127 N0VT.getVectorNumElements());
4129 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4131 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4132 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4136 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4137 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4139 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4141 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4142 NegOne, DAG.getConstant(0, VT),
4143 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4144 if (SCC.getNode()) return SCC;
4145 if (!LegalOperations ||
4146 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4147 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4148 DAG.getSetCC(N->getDebugLoc(),
4149 TLI.getSetCCResultType(VT),
4150 N0.getOperand(0), N0.getOperand(1),
4151 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4152 NegOne, DAG.getConstant(0, VT));
4155 // fold (sext x) -> (zext x) if the sign bit is known zero.
4156 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4157 DAG.SignBitIsZero(N0))
4158 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4163 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4164 SDValue N0 = N->getOperand(0);
4165 EVT VT = N->getValueType(0);
4167 // fold (zext c1) -> c1
4168 if (isa<ConstantSDNode>(N0))
4169 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4170 // fold (zext (zext x)) -> (zext x)
4171 // fold (zext (aext x)) -> (zext x)
4172 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4173 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4176 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4177 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4178 if (N0.getOpcode() == ISD::TRUNCATE) {
4179 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4180 if (NarrowLoad.getNode()) {
4181 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4182 if (NarrowLoad.getNode() != N0.getNode()) {
4183 CombineTo(N0.getNode(), NarrowLoad);
4184 // CombineTo deleted the truncate, if needed, but not what's under it.
4187 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4191 // fold (zext (truncate x)) -> (and x, mask)
4192 if (N0.getOpcode() == ISD::TRUNCATE &&
4193 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4195 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4196 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4197 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4198 if (NarrowLoad.getNode()) {
4199 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4200 if (NarrowLoad.getNode() != N0.getNode()) {
4201 CombineTo(N0.getNode(), NarrowLoad);
4202 // CombineTo deleted the truncate, if needed, but not what's under it.
4205 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4208 SDValue Op = N0.getOperand(0);
4209 if (Op.getValueType().bitsLT(VT)) {
4210 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4211 } else if (Op.getValueType().bitsGT(VT)) {
4212 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4214 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4215 N0.getValueType().getScalarType());
4218 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4219 // if either of the casts is not free.
4220 if (N0.getOpcode() == ISD::AND &&
4221 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4222 N0.getOperand(1).getOpcode() == ISD::Constant &&
4223 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4224 N0.getValueType()) ||
4225 !TLI.isZExtFree(N0.getValueType(), VT))) {
4226 SDValue X = N0.getOperand(0).getOperand(0);
4227 if (X.getValueType().bitsLT(VT)) {
4228 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4229 } else if (X.getValueType().bitsGT(VT)) {
4230 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4232 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4233 Mask = Mask.zext(VT.getSizeInBits());
4234 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4235 X, DAG.getConstant(Mask, VT));
4238 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4239 // None of the supported targets knows how to perform load and vector_zext
4240 // on vectors in one instruction. We only perform this transformation on
4242 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4243 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4244 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4245 bool DoXform = true;
4246 SmallVector<SDNode*, 4> SetCCs;
4247 if (!N0.hasOneUse())
4248 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4250 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4251 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4253 LN0->getBasePtr(), LN0->getPointerInfo(),
4255 LN0->isVolatile(), LN0->isNonTemporal(),
4256 LN0->getAlignment());
4257 CombineTo(N, ExtLoad);
4258 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4259 N0.getValueType(), ExtLoad);
4260 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4262 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4264 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4268 // fold (zext (and/or/xor (load x), cst)) ->
4269 // (and/or/xor (zextload x), (zext cst))
4270 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4271 N0.getOpcode() == ISD::XOR) &&
4272 isa<LoadSDNode>(N0.getOperand(0)) &&
4273 N0.getOperand(1).getOpcode() == ISD::Constant &&
4274 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4275 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4276 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4277 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4278 bool DoXform = true;
4279 SmallVector<SDNode*, 4> SetCCs;
4280 if (!N0.hasOneUse())
4281 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4284 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4285 LN0->getChain(), LN0->getBasePtr(),
4286 LN0->getPointerInfo(),
4289 LN0->isNonTemporal(),
4290 LN0->getAlignment());
4291 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4292 Mask = Mask.zext(VT.getSizeInBits());
4293 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4294 ExtLoad, DAG.getConstant(Mask, VT));
4295 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4296 N0.getOperand(0).getDebugLoc(),
4297 N0.getOperand(0).getValueType(), ExtLoad);
4299 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4300 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4302 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4307 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4308 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4309 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4310 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4311 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4312 EVT MemVT = LN0->getMemoryVT();
4313 if ((!LegalOperations && !LN0->isVolatile()) ||
4314 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4315 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4317 LN0->getBasePtr(), LN0->getPointerInfo(),
4319 LN0->isVolatile(), LN0->isNonTemporal(),
4320 LN0->getAlignment());
4321 CombineTo(N, ExtLoad);
4322 CombineTo(N0.getNode(),
4323 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4325 ExtLoad.getValue(1));
4326 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4330 if (N0.getOpcode() == ISD::SETCC) {
4331 if (!LegalOperations && VT.isVector()) {
4332 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4333 // Only do this before legalize for now.
4334 EVT N0VT = N0.getOperand(0).getValueType();
4335 EVT EltVT = VT.getVectorElementType();
4336 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4337 DAG.getConstant(1, EltVT));
4338 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4339 // We know that the # elements of the results is the same as the
4340 // # elements of the compare (and the # elements of the compare result
4341 // for that matter). Check to see that they are the same size. If so,
4342 // we know that the element size of the sext'd result matches the
4343 // element size of the compare operands.
4344 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4345 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4347 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4348 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4349 &OneOps[0], OneOps.size()));
4351 // If the desired elements are smaller or larger than the source
4352 // elements we can use a matching integer vector type and then
4353 // truncate/sign extend
4354 EVT MatchingElementType =
4355 EVT::getIntegerVT(*DAG.getContext(),
4356 N0VT.getScalarType().getSizeInBits());
4357 EVT MatchingVectorType =
4358 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4359 N0VT.getVectorNumElements());
4361 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4363 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4364 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4365 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4366 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4367 &OneOps[0], OneOps.size()));
4370 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4372 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4373 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4374 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4375 if (SCC.getNode()) return SCC;
4378 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4379 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4380 isa<ConstantSDNode>(N0.getOperand(1)) &&
4381 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4383 SDValue ShAmt = N0.getOperand(1);
4384 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4385 if (N0.getOpcode() == ISD::SHL) {
4386 SDValue InnerZExt = N0.getOperand(0);
4387 // If the original shl may be shifting out bits, do not perform this
4389 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4390 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4391 if (ShAmtVal > KnownZeroBits)
4395 DebugLoc DL = N->getDebugLoc();
4397 // Ensure that the shift amount is wide enough for the shifted value.
4398 if (VT.getSizeInBits() >= 256)
4399 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4401 return DAG.getNode(N0.getOpcode(), DL, VT,
4402 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4409 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4410 SDValue N0 = N->getOperand(0);
4411 EVT VT = N->getValueType(0);
4413 // fold (aext c1) -> c1
4414 if (isa<ConstantSDNode>(N0))
4415 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4416 // fold (aext (aext x)) -> (aext x)
4417 // fold (aext (zext x)) -> (zext x)
4418 // fold (aext (sext x)) -> (sext x)
4419 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4420 N0.getOpcode() == ISD::ZERO_EXTEND ||
4421 N0.getOpcode() == ISD::SIGN_EXTEND)
4422 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4424 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4425 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4426 if (N0.getOpcode() == ISD::TRUNCATE) {
4427 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4428 if (NarrowLoad.getNode()) {
4429 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4430 if (NarrowLoad.getNode() != N0.getNode()) {
4431 CombineTo(N0.getNode(), NarrowLoad);
4432 // CombineTo deleted the truncate, if needed, but not what's under it.
4435 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4439 // fold (aext (truncate x))
4440 if (N0.getOpcode() == ISD::TRUNCATE) {
4441 SDValue TruncOp = N0.getOperand(0);
4442 if (TruncOp.getValueType() == VT)
4443 return TruncOp; // x iff x size == zext size.
4444 if (TruncOp.getValueType().bitsGT(VT))
4445 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4446 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4449 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4450 // if the trunc is not free.
4451 if (N0.getOpcode() == ISD::AND &&
4452 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4453 N0.getOperand(1).getOpcode() == ISD::Constant &&
4454 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4455 N0.getValueType())) {
4456 SDValue X = N0.getOperand(0).getOperand(0);
4457 if (X.getValueType().bitsLT(VT)) {
4458 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4459 } else if (X.getValueType().bitsGT(VT)) {
4460 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4462 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4463 Mask = Mask.zext(VT.getSizeInBits());
4464 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4465 X, DAG.getConstant(Mask, VT));
4468 // fold (aext (load x)) -> (aext (truncate (extload x)))
4469 // None of the supported targets knows how to perform load and any_ext
4470 // on vectors in one instruction. We only perform this transformation on
4472 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4473 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4474 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4475 bool DoXform = true;
4476 SmallVector<SDNode*, 4> SetCCs;
4477 if (!N0.hasOneUse())
4478 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4480 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4481 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4483 LN0->getBasePtr(), LN0->getPointerInfo(),
4485 LN0->isVolatile(), LN0->isNonTemporal(),
4486 LN0->getAlignment());
4487 CombineTo(N, ExtLoad);
4488 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4489 N0.getValueType(), ExtLoad);
4490 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4491 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4493 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4497 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4498 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4499 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4500 if (N0.getOpcode() == ISD::LOAD &&
4501 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4503 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4504 EVT MemVT = LN0->getMemoryVT();
4505 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4506 VT, LN0->getChain(), LN0->getBasePtr(),
4507 LN0->getPointerInfo(), MemVT,
4508 LN0->isVolatile(), LN0->isNonTemporal(),
4509 LN0->getAlignment());
4510 CombineTo(N, ExtLoad);
4511 CombineTo(N0.getNode(),
4512 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4513 N0.getValueType(), ExtLoad),
4514 ExtLoad.getValue(1));
4515 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4518 if (N0.getOpcode() == ISD::SETCC) {
4519 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4520 // Only do this before legalize for now.
4521 if (VT.isVector() && !LegalOperations) {
4522 EVT N0VT = N0.getOperand(0).getValueType();
4523 // We know that the # elements of the results is the same as the
4524 // # elements of the compare (and the # elements of the compare result
4525 // for that matter). Check to see that they are the same size. If so,
4526 // we know that the element size of the sext'd result matches the
4527 // element size of the compare operands.
4528 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4529 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4531 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4532 // If the desired elements are smaller or larger than the source
4533 // elements we can use a matching integer vector type and then
4534 // truncate/sign extend
4536 EVT MatchingElementType =
4537 EVT::getIntegerVT(*DAG.getContext(),
4538 N0VT.getScalarType().getSizeInBits());
4539 EVT MatchingVectorType =
4540 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4541 N0VT.getVectorNumElements());
4543 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4545 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4546 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4550 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4552 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4553 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4554 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4562 /// GetDemandedBits - See if the specified operand can be simplified with the
4563 /// knowledge that only the bits specified by Mask are used. If so, return the
4564 /// simpler operand, otherwise return a null SDValue.
4565 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4566 switch (V.getOpcode()) {
4570 // If the LHS or RHS don't contribute bits to the or, drop them.
4571 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4572 return V.getOperand(1);
4573 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4574 return V.getOperand(0);
4577 // Only look at single-use SRLs.
4578 if (!V.getNode()->hasOneUse())
4580 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4581 // See if we can recursively simplify the LHS.
4582 unsigned Amt = RHSC->getZExtValue();
4584 // Watch out for shift count overflow though.
4585 if (Amt >= Mask.getBitWidth()) break;
4586 APInt NewMask = Mask << Amt;
4587 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4588 if (SimplifyLHS.getNode())
4589 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4590 SimplifyLHS, V.getOperand(1));
4596 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4597 /// bits and then truncated to a narrower type and where N is a multiple
4598 /// of number of bits of the narrower type, transform it to a narrower load
4599 /// from address + N / num of bits of new type. If the result is to be
4600 /// extended, also fold the extension to form a extending load.
4601 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4602 unsigned Opc = N->getOpcode();
4604 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4605 SDValue N0 = N->getOperand(0);
4606 EVT VT = N->getValueType(0);
4609 // This transformation isn't valid for vector loads.
4613 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4615 if (Opc == ISD::SIGN_EXTEND_INREG) {
4616 ExtType = ISD::SEXTLOAD;
4617 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4618 } else if (Opc == ISD::SRL) {
4619 // Another special-case: SRL is basically zero-extending a narrower value.
4620 ExtType = ISD::ZEXTLOAD;
4622 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4623 if (!N01) return SDValue();
4624 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4625 VT.getSizeInBits() - N01->getZExtValue());
4627 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4630 unsigned EVTBits = ExtVT.getSizeInBits();
4632 // Do not generate loads of non-round integer types since these can
4633 // be expensive (and would be wrong if the type is not byte sized).
4634 if (!ExtVT.isRound())
4638 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4639 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4640 ShAmt = N01->getZExtValue();
4641 // Is the shift amount a multiple of size of VT?
4642 if ((ShAmt & (EVTBits-1)) == 0) {
4643 N0 = N0.getOperand(0);
4644 // Is the load width a multiple of size of VT?
4645 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4649 // At this point, we must have a load or else we can't do the transform.
4650 if (!isa<LoadSDNode>(N0)) return SDValue();
4652 // If the shift amount is larger than the input type then we're not
4653 // accessing any of the loaded bytes. If the load was a zextload/extload
4654 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4655 // If the load was a sextload then the result is a splat of the sign bit
4656 // of the extended byte. This is not worth optimizing for.
4657 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4662 // If the load is shifted left (and the result isn't shifted back right),
4663 // we can fold the truncate through the shift.
4664 unsigned ShLeftAmt = 0;
4665 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4666 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4667 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4668 ShLeftAmt = N01->getZExtValue();
4669 N0 = N0.getOperand(0);
4673 // If we haven't found a load, we can't narrow it. Don't transform one with
4674 // multiple uses, this would require adding a new load.
4675 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
4676 // Don't change the width of a volatile load.
4677 cast<LoadSDNode>(N0)->isVolatile())
4680 // Verify that we are actually reducing a load width here.
4681 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
4684 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4685 EVT PtrType = N0.getOperand(1).getValueType();
4687 // For big endian targets, we need to adjust the offset to the pointer to
4688 // load the correct bytes.
4689 if (TLI.isBigEndian()) {
4690 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4691 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4692 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4695 uint64_t PtrOff = ShAmt / 8;
4696 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4697 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4698 PtrType, LN0->getBasePtr(),
4699 DAG.getConstant(PtrOff, PtrType));
4700 AddToWorkList(NewPtr.getNode());
4703 if (ExtType == ISD::NON_EXTLOAD)
4704 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4705 LN0->getPointerInfo().getWithOffset(PtrOff),
4706 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign);
4708 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
4709 LN0->getPointerInfo().getWithOffset(PtrOff),
4710 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4713 // Replace the old load's chain with the new load's chain.
4714 WorkListRemover DeadNodes(*this);
4715 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4718 // Shift the result left, if we've swallowed a left shift.
4719 SDValue Result = Load;
4720 if (ShLeftAmt != 0) {
4721 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
4722 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
4724 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4725 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
4728 // Return the new loaded value.
4732 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4733 SDValue N0 = N->getOperand(0);
4734 SDValue N1 = N->getOperand(1);
4735 EVT VT = N->getValueType(0);
4736 EVT EVT = cast<VTSDNode>(N1)->getVT();
4737 unsigned VTBits = VT.getScalarType().getSizeInBits();
4738 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4740 // fold (sext_in_reg c1) -> c1
4741 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4742 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4744 // If the input is already sign extended, just drop the extension.
4745 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4748 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4749 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4750 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4751 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4752 N0.getOperand(0), N1);
4755 // fold (sext_in_reg (sext x)) -> (sext x)
4756 // fold (sext_in_reg (aext x)) -> (sext x)
4757 // if x is small enough.
4758 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4759 SDValue N00 = N0.getOperand(0);
4760 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4761 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4762 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4765 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4766 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4767 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4769 // fold operands of sext_in_reg based on knowledge that the top bits are not
4771 if (SimplifyDemandedBits(SDValue(N, 0)))
4772 return SDValue(N, 0);
4774 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4775 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4776 SDValue NarrowLoad = ReduceLoadWidth(N);
4777 if (NarrowLoad.getNode())
4780 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4781 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4782 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4783 if (N0.getOpcode() == ISD::SRL) {
4784 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4785 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4786 // We can turn this into an SRA iff the input to the SRL is already sign
4788 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4789 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4790 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4791 N0.getOperand(0), N0.getOperand(1));
4795 // fold (sext_inreg (extload x)) -> (sextload x)
4796 if (ISD::isEXTLoad(N0.getNode()) &&
4797 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4798 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4799 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4800 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4801 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4802 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4804 LN0->getBasePtr(), LN0->getPointerInfo(),
4806 LN0->isVolatile(), LN0->isNonTemporal(),
4807 LN0->getAlignment());
4808 CombineTo(N, ExtLoad);
4809 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4810 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4812 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4813 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4815 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4816 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4817 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4818 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4819 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4821 LN0->getBasePtr(), LN0->getPointerInfo(),
4823 LN0->isVolatile(), LN0->isNonTemporal(),
4824 LN0->getAlignment());
4825 CombineTo(N, ExtLoad);
4826 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4827 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4830 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
4831 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
4832 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
4833 N0.getOperand(1), false);
4834 if (BSwap.getNode() != 0)
4835 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4842 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4843 SDValue N0 = N->getOperand(0);
4844 EVT VT = N->getValueType(0);
4847 if (N0.getValueType() == N->getValueType(0))
4849 // fold (truncate c1) -> c1
4850 if (isa<ConstantSDNode>(N0))
4851 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4852 // fold (truncate (truncate x)) -> (truncate x)
4853 if (N0.getOpcode() == ISD::TRUNCATE)
4854 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4855 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4856 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4857 N0.getOpcode() == ISD::SIGN_EXTEND ||
4858 N0.getOpcode() == ISD::ANY_EXTEND) {
4859 if (N0.getOperand(0).getValueType().bitsLT(VT))
4860 // if the source is smaller than the dest, we still need an extend
4861 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4863 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4864 // if the source is larger than the dest, than we just need the truncate
4865 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4867 // if the source and dest are the same type, we can drop both the extend
4868 // and the truncate.
4869 return N0.getOperand(0);
4872 // See if we can simplify the input to this truncate through knowledge that
4873 // only the low bits are being used.
4874 // For example "trunc (or (shl x, 8), y)" // -> trunc y
4875 // Currently we only perform this optimization on scalars because vectors
4876 // may have different active low bits.
4877 if (!VT.isVector()) {
4879 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4880 VT.getSizeInBits()));
4881 if (Shorter.getNode())
4882 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4884 // fold (truncate (load x)) -> (smaller load x)
4885 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4886 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4887 SDValue Reduced = ReduceLoadWidth(N);
4888 if (Reduced.getNode())
4892 // Simplify the operands using demanded-bits information.
4893 if (!VT.isVector() &&
4894 SimplifyDemandedBits(SDValue(N, 0)))
4895 return SDValue(N, 0);
4900 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4901 SDValue Elt = N->getOperand(i);
4902 if (Elt.getOpcode() != ISD::MERGE_VALUES)
4903 return Elt.getNode();
4904 return Elt.getOperand(Elt.getResNo()).getNode();
4907 /// CombineConsecutiveLoads - build_pair (load, load) -> load
4908 /// if load locations are consecutive.
4909 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4910 assert(N->getOpcode() == ISD::BUILD_PAIR);
4912 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4913 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4914 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
4915 LD1->getPointerInfo().getAddrSpace() !=
4916 LD2->getPointerInfo().getAddrSpace())
4918 EVT LD1VT = LD1->getValueType(0);
4920 if (ISD::isNON_EXTLoad(LD2) &&
4922 // If both are volatile this would reduce the number of volatile loads.
4923 // If one is volatile it might be ok, but play conservative and bail out.
4924 !LD1->isVolatile() &&
4925 !LD2->isVolatile() &&
4926 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4927 unsigned Align = LD1->getAlignment();
4928 unsigned NewAlign = TLI.getTargetData()->
4929 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4931 if (NewAlign <= Align &&
4932 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4933 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4934 LD1->getBasePtr(), LD1->getPointerInfo(),
4935 false, false, Align);
4941 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
4942 SDValue N0 = N->getOperand(0);
4943 EVT VT = N->getValueType(0);
4945 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
4946 // Only do this before legalize, since afterward the target may be depending
4947 // on the bitconvert.
4948 // First check to see if this is all constant.
4950 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4952 bool isSimple = true;
4953 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4954 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4955 N0.getOperand(i).getOpcode() != ISD::Constant &&
4956 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4961 EVT DestEltVT = N->getValueType(0).getVectorElementType();
4962 assert(!DestEltVT.isVector() &&
4963 "Element type of vector ValueType must not be vector!");
4965 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4968 // If the input is a constant, let getNode fold it.
4969 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4970 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
4971 if (Res.getNode() != N) {
4972 if (!LegalOperations ||
4973 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4976 // Folding it resulted in an illegal node, and it's too late to
4977 // do that. Clean up the old node and forego the transformation.
4978 // Ideally this won't happen very often, because instcombine
4979 // and the earlier dagcombine runs (where illegal nodes are
4980 // permitted) should have folded most of them already.
4981 DAG.DeleteNode(Res.getNode());
4985 // (conv (conv x, t1), t2) -> (conv x, t2)
4986 if (N0.getOpcode() == ISD::BITCAST)
4987 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
4990 // fold (conv (load x)) -> (load (conv*)x)
4991 // If the resultant load doesn't need a higher alignment than the original!
4992 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4993 // Do not change the width of a volatile load.
4994 !cast<LoadSDNode>(N0)->isVolatile() &&
4995 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4996 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4997 unsigned Align = TLI.getTargetData()->
4998 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4999 unsigned OrigAlign = LN0->getAlignment();
5001 if (Align <= OrigAlign) {
5002 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5003 LN0->getBasePtr(), LN0->getPointerInfo(),
5004 LN0->isVolatile(), LN0->isNonTemporal(),
5007 CombineTo(N0.getNode(),
5008 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5009 N0.getValueType(), Load),
5015 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5016 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5017 // This often reduces constant pool loads.
5018 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
5019 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
5020 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5022 AddToWorkList(NewConv.getNode());
5024 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5025 if (N0.getOpcode() == ISD::FNEG)
5026 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5027 NewConv, DAG.getConstant(SignBit, VT));
5028 assert(N0.getOpcode() == ISD::FABS);
5029 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5030 NewConv, DAG.getConstant(~SignBit, VT));
5033 // fold (bitconvert (fcopysign cst, x)) ->
5034 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5035 // Note that we don't handle (copysign x, cst) because this can always be
5036 // folded to an fneg or fabs.
5037 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5038 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5039 VT.isInteger() && !VT.isVector()) {
5040 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5041 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5042 if (isTypeLegal(IntXVT)) {
5043 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5044 IntXVT, N0.getOperand(1));
5045 AddToWorkList(X.getNode());
5047 // If X has a different width than the result/lhs, sext it or truncate it.
5048 unsigned VTWidth = VT.getSizeInBits();
5049 if (OrigXWidth < VTWidth) {
5050 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5051 AddToWorkList(X.getNode());
5052 } else if (OrigXWidth > VTWidth) {
5053 // To get the sign bit in the right place, we have to shift it right
5054 // before truncating.
5055 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5056 X.getValueType(), X,
5057 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5058 AddToWorkList(X.getNode());
5059 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5060 AddToWorkList(X.getNode());
5063 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5064 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5065 X, DAG.getConstant(SignBit, VT));
5066 AddToWorkList(X.getNode());
5068 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5069 VT, N0.getOperand(0));
5070 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5071 Cst, DAG.getConstant(~SignBit, VT));
5072 AddToWorkList(Cst.getNode());
5074 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5078 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5079 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5080 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5081 if (CombineLD.getNode())
5088 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5089 EVT VT = N->getValueType(0);
5090 return CombineConsecutiveLoads(N, VT);
5093 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5094 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5095 /// destination element value type.
5096 SDValue DAGCombiner::
5097 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5098 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5100 // If this is already the right type, we're done.
5101 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5103 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5104 unsigned DstBitSize = DstEltVT.getSizeInBits();
5106 // If this is a conversion of N elements of one type to N elements of another
5107 // type, convert each element. This handles FP<->INT cases.
5108 if (SrcBitSize == DstBitSize) {
5109 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5110 BV->getValueType(0).getVectorNumElements());
5112 // Due to the FP element handling below calling this routine recursively,
5113 // we can end up with a scalar-to-vector node here.
5114 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5115 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5116 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5117 DstEltVT, BV->getOperand(0)));
5119 SmallVector<SDValue, 8> Ops;
5120 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5121 SDValue Op = BV->getOperand(i);
5122 // If the vector element type is not legal, the BUILD_VECTOR operands
5123 // are promoted and implicitly truncated. Make that explicit here.
5124 if (Op.getValueType() != SrcEltVT)
5125 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5126 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5128 AddToWorkList(Ops.back().getNode());
5130 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5131 &Ops[0], Ops.size());
5134 // Otherwise, we're growing or shrinking the elements. To avoid having to
5135 // handle annoying details of growing/shrinking FP values, we convert them to
5137 if (SrcEltVT.isFloatingPoint()) {
5138 // Convert the input float vector to a int vector where the elements are the
5140 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5141 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5142 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5146 // Now we know the input is an integer vector. If the output is a FP type,
5147 // convert to integer first, then to FP of the right size.
5148 if (DstEltVT.isFloatingPoint()) {
5149 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5150 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5151 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5153 // Next, convert to FP elements of the same size.
5154 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5157 // Okay, we know the src/dst types are both integers of differing types.
5158 // Handling growing first.
5159 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5160 if (SrcBitSize < DstBitSize) {
5161 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5163 SmallVector<SDValue, 8> Ops;
5164 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5165 i += NumInputsPerOutput) {
5166 bool isLE = TLI.isLittleEndian();
5167 APInt NewBits = APInt(DstBitSize, 0);
5168 bool EltIsUndef = true;
5169 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5170 // Shift the previously computed bits over.
5171 NewBits <<= SrcBitSize;
5172 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5173 if (Op.getOpcode() == ISD::UNDEF) continue;
5176 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5177 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5181 Ops.push_back(DAG.getUNDEF(DstEltVT));
5183 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5186 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5187 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5188 &Ops[0], Ops.size());
5191 // Finally, this must be the case where we are shrinking elements: each input
5192 // turns into multiple outputs.
5193 bool isS2V = ISD::isScalarToVector(BV);
5194 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5195 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5196 NumOutputsPerInput*BV->getNumOperands());
5197 SmallVector<SDValue, 8> Ops;
5199 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5200 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5201 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5202 Ops.push_back(DAG.getUNDEF(DstEltVT));
5206 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5207 getAPIntValue().zextOrTrunc(SrcBitSize);
5209 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5210 APInt ThisVal = OpVal.trunc(DstBitSize);
5211 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5212 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5213 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5214 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5216 OpVal = OpVal.lshr(DstBitSize);
5219 // For big endian targets, swap the order of the pieces of each element.
5220 if (TLI.isBigEndian())
5221 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5224 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5225 &Ops[0], Ops.size());
5228 SDValue DAGCombiner::visitFADD(SDNode *N) {
5229 SDValue N0 = N->getOperand(0);
5230 SDValue N1 = N->getOperand(1);
5231 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5232 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5233 EVT VT = N->getValueType(0);
5236 if (VT.isVector()) {
5237 SDValue FoldedVOp = SimplifyVBinOp(N);
5238 if (FoldedVOp.getNode()) return FoldedVOp;
5241 // fold (fadd c1, c2) -> (fadd c1, c2)
5242 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5243 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5244 // canonicalize constant to RHS
5245 if (N0CFP && !N1CFP)
5246 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5247 // fold (fadd A, 0) -> A
5248 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5250 // fold (fadd A, (fneg B)) -> (fsub A, B)
5251 if (isNegatibleForFree(N1, LegalOperations) == 2)
5252 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5253 GetNegatedExpression(N1, DAG, LegalOperations));
5254 // fold (fadd (fneg A), B) -> (fsub B, A)
5255 if (isNegatibleForFree(N0, LegalOperations) == 2)
5256 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5257 GetNegatedExpression(N0, DAG, LegalOperations));
5259 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5260 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
5261 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5262 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5263 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5264 N0.getOperand(1), N1));
5269 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5270 SDValue N0 = N->getOperand(0);
5271 SDValue N1 = N->getOperand(1);
5272 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5273 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5274 EVT VT = N->getValueType(0);
5277 if (VT.isVector()) {
5278 SDValue FoldedVOp = SimplifyVBinOp(N);
5279 if (FoldedVOp.getNode()) return FoldedVOp;
5282 // fold (fsub c1, c2) -> c1-c2
5283 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5284 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5285 // fold (fsub A, 0) -> A
5286 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5288 // fold (fsub 0, B) -> -B
5289 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
5290 if (isNegatibleForFree(N1, LegalOperations))
5291 return GetNegatedExpression(N1, DAG, LegalOperations);
5292 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5293 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5295 // fold (fsub A, (fneg B)) -> (fadd A, B)
5296 if (isNegatibleForFree(N1, LegalOperations))
5297 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5298 GetNegatedExpression(N1, DAG, LegalOperations));
5303 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5304 SDValue N0 = N->getOperand(0);
5305 SDValue N1 = N->getOperand(1);
5306 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5307 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5308 EVT VT = N->getValueType(0);
5311 if (VT.isVector()) {
5312 SDValue FoldedVOp = SimplifyVBinOp(N);
5313 if (FoldedVOp.getNode()) return FoldedVOp;
5316 // fold (fmul c1, c2) -> c1*c2
5317 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5318 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5319 // canonicalize constant to RHS
5320 if (N0CFP && !N1CFP)
5321 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5322 // fold (fmul A, 0) -> 0
5323 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5325 // fold (fmul A, 0) -> 0, vector edition.
5326 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
5328 // fold (fmul X, 2.0) -> (fadd X, X)
5329 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5330 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5331 // fold (fmul X, -1.0) -> (fneg X)
5332 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5333 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5334 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5336 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5337 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5338 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5339 // Both can be negated for free, check to see if at least one is cheaper
5341 if (LHSNeg == 2 || RHSNeg == 2)
5342 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5343 GetNegatedExpression(N0, DAG, LegalOperations),
5344 GetNegatedExpression(N1, DAG, LegalOperations));
5348 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5349 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
5350 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5351 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5352 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5353 N0.getOperand(1), N1));
5358 SDValue DAGCombiner::visitFDIV(SDNode *N) {
5359 SDValue N0 = N->getOperand(0);
5360 SDValue N1 = N->getOperand(1);
5361 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5362 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5363 EVT VT = N->getValueType(0);
5366 if (VT.isVector()) {
5367 SDValue FoldedVOp = SimplifyVBinOp(N);
5368 if (FoldedVOp.getNode()) return FoldedVOp;
5371 // fold (fdiv c1, c2) -> c1/c2
5372 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5373 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5376 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5377 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5378 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5379 // Both can be negated for free, check to see if at least one is cheaper
5381 if (LHSNeg == 2 || RHSNeg == 2)
5382 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5383 GetNegatedExpression(N0, DAG, LegalOperations),
5384 GetNegatedExpression(N1, DAG, LegalOperations));
5391 SDValue DAGCombiner::visitFREM(SDNode *N) {
5392 SDValue N0 = N->getOperand(0);
5393 SDValue N1 = N->getOperand(1);
5394 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5395 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5396 EVT VT = N->getValueType(0);
5398 // fold (frem c1, c2) -> fmod(c1,c2)
5399 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5400 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5405 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5406 SDValue N0 = N->getOperand(0);
5407 SDValue N1 = N->getOperand(1);
5408 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5409 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5410 EVT VT = N->getValueType(0);
5412 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
5413 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5416 const APFloat& V = N1CFP->getValueAPF();
5417 // copysign(x, c1) -> fabs(x) iff ispos(c1)
5418 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5419 if (!V.isNegative()) {
5420 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5421 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5423 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5424 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5425 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5429 // copysign(fabs(x), y) -> copysign(x, y)
5430 // copysign(fneg(x), y) -> copysign(x, y)
5431 // copysign(copysign(x,z), y) -> copysign(x, y)
5432 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5433 N0.getOpcode() == ISD::FCOPYSIGN)
5434 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5435 N0.getOperand(0), N1);
5437 // copysign(x, abs(y)) -> abs(x)
5438 if (N1.getOpcode() == ISD::FABS)
5439 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5441 // copysign(x, copysign(y,z)) -> copysign(x, z)
5442 if (N1.getOpcode() == ISD::FCOPYSIGN)
5443 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5444 N0, N1.getOperand(1));
5446 // copysign(x, fp_extend(y)) -> copysign(x, y)
5447 // copysign(x, fp_round(y)) -> copysign(x, y)
5448 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5449 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5450 N0, N1.getOperand(0));
5455 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5456 SDValue N0 = N->getOperand(0);
5457 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5458 EVT VT = N->getValueType(0);
5459 EVT OpVT = N0.getValueType();
5461 // fold (sint_to_fp c1) -> c1fp
5462 if (N0C && OpVT != MVT::ppcf128 &&
5463 // ...but only if the target supports immediate floating-point values
5464 (Level == llvm::Unrestricted ||
5465 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5466 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5468 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5469 // but UINT_TO_FP is legal on this target, try to convert.
5470 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5471 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5472 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
5473 if (DAG.SignBitIsZero(N0))
5474 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5480 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5481 SDValue N0 = N->getOperand(0);
5482 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5483 EVT VT = N->getValueType(0);
5484 EVT OpVT = N0.getValueType();
5486 // fold (uint_to_fp c1) -> c1fp
5487 if (N0C && OpVT != MVT::ppcf128 &&
5488 // ...but only if the target supports immediate floating-point values
5489 (Level == llvm::Unrestricted ||
5490 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5491 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5493 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5494 // but SINT_TO_FP is legal on this target, try to convert.
5495 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5496 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5497 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5498 if (DAG.SignBitIsZero(N0))
5499 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5505 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5506 SDValue N0 = N->getOperand(0);
5507 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5508 EVT VT = N->getValueType(0);
5510 // fold (fp_to_sint c1fp) -> c1
5512 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5517 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5518 SDValue N0 = N->getOperand(0);
5519 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5520 EVT VT = N->getValueType(0);
5522 // fold (fp_to_uint c1fp) -> c1
5523 if (N0CFP && VT != MVT::ppcf128)
5524 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5529 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5530 SDValue N0 = N->getOperand(0);
5531 SDValue N1 = N->getOperand(1);
5532 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5533 EVT VT = N->getValueType(0);
5535 // fold (fp_round c1fp) -> c1fp
5536 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5537 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5539 // fold (fp_round (fp_extend x)) -> x
5540 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5541 return N0.getOperand(0);
5543 // fold (fp_round (fp_round x)) -> (fp_round x)
5544 if (N0.getOpcode() == ISD::FP_ROUND) {
5545 // This is a value preserving truncation if both round's are.
5546 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5547 N0.getNode()->getConstantOperandVal(1) == 1;
5548 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5549 DAG.getIntPtrConstant(IsTrunc));
5552 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5553 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5554 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5555 N0.getOperand(0), N1);
5556 AddToWorkList(Tmp.getNode());
5557 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5558 Tmp, N0.getOperand(1));
5564 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
5565 SDValue N0 = N->getOperand(0);
5566 EVT VT = N->getValueType(0);
5567 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5568 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5570 // fold (fp_round_inreg c1fp) -> c1fp
5571 if (N0CFP && isTypeLegal(EVT)) {
5572 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
5573 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
5579 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
5580 SDValue N0 = N->getOperand(0);
5581 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5582 EVT VT = N->getValueType(0);
5584 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
5585 if (N->hasOneUse() &&
5586 N->use_begin()->getOpcode() == ISD::FP_ROUND)
5589 // fold (fp_extend c1fp) -> c1fp
5590 if (N0CFP && VT != MVT::ppcf128)
5591 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5593 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
5595 if (N0.getOpcode() == ISD::FP_ROUND
5596 && N0.getNode()->getConstantOperandVal(1) == 1) {
5597 SDValue In = N0.getOperand(0);
5598 if (In.getValueType() == VT) return In;
5599 if (VT.bitsLT(In.getValueType()))
5600 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
5601 In, N0.getOperand(1));
5602 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5605 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5606 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5607 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5608 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5609 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5610 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
5612 LN0->getBasePtr(), LN0->getPointerInfo(),
5614 LN0->isVolatile(), LN0->isNonTemporal(),
5615 LN0->getAlignment());
5616 CombineTo(N, ExtLoad);
5617 CombineTo(N0.getNode(),
5618 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5619 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5620 ExtLoad.getValue(1));
5621 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5627 SDValue DAGCombiner::visitFNEG(SDNode *N) {
5628 SDValue N0 = N->getOperand(0);
5629 EVT VT = N->getValueType(0);
5631 if (isNegatibleForFree(N0, LegalOperations))
5632 return GetNegatedExpression(N0, DAG, LegalOperations);
5634 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5635 // constant pool values.
5636 if (N0.getOpcode() == ISD::BITCAST &&
5638 N0.getNode()->hasOneUse() &&
5639 N0.getOperand(0).getValueType().isInteger()) {
5640 SDValue Int = N0.getOperand(0);
5641 EVT IntVT = Int.getValueType();
5642 if (IntVT.isInteger() && !IntVT.isVector()) {
5643 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5644 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5645 AddToWorkList(Int.getNode());
5646 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5654 SDValue DAGCombiner::visitFABS(SDNode *N) {
5655 SDValue N0 = N->getOperand(0);
5656 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5657 EVT VT = N->getValueType(0);
5659 // fold (fabs c1) -> fabs(c1)
5660 if (N0CFP && VT != MVT::ppcf128)
5661 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5662 // fold (fabs (fabs x)) -> (fabs x)
5663 if (N0.getOpcode() == ISD::FABS)
5664 return N->getOperand(0);
5665 // fold (fabs (fneg x)) -> (fabs x)
5666 // fold (fabs (fcopysign x, y)) -> (fabs x)
5667 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5668 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5670 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5671 // constant pool values.
5672 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5673 N0.getOperand(0).getValueType().isInteger() &&
5674 !N0.getOperand(0).getValueType().isVector()) {
5675 SDValue Int = N0.getOperand(0);
5676 EVT IntVT = Int.getValueType();
5677 if (IntVT.isInteger() && !IntVT.isVector()) {
5678 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5679 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5680 AddToWorkList(Int.getNode());
5681 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5682 N->getValueType(0), Int);
5689 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5690 SDValue Chain = N->getOperand(0);
5691 SDValue N1 = N->getOperand(1);
5692 SDValue N2 = N->getOperand(2);
5694 // If N is a constant we could fold this into a fallthrough or unconditional
5695 // branch. However that doesn't happen very often in normal code, because
5696 // Instcombine/SimplifyCFG should have handled the available opportunities.
5697 // If we did this folding here, it would be necessary to update the
5698 // MachineBasicBlock CFG, which is awkward.
5700 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5702 if (N1.getOpcode() == ISD::SETCC &&
5703 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5704 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5705 Chain, N1.getOperand(2),
5706 N1.getOperand(0), N1.getOperand(1), N2);
5709 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5710 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5711 (N1.getOperand(0).hasOneUse() &&
5712 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5714 if (N1.getOpcode() == ISD::TRUNCATE) {
5715 // Look pass the truncate.
5716 Trunc = N1.getNode();
5717 N1 = N1.getOperand(0);
5720 // Match this pattern so that we can generate simpler code:
5723 // %b = and i32 %a, 2
5724 // %c = srl i32 %b, 1
5725 // brcond i32 %c ...
5730 // %b = and i32 %a, 2
5731 // %c = setcc eq %b, 0
5734 // This applies only when the AND constant value has one bit set and the
5735 // SRL constant is equal to the log2 of the AND constant. The back-end is
5736 // smart enough to convert the result into a TEST/JMP sequence.
5737 SDValue Op0 = N1.getOperand(0);
5738 SDValue Op1 = N1.getOperand(1);
5740 if (Op0.getOpcode() == ISD::AND &&
5741 Op1.getOpcode() == ISD::Constant) {
5742 SDValue AndOp1 = Op0.getOperand(1);
5744 if (AndOp1.getOpcode() == ISD::Constant) {
5745 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5747 if (AndConst.isPowerOf2() &&
5748 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5750 DAG.getSetCC(N->getDebugLoc(),
5751 TLI.getSetCCResultType(Op0.getValueType()),
5752 Op0, DAG.getConstant(0, Op0.getValueType()),
5755 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5756 MVT::Other, Chain, SetCC, N2);
5757 // Don't add the new BRCond into the worklist or else SimplifySelectCC
5758 // will convert it back to (X & C1) >> C2.
5759 CombineTo(N, NewBRCond, false);
5760 // Truncate is dead.
5762 removeFromWorkList(Trunc);
5763 DAG.DeleteNode(Trunc);
5765 // Replace the uses of SRL with SETCC
5766 WorkListRemover DeadNodes(*this);
5767 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5768 removeFromWorkList(N1.getNode());
5769 DAG.DeleteNode(N1.getNode());
5770 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5776 // Restore N1 if the above transformation doesn't match.
5777 N1 = N->getOperand(1);
5780 // Transform br(xor(x, y)) -> br(x != y)
5781 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5782 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5783 SDNode *TheXor = N1.getNode();
5784 SDValue Op0 = TheXor->getOperand(0);
5785 SDValue Op1 = TheXor->getOperand(1);
5786 if (Op0.getOpcode() == Op1.getOpcode()) {
5787 // Avoid missing important xor optimizations.
5788 SDValue Tmp = visitXOR(TheXor);
5789 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5790 DEBUG(dbgs() << "\nReplacing.8 ";
5792 dbgs() << "\nWith: ";
5793 Tmp.getNode()->dump(&DAG);
5795 WorkListRemover DeadNodes(*this);
5796 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5797 removeFromWorkList(TheXor);
5798 DAG.DeleteNode(TheXor);
5799 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5800 MVT::Other, Chain, Tmp, N2);
5804 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5806 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5807 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5808 Op0.getOpcode() == ISD::XOR) {
5809 TheXor = Op0.getNode();
5813 EVT SetCCVT = N1.getValueType();
5815 SetCCVT = TLI.getSetCCResultType(SetCCVT);
5816 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5819 Equal ? ISD::SETEQ : ISD::SETNE);
5820 // Replace the uses of XOR with SETCC
5821 WorkListRemover DeadNodes(*this);
5822 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5823 removeFromWorkList(N1.getNode());
5824 DAG.DeleteNode(N1.getNode());
5825 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5826 MVT::Other, Chain, SetCC, N2);
5833 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5835 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5836 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5837 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5839 // If N is a constant we could fold this into a fallthrough or unconditional
5840 // branch. However that doesn't happen very often in normal code, because
5841 // Instcombine/SimplifyCFG should have handled the available opportunities.
5842 // If we did this folding here, it would be necessary to update the
5843 // MachineBasicBlock CFG, which is awkward.
5845 // Use SimplifySetCC to simplify SETCC's.
5846 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5847 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5849 if (Simp.getNode()) AddToWorkList(Simp.getNode());
5851 // fold to a simpler setcc
5852 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5853 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5854 N->getOperand(0), Simp.getOperand(2),
5855 Simp.getOperand(0), Simp.getOperand(1),
5861 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
5862 /// pre-indexed load / store when the base pointer is an add or subtract
5863 /// and it has other uses besides the load / store. After the
5864 /// transformation, the new indexed load / store has effectively folded
5865 /// the add / subtract in and all of its other uses are redirected to the
5866 /// new load / store.
5867 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5868 if (!LegalOperations)
5874 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5875 if (LD->isIndexed())
5877 VT = LD->getMemoryVT();
5878 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5879 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5881 Ptr = LD->getBasePtr();
5882 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5883 if (ST->isIndexed())
5885 VT = ST->getMemoryVT();
5886 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5887 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5889 Ptr = ST->getBasePtr();
5895 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5896 // out. There is no reason to make this a preinc/predec.
5897 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5898 Ptr.getNode()->hasOneUse())
5901 // Ask the target to do addressing mode selection.
5904 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5905 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5907 // Don't create a indexed load / store with zero offset.
5908 if (isa<ConstantSDNode>(Offset) &&
5909 cast<ConstantSDNode>(Offset)->isNullValue())
5912 // Try turning it into a pre-indexed load / store except when:
5913 // 1) The new base ptr is a frame index.
5914 // 2) If N is a store and the new base ptr is either the same as or is a
5915 // predecessor of the value being stored.
5916 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5917 // that would create a cycle.
5918 // 4) All uses are load / store ops that use it as old base ptr.
5920 // Check #1. Preinc'ing a frame index would require copying the stack pointer
5921 // (plus the implicit offset) to a register to preinc anyway.
5922 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5927 SDValue Val = cast<StoreSDNode>(N)->getValue();
5928 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5932 // Now check for #3 and #4.
5933 bool RealUse = false;
5935 // Caches for hasPredecessorHelper
5936 SmallPtrSet<const SDNode *, 32> Visited;
5937 SmallVector<const SDNode *, 16> Worklist;
5939 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5940 E = Ptr.getNode()->use_end(); I != E; ++I) {
5944 if (N->hasPredecessorHelper(Use, Visited, Worklist))
5947 if (!((Use->getOpcode() == ISD::LOAD &&
5948 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5949 (Use->getOpcode() == ISD::STORE &&
5950 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5959 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5960 BasePtr, Offset, AM);
5962 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5963 BasePtr, Offset, AM);
5966 DEBUG(dbgs() << "\nReplacing.4 ";
5968 dbgs() << "\nWith: ";
5969 Result.getNode()->dump(&DAG);
5971 WorkListRemover DeadNodes(*this);
5973 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5975 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5978 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5982 // Finally, since the node is now dead, remove it from the graph.
5985 // Replace the uses of Ptr with uses of the updated base value.
5986 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5988 removeFromWorkList(Ptr.getNode());
5989 DAG.DeleteNode(Ptr.getNode());
5994 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5995 /// add / sub of the base pointer node into a post-indexed load / store.
5996 /// The transformation folded the add / subtract into the new indexed
5997 /// load / store effectively and all of its uses are redirected to the
5998 /// new load / store.
5999 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6000 if (!LegalOperations)
6006 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6007 if (LD->isIndexed())
6009 VT = LD->getMemoryVT();
6010 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6011 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6013 Ptr = LD->getBasePtr();
6014 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6015 if (ST->isIndexed())
6017 VT = ST->getMemoryVT();
6018 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6019 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6021 Ptr = ST->getBasePtr();
6027 if (Ptr.getNode()->hasOneUse())
6030 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6031 E = Ptr.getNode()->use_end(); I != E; ++I) {
6034 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6039 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6040 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6041 // Don't create a indexed load / store with zero offset.
6042 if (isa<ConstantSDNode>(Offset) &&
6043 cast<ConstantSDNode>(Offset)->isNullValue())
6046 // Try turning it into a post-indexed load / store except when
6047 // 1) All uses are load / store ops that use it as base ptr.
6048 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6049 // nor a successor of N. Otherwise, if Op is folded that would
6052 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6056 bool TryNext = false;
6057 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6058 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6060 if (Use == Ptr.getNode())
6063 // If all the uses are load / store addresses, then don't do the
6065 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6066 bool RealUse = false;
6067 for (SDNode::use_iterator III = Use->use_begin(),
6068 EEE = Use->use_end(); III != EEE; ++III) {
6069 SDNode *UseUse = *III;
6070 if (!((UseUse->getOpcode() == ISD::LOAD &&
6071 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
6072 (UseUse->getOpcode() == ISD::STORE &&
6073 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
6088 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6089 SDValue Result = isLoad
6090 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6091 BasePtr, Offset, AM)
6092 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6093 BasePtr, Offset, AM);
6096 DEBUG(dbgs() << "\nReplacing.5 ";
6098 dbgs() << "\nWith: ";
6099 Result.getNode()->dump(&DAG);
6101 WorkListRemover DeadNodes(*this);
6103 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
6105 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
6108 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
6112 // Finally, since the node is now dead, remove it from the graph.
6115 // Replace the uses of Use with uses of the updated base value.
6116 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6117 Result.getValue(isLoad ? 1 : 0),
6119 removeFromWorkList(Op);
6129 SDValue DAGCombiner::visitLOAD(SDNode *N) {
6130 LoadSDNode *LD = cast<LoadSDNode>(N);
6131 SDValue Chain = LD->getChain();
6132 SDValue Ptr = LD->getBasePtr();
6134 // If load is not volatile and there are no uses of the loaded value (and
6135 // the updated indexed value in case of indexed loads), change uses of the
6136 // chain value into uses of the chain input (i.e. delete the dead load).
6137 if (!LD->isVolatile()) {
6138 if (N->getValueType(1) == MVT::Other) {
6140 if (N->hasNUsesOfValue(0, 0)) {
6141 // It's not safe to use the two value CombineTo variant here. e.g.
6142 // v1, chain2 = load chain1, loc
6143 // v2, chain3 = load chain2, loc
6145 // Now we replace use of chain2 with chain1. This makes the second load
6146 // isomorphic to the one we are deleting, and thus makes this load live.
6147 DEBUG(dbgs() << "\nReplacing.6 ";
6149 dbgs() << "\nWith chain: ";
6150 Chain.getNode()->dump(&DAG);
6152 WorkListRemover DeadNodes(*this);
6153 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
6155 if (N->use_empty()) {
6156 removeFromWorkList(N);
6160 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6164 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
6165 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
6166 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
6167 DEBUG(dbgs() << "\nReplacing.7 ";
6169 dbgs() << "\nWith: ";
6170 Undef.getNode()->dump(&DAG);
6171 dbgs() << " and 2 other values\n");
6172 WorkListRemover DeadNodes(*this);
6173 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
6174 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
6175 DAG.getUNDEF(N->getValueType(1)),
6177 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
6178 removeFromWorkList(N);
6180 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6185 // If this load is directly stored, replace the load value with the stored
6187 // TODO: Handle store large -> read small portion.
6188 // TODO: Handle TRUNCSTORE/LOADEXT
6189 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
6190 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
6191 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
6192 if (PrevST->getBasePtr() == Ptr &&
6193 PrevST->getValue().getValueType() == N->getValueType(0))
6194 return CombineTo(N, Chain.getOperand(1), Chain);
6198 // Try to infer better alignment information than the load already has.
6199 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
6200 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6201 if (Align > LD->getAlignment())
6202 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
6203 LD->getValueType(0),
6204 Chain, Ptr, LD->getPointerInfo(),
6206 LD->isVolatile(), LD->isNonTemporal(), Align);
6211 // Walk up chain skipping non-aliasing memory nodes.
6212 SDValue BetterChain = FindBetterChain(N, Chain);
6214 // If there is a better chain.
6215 if (Chain != BetterChain) {
6218 // Replace the chain to void dependency.
6219 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
6220 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
6221 BetterChain, Ptr, LD->getPointerInfo(),
6222 LD->isVolatile(), LD->isNonTemporal(),
6223 LD->getAlignment());
6225 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
6226 LD->getValueType(0),
6227 BetterChain, Ptr, LD->getPointerInfo(),
6230 LD->isNonTemporal(),
6231 LD->getAlignment());
6234 // Create token factor to keep old chain connected.
6235 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6236 MVT::Other, Chain, ReplLoad.getValue(1));
6238 // Make sure the new and old chains are cleaned up.
6239 AddToWorkList(Token.getNode());
6241 // Replace uses with load result and token factor. Don't add users
6243 return CombineTo(N, ReplLoad.getValue(0), Token, false);
6247 // Try transforming N to an indexed load.
6248 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6249 return SDValue(N, 0);
6254 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
6255 /// load is having specific bytes cleared out. If so, return the byte size
6256 /// being masked out and the shift amount.
6257 static std::pair<unsigned, unsigned>
6258 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
6259 std::pair<unsigned, unsigned> Result(0, 0);
6261 // Check for the structure we're looking for.
6262 if (V->getOpcode() != ISD::AND ||
6263 !isa<ConstantSDNode>(V->getOperand(1)) ||
6264 !ISD::isNormalLoad(V->getOperand(0).getNode()))
6267 // Check the chain and pointer.
6268 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
6269 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
6271 // The store should be chained directly to the load or be an operand of a
6273 if (LD == Chain.getNode())
6275 else if (Chain->getOpcode() != ISD::TokenFactor)
6276 return Result; // Fail.
6279 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
6280 if (Chain->getOperand(i).getNode() == LD) {
6284 if (!isOk) return Result;
6287 // This only handles simple types.
6288 if (V.getValueType() != MVT::i16 &&
6289 V.getValueType() != MVT::i32 &&
6290 V.getValueType() != MVT::i64)
6293 // Check the constant mask. Invert it so that the bits being masked out are
6294 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
6295 // follow the sign bit for uniformity.
6296 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
6297 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
6298 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
6299 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
6300 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
6301 if (NotMaskLZ == 64) return Result; // All zero mask.
6303 // See if we have a continuous run of bits. If so, we have 0*1+0*
6304 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
6307 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
6308 if (V.getValueType() != MVT::i64 && NotMaskLZ)
6309 NotMaskLZ -= 64-V.getValueSizeInBits();
6311 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
6312 switch (MaskedBytes) {
6316 default: return Result; // All one mask, or 5-byte mask.
6319 // Verify that the first bit starts at a multiple of mask so that the access
6320 // is aligned the same as the access width.
6321 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6323 Result.first = MaskedBytes;
6324 Result.second = NotMaskTZ/8;
6329 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6330 /// provides a value as specified by MaskInfo. If so, replace the specified
6331 /// store with a narrower store of truncated IVal.
6333 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6334 SDValue IVal, StoreSDNode *St,
6336 unsigned NumBytes = MaskInfo.first;
6337 unsigned ByteShift = MaskInfo.second;
6338 SelectionDAG &DAG = DC->getDAG();
6340 // Check to see if IVal is all zeros in the part being masked in by the 'or'
6341 // that uses this. If not, this is not a replacement.
6342 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6343 ByteShift*8, (ByteShift+NumBytes)*8);
6344 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6346 // Check that it is legal on the target to do this. It is legal if the new
6347 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6349 MVT VT = MVT::getIntegerVT(NumBytes*8);
6350 if (!DC->isTypeLegal(VT))
6353 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
6354 // shifted by ByteShift and truncated down to NumBytes.
6356 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6357 DAG.getConstant(ByteShift*8,
6358 DC->getShiftAmountTy(IVal.getValueType())));
6360 // Figure out the offset for the store and the alignment of the access.
6362 unsigned NewAlign = St->getAlignment();
6364 if (DAG.getTargetLoweringInfo().isLittleEndian())
6365 StOffset = ByteShift;
6367 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6369 SDValue Ptr = St->getBasePtr();
6371 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6372 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6373 NewAlign = MinAlign(NewAlign, StOffset);
6376 // Truncate down to the new size.
6377 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6380 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6381 St->getPointerInfo().getWithOffset(StOffset),
6382 false, false, NewAlign).getNode();
6386 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6387 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6388 /// of the loaded bits, try narrowing the load and store if it would end up
6389 /// being a win for performance or code size.
6390 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6391 StoreSDNode *ST = cast<StoreSDNode>(N);
6392 if (ST->isVolatile())
6395 SDValue Chain = ST->getChain();
6396 SDValue Value = ST->getValue();
6397 SDValue Ptr = ST->getBasePtr();
6398 EVT VT = Value.getValueType();
6400 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6403 unsigned Opc = Value.getOpcode();
6405 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
6406 // is a byte mask indicating a consecutive number of bytes, check to see if
6407 // Y is known to provide just those bytes. If so, we try to replace the
6408 // load + replace + store sequence with a single (narrower) store, which makes
6410 if (Opc == ISD::OR) {
6411 std::pair<unsigned, unsigned> MaskedLoad;
6412 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
6413 if (MaskedLoad.first)
6414 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6415 Value.getOperand(1), ST,this))
6416 return SDValue(NewST, 0);
6418 // Or is commutative, so try swapping X and Y.
6419 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
6420 if (MaskedLoad.first)
6421 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6422 Value.getOperand(0), ST,this))
6423 return SDValue(NewST, 0);
6426 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6427 Value.getOperand(1).getOpcode() != ISD::Constant)
6430 SDValue N0 = Value.getOperand(0);
6431 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6432 Chain == SDValue(N0.getNode(), 1)) {
6433 LoadSDNode *LD = cast<LoadSDNode>(N0);
6434 if (LD->getBasePtr() != Ptr ||
6435 LD->getPointerInfo().getAddrSpace() !=
6436 ST->getPointerInfo().getAddrSpace())
6439 // Find the type to narrow it the load / op / store to.
6440 SDValue N1 = Value.getOperand(1);
6441 unsigned BitWidth = N1.getValueSizeInBits();
6442 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
6443 if (Opc == ISD::AND)
6444 Imm ^= APInt::getAllOnesValue(BitWidth);
6445 if (Imm == 0 || Imm.isAllOnesValue())
6447 unsigned ShAmt = Imm.countTrailingZeros();
6448 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
6449 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
6450 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6451 while (NewBW < BitWidth &&
6452 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6453 TLI.isNarrowingProfitable(VT, NewVT))) {
6454 NewBW = NextPowerOf2(NewBW);
6455 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6457 if (NewBW >= BitWidth)
6460 // If the lsb changed does not start at the type bitwidth boundary,
6461 // start at the previous one.
6463 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
6464 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
6465 if ((Imm & Mask) == Imm) {
6466 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
6467 if (Opc == ISD::AND)
6468 NewImm ^= APInt::getAllOnesValue(NewBW);
6469 uint64_t PtrOff = ShAmt / 8;
6470 // For big endian targets, we need to adjust the offset to the pointer to
6471 // load the correct bytes.
6472 if (TLI.isBigEndian())
6473 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
6475 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
6476 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
6477 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
6480 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6481 Ptr.getValueType(), Ptr,
6482 DAG.getConstant(PtrOff, Ptr.getValueType()));
6483 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6484 LD->getChain(), NewPtr,
6485 LD->getPointerInfo().getWithOffset(PtrOff),
6486 LD->isVolatile(), LD->isNonTemporal(),
6488 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6489 DAG.getConstant(NewImm, NewVT));
6490 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6492 ST->getPointerInfo().getWithOffset(PtrOff),
6493 false, false, NewAlign);
6495 AddToWorkList(NewPtr.getNode());
6496 AddToWorkList(NewLD.getNode());
6497 AddToWorkList(NewVal.getNode());
6498 WorkListRemover DeadNodes(*this);
6499 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
6509 /// TransformFPLoadStorePair - For a given floating point load / store pair,
6510 /// if the load value isn't used by any other operations, then consider
6511 /// transforming the pair to integer load / store operations if the target
6512 /// deems the transformation profitable.
6513 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
6514 StoreSDNode *ST = cast<StoreSDNode>(N);
6515 SDValue Chain = ST->getChain();
6516 SDValue Value = ST->getValue();
6517 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6518 Value.hasOneUse() &&
6519 Chain == SDValue(Value.getNode(), 1)) {
6520 LoadSDNode *LD = cast<LoadSDNode>(Value);
6521 EVT VT = LD->getMemoryVT();
6522 if (!VT.isFloatingPoint() ||
6523 VT != ST->getMemoryVT() ||
6524 LD->isNonTemporal() ||
6525 ST->isNonTemporal() ||
6526 LD->getPointerInfo().getAddrSpace() != 0 ||
6527 ST->getPointerInfo().getAddrSpace() != 0)
6530 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
6531 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
6532 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
6533 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
6534 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
6537 unsigned LDAlign = LD->getAlignment();
6538 unsigned STAlign = ST->getAlignment();
6539 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
6540 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
6541 if (LDAlign < ABIAlign || STAlign < ABIAlign)
6544 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
6545 LD->getChain(), LD->getBasePtr(),
6546 LD->getPointerInfo(),
6547 false, false, LDAlign);
6549 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
6550 NewLD, ST->getBasePtr(),
6551 ST->getPointerInfo(),
6552 false, false, STAlign);
6554 AddToWorkList(NewLD.getNode());
6555 AddToWorkList(NewST.getNode());
6556 WorkListRemover DeadNodes(*this);
6557 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1),
6566 SDValue DAGCombiner::visitSTORE(SDNode *N) {
6567 StoreSDNode *ST = cast<StoreSDNode>(N);
6568 SDValue Chain = ST->getChain();
6569 SDValue Value = ST->getValue();
6570 SDValue Ptr = ST->getBasePtr();
6572 // If this is a store of a bit convert, store the input value if the
6573 // resultant store does not need a higher alignment than the original.
6574 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
6575 ST->isUnindexed()) {
6576 unsigned OrigAlign = ST->getAlignment();
6577 EVT SVT = Value.getOperand(0).getValueType();
6578 unsigned Align = TLI.getTargetData()->
6579 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
6580 if (Align <= OrigAlign &&
6581 ((!LegalOperations && !ST->isVolatile()) ||
6582 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
6583 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6584 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6585 ST->isNonTemporal(), OrigAlign);
6588 // Turn 'store undef, Ptr' -> nothing.
6589 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
6592 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
6593 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
6594 // NOTE: If the original store is volatile, this transform must not increase
6595 // the number of stores. For example, on x86-32 an f64 can be stored in one
6596 // processor operation but an i64 (which is not legal) requires two. So the
6597 // transform should not be done in this case.
6598 if (Value.getOpcode() != ISD::TargetConstantFP) {
6600 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
6601 default: llvm_unreachable("Unknown FP type");
6602 case MVT::f80: // We don't do this for these yet.
6607 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
6608 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6609 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
6610 bitcastToAPInt().getZExtValue(), MVT::i32);
6611 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6612 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6613 ST->isNonTemporal(), ST->getAlignment());
6617 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
6618 !ST->isVolatile()) ||
6619 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
6620 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
6621 getZExtValue(), MVT::i64);
6622 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6623 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6624 ST->isNonTemporal(), ST->getAlignment());
6627 if (!ST->isVolatile() &&
6628 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6629 // Many FP stores are not made apparent until after legalize, e.g. for
6630 // argument passing. Since this is so common, custom legalize the
6631 // 64-bit integer store into two 32-bit stores.
6632 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
6633 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
6634 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
6635 if (TLI.isBigEndian()) std::swap(Lo, Hi);
6637 unsigned Alignment = ST->getAlignment();
6638 bool isVolatile = ST->isVolatile();
6639 bool isNonTemporal = ST->isNonTemporal();
6641 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
6642 Ptr, ST->getPointerInfo(),
6643 isVolatile, isNonTemporal,
6644 ST->getAlignment());
6645 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
6646 DAG.getConstant(4, Ptr.getValueType()));
6647 Alignment = MinAlign(Alignment, 4U);
6648 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
6649 Ptr, ST->getPointerInfo().getWithOffset(4),
6650 isVolatile, isNonTemporal,
6652 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6661 // Try to infer better alignment information than the store already has.
6662 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
6663 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6664 if (Align > ST->getAlignment())
6665 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
6666 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6667 ST->isVolatile(), ST->isNonTemporal(), Align);
6671 // Try transforming a pair floating point load / store ops to integer
6672 // load / store ops.
6673 SDValue NewST = TransformFPLoadStorePair(N);
6674 if (NewST.getNode())
6678 // Walk up chain skipping non-aliasing memory nodes.
6679 SDValue BetterChain = FindBetterChain(N, Chain);
6681 // If there is a better chain.
6682 if (Chain != BetterChain) {
6685 // Replace the chain to avoid dependency.
6686 if (ST->isTruncatingStore()) {
6687 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6688 ST->getPointerInfo(),
6689 ST->getMemoryVT(), ST->isVolatile(),
6690 ST->isNonTemporal(), ST->getAlignment());
6692 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6693 ST->getPointerInfo(),
6694 ST->isVolatile(), ST->isNonTemporal(),
6695 ST->getAlignment());
6698 // Create token to keep both nodes around.
6699 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6700 MVT::Other, Chain, ReplStore);
6702 // Make sure the new and old chains are cleaned up.
6703 AddToWorkList(Token.getNode());
6705 // Don't add users to work list.
6706 return CombineTo(N, Token, false);
6710 // Try transforming N to an indexed store.
6711 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6712 return SDValue(N, 0);
6714 // FIXME: is there such a thing as a truncating indexed store?
6715 if (ST->isTruncatingStore() && ST->isUnindexed() &&
6716 Value.getValueType().isInteger()) {
6717 // See if we can simplify the input to this truncstore with knowledge that
6718 // only the low bits are being used. For example:
6719 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
6721 GetDemandedBits(Value,
6722 APInt::getLowBitsSet(
6723 Value.getValueType().getScalarType().getSizeInBits(),
6724 ST->getMemoryVT().getScalarType().getSizeInBits()));
6725 AddToWorkList(Value.getNode());
6726 if (Shorter.getNode())
6727 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6728 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6729 ST->isVolatile(), ST->isNonTemporal(),
6730 ST->getAlignment());
6732 // Otherwise, see if we can simplify the operation with
6733 // SimplifyDemandedBits, which only works if the value has a single use.
6734 if (SimplifyDemandedBits(Value,
6735 APInt::getLowBitsSet(
6736 Value.getValueType().getScalarType().getSizeInBits(),
6737 ST->getMemoryVT().getScalarType().getSizeInBits())))
6738 return SDValue(N, 0);
6741 // If this is a load followed by a store to the same location, then the store
6743 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6744 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6745 ST->isUnindexed() && !ST->isVolatile() &&
6746 // There can't be any side effects between the load and store, such as
6748 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6749 // The store is dead, remove it.
6754 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6755 // truncating store. We can do this even if this is already a truncstore.
6756 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6757 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6758 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6759 ST->getMemoryVT())) {
6760 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6761 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6762 ST->isVolatile(), ST->isNonTemporal(),
6763 ST->getAlignment());
6766 return ReduceLoadOpStoreWidth(N);
6769 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6770 SDValue InVec = N->getOperand(0);
6771 SDValue InVal = N->getOperand(1);
6772 SDValue EltNo = N->getOperand(2);
6774 // If the inserted element is an UNDEF, just use the input vector.
6775 if (InVal.getOpcode() == ISD::UNDEF)
6778 EVT VT = InVec.getValueType();
6780 // If we can't generate a legal BUILD_VECTOR, exit
6781 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
6784 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
6785 // vector with the inserted element.
6786 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
6787 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6788 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
6789 InVec.getNode()->op_end());
6790 if (Elt < Ops.size())
6792 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6793 VT, &Ops[0], Ops.size());
6795 // If the invec is an UNDEF and if EltNo is a constant, create a new
6796 // BUILD_VECTOR with undef elements and the inserted element.
6797 if (InVec.getOpcode() == ISD::UNDEF &&
6798 isa<ConstantSDNode>(EltNo)) {
6799 EVT EltVT = VT.getVectorElementType();
6800 unsigned NElts = VT.getVectorNumElements();
6801 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
6803 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6804 if (Elt < Ops.size())
6806 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6807 VT, &Ops[0], Ops.size());
6812 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6813 // (vextract (scalar_to_vector val, 0) -> val
6814 SDValue InVec = N->getOperand(0);
6816 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6817 // Check if the result type doesn't match the inserted element type. A
6818 // SCALAR_TO_VECTOR may truncate the inserted element and the
6819 // EXTRACT_VECTOR_ELT may widen the extracted vector.
6820 SDValue InOp = InVec.getOperand(0);
6821 EVT NVT = N->getValueType(0);
6822 if (InOp.getValueType() != NVT) {
6823 assert(InOp.getValueType().isInteger() && NVT.isInteger());
6824 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6829 // Perform only after legalization to ensure build_vector / vector_shuffle
6830 // optimizations have already been done.
6831 if (!LegalOperations) return SDValue();
6833 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6834 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6835 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6836 SDValue EltNo = N->getOperand(1);
6838 if (isa<ConstantSDNode>(EltNo)) {
6839 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6840 bool NewLoad = false;
6841 bool BCNumEltsChanged = false;
6842 EVT VT = InVec.getValueType();
6843 EVT ExtVT = VT.getVectorElementType();
6846 if (InVec.getOpcode() == ISD::BITCAST) {
6847 EVT BCVT = InVec.getOperand(0).getValueType();
6848 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6850 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6851 BCNumEltsChanged = true;
6852 InVec = InVec.getOperand(0);
6853 ExtVT = BCVT.getVectorElementType();
6857 LoadSDNode *LN0 = NULL;
6858 const ShuffleVectorSDNode *SVN = NULL;
6859 if (ISD::isNormalLoad(InVec.getNode())) {
6860 LN0 = cast<LoadSDNode>(InVec);
6861 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6862 InVec.getOperand(0).getValueType() == ExtVT &&
6863 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6864 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6865 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6866 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6868 // (load $addr+1*size)
6870 // If the bit convert changed the number of elements, it is unsafe
6871 // to examine the mask.
6872 if (BCNumEltsChanged)
6875 // Select the input vector, guarding against out of range extract vector.
6876 unsigned NumElems = VT.getVectorNumElements();
6877 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
6878 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6880 if (InVec.getOpcode() == ISD::BITCAST)
6881 InVec = InVec.getOperand(0);
6882 if (ISD::isNormalLoad(InVec.getNode())) {
6883 LN0 = cast<LoadSDNode>(InVec);
6884 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6888 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6891 // If Idx was -1 above, Elt is going to be -1, so just return undef.
6893 return DAG.getUNDEF(LVT);
6895 unsigned Align = LN0->getAlignment();
6897 // Check the resultant load doesn't need a higher alignment than the
6901 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6903 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6909 SDValue NewPtr = LN0->getBasePtr();
6910 unsigned PtrOff = 0;
6913 PtrOff = LVT.getSizeInBits() * Elt / 8;
6914 EVT PtrType = NewPtr.getValueType();
6915 if (TLI.isBigEndian())
6916 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6917 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6918 DAG.getConstant(PtrOff, PtrType));
6921 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6922 LN0->getPointerInfo().getWithOffset(PtrOff),
6923 LN0->isVolatile(), LN0->isNonTemporal(), Align);
6929 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6930 unsigned NumInScalars = N->getNumOperands();
6931 EVT VT = N->getValueType(0);
6933 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
6934 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
6935 // at most two distinct vectors, turn this into a shuffle node.
6936 SDValue VecIn1, VecIn2;
6937 for (unsigned i = 0; i != NumInScalars; ++i) {
6938 // Ignore undef inputs.
6939 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6941 // If this input is something other than a EXTRACT_VECTOR_ELT with a
6942 // constant index, bail out.
6943 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6944 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
6945 VecIn1 = VecIn2 = SDValue(0, 0);
6949 // If the input vector type disagrees with the result of the build_vector,
6950 // we can't make a shuffle.
6951 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
6952 if (ExtractedFromVec.getValueType() != VT) {
6953 VecIn1 = VecIn2 = SDValue(0, 0);
6957 // Otherwise, remember this. We allow up to two distinct input vectors.
6958 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
6961 if (VecIn1.getNode() == 0) {
6962 VecIn1 = ExtractedFromVec;
6963 } else if (VecIn2.getNode() == 0) {
6964 VecIn2 = ExtractedFromVec;
6967 VecIn1 = VecIn2 = SDValue(0, 0);
6972 // If everything is good, we can make a shuffle operation.
6973 if (VecIn1.getNode()) {
6974 SmallVector<int, 8> Mask;
6975 for (unsigned i = 0; i != NumInScalars; ++i) {
6976 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
6981 // If extracting from the first vector, just use the index directly.
6982 SDValue Extract = N->getOperand(i);
6983 SDValue ExtVal = Extract.getOperand(1);
6984 if (Extract.getOperand(0) == VecIn1) {
6985 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6986 if (ExtIndex > VT.getVectorNumElements())
6989 Mask.push_back(ExtIndex);
6993 // Otherwise, use InIdx + VecSize
6994 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6995 Mask.push_back(Idx+NumInScalars);
6998 // Add count and size info.
6999 if (!isTypeLegal(VT))
7002 // Return the new VECTOR_SHUFFLE node.
7005 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
7006 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
7012 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
7013 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
7014 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
7015 // inputs come from at most two distinct vectors, turn this into a shuffle
7018 // If we only have one input vector, we don't need to do any concatenation.
7019 if (N->getNumOperands() == 1)
7020 return N->getOperand(0);
7025 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
7026 EVT VT = N->getValueType(0);
7027 unsigned NumElts = VT.getVectorNumElements();
7029 SDValue N0 = N->getOperand(0);
7031 assert(N0.getValueType().getVectorNumElements() == NumElts &&
7032 "Vector shuffle must be normalized in DAG");
7034 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
7036 // If it is a splat, check if the argument vector is another splat or a
7037 // build_vector with all scalar elements the same.
7038 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7039 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
7040 SDNode *V = N0.getNode();
7042 // If this is a bit convert that changes the element type of the vector but
7043 // not the number of vector elements, look through it. Be careful not to
7044 // look though conversions that change things like v4f32 to v2f64.
7045 if (V->getOpcode() == ISD::BITCAST) {
7046 SDValue ConvInput = V->getOperand(0);
7047 if (ConvInput.getValueType().isVector() &&
7048 ConvInput.getValueType().getVectorNumElements() == NumElts)
7049 V = ConvInput.getNode();
7052 if (V->getOpcode() == ISD::BUILD_VECTOR) {
7053 assert(V->getNumOperands() == NumElts &&
7054 "BUILD_VECTOR has wrong number of operands");
7056 bool AllSame = true;
7057 for (unsigned i = 0; i != NumElts; ++i) {
7058 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
7059 Base = V->getOperand(i);
7063 // Splat of <u, u, u, u>, return <u, u, u, u>
7064 if (!Base.getNode())
7066 for (unsigned i = 0; i != NumElts; ++i) {
7067 if (V->getOperand(i) != Base) {
7072 // Splat of <x, x, x, x>, return <x, x, x, x>
7080 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
7081 if (!TLI.getShouldFoldAtomicFences())
7084 SDValue atomic = N->getOperand(0);
7085 switch (atomic.getOpcode()) {
7086 case ISD::ATOMIC_CMP_SWAP:
7087 case ISD::ATOMIC_SWAP:
7088 case ISD::ATOMIC_LOAD_ADD:
7089 case ISD::ATOMIC_LOAD_SUB:
7090 case ISD::ATOMIC_LOAD_AND:
7091 case ISD::ATOMIC_LOAD_OR:
7092 case ISD::ATOMIC_LOAD_XOR:
7093 case ISD::ATOMIC_LOAD_NAND:
7094 case ISD::ATOMIC_LOAD_MIN:
7095 case ISD::ATOMIC_LOAD_MAX:
7096 case ISD::ATOMIC_LOAD_UMIN:
7097 case ISD::ATOMIC_LOAD_UMAX:
7103 SDValue fence = atomic.getOperand(0);
7104 if (fence.getOpcode() != ISD::MEMBARRIER)
7107 switch (atomic.getOpcode()) {
7108 case ISD::ATOMIC_CMP_SWAP:
7109 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7110 fence.getOperand(0),
7111 atomic.getOperand(1), atomic.getOperand(2),
7112 atomic.getOperand(3)), atomic.getResNo());
7113 case ISD::ATOMIC_SWAP:
7114 case ISD::ATOMIC_LOAD_ADD:
7115 case ISD::ATOMIC_LOAD_SUB:
7116 case ISD::ATOMIC_LOAD_AND:
7117 case ISD::ATOMIC_LOAD_OR:
7118 case ISD::ATOMIC_LOAD_XOR:
7119 case ISD::ATOMIC_LOAD_NAND:
7120 case ISD::ATOMIC_LOAD_MIN:
7121 case ISD::ATOMIC_LOAD_MAX:
7122 case ISD::ATOMIC_LOAD_UMIN:
7123 case ISD::ATOMIC_LOAD_UMAX:
7124 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7125 fence.getOperand(0),
7126 atomic.getOperand(1), atomic.getOperand(2)),
7133 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
7134 /// an AND to a vector_shuffle with the destination vector and a zero vector.
7135 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
7136 /// vector_shuffle V, Zero, <0, 4, 2, 4>
7137 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
7138 EVT VT = N->getValueType(0);
7139 DebugLoc dl = N->getDebugLoc();
7140 SDValue LHS = N->getOperand(0);
7141 SDValue RHS = N->getOperand(1);
7142 if (N->getOpcode() == ISD::AND) {
7143 if (RHS.getOpcode() == ISD::BITCAST)
7144 RHS = RHS.getOperand(0);
7145 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
7146 SmallVector<int, 8> Indices;
7147 unsigned NumElts = RHS.getNumOperands();
7148 for (unsigned i = 0; i != NumElts; ++i) {
7149 SDValue Elt = RHS.getOperand(i);
7150 if (!isa<ConstantSDNode>(Elt))
7152 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
7153 Indices.push_back(i);
7154 else if (cast<ConstantSDNode>(Elt)->isNullValue())
7155 Indices.push_back(NumElts);
7160 // Let's see if the target supports this vector_shuffle.
7161 EVT RVT = RHS.getValueType();
7162 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
7165 // Return the new VECTOR_SHUFFLE node.
7166 EVT EltVT = RVT.getVectorElementType();
7167 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
7168 DAG.getConstant(0, EltVT));
7169 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7170 RVT, &ZeroOps[0], ZeroOps.size());
7171 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
7172 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
7173 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
7180 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
7181 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
7182 // After legalize, the target may be depending on adds and other
7183 // binary ops to provide legal ways to construct constants or other
7184 // things. Simplifying them may result in a loss of legality.
7185 if (LegalOperations) return SDValue();
7187 assert(N->getValueType(0).isVector() &&
7188 "SimplifyVBinOp only works on vectors!");
7190 SDValue LHS = N->getOperand(0);
7191 SDValue RHS = N->getOperand(1);
7192 SDValue Shuffle = XformToShuffleWithZero(N);
7193 if (Shuffle.getNode()) return Shuffle;
7195 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
7197 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
7198 RHS.getOpcode() == ISD::BUILD_VECTOR) {
7199 SmallVector<SDValue, 8> Ops;
7200 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
7201 SDValue LHSOp = LHS.getOperand(i);
7202 SDValue RHSOp = RHS.getOperand(i);
7203 // If these two elements can't be folded, bail out.
7204 if ((LHSOp.getOpcode() != ISD::UNDEF &&
7205 LHSOp.getOpcode() != ISD::Constant &&
7206 LHSOp.getOpcode() != ISD::ConstantFP) ||
7207 (RHSOp.getOpcode() != ISD::UNDEF &&
7208 RHSOp.getOpcode() != ISD::Constant &&
7209 RHSOp.getOpcode() != ISD::ConstantFP))
7212 // Can't fold divide by zero.
7213 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
7214 N->getOpcode() == ISD::FDIV) {
7215 if ((RHSOp.getOpcode() == ISD::Constant &&
7216 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
7217 (RHSOp.getOpcode() == ISD::ConstantFP &&
7218 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
7222 EVT VT = LHSOp.getValueType();
7223 assert(RHSOp.getValueType() == VT &&
7224 "SimplifyVBinOp with different BUILD_VECTOR element types");
7225 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
7227 if (FoldOp.getOpcode() != ISD::UNDEF &&
7228 FoldOp.getOpcode() != ISD::Constant &&
7229 FoldOp.getOpcode() != ISD::ConstantFP)
7231 Ops.push_back(FoldOp);
7232 AddToWorkList(FoldOp.getNode());
7235 if (Ops.size() == LHS.getNumOperands())
7236 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7237 LHS.getValueType(), &Ops[0], Ops.size());
7243 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
7244 SDValue N1, SDValue N2){
7245 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
7247 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
7248 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7250 // If we got a simplified select_cc node back from SimplifySelectCC, then
7251 // break it down into a new SETCC node, and a new SELECT node, and then return
7252 // the SELECT node, since we were called with a SELECT node.
7253 if (SCC.getNode()) {
7254 // Check to see if we got a select_cc back (to turn into setcc/select).
7255 // Otherwise, just return whatever node we got back, like fabs.
7256 if (SCC.getOpcode() == ISD::SELECT_CC) {
7257 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
7259 SCC.getOperand(0), SCC.getOperand(1),
7261 AddToWorkList(SETCC.getNode());
7262 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
7263 SCC.getOperand(2), SCC.getOperand(3), SETCC);
7271 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
7272 /// are the two values being selected between, see if we can simplify the
7273 /// select. Callers of this should assume that TheSelect is deleted if this
7274 /// returns true. As such, they should return the appropriate thing (e.g. the
7275 /// node) back to the top-level of the DAG combiner loop to avoid it being
7277 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
7280 // Cannot simplify select with vector condition
7281 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
7283 // If this is a select from two identical things, try to pull the operation
7284 // through the select.
7285 if (LHS.getOpcode() != RHS.getOpcode() ||
7286 !LHS.hasOneUse() || !RHS.hasOneUse())
7289 // If this is a load and the token chain is identical, replace the select
7290 // of two loads with a load through a select of the address to load from.
7291 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
7292 // constants have been dropped into the constant pool.
7293 if (LHS.getOpcode() == ISD::LOAD) {
7294 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
7295 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
7297 // Token chains must be identical.
7298 if (LHS.getOperand(0) != RHS.getOperand(0) ||
7299 // Do not let this transformation reduce the number of volatile loads.
7300 LLD->isVolatile() || RLD->isVolatile() ||
7301 // If this is an EXTLOAD, the VT's must match.
7302 LLD->getMemoryVT() != RLD->getMemoryVT() ||
7303 // If this is an EXTLOAD, the kind of extension must match.
7304 (LLD->getExtensionType() != RLD->getExtensionType() &&
7305 // The only exception is if one of the extensions is anyext.
7306 LLD->getExtensionType() != ISD::EXTLOAD &&
7307 RLD->getExtensionType() != ISD::EXTLOAD) ||
7308 // FIXME: this discards src value information. This is
7309 // over-conservative. It would be beneficial to be able to remember
7310 // both potential memory locations. Since we are discarding
7311 // src value info, don't do the transformation if the memory
7312 // locations are not in the default address space.
7313 LLD->getPointerInfo().getAddrSpace() != 0 ||
7314 RLD->getPointerInfo().getAddrSpace() != 0)
7317 // Check that the select condition doesn't reach either load. If so,
7318 // folding this will induce a cycle into the DAG. If not, this is safe to
7319 // xform, so create a select of the addresses.
7321 if (TheSelect->getOpcode() == ISD::SELECT) {
7322 SDNode *CondNode = TheSelect->getOperand(0).getNode();
7323 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
7324 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
7326 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
7327 LLD->getBasePtr().getValueType(),
7328 TheSelect->getOperand(0), LLD->getBasePtr(),
7330 } else { // Otherwise SELECT_CC
7331 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
7332 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
7334 if ((LLD->hasAnyUseOfValue(1) &&
7335 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
7336 (LLD->hasAnyUseOfValue(1) &&
7337 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
7340 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
7341 LLD->getBasePtr().getValueType(),
7342 TheSelect->getOperand(0),
7343 TheSelect->getOperand(1),
7344 LLD->getBasePtr(), RLD->getBasePtr(),
7345 TheSelect->getOperand(4));
7349 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
7350 Load = DAG.getLoad(TheSelect->getValueType(0),
7351 TheSelect->getDebugLoc(),
7352 // FIXME: Discards pointer info.
7353 LLD->getChain(), Addr, MachinePointerInfo(),
7354 LLD->isVolatile(), LLD->isNonTemporal(),
7355 LLD->getAlignment());
7357 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
7358 RLD->getExtensionType() : LLD->getExtensionType(),
7359 TheSelect->getDebugLoc(),
7360 TheSelect->getValueType(0),
7361 // FIXME: Discards pointer info.
7362 LLD->getChain(), Addr, MachinePointerInfo(),
7363 LLD->getMemoryVT(), LLD->isVolatile(),
7364 LLD->isNonTemporal(), LLD->getAlignment());
7367 // Users of the select now use the result of the load.
7368 CombineTo(TheSelect, Load);
7370 // Users of the old loads now use the new load's chain. We know the
7371 // old-load value is dead now.
7372 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
7373 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
7380 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
7381 /// where 'cond' is the comparison specified by CC.
7382 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
7383 SDValue N2, SDValue N3,
7384 ISD::CondCode CC, bool NotExtCompare) {
7385 // (x ? y : y) -> y.
7386 if (N2 == N3) return N2;
7388 EVT VT = N2.getValueType();
7389 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
7390 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
7391 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
7393 // Determine if the condition we're dealing with is constant
7394 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
7395 N0, N1, CC, DL, false);
7396 if (SCC.getNode()) AddToWorkList(SCC.getNode());
7397 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
7399 // fold select_cc true, x, y -> x
7400 if (SCCC && !SCCC->isNullValue())
7402 // fold select_cc false, x, y -> y
7403 if (SCCC && SCCC->isNullValue())
7406 // Check to see if we can simplify the select into an fabs node
7407 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
7408 // Allow either -0.0 or 0.0
7409 if (CFP->getValueAPF().isZero()) {
7410 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
7411 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
7412 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
7413 N2 == N3.getOperand(0))
7414 return DAG.getNode(ISD::FABS, DL, VT, N0);
7416 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
7417 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
7418 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
7419 N2.getOperand(0) == N3)
7420 return DAG.getNode(ISD::FABS, DL, VT, N3);
7424 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
7425 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
7426 // in it. This is a win when the constant is not otherwise available because
7427 // it replaces two constant pool loads with one. We only do this if the FP
7428 // type is known to be legal, because if it isn't, then we are before legalize
7429 // types an we want the other legalization to happen first (e.g. to avoid
7430 // messing with soft float) and if the ConstantFP is not legal, because if
7431 // it is legal, we may not need to store the FP constant in a constant pool.
7432 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
7433 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
7434 if (TLI.isTypeLegal(N2.getValueType()) &&
7435 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
7436 TargetLowering::Legal) &&
7437 // If both constants have multiple uses, then we won't need to do an
7438 // extra load, they are likely around in registers for other users.
7439 (TV->hasOneUse() || FV->hasOneUse())) {
7440 Constant *Elts[] = {
7441 const_cast<ConstantFP*>(FV->getConstantFPValue()),
7442 const_cast<ConstantFP*>(TV->getConstantFPValue())
7444 Type *FPTy = Elts[0]->getType();
7445 const TargetData &TD = *TLI.getTargetData();
7447 // Create a ConstantArray of the two constants.
7448 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
7449 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
7450 TD.getPrefTypeAlignment(FPTy));
7451 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
7453 // Get the offsets to the 0 and 1 element of the array so that we can
7454 // select between them.
7455 SDValue Zero = DAG.getIntPtrConstant(0);
7456 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
7457 SDValue One = DAG.getIntPtrConstant(EltSize);
7459 SDValue Cond = DAG.getSetCC(DL,
7460 TLI.getSetCCResultType(N0.getValueType()),
7462 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
7464 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
7466 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
7467 MachinePointerInfo::getConstantPool(), false,
7473 // Check to see if we can perform the "gzip trick", transforming
7474 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
7475 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
7476 N0.getValueType().isInteger() &&
7477 N2.getValueType().isInteger() &&
7478 (N1C->isNullValue() || // (a < 0) ? b : 0
7479 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
7480 EVT XType = N0.getValueType();
7481 EVT AType = N2.getValueType();
7482 if (XType.bitsGE(AType)) {
7483 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
7484 // single-bit constant.
7485 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
7486 unsigned ShCtV = N2C->getAPIntValue().logBase2();
7487 ShCtV = XType.getSizeInBits()-ShCtV-1;
7488 SDValue ShCt = DAG.getConstant(ShCtV,
7489 getShiftAmountTy(N0.getValueType()));
7490 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
7492 AddToWorkList(Shift.getNode());
7494 if (XType.bitsGT(AType)) {
7495 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7496 AddToWorkList(Shift.getNode());
7499 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7502 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
7504 DAG.getConstant(XType.getSizeInBits()-1,
7505 getShiftAmountTy(N0.getValueType())));
7506 AddToWorkList(Shift.getNode());
7508 if (XType.bitsGT(AType)) {
7509 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7510 AddToWorkList(Shift.getNode());
7513 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7517 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
7518 // where y is has a single bit set.
7519 // A plaintext description would be, we can turn the SELECT_CC into an AND
7520 // when the condition can be materialized as an all-ones register. Any
7521 // single bit-test can be materialized as an all-ones register with
7522 // shift-left and shift-right-arith.
7523 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
7524 N0->getValueType(0) == VT &&
7525 N1C && N1C->isNullValue() &&
7526 N2C && N2C->isNullValue()) {
7527 SDValue AndLHS = N0->getOperand(0);
7528 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
7529 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
7530 // Shift the tested bit over the sign bit.
7531 APInt AndMask = ConstAndRHS->getAPIntValue();
7533 DAG.getConstant(AndMask.countLeadingZeros(),
7534 getShiftAmountTy(AndLHS.getValueType()));
7535 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
7537 // Now arithmetic right shift it all the way over, so the result is either
7538 // all-ones, or zero.
7540 DAG.getConstant(AndMask.getBitWidth()-1,
7541 getShiftAmountTy(Shl.getValueType()));
7542 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
7544 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
7548 // fold select C, 16, 0 -> shl C, 4
7549 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
7550 TLI.getBooleanContents(N0.getValueType().isVector()) ==
7551 TargetLowering::ZeroOrOneBooleanContent) {
7553 // If the caller doesn't want us to simplify this into a zext of a compare,
7555 if (NotExtCompare && N2C->getAPIntValue() == 1)
7558 // Get a SetCC of the condition
7559 // FIXME: Should probably make sure that setcc is legal if we ever have a
7560 // target where it isn't.
7562 // cast from setcc result type to select result type
7564 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
7566 if (N2.getValueType().bitsLT(SCC.getValueType()))
7567 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
7569 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7570 N2.getValueType(), SCC);
7572 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
7573 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7574 N2.getValueType(), SCC);
7577 AddToWorkList(SCC.getNode());
7578 AddToWorkList(Temp.getNode());
7580 if (N2C->getAPIntValue() == 1)
7583 // shl setcc result by log2 n2c
7584 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
7585 DAG.getConstant(N2C->getAPIntValue().logBase2(),
7586 getShiftAmountTy(Temp.getValueType())));
7589 // Check to see if this is the equivalent of setcc
7590 // FIXME: Turn all of these into setcc if setcc if setcc is legal
7591 // otherwise, go ahead with the folds.
7592 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
7593 EVT XType = N0.getValueType();
7594 if (!LegalOperations ||
7595 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
7596 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
7597 if (Res.getValueType() != VT)
7598 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
7602 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
7603 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
7604 (!LegalOperations ||
7605 TLI.isOperationLegal(ISD::CTLZ, XType))) {
7606 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
7607 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
7608 DAG.getConstant(Log2_32(XType.getSizeInBits()),
7609 getShiftAmountTy(Ctlz.getValueType())));
7611 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
7612 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
7613 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
7614 XType, DAG.getConstant(0, XType), N0);
7615 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
7616 return DAG.getNode(ISD::SRL, DL, XType,
7617 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
7618 DAG.getConstant(XType.getSizeInBits()-1,
7619 getShiftAmountTy(XType)));
7621 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
7622 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
7623 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
7624 DAG.getConstant(XType.getSizeInBits()-1,
7625 getShiftAmountTy(N0.getValueType())));
7626 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
7630 // Check to see if this is an integer abs.
7631 // select_cc setg[te] X, 0, X, -X ->
7632 // select_cc setgt X, -1, X, -X ->
7633 // select_cc setl[te] X, 0, -X, X ->
7634 // select_cc setlt X, 1, -X, X ->
7635 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
7637 ConstantSDNode *SubC = NULL;
7638 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
7639 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
7640 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
7641 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
7642 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
7643 (N1C->isOne() && CC == ISD::SETLT)) &&
7644 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
7645 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
7647 EVT XType = N0.getValueType();
7648 if (SubC && SubC->isNullValue() && XType.isInteger()) {
7649 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
7651 DAG.getConstant(XType.getSizeInBits()-1,
7652 getShiftAmountTy(N0.getValueType())));
7653 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
7655 AddToWorkList(Shift.getNode());
7656 AddToWorkList(Add.getNode());
7657 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
7664 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
7665 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
7666 SDValue N1, ISD::CondCode Cond,
7667 DebugLoc DL, bool foldBooleans) {
7668 TargetLowering::DAGCombinerInfo
7669 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
7670 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
7673 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
7674 /// return a DAG expression to select that will generate the same value by
7675 /// multiplying by a magic number. See:
7676 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7677 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
7678 std::vector<SDNode*> Built;
7679 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
7681 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7687 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
7688 /// return a DAG expression to select that will generate the same value by
7689 /// multiplying by a magic number. See:
7690 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7691 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
7692 std::vector<SDNode*> Built;
7693 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
7695 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7701 /// FindBaseOffset - Return true if base is a frame index, which is known not
7702 // to alias with anything but itself. Provides base object and offset as
7704 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
7705 const GlobalValue *&GV, void *&CV) {
7706 // Assume it is a primitive operation.
7707 Base = Ptr; Offset = 0; GV = 0; CV = 0;
7709 // If it's an adding a simple constant then integrate the offset.
7710 if (Base.getOpcode() == ISD::ADD) {
7711 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
7712 Base = Base.getOperand(0);
7713 Offset += C->getZExtValue();
7717 // Return the underlying GlobalValue, and update the Offset. Return false
7718 // for GlobalAddressSDNode since the same GlobalAddress may be represented
7719 // by multiple nodes with different offsets.
7720 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
7721 GV = G->getGlobal();
7722 Offset += G->getOffset();
7726 // Return the underlying Constant value, and update the Offset. Return false
7727 // for ConstantSDNodes since the same constant pool entry may be represented
7728 // by multiple nodes with different offsets.
7729 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
7730 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
7731 : (void *)C->getConstVal();
7732 Offset += C->getOffset();
7735 // If it's any of the following then it can't alias with anything but itself.
7736 return isa<FrameIndexSDNode>(Base);
7739 /// isAlias - Return true if there is any possibility that the two addresses
7741 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
7742 const Value *SrcValue1, int SrcValueOffset1,
7743 unsigned SrcValueAlign1,
7744 const MDNode *TBAAInfo1,
7745 SDValue Ptr2, int64_t Size2,
7746 const Value *SrcValue2, int SrcValueOffset2,
7747 unsigned SrcValueAlign2,
7748 const MDNode *TBAAInfo2) const {
7749 // If they are the same then they must be aliases.
7750 if (Ptr1 == Ptr2) return true;
7752 // Gather base node and offset information.
7753 SDValue Base1, Base2;
7754 int64_t Offset1, Offset2;
7755 const GlobalValue *GV1, *GV2;
7757 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
7758 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
7760 // If they have a same base address then check to see if they overlap.
7761 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
7762 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7764 // It is possible for different frame indices to alias each other, mostly
7765 // when tail call optimization reuses return address slots for arguments.
7766 // To catch this case, look up the actual index of frame indices to compute
7767 // the real alias relationship.
7768 if (isFrameIndex1 && isFrameIndex2) {
7769 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7770 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
7771 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
7772 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7775 // Otherwise, if we know what the bases are, and they aren't identical, then
7776 // we know they cannot alias.
7777 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
7780 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
7781 // compared to the size and offset of the access, we may be able to prove they
7782 // do not alias. This check is conservative for now to catch cases created by
7783 // splitting vector types.
7784 if ((SrcValueAlign1 == SrcValueAlign2) &&
7785 (SrcValueOffset1 != SrcValueOffset2) &&
7786 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
7787 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
7788 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
7790 // There is no overlap between these relatively aligned accesses of similar
7791 // size, return no alias.
7792 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
7796 if (CombinerGlobalAA) {
7797 // Use alias analysis information.
7798 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
7799 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
7800 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
7801 AliasAnalysis::AliasResult AAResult =
7802 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
7803 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
7804 if (AAResult == AliasAnalysis::NoAlias)
7808 // Otherwise we have to assume they alias.
7812 /// FindAliasInfo - Extracts the relevant alias information from the memory
7813 /// node. Returns true if the operand was a load.
7814 bool DAGCombiner::FindAliasInfo(SDNode *N,
7815 SDValue &Ptr, int64_t &Size,
7816 const Value *&SrcValue,
7817 int &SrcValueOffset,
7818 unsigned &SrcValueAlign,
7819 const MDNode *&TBAAInfo) const {
7820 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7821 Ptr = LD->getBasePtr();
7822 Size = LD->getMemoryVT().getSizeInBits() >> 3;
7823 SrcValue = LD->getSrcValue();
7824 SrcValueOffset = LD->getSrcValueOffset();
7825 SrcValueAlign = LD->getOriginalAlignment();
7826 TBAAInfo = LD->getTBAAInfo();
7829 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7830 Ptr = ST->getBasePtr();
7831 Size = ST->getMemoryVT().getSizeInBits() >> 3;
7832 SrcValue = ST->getSrcValue();
7833 SrcValueOffset = ST->getSrcValueOffset();
7834 SrcValueAlign = ST->getOriginalAlignment();
7835 TBAAInfo = ST->getTBAAInfo();
7838 llvm_unreachable("FindAliasInfo expected a memory operand");
7841 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7842 /// looking for aliasing nodes and adding them to the Aliases vector.
7843 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7844 SmallVector<SDValue, 8> &Aliases) {
7845 SmallVector<SDValue, 8> Chains; // List of chains to visit.
7846 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
7848 // Get alias information for node.
7851 const Value *SrcValue;
7853 unsigned SrcValueAlign;
7854 const MDNode *SrcTBAAInfo;
7855 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
7856 SrcValueAlign, SrcTBAAInfo);
7859 Chains.push_back(OriginalChain);
7862 // Look at each chain and determine if it is an alias. If so, add it to the
7863 // aliases list. If not, then continue up the chain looking for the next
7865 while (!Chains.empty()) {
7866 SDValue Chain = Chains.back();
7869 // For TokenFactor nodes, look at each operand and only continue up the
7870 // chain until we find two aliases. If we've seen two aliases, assume we'll
7871 // find more and revert to original chain since the xform is unlikely to be
7874 // FIXME: The depth check could be made to return the last non-aliasing
7875 // chain we found before we hit a tokenfactor rather than the original
7877 if (Depth > 6 || Aliases.size() == 2) {
7879 Aliases.push_back(OriginalChain);
7883 // Don't bother if we've been before.
7884 if (!Visited.insert(Chain.getNode()))
7887 switch (Chain.getOpcode()) {
7888 case ISD::EntryToken:
7889 // Entry token is ideal chain operand, but handled in FindBetterChain.
7894 // Get alias information for Chain.
7897 const Value *OpSrcValue;
7898 int OpSrcValueOffset;
7899 unsigned OpSrcValueAlign;
7900 const MDNode *OpSrcTBAAInfo;
7901 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
7902 OpSrcValue, OpSrcValueOffset,
7906 // If chain is alias then stop here.
7907 if (!(IsLoad && IsOpLoad) &&
7908 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
7910 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
7911 OpSrcValueAlign, OpSrcTBAAInfo)) {
7912 Aliases.push_back(Chain);
7914 // Look further up the chain.
7915 Chains.push_back(Chain.getOperand(0));
7921 case ISD::TokenFactor:
7922 // We have to check each of the operands of the token factor for "small"
7923 // token factors, so we queue them up. Adding the operands to the queue
7924 // (stack) in reverse order maintains the original order and increases the
7925 // likelihood that getNode will find a matching token factor (CSE.)
7926 if (Chain.getNumOperands() > 16) {
7927 Aliases.push_back(Chain);
7930 for (unsigned n = Chain.getNumOperands(); n;)
7931 Chains.push_back(Chain.getOperand(--n));
7936 // For all other instructions we will just have to take what we can get.
7937 Aliases.push_back(Chain);
7943 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
7944 /// for a better chain (aliasing node.)
7945 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
7946 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
7948 // Accumulate all the aliases to this node.
7949 GatherAllAliases(N, OldChain, Aliases);
7951 // If no operands then chain to entry token.
7952 if (Aliases.size() == 0)
7953 return DAG.getEntryNode();
7955 // If a single operand then chain to it. We don't need to revisit it.
7956 if (Aliases.size() == 1)
7959 // Construct a custom tailored token factor.
7960 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7961 &Aliases[0], Aliases.size());
7964 // SelectionDAG::Combine - This is the entry point for the file.
7966 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
7967 CodeGenOpt::Level OptLevel) {
7968 /// run - This is the main entry point to this class.
7970 DAGCombiner(*this, AA, OptLevel).Run(Level);