1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
41 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
42 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
44 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48 CombinerAA("combiner-alias-analysis", cl::Hidden,
49 cl::desc("Turn on alias analysis during testing"));
52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
53 cl::desc("Include global information in alias analysis"));
55 //------------------------------ DAGCombiner ---------------------------------//
59 const TargetLowering &TLI;
61 CodeGenOpt::Level OptLevel;
65 // Worklist of all of the nodes that need to be simplified.
67 // This has the semantics that when adding to the worklist,
68 // the item added must be next to be processed. It should
69 // also only appear once. The naive approach to this takes
72 // To reduce the insert/remove time to logarithmic, we use
73 // a set and a vector to maintain our worklist.
75 // The set contains the items on the worklist, but does not
76 // maintain the order they should be visited.
78 // The vector maintains the order nodes should be visited, but may
79 // contain duplicate or removed nodes. When choosing a node to
80 // visit, we pop off the order stack until we find an item that is
81 // also in the contents set. All operations are O(log N).
82 SmallPtrSet<SDNode*, 64> WorkListContents;
83 SmallVector<SDNode*, 64> WorkListOrder;
85 // AA - Used for DAG load/store alias analysis.
88 /// AddUsersToWorkList - When an instruction is simplified, add all users of
89 /// the instruction to the work lists because they might get more simplified
92 void AddUsersToWorkList(SDNode *N) {
93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
98 /// visit - call the node-specific routine that knows how to fold each
99 /// particular type of node.
100 SDValue visit(SDNode *N);
103 /// AddToWorkList - Add to the work list making sure its instance is at the
104 /// back (next to be processed.)
105 void AddToWorkList(SDNode *N) {
106 WorkListContents.insert(N);
107 WorkListOrder.push_back(N);
110 /// removeFromWorkList - remove all instances of N from the worklist.
112 void removeFromWorkList(SDNode *N) {
113 WorkListContents.erase(N);
116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
120 return CombineTo(N, &Res, 1, AddTo);
123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
125 SDValue To[] = { Res0, Res1 };
126 return CombineTo(N, To, 2, AddTo);
129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
133 /// SimplifyDemandedBits - Check the specified integer node value to see if
134 /// it can be simplified or if things it uses can be simplified by bit
135 /// propagation. If so, return true.
136 bool SimplifyDemandedBits(SDValue Op) {
137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
138 APInt Demanded = APInt::getAllOnesValue(BitWidth);
139 return SimplifyDemandedBits(Op, Demanded);
142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
144 bool CombineToPreIndexedLoadStore(SDNode *N);
145 bool CombineToPostIndexedLoadStore(SDNode *N);
147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue PromoteIntBinOp(SDValue Op);
152 SDValue PromoteIntShiftOp(SDValue Op);
153 SDValue PromoteExtend(SDValue Op);
154 bool PromoteLoad(SDValue Op);
156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
158 ISD::NodeType ExtType);
160 /// combine - call the node-specific routine that knows how to fold each
161 /// particular type of node. If that doesn't do anything, try the
162 /// target-specific DAG combines.
163 SDValue combine(SDNode *N);
165 // Visitation implementation - Implement dag node combining for different
166 // node types. The semantics are as follows:
168 // SDValue.getNode() == 0 - No change was made
169 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
170 // otherwise - N should be replaced by the returned Operand.
172 SDValue visitTokenFactor(SDNode *N);
173 SDValue visitMERGE_VALUES(SDNode *N);
174 SDValue visitADD(SDNode *N);
175 SDValue visitSUB(SDNode *N);
176 SDValue visitADDC(SDNode *N);
177 SDValue visitSUBC(SDNode *N);
178 SDValue visitADDE(SDNode *N);
179 SDValue visitSUBE(SDNode *N);
180 SDValue visitMUL(SDNode *N);
181 SDValue visitSDIV(SDNode *N);
182 SDValue visitUDIV(SDNode *N);
183 SDValue visitSREM(SDNode *N);
184 SDValue visitUREM(SDNode *N);
185 SDValue visitMULHU(SDNode *N);
186 SDValue visitMULHS(SDNode *N);
187 SDValue visitSMUL_LOHI(SDNode *N);
188 SDValue visitUMUL_LOHI(SDNode *N);
189 SDValue visitSMULO(SDNode *N);
190 SDValue visitUMULO(SDNode *N);
191 SDValue visitSDIVREM(SDNode *N);
192 SDValue visitUDIVREM(SDNode *N);
193 SDValue visitAND(SDNode *N);
194 SDValue visitOR(SDNode *N);
195 SDValue visitXOR(SDNode *N);
196 SDValue SimplifyVBinOp(SDNode *N);
197 SDValue visitSHL(SDNode *N);
198 SDValue visitSRA(SDNode *N);
199 SDValue visitSRL(SDNode *N);
200 SDValue visitCTLZ(SDNode *N);
201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
202 SDValue visitCTTZ(SDNode *N);
203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
204 SDValue visitCTPOP(SDNode *N);
205 SDValue visitSELECT(SDNode *N);
206 SDValue visitSELECT_CC(SDNode *N);
207 SDValue visitSETCC(SDNode *N);
208 SDValue visitSIGN_EXTEND(SDNode *N);
209 SDValue visitZERO_EXTEND(SDNode *N);
210 SDValue visitANY_EXTEND(SDNode *N);
211 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
212 SDValue visitTRUNCATE(SDNode *N);
213 SDValue visitBITCAST(SDNode *N);
214 SDValue visitBUILD_PAIR(SDNode *N);
215 SDValue visitFADD(SDNode *N);
216 SDValue visitFSUB(SDNode *N);
217 SDValue visitFMUL(SDNode *N);
218 SDValue visitFMA(SDNode *N);
219 SDValue visitFDIV(SDNode *N);
220 SDValue visitFREM(SDNode *N);
221 SDValue visitFCOPYSIGN(SDNode *N);
222 SDValue visitSINT_TO_FP(SDNode *N);
223 SDValue visitUINT_TO_FP(SDNode *N);
224 SDValue visitFP_TO_SINT(SDNode *N);
225 SDValue visitFP_TO_UINT(SDNode *N);
226 SDValue visitFP_ROUND(SDNode *N);
227 SDValue visitFP_ROUND_INREG(SDNode *N);
228 SDValue visitFP_EXTEND(SDNode *N);
229 SDValue visitFNEG(SDNode *N);
230 SDValue visitFABS(SDNode *N);
231 SDValue visitBRCOND(SDNode *N);
232 SDValue visitBR_CC(SDNode *N);
233 SDValue visitLOAD(SDNode *N);
234 SDValue visitSTORE(SDNode *N);
235 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
236 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
237 SDValue visitBUILD_VECTOR(SDNode *N);
238 SDValue visitCONCAT_VECTORS(SDNode *N);
239 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
240 SDValue visitVECTOR_SHUFFLE(SDNode *N);
241 SDValue visitMEMBARRIER(SDNode *N);
243 SDValue XformToShuffleWithZero(SDNode *N);
244 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
246 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
248 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
249 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
250 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
251 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
252 SDValue N3, ISD::CondCode CC,
253 bool NotExtCompare = false);
254 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
255 DebugLoc DL, bool foldBooleans = true);
256 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
258 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
259 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
260 SDValue BuildSDIV(SDNode *N);
261 SDValue BuildUDIV(SDNode *N);
262 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
263 bool DemandHighBits = true);
264 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
265 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
266 SDValue ReduceLoadWidth(SDNode *N);
267 SDValue ReduceLoadOpStoreWidth(SDNode *N);
268 SDValue TransformFPLoadStorePair(SDNode *N);
270 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
272 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
273 /// looking for aliasing nodes and adding them to the Aliases vector.
274 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
275 SmallVector<SDValue, 8> &Aliases);
277 /// isAlias - Return true if there is any possibility that the two addresses
279 bool isAlias(SDValue Ptr1, int64_t Size1,
280 const Value *SrcValue1, int SrcValueOffset1,
281 unsigned SrcValueAlign1,
282 const MDNode *TBAAInfo1,
283 SDValue Ptr2, int64_t Size2,
284 const Value *SrcValue2, int SrcValueOffset2,
285 unsigned SrcValueAlign2,
286 const MDNode *TBAAInfo2) const;
288 /// FindAliasInfo - Extracts the relevant alias information from the memory
289 /// node. Returns true if the operand was a load.
290 bool FindAliasInfo(SDNode *N,
291 SDValue &Ptr, int64_t &Size,
292 const Value *&SrcValue, int &SrcValueOffset,
293 unsigned &SrcValueAlignment,
294 const MDNode *&TBAAInfo) const;
296 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
297 /// looking for a better chain (aliasing node.)
298 SDValue FindBetterChain(SDNode *N, SDValue Chain);
301 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
302 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
303 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
305 /// Run - runs the dag combiner on all nodes in the work list
306 void Run(CombineLevel AtLevel);
308 SelectionDAG &getDAG() const { return DAG; }
310 /// getShiftAmountTy - Returns a type large enough to hold any valid
311 /// shift amount - before type legalization these can be huge.
312 EVT getShiftAmountTy(EVT LHSTy) {
313 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
316 /// isTypeLegal - This method returns true if we are running before type
317 /// legalization or if the specified VT is legal.
318 bool isTypeLegal(const EVT &VT) {
319 if (!LegalTypes) return true;
320 return TLI.isTypeLegal(VT);
327 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
328 /// nodes from the worklist.
329 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
332 explicit WorkListRemover(DAGCombiner &dc)
333 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
335 virtual void NodeDeleted(SDNode *N, SDNode *E) {
336 DC.removeFromWorkList(N);
341 //===----------------------------------------------------------------------===//
342 // TargetLowering::DAGCombinerInfo implementation
343 //===----------------------------------------------------------------------===//
345 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
346 ((DAGCombiner*)DC)->AddToWorkList(N);
349 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
350 ((DAGCombiner*)DC)->removeFromWorkList(N);
353 SDValue TargetLowering::DAGCombinerInfo::
354 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
355 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
358 SDValue TargetLowering::DAGCombinerInfo::
359 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
360 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
364 SDValue TargetLowering::DAGCombinerInfo::
365 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
366 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
369 void TargetLowering::DAGCombinerInfo::
370 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
371 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
374 //===----------------------------------------------------------------------===//
376 //===----------------------------------------------------------------------===//
378 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
379 /// specified expression for the same cost as the expression itself, or 2 if we
380 /// can compute the negated form more cheaply than the expression itself.
381 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
382 const TargetLowering &TLI,
383 const TargetOptions *Options,
384 unsigned Depth = 0) {
385 // No compile time optimizations on this type.
386 if (Op.getValueType() == MVT::ppcf128)
389 // fneg is removable even if it has multiple uses.
390 if (Op.getOpcode() == ISD::FNEG) return 2;
392 // Don't allow anything with multiple uses.
393 if (!Op.hasOneUse()) return 0;
395 // Don't recurse exponentially.
396 if (Depth > 6) return 0;
398 switch (Op.getOpcode()) {
399 default: return false;
400 case ISD::ConstantFP:
401 // Don't invert constant FP values after legalize. The negated constant
402 // isn't necessarily legal.
403 return LegalOperations ? 0 : 1;
405 // FIXME: determine better conditions for this xform.
406 if (!Options->UnsafeFPMath) return 0;
408 // After operation legalization, it might not be legal to create new FSUBs.
409 if (LegalOperations &&
410 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
413 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
414 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
417 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
418 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
421 // We can't turn -(A-B) into B-A when we honor signed zeros.
422 if (!Options->UnsafeFPMath) return 0;
424 // fold (fneg (fsub A, B)) -> (fsub B, A)
429 if (Options->HonorSignDependentRoundingFPMath()) return 0;
431 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
432 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
436 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
442 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
447 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
448 /// returns the newly negated expression.
449 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
450 bool LegalOperations, unsigned Depth = 0) {
451 // fneg is removable even if it has multiple uses.
452 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
454 // Don't allow anything with multiple uses.
455 assert(Op.hasOneUse() && "Unknown reuse!");
457 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
458 switch (Op.getOpcode()) {
459 default: llvm_unreachable("Unknown code");
460 case ISD::ConstantFP: {
461 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
463 return DAG.getConstantFP(V, Op.getValueType());
466 // FIXME: determine better conditions for this xform.
467 assert(DAG.getTarget().Options.UnsafeFPMath);
469 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
470 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
471 DAG.getTargetLoweringInfo(),
472 &DAG.getTarget().Options, Depth+1))
473 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
474 GetNegatedExpression(Op.getOperand(0), DAG,
475 LegalOperations, Depth+1),
477 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
478 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
479 GetNegatedExpression(Op.getOperand(1), DAG,
480 LegalOperations, Depth+1),
483 // We can't turn -(A-B) into B-A when we honor signed zeros.
484 assert(DAG.getTarget().Options.UnsafeFPMath);
486 // fold (fneg (fsub 0, B)) -> B
487 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
488 if (N0CFP->getValueAPF().isZero())
489 return Op.getOperand(1);
491 // fold (fneg (fsub A, B)) -> (fsub B, A)
492 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
493 Op.getOperand(1), Op.getOperand(0));
497 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
499 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
500 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
501 DAG.getTargetLoweringInfo(),
502 &DAG.getTarget().Options, Depth+1))
503 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
504 GetNegatedExpression(Op.getOperand(0), DAG,
505 LegalOperations, Depth+1),
508 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
509 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
511 GetNegatedExpression(Op.getOperand(1), DAG,
512 LegalOperations, Depth+1));
516 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
517 GetNegatedExpression(Op.getOperand(0), DAG,
518 LegalOperations, Depth+1));
520 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
521 GetNegatedExpression(Op.getOperand(0), DAG,
522 LegalOperations, Depth+1),
528 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
529 // that selects between the values 1 and 0, making it equivalent to a setcc.
530 // Also, set the incoming LHS, RHS, and CC references to the appropriate
531 // nodes based on the type of node we are checking. This simplifies life a
532 // bit for the callers.
533 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
535 if (N.getOpcode() == ISD::SETCC) {
536 LHS = N.getOperand(0);
537 RHS = N.getOperand(1);
538 CC = N.getOperand(2);
541 if (N.getOpcode() == ISD::SELECT_CC &&
542 N.getOperand(2).getOpcode() == ISD::Constant &&
543 N.getOperand(3).getOpcode() == ISD::Constant &&
544 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
545 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
546 LHS = N.getOperand(0);
547 RHS = N.getOperand(1);
548 CC = N.getOperand(4);
554 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
555 // one use. If this is true, it allows the users to invert the operation for
556 // free when it is profitable to do so.
557 static bool isOneUseSetCC(SDValue N) {
559 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
564 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
565 SDValue N0, SDValue N1) {
566 EVT VT = N0.getValueType();
567 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
568 if (isa<ConstantSDNode>(N1)) {
569 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
571 DAG.FoldConstantArithmetic(Opc, VT,
572 cast<ConstantSDNode>(N0.getOperand(1)),
573 cast<ConstantSDNode>(N1));
574 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
576 if (N0.hasOneUse()) {
577 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
578 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
579 N0.getOperand(0), N1);
580 AddToWorkList(OpNode.getNode());
581 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
585 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
586 if (isa<ConstantSDNode>(N0)) {
587 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
589 DAG.FoldConstantArithmetic(Opc, VT,
590 cast<ConstantSDNode>(N1.getOperand(1)),
591 cast<ConstantSDNode>(N0));
592 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
594 if (N1.hasOneUse()) {
595 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
596 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
597 N1.getOperand(0), N0);
598 AddToWorkList(OpNode.getNode());
599 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
606 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
608 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
610 DEBUG(dbgs() << "\nReplacing.1 ";
612 dbgs() << "\nWith: ";
613 To[0].getNode()->dump(&DAG);
614 dbgs() << " and " << NumTo-1 << " other values\n";
615 for (unsigned i = 0, e = NumTo; i != e; ++i)
616 assert((!To[i].getNode() ||
617 N->getValueType(i) == To[i].getValueType()) &&
618 "Cannot combine value to value of different type!"));
619 WorkListRemover DeadNodes(*this);
620 DAG.ReplaceAllUsesWith(N, To);
622 // Push the new nodes and any users onto the worklist
623 for (unsigned i = 0, e = NumTo; i != e; ++i) {
624 if (To[i].getNode()) {
625 AddToWorkList(To[i].getNode());
626 AddUsersToWorkList(To[i].getNode());
631 // Finally, if the node is now dead, remove it from the graph. The node
632 // may not be dead if the replacement process recursively simplified to
633 // something else needing this node.
634 if (N->use_empty()) {
635 // Nodes can be reintroduced into the worklist. Make sure we do not
636 // process a node that has been replaced.
637 removeFromWorkList(N);
639 // Finally, since the node is now dead, remove it from the graph.
642 return SDValue(N, 0);
646 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
647 // Replace all uses. If any nodes become isomorphic to other nodes and
648 // are deleted, make sure to remove them from our worklist.
649 WorkListRemover DeadNodes(*this);
650 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
652 // Push the new node and any (possibly new) users onto the worklist.
653 AddToWorkList(TLO.New.getNode());
654 AddUsersToWorkList(TLO.New.getNode());
656 // Finally, if the node is now dead, remove it from the graph. The node
657 // may not be dead if the replacement process recursively simplified to
658 // something else needing this node.
659 if (TLO.Old.getNode()->use_empty()) {
660 removeFromWorkList(TLO.Old.getNode());
662 // If the operands of this node are only used by the node, they will now
663 // be dead. Make sure to visit them first to delete dead nodes early.
664 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
665 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
666 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
668 DAG.DeleteNode(TLO.Old.getNode());
672 /// SimplifyDemandedBits - Check the specified integer node value to see if
673 /// it can be simplified or if things it uses can be simplified by bit
674 /// propagation. If so, return true.
675 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
676 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
677 APInt KnownZero, KnownOne;
678 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
682 AddToWorkList(Op.getNode());
684 // Replace the old value with the new one.
686 DEBUG(dbgs() << "\nReplacing.2 ";
687 TLO.Old.getNode()->dump(&DAG);
688 dbgs() << "\nWith: ";
689 TLO.New.getNode()->dump(&DAG);
692 CommitTargetLoweringOpt(TLO);
696 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
697 DebugLoc dl = Load->getDebugLoc();
698 EVT VT = Load->getValueType(0);
699 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
701 DEBUG(dbgs() << "\nReplacing.9 ";
703 dbgs() << "\nWith: ";
704 Trunc.getNode()->dump(&DAG);
706 WorkListRemover DeadNodes(*this);
707 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
708 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
709 removeFromWorkList(Load);
710 DAG.DeleteNode(Load);
711 AddToWorkList(Trunc.getNode());
714 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
716 DebugLoc dl = Op.getDebugLoc();
717 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
718 EVT MemVT = LD->getMemoryVT();
719 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
720 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
722 : LD->getExtensionType();
724 return DAG.getExtLoad(ExtType, dl, PVT,
725 LD->getChain(), LD->getBasePtr(),
726 LD->getPointerInfo(),
727 MemVT, LD->isVolatile(),
728 LD->isNonTemporal(), LD->getAlignment());
731 unsigned Opc = Op.getOpcode();
734 case ISD::AssertSext:
735 return DAG.getNode(ISD::AssertSext, dl, PVT,
736 SExtPromoteOperand(Op.getOperand(0), PVT),
738 case ISD::AssertZext:
739 return DAG.getNode(ISD::AssertZext, dl, PVT,
740 ZExtPromoteOperand(Op.getOperand(0), PVT),
742 case ISD::Constant: {
744 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
745 return DAG.getNode(ExtOpc, dl, PVT, Op);
749 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
751 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
754 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
755 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
757 EVT OldVT = Op.getValueType();
758 DebugLoc dl = Op.getDebugLoc();
759 bool Replace = false;
760 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
761 if (NewOp.getNode() == 0)
763 AddToWorkList(NewOp.getNode());
766 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
767 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
768 DAG.getValueType(OldVT));
771 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
772 EVT OldVT = Op.getValueType();
773 DebugLoc dl = Op.getDebugLoc();
774 bool Replace = false;
775 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
776 if (NewOp.getNode() == 0)
778 AddToWorkList(NewOp.getNode());
781 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
782 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
785 /// PromoteIntBinOp - Promote the specified integer binary operation if the
786 /// target indicates it is beneficial. e.g. On x86, it's usually better to
787 /// promote i16 operations to i32 since i16 instructions are longer.
788 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
789 if (!LegalOperations)
792 EVT VT = Op.getValueType();
793 if (VT.isVector() || !VT.isInteger())
796 // If operation type is 'undesirable', e.g. i16 on x86, consider
798 unsigned Opc = Op.getOpcode();
799 if (TLI.isTypeDesirableForOp(Opc, VT))
803 // Consult target whether it is a good idea to promote this operation and
804 // what's the right type to promote it to.
805 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
806 assert(PVT != VT && "Don't know what type to promote to!");
808 bool Replace0 = false;
809 SDValue N0 = Op.getOperand(0);
810 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
811 if (NN0.getNode() == 0)
814 bool Replace1 = false;
815 SDValue N1 = Op.getOperand(1);
820 NN1 = PromoteOperand(N1, PVT, Replace1);
821 if (NN1.getNode() == 0)
825 AddToWorkList(NN0.getNode());
827 AddToWorkList(NN1.getNode());
830 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
832 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
834 DEBUG(dbgs() << "\nPromoting ";
835 Op.getNode()->dump(&DAG));
836 DebugLoc dl = Op.getDebugLoc();
837 return DAG.getNode(ISD::TRUNCATE, dl, VT,
838 DAG.getNode(Opc, dl, PVT, NN0, NN1));
843 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
844 /// target indicates it is beneficial. e.g. On x86, it's usually better to
845 /// promote i16 operations to i32 since i16 instructions are longer.
846 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
847 if (!LegalOperations)
850 EVT VT = Op.getValueType();
851 if (VT.isVector() || !VT.isInteger())
854 // If operation type is 'undesirable', e.g. i16 on x86, consider
856 unsigned Opc = Op.getOpcode();
857 if (TLI.isTypeDesirableForOp(Opc, VT))
861 // Consult target whether it is a good idea to promote this operation and
862 // what's the right type to promote it to.
863 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
864 assert(PVT != VT && "Don't know what type to promote to!");
866 bool Replace = false;
867 SDValue N0 = Op.getOperand(0);
869 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
870 else if (Opc == ISD::SRL)
871 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
873 N0 = PromoteOperand(N0, PVT, Replace);
874 if (N0.getNode() == 0)
877 AddToWorkList(N0.getNode());
879 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
881 DEBUG(dbgs() << "\nPromoting ";
882 Op.getNode()->dump(&DAG));
883 DebugLoc dl = Op.getDebugLoc();
884 return DAG.getNode(ISD::TRUNCATE, dl, VT,
885 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
890 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
891 if (!LegalOperations)
894 EVT VT = Op.getValueType();
895 if (VT.isVector() || !VT.isInteger())
898 // If operation type is 'undesirable', e.g. i16 on x86, consider
900 unsigned Opc = Op.getOpcode();
901 if (TLI.isTypeDesirableForOp(Opc, VT))
905 // Consult target whether it is a good idea to promote this operation and
906 // what's the right type to promote it to.
907 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
908 assert(PVT != VT && "Don't know what type to promote to!");
909 // fold (aext (aext x)) -> (aext x)
910 // fold (aext (zext x)) -> (zext x)
911 // fold (aext (sext x)) -> (sext x)
912 DEBUG(dbgs() << "\nPromoting ";
913 Op.getNode()->dump(&DAG));
914 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
919 bool DAGCombiner::PromoteLoad(SDValue Op) {
920 if (!LegalOperations)
923 EVT VT = Op.getValueType();
924 if (VT.isVector() || !VT.isInteger())
927 // If operation type is 'undesirable', e.g. i16 on x86, consider
929 unsigned Opc = Op.getOpcode();
930 if (TLI.isTypeDesirableForOp(Opc, VT))
934 // Consult target whether it is a good idea to promote this operation and
935 // what's the right type to promote it to.
936 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
937 assert(PVT != VT && "Don't know what type to promote to!");
939 DebugLoc dl = Op.getDebugLoc();
940 SDNode *N = Op.getNode();
941 LoadSDNode *LD = cast<LoadSDNode>(N);
942 EVT MemVT = LD->getMemoryVT();
943 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
944 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
946 : LD->getExtensionType();
947 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
948 LD->getChain(), LD->getBasePtr(),
949 LD->getPointerInfo(),
950 MemVT, LD->isVolatile(),
951 LD->isNonTemporal(), LD->getAlignment());
952 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
954 DEBUG(dbgs() << "\nPromoting ";
957 Result.getNode()->dump(&DAG);
959 WorkListRemover DeadNodes(*this);
960 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
961 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
962 removeFromWorkList(N);
964 AddToWorkList(Result.getNode());
971 //===----------------------------------------------------------------------===//
972 // Main DAG Combiner implementation
973 //===----------------------------------------------------------------------===//
975 void DAGCombiner::Run(CombineLevel AtLevel) {
976 // set the instance variables, so that the various visit routines may use it.
978 LegalOperations = Level >= AfterLegalizeVectorOps;
979 LegalTypes = Level >= AfterLegalizeTypes;
981 // Add all the dag nodes to the worklist.
982 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
983 E = DAG.allnodes_end(); I != E; ++I)
986 // Create a dummy node (which is not added to allnodes), that adds a reference
987 // to the root node, preventing it from being deleted, and tracking any
988 // changes of the root.
989 HandleSDNode Dummy(DAG.getRoot());
991 // The root of the dag may dangle to deleted nodes until the dag combiner is
992 // done. Set it to null to avoid confusion.
993 DAG.setRoot(SDValue());
995 // while the worklist isn't empty, find a node and
996 // try and combine it.
997 while (!WorkListContents.empty()) {
999 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
1000 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1001 // worklist *should* contain, and check the node we want to visit is should
1002 // actually be visited.
1004 N = WorkListOrder.pop_back_val();
1005 } while (!WorkListContents.erase(N));
1007 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1008 // N is deleted from the DAG, since they too may now be dead or may have a
1009 // reduced number of uses, allowing other xforms.
1010 if (N->use_empty() && N != &Dummy) {
1011 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1012 AddToWorkList(N->getOperand(i).getNode());
1018 SDValue RV = combine(N);
1020 if (RV.getNode() == 0)
1025 // If we get back the same node we passed in, rather than a new node or
1026 // zero, we know that the node must have defined multiple values and
1027 // CombineTo was used. Since CombineTo takes care of the worklist
1028 // mechanics for us, we have no work to do in this case.
1029 if (RV.getNode() == N)
1032 assert(N->getOpcode() != ISD::DELETED_NODE &&
1033 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1034 "Node was deleted but visit returned new node!");
1036 DEBUG(dbgs() << "\nReplacing.3 ";
1038 dbgs() << "\nWith: ";
1039 RV.getNode()->dump(&DAG);
1042 // Transfer debug value.
1043 DAG.TransferDbgValues(SDValue(N, 0), RV);
1044 WorkListRemover DeadNodes(*this);
1045 if (N->getNumValues() == RV.getNode()->getNumValues())
1046 DAG.ReplaceAllUsesWith(N, RV.getNode());
1048 assert(N->getValueType(0) == RV.getValueType() &&
1049 N->getNumValues() == 1 && "Type mismatch");
1051 DAG.ReplaceAllUsesWith(N, &OpV);
1054 // Push the new node and any users onto the worklist
1055 AddToWorkList(RV.getNode());
1056 AddUsersToWorkList(RV.getNode());
1058 // Add any uses of the old node to the worklist in case this node is the
1059 // last one that uses them. They may become dead after this node is
1061 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1062 AddToWorkList(N->getOperand(i).getNode());
1064 // Finally, if the node is now dead, remove it from the graph. The node
1065 // may not be dead if the replacement process recursively simplified to
1066 // something else needing this node.
1067 if (N->use_empty()) {
1068 // Nodes can be reintroduced into the worklist. Make sure we do not
1069 // process a node that has been replaced.
1070 removeFromWorkList(N);
1072 // Finally, since the node is now dead, remove it from the graph.
1077 // If the root changed (e.g. it was a dead load, update the root).
1078 DAG.setRoot(Dummy.getValue());
1079 DAG.RemoveDeadNodes();
1082 SDValue DAGCombiner::visit(SDNode *N) {
1083 switch (N->getOpcode()) {
1085 case ISD::TokenFactor: return visitTokenFactor(N);
1086 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1087 case ISD::ADD: return visitADD(N);
1088 case ISD::SUB: return visitSUB(N);
1089 case ISD::ADDC: return visitADDC(N);
1090 case ISD::SUBC: return visitSUBC(N);
1091 case ISD::ADDE: return visitADDE(N);
1092 case ISD::SUBE: return visitSUBE(N);
1093 case ISD::MUL: return visitMUL(N);
1094 case ISD::SDIV: return visitSDIV(N);
1095 case ISD::UDIV: return visitUDIV(N);
1096 case ISD::SREM: return visitSREM(N);
1097 case ISD::UREM: return visitUREM(N);
1098 case ISD::MULHU: return visitMULHU(N);
1099 case ISD::MULHS: return visitMULHS(N);
1100 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1101 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1102 case ISD::SMULO: return visitSMULO(N);
1103 case ISD::UMULO: return visitUMULO(N);
1104 case ISD::SDIVREM: return visitSDIVREM(N);
1105 case ISD::UDIVREM: return visitUDIVREM(N);
1106 case ISD::AND: return visitAND(N);
1107 case ISD::OR: return visitOR(N);
1108 case ISD::XOR: return visitXOR(N);
1109 case ISD::SHL: return visitSHL(N);
1110 case ISD::SRA: return visitSRA(N);
1111 case ISD::SRL: return visitSRL(N);
1112 case ISD::CTLZ: return visitCTLZ(N);
1113 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1114 case ISD::CTTZ: return visitCTTZ(N);
1115 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1116 case ISD::CTPOP: return visitCTPOP(N);
1117 case ISD::SELECT: return visitSELECT(N);
1118 case ISD::SELECT_CC: return visitSELECT_CC(N);
1119 case ISD::SETCC: return visitSETCC(N);
1120 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1121 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1122 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1123 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1124 case ISD::TRUNCATE: return visitTRUNCATE(N);
1125 case ISD::BITCAST: return visitBITCAST(N);
1126 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1127 case ISD::FADD: return visitFADD(N);
1128 case ISD::FSUB: return visitFSUB(N);
1129 case ISD::FMUL: return visitFMUL(N);
1130 case ISD::FMA: return visitFMA(N);
1131 case ISD::FDIV: return visitFDIV(N);
1132 case ISD::FREM: return visitFREM(N);
1133 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1134 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1135 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1136 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1137 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1138 case ISD::FP_ROUND: return visitFP_ROUND(N);
1139 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1140 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1141 case ISD::FNEG: return visitFNEG(N);
1142 case ISD::FABS: return visitFABS(N);
1143 case ISD::BRCOND: return visitBRCOND(N);
1144 case ISD::BR_CC: return visitBR_CC(N);
1145 case ISD::LOAD: return visitLOAD(N);
1146 case ISD::STORE: return visitSTORE(N);
1147 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1148 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1149 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1150 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1151 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1152 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1153 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1158 SDValue DAGCombiner::combine(SDNode *N) {
1159 SDValue RV = visit(N);
1161 // If nothing happened, try a target-specific DAG combine.
1162 if (RV.getNode() == 0) {
1163 assert(N->getOpcode() != ISD::DELETED_NODE &&
1164 "Node was deleted but visit returned NULL!");
1166 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1167 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1169 // Expose the DAG combiner to the target combiner impls.
1170 TargetLowering::DAGCombinerInfo
1171 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1173 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1177 // If nothing happened still, try promoting the operation.
1178 if (RV.getNode() == 0) {
1179 switch (N->getOpcode()) {
1187 RV = PromoteIntBinOp(SDValue(N, 0));
1192 RV = PromoteIntShiftOp(SDValue(N, 0));
1194 case ISD::SIGN_EXTEND:
1195 case ISD::ZERO_EXTEND:
1196 case ISD::ANY_EXTEND:
1197 RV = PromoteExtend(SDValue(N, 0));
1200 if (PromoteLoad(SDValue(N, 0)))
1206 // If N is a commutative binary node, try commuting it to enable more
1208 if (RV.getNode() == 0 &&
1209 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1210 N->getNumValues() == 1) {
1211 SDValue N0 = N->getOperand(0);
1212 SDValue N1 = N->getOperand(1);
1214 // Constant operands are canonicalized to RHS.
1215 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1216 SDValue Ops[] = { N1, N0 };
1217 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1220 return SDValue(CSENode, 0);
1227 /// getInputChainForNode - Given a node, return its input chain if it has one,
1228 /// otherwise return a null sd operand.
1229 static SDValue getInputChainForNode(SDNode *N) {
1230 if (unsigned NumOps = N->getNumOperands()) {
1231 if (N->getOperand(0).getValueType() == MVT::Other)
1232 return N->getOperand(0);
1233 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1234 return N->getOperand(NumOps-1);
1235 for (unsigned i = 1; i < NumOps-1; ++i)
1236 if (N->getOperand(i).getValueType() == MVT::Other)
1237 return N->getOperand(i);
1242 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1243 // If N has two operands, where one has an input chain equal to the other,
1244 // the 'other' chain is redundant.
1245 if (N->getNumOperands() == 2) {
1246 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1247 return N->getOperand(0);
1248 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1249 return N->getOperand(1);
1252 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1253 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1254 SmallPtrSet<SDNode*, 16> SeenOps;
1255 bool Changed = false; // If we should replace this token factor.
1257 // Start out with this token factor.
1260 // Iterate through token factors. The TFs grows when new token factors are
1262 for (unsigned i = 0; i < TFs.size(); ++i) {
1263 SDNode *TF = TFs[i];
1265 // Check each of the operands.
1266 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1267 SDValue Op = TF->getOperand(i);
1269 switch (Op.getOpcode()) {
1270 case ISD::EntryToken:
1271 // Entry tokens don't need to be added to the list. They are
1276 case ISD::TokenFactor:
1277 if (Op.hasOneUse() &&
1278 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1279 // Queue up for processing.
1280 TFs.push_back(Op.getNode());
1281 // Clean up in case the token factor is removed.
1282 AddToWorkList(Op.getNode());
1289 // Only add if it isn't already in the list.
1290 if (SeenOps.insert(Op.getNode()))
1301 // If we've change things around then replace token factor.
1304 // The entry token is the only possible outcome.
1305 Result = DAG.getEntryNode();
1307 // New and improved token factor.
1308 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1309 MVT::Other, &Ops[0], Ops.size());
1312 // Don't add users to work list.
1313 return CombineTo(N, Result, false);
1319 /// MERGE_VALUES can always be eliminated.
1320 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1321 WorkListRemover DeadNodes(*this);
1322 // Replacing results may cause a different MERGE_VALUES to suddenly
1323 // be CSE'd with N, and carry its uses with it. Iterate until no
1324 // uses remain, to ensure that the node can be safely deleted.
1326 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1327 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1328 } while (!N->use_empty());
1329 removeFromWorkList(N);
1331 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1335 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1336 SelectionDAG &DAG) {
1337 EVT VT = N0.getValueType();
1338 SDValue N00 = N0.getOperand(0);
1339 SDValue N01 = N0.getOperand(1);
1340 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1342 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1343 isa<ConstantSDNode>(N00.getOperand(1))) {
1344 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1345 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1346 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1347 N00.getOperand(0), N01),
1348 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1349 N00.getOperand(1), N01));
1350 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1356 SDValue DAGCombiner::visitADD(SDNode *N) {
1357 SDValue N0 = N->getOperand(0);
1358 SDValue N1 = N->getOperand(1);
1359 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1360 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1361 EVT VT = N0.getValueType();
1364 if (VT.isVector()) {
1365 SDValue FoldedVOp = SimplifyVBinOp(N);
1366 if (FoldedVOp.getNode()) return FoldedVOp;
1369 // fold (add x, undef) -> undef
1370 if (N0.getOpcode() == ISD::UNDEF)
1372 if (N1.getOpcode() == ISD::UNDEF)
1374 // fold (add c1, c2) -> c1+c2
1376 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1377 // canonicalize constant to RHS
1379 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1380 // fold (add x, 0) -> x
1381 if (N1C && N1C->isNullValue())
1383 // fold (add Sym, c) -> Sym+c
1384 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1385 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1386 GA->getOpcode() == ISD::GlobalAddress)
1387 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1389 (uint64_t)N1C->getSExtValue());
1390 // fold ((c1-A)+c2) -> (c1+c2)-A
1391 if (N1C && N0.getOpcode() == ISD::SUB)
1392 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1393 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1394 DAG.getConstant(N1C->getAPIntValue()+
1395 N0C->getAPIntValue(), VT),
1398 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1399 if (RADD.getNode() != 0)
1401 // fold ((0-A) + B) -> B-A
1402 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1403 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1404 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1405 // fold (A + (0-B)) -> A-B
1406 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1407 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1408 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1409 // fold (A+(B-A)) -> B
1410 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1411 return N1.getOperand(0);
1412 // fold ((B-A)+A) -> B
1413 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1414 return N0.getOperand(0);
1415 // fold (A+(B-(A+C))) to (B-C)
1416 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1417 N0 == N1.getOperand(1).getOperand(0))
1418 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1419 N1.getOperand(1).getOperand(1));
1420 // fold (A+(B-(C+A))) to (B-C)
1421 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1422 N0 == N1.getOperand(1).getOperand(1))
1423 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1424 N1.getOperand(1).getOperand(0));
1425 // fold (A+((B-A)+or-C)) to (B+or-C)
1426 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1427 N1.getOperand(0).getOpcode() == ISD::SUB &&
1428 N0 == N1.getOperand(0).getOperand(1))
1429 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1430 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1432 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1433 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1434 SDValue N00 = N0.getOperand(0);
1435 SDValue N01 = N0.getOperand(1);
1436 SDValue N10 = N1.getOperand(0);
1437 SDValue N11 = N1.getOperand(1);
1439 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1440 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1441 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1442 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1445 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1446 return SDValue(N, 0);
1448 // fold (a+b) -> (a|b) iff a and b share no bits.
1449 if (VT.isInteger() && !VT.isVector()) {
1450 APInt LHSZero, LHSOne;
1451 APInt RHSZero, RHSOne;
1452 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1454 if (LHSZero.getBoolValue()) {
1455 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1457 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1458 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1459 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1460 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1464 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1465 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1466 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1467 if (Result.getNode()) return Result;
1469 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1470 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1471 if (Result.getNode()) return Result;
1474 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1475 if (N1.getOpcode() == ISD::SHL &&
1476 N1.getOperand(0).getOpcode() == ISD::SUB)
1477 if (ConstantSDNode *C =
1478 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1479 if (C->getAPIntValue() == 0)
1480 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1481 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1482 N1.getOperand(0).getOperand(1),
1484 if (N0.getOpcode() == ISD::SHL &&
1485 N0.getOperand(0).getOpcode() == ISD::SUB)
1486 if (ConstantSDNode *C =
1487 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1488 if (C->getAPIntValue() == 0)
1489 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1490 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1491 N0.getOperand(0).getOperand(1),
1494 if (N1.getOpcode() == ISD::AND) {
1495 SDValue AndOp0 = N1.getOperand(0);
1496 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1497 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1498 unsigned DestBits = VT.getScalarType().getSizeInBits();
1500 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1501 // and similar xforms where the inner op is either ~0 or 0.
1502 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1503 DebugLoc DL = N->getDebugLoc();
1504 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1508 // add (sext i1), X -> sub X, (zext i1)
1509 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1510 N0.getOperand(0).getValueType() == MVT::i1 &&
1511 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1512 DebugLoc DL = N->getDebugLoc();
1513 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1514 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1520 SDValue DAGCombiner::visitADDC(SDNode *N) {
1521 SDValue N0 = N->getOperand(0);
1522 SDValue N1 = N->getOperand(1);
1523 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1524 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1525 EVT VT = N0.getValueType();
1527 // If the flag result is dead, turn this into an ADD.
1528 if (!N->hasAnyUseOfValue(1))
1529 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1530 DAG.getNode(ISD::CARRY_FALSE,
1531 N->getDebugLoc(), MVT::Glue));
1533 // canonicalize constant to RHS.
1535 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1537 // fold (addc x, 0) -> x + no carry out
1538 if (N1C && N1C->isNullValue())
1539 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1540 N->getDebugLoc(), MVT::Glue));
1542 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1543 APInt LHSZero, LHSOne;
1544 APInt RHSZero, RHSOne;
1545 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1547 if (LHSZero.getBoolValue()) {
1548 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1550 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1551 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1552 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1553 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1554 DAG.getNode(ISD::CARRY_FALSE,
1555 N->getDebugLoc(), MVT::Glue));
1561 SDValue DAGCombiner::visitADDE(SDNode *N) {
1562 SDValue N0 = N->getOperand(0);
1563 SDValue N1 = N->getOperand(1);
1564 SDValue CarryIn = N->getOperand(2);
1565 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1566 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1568 // canonicalize constant to RHS
1570 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1573 // fold (adde x, y, false) -> (addc x, y)
1574 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1575 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1580 // Since it may not be valid to emit a fold to zero for vector initializers
1581 // check if we can before folding.
1582 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1583 SelectionDAG &DAG, bool LegalOperations) {
1584 if (!VT.isVector()) {
1585 return DAG.getConstant(0, VT);
1587 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1588 // Produce a vector of zeros.
1589 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1590 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1591 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1592 &Ops[0], Ops.size());
1597 SDValue DAGCombiner::visitSUB(SDNode *N) {
1598 SDValue N0 = N->getOperand(0);
1599 SDValue N1 = N->getOperand(1);
1600 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1601 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1602 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1603 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1604 EVT VT = N0.getValueType();
1607 if (VT.isVector()) {
1608 SDValue FoldedVOp = SimplifyVBinOp(N);
1609 if (FoldedVOp.getNode()) return FoldedVOp;
1612 // fold (sub x, x) -> 0
1613 // FIXME: Refactor this and xor and other similar operations together.
1615 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1616 // fold (sub c1, c2) -> c1-c2
1618 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1619 // fold (sub x, c) -> (add x, -c)
1621 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1622 DAG.getConstant(-N1C->getAPIntValue(), VT));
1623 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1624 if (N0C && N0C->isAllOnesValue())
1625 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1626 // fold A-(A-B) -> B
1627 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1628 return N1.getOperand(1);
1629 // fold (A+B)-A -> B
1630 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1631 return N0.getOperand(1);
1632 // fold (A+B)-B -> A
1633 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1634 return N0.getOperand(0);
1635 // fold C2-(A+C1) -> (C2-C1)-A
1636 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1637 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
1638 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1641 // fold ((A+(B+or-C))-B) -> A+or-C
1642 if (N0.getOpcode() == ISD::ADD &&
1643 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1644 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1645 N0.getOperand(1).getOperand(0) == N1)
1646 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1647 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1648 // fold ((A+(C+B))-B) -> A+C
1649 if (N0.getOpcode() == ISD::ADD &&
1650 N0.getOperand(1).getOpcode() == ISD::ADD &&
1651 N0.getOperand(1).getOperand(1) == N1)
1652 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1653 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1654 // fold ((A-(B-C))-C) -> A-B
1655 if (N0.getOpcode() == ISD::SUB &&
1656 N0.getOperand(1).getOpcode() == ISD::SUB &&
1657 N0.getOperand(1).getOperand(1) == N1)
1658 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1659 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1661 // If either operand of a sub is undef, the result is undef
1662 if (N0.getOpcode() == ISD::UNDEF)
1664 if (N1.getOpcode() == ISD::UNDEF)
1667 // If the relocation model supports it, consider symbol offsets.
1668 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1669 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1670 // fold (sub Sym, c) -> Sym-c
1671 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1672 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1674 (uint64_t)N1C->getSExtValue());
1675 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1676 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1677 if (GA->getGlobal() == GB->getGlobal())
1678 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1685 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1686 SDValue N0 = N->getOperand(0);
1687 SDValue N1 = N->getOperand(1);
1688 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1689 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1690 EVT VT = N0.getValueType();
1692 // If the flag result is dead, turn this into an SUB.
1693 if (!N->hasAnyUseOfValue(1))
1694 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1695 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1698 // fold (subc x, x) -> 0 + no borrow
1700 return CombineTo(N, DAG.getConstant(0, VT),
1701 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1704 // fold (subc x, 0) -> x + no borrow
1705 if (N1C && N1C->isNullValue())
1706 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1709 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1710 if (N0C && N0C->isAllOnesValue())
1711 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1712 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1718 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1719 SDValue N0 = N->getOperand(0);
1720 SDValue N1 = N->getOperand(1);
1721 SDValue CarryIn = N->getOperand(2);
1723 // fold (sube x, y, false) -> (subc x, y)
1724 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1725 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1730 SDValue DAGCombiner::visitMUL(SDNode *N) {
1731 SDValue N0 = N->getOperand(0);
1732 SDValue N1 = N->getOperand(1);
1733 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1734 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1735 EVT VT = N0.getValueType();
1738 if (VT.isVector()) {
1739 SDValue FoldedVOp = SimplifyVBinOp(N);
1740 if (FoldedVOp.getNode()) return FoldedVOp;
1743 // fold (mul x, undef) -> 0
1744 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1745 return DAG.getConstant(0, VT);
1746 // fold (mul c1, c2) -> c1*c2
1748 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1749 // canonicalize constant to RHS
1751 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1752 // fold (mul x, 0) -> 0
1753 if (N1C && N1C->isNullValue())
1755 // fold (mul x, -1) -> 0-x
1756 if (N1C && N1C->isAllOnesValue())
1757 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1758 DAG.getConstant(0, VT), N0);
1759 // fold (mul x, (1 << c)) -> x << c
1760 if (N1C && N1C->getAPIntValue().isPowerOf2())
1761 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1762 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1763 getShiftAmountTy(N0.getValueType())));
1764 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1765 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1766 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1767 // FIXME: If the input is something that is easily negated (e.g. a
1768 // single-use add), we should put the negate there.
1769 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1770 DAG.getConstant(0, VT),
1771 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1772 DAG.getConstant(Log2Val,
1773 getShiftAmountTy(N0.getValueType()))));
1775 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1776 if (N1C && N0.getOpcode() == ISD::SHL &&
1777 isa<ConstantSDNode>(N0.getOperand(1))) {
1778 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1779 N1, N0.getOperand(1));
1780 AddToWorkList(C3.getNode());
1781 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1782 N0.getOperand(0), C3);
1785 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1788 SDValue Sh(0,0), Y(0,0);
1789 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1790 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1791 N0.getNode()->hasOneUse()) {
1793 } else if (N1.getOpcode() == ISD::SHL &&
1794 isa<ConstantSDNode>(N1.getOperand(1)) &&
1795 N1.getNode()->hasOneUse()) {
1800 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1801 Sh.getOperand(0), Y);
1802 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1803 Mul, Sh.getOperand(1));
1807 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1808 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1809 isa<ConstantSDNode>(N0.getOperand(1)))
1810 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1811 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1812 N0.getOperand(0), N1),
1813 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1814 N0.getOperand(1), N1));
1817 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1818 if (RMUL.getNode() != 0)
1824 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1825 SDValue N0 = N->getOperand(0);
1826 SDValue N1 = N->getOperand(1);
1827 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1828 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1829 EVT VT = N->getValueType(0);
1832 if (VT.isVector()) {
1833 SDValue FoldedVOp = SimplifyVBinOp(N);
1834 if (FoldedVOp.getNode()) return FoldedVOp;
1837 // fold (sdiv c1, c2) -> c1/c2
1838 if (N0C && N1C && !N1C->isNullValue())
1839 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1840 // fold (sdiv X, 1) -> X
1841 if (N1C && N1C->getAPIntValue() == 1LL)
1843 // fold (sdiv X, -1) -> 0-X
1844 if (N1C && N1C->isAllOnesValue())
1845 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1846 DAG.getConstant(0, VT), N0);
1847 // If we know the sign bits of both operands are zero, strength reduce to a
1848 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1849 if (!VT.isVector()) {
1850 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1851 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1854 // fold (sdiv X, pow2) -> simple ops after legalize
1855 if (N1C && !N1C->isNullValue() &&
1856 (N1C->getAPIntValue().isPowerOf2() ||
1857 (-N1C->getAPIntValue()).isPowerOf2())) {
1858 // If dividing by powers of two is cheap, then don't perform the following
1860 if (TLI.isPow2DivCheap())
1863 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1865 // Splat the sign bit into the register
1866 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1867 DAG.getConstant(VT.getSizeInBits()-1,
1868 getShiftAmountTy(N0.getValueType())));
1869 AddToWorkList(SGN.getNode());
1871 // Add (N0 < 0) ? abs2 - 1 : 0;
1872 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1873 DAG.getConstant(VT.getSizeInBits() - lg2,
1874 getShiftAmountTy(SGN.getValueType())));
1875 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1876 AddToWorkList(SRL.getNode());
1877 AddToWorkList(ADD.getNode()); // Divide by pow2
1878 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1879 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1881 // If we're dividing by a positive value, we're done. Otherwise, we must
1882 // negate the result.
1883 if (N1C->getAPIntValue().isNonNegative())
1886 AddToWorkList(SRA.getNode());
1887 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1888 DAG.getConstant(0, VT), SRA);
1891 // if integer divide is expensive and we satisfy the requirements, emit an
1892 // alternate sequence.
1893 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1894 SDValue Op = BuildSDIV(N);
1895 if (Op.getNode()) return Op;
1899 if (N0.getOpcode() == ISD::UNDEF)
1900 return DAG.getConstant(0, VT);
1901 // X / undef -> undef
1902 if (N1.getOpcode() == ISD::UNDEF)
1908 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1909 SDValue N0 = N->getOperand(0);
1910 SDValue N1 = N->getOperand(1);
1911 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1912 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1913 EVT VT = N->getValueType(0);
1916 if (VT.isVector()) {
1917 SDValue FoldedVOp = SimplifyVBinOp(N);
1918 if (FoldedVOp.getNode()) return FoldedVOp;
1921 // fold (udiv c1, c2) -> c1/c2
1922 if (N0C && N1C && !N1C->isNullValue())
1923 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1924 // fold (udiv x, (1 << c)) -> x >>u c
1925 if (N1C && N1C->getAPIntValue().isPowerOf2())
1926 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1927 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1928 getShiftAmountTy(N0.getValueType())));
1929 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1930 if (N1.getOpcode() == ISD::SHL) {
1931 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1932 if (SHC->getAPIntValue().isPowerOf2()) {
1933 EVT ADDVT = N1.getOperand(1).getValueType();
1934 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1936 DAG.getConstant(SHC->getAPIntValue()
1939 AddToWorkList(Add.getNode());
1940 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1944 // fold (udiv x, c) -> alternate
1945 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1946 SDValue Op = BuildUDIV(N);
1947 if (Op.getNode()) return Op;
1951 if (N0.getOpcode() == ISD::UNDEF)
1952 return DAG.getConstant(0, VT);
1953 // X / undef -> undef
1954 if (N1.getOpcode() == ISD::UNDEF)
1960 SDValue DAGCombiner::visitSREM(SDNode *N) {
1961 SDValue N0 = N->getOperand(0);
1962 SDValue N1 = N->getOperand(1);
1963 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1964 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1965 EVT VT = N->getValueType(0);
1967 // fold (srem c1, c2) -> c1%c2
1968 if (N0C && N1C && !N1C->isNullValue())
1969 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1970 // If we know the sign bits of both operands are zero, strength reduce to a
1971 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1972 if (!VT.isVector()) {
1973 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1974 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1977 // If X/C can be simplified by the division-by-constant logic, lower
1978 // X%C to the equivalent of X-X/C*C.
1979 if (N1C && !N1C->isNullValue()) {
1980 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1981 AddToWorkList(Div.getNode());
1982 SDValue OptimizedDiv = combine(Div.getNode());
1983 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1984 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1986 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1987 AddToWorkList(Mul.getNode());
1993 if (N0.getOpcode() == ISD::UNDEF)
1994 return DAG.getConstant(0, VT);
1995 // X % undef -> undef
1996 if (N1.getOpcode() == ISD::UNDEF)
2002 SDValue DAGCombiner::visitUREM(SDNode *N) {
2003 SDValue N0 = N->getOperand(0);
2004 SDValue N1 = N->getOperand(1);
2005 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2006 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2007 EVT VT = N->getValueType(0);
2009 // fold (urem c1, c2) -> c1%c2
2010 if (N0C && N1C && !N1C->isNullValue())
2011 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2012 // fold (urem x, pow2) -> (and x, pow2-1)
2013 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2014 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2015 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2016 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2017 if (N1.getOpcode() == ISD::SHL) {
2018 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2019 if (SHC->getAPIntValue().isPowerOf2()) {
2021 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2022 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2024 AddToWorkList(Add.getNode());
2025 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2030 // If X/C can be simplified by the division-by-constant logic, lower
2031 // X%C to the equivalent of X-X/C*C.
2032 if (N1C && !N1C->isNullValue()) {
2033 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2034 AddToWorkList(Div.getNode());
2035 SDValue OptimizedDiv = combine(Div.getNode());
2036 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2037 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2039 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2040 AddToWorkList(Mul.getNode());
2046 if (N0.getOpcode() == ISD::UNDEF)
2047 return DAG.getConstant(0, VT);
2048 // X % undef -> undef
2049 if (N1.getOpcode() == ISD::UNDEF)
2055 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2056 SDValue N0 = N->getOperand(0);
2057 SDValue N1 = N->getOperand(1);
2058 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2059 EVT VT = N->getValueType(0);
2060 DebugLoc DL = N->getDebugLoc();
2062 // fold (mulhs x, 0) -> 0
2063 if (N1C && N1C->isNullValue())
2065 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2066 if (N1C && N1C->getAPIntValue() == 1)
2067 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2068 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2069 getShiftAmountTy(N0.getValueType())));
2070 // fold (mulhs x, undef) -> 0
2071 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2072 return DAG.getConstant(0, VT);
2074 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2076 if (VT.isSimple() && !VT.isVector()) {
2077 MVT Simple = VT.getSimpleVT();
2078 unsigned SimpleSize = Simple.getSizeInBits();
2079 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2080 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2081 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2082 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2083 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2084 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2085 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2086 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2093 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2094 SDValue N0 = N->getOperand(0);
2095 SDValue N1 = N->getOperand(1);
2096 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2097 EVT VT = N->getValueType(0);
2098 DebugLoc DL = N->getDebugLoc();
2100 // fold (mulhu x, 0) -> 0
2101 if (N1C && N1C->isNullValue())
2103 // fold (mulhu x, 1) -> 0
2104 if (N1C && N1C->getAPIntValue() == 1)
2105 return DAG.getConstant(0, N0.getValueType());
2106 // fold (mulhu x, undef) -> 0
2107 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2108 return DAG.getConstant(0, VT);
2110 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2112 if (VT.isSimple() && !VT.isVector()) {
2113 MVT Simple = VT.getSimpleVT();
2114 unsigned SimpleSize = Simple.getSizeInBits();
2115 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2116 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2117 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2118 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2119 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2120 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2121 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2122 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2129 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2130 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2131 /// that are being performed. Return true if a simplification was made.
2133 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2135 // If the high half is not needed, just compute the low half.
2136 bool HiExists = N->hasAnyUseOfValue(1);
2138 (!LegalOperations ||
2139 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2140 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2141 N->op_begin(), N->getNumOperands());
2142 return CombineTo(N, Res, Res);
2145 // If the low half is not needed, just compute the high half.
2146 bool LoExists = N->hasAnyUseOfValue(0);
2148 (!LegalOperations ||
2149 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2150 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2151 N->op_begin(), N->getNumOperands());
2152 return CombineTo(N, Res, Res);
2155 // If both halves are used, return as it is.
2156 if (LoExists && HiExists)
2159 // If the two computed results can be simplified separately, separate them.
2161 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2162 N->op_begin(), N->getNumOperands());
2163 AddToWorkList(Lo.getNode());
2164 SDValue LoOpt = combine(Lo.getNode());
2165 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2166 (!LegalOperations ||
2167 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2168 return CombineTo(N, LoOpt, LoOpt);
2172 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2173 N->op_begin(), N->getNumOperands());
2174 AddToWorkList(Hi.getNode());
2175 SDValue HiOpt = combine(Hi.getNode());
2176 if (HiOpt.getNode() && HiOpt != Hi &&
2177 (!LegalOperations ||
2178 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2179 return CombineTo(N, HiOpt, HiOpt);
2185 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2186 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2187 if (Res.getNode()) return Res;
2189 EVT VT = N->getValueType(0);
2190 DebugLoc DL = N->getDebugLoc();
2192 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2194 if (VT.isSimple() && !VT.isVector()) {
2195 MVT Simple = VT.getSimpleVT();
2196 unsigned SimpleSize = Simple.getSizeInBits();
2197 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2198 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2199 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2200 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2201 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2202 // Compute the high part as N1.
2203 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2204 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2205 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2206 // Compute the low part as N0.
2207 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2208 return CombineTo(N, Lo, Hi);
2215 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2216 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2217 if (Res.getNode()) return Res;
2219 EVT VT = N->getValueType(0);
2220 DebugLoc DL = N->getDebugLoc();
2222 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2224 if (VT.isSimple() && !VT.isVector()) {
2225 MVT Simple = VT.getSimpleVT();
2226 unsigned SimpleSize = Simple.getSizeInBits();
2227 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2228 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2229 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2230 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2231 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2232 // Compute the high part as N1.
2233 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2234 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2235 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2236 // Compute the low part as N0.
2237 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2238 return CombineTo(N, Lo, Hi);
2245 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2246 // (smulo x, 2) -> (saddo x, x)
2247 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2248 if (C2->getAPIntValue() == 2)
2249 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2250 N->getOperand(0), N->getOperand(0));
2255 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2256 // (umulo x, 2) -> (uaddo x, x)
2257 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2258 if (C2->getAPIntValue() == 2)
2259 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2260 N->getOperand(0), N->getOperand(0));
2265 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2266 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2267 if (Res.getNode()) return Res;
2272 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2273 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2274 if (Res.getNode()) return Res;
2279 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2280 /// two operands of the same opcode, try to simplify it.
2281 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2282 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2283 EVT VT = N0.getValueType();
2284 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2286 // Bail early if none of these transforms apply.
2287 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2289 // For each of OP in AND/OR/XOR:
2290 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2291 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2292 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2293 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2295 // do not sink logical op inside of a vector extend, since it may combine
2297 EVT Op0VT = N0.getOperand(0).getValueType();
2298 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2299 N0.getOpcode() == ISD::SIGN_EXTEND ||
2300 // Avoid infinite looping with PromoteIntBinOp.
2301 (N0.getOpcode() == ISD::ANY_EXTEND &&
2302 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2303 (N0.getOpcode() == ISD::TRUNCATE &&
2304 (!TLI.isZExtFree(VT, Op0VT) ||
2305 !TLI.isTruncateFree(Op0VT, VT)) &&
2306 TLI.isTypeLegal(Op0VT))) &&
2308 Op0VT == N1.getOperand(0).getValueType() &&
2309 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2310 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2311 N0.getOperand(0).getValueType(),
2312 N0.getOperand(0), N1.getOperand(0));
2313 AddToWorkList(ORNode.getNode());
2314 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2317 // For each of OP in SHL/SRL/SRA/AND...
2318 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2319 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2320 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2321 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2322 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2323 N0.getOperand(1) == N1.getOperand(1)) {
2324 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2325 N0.getOperand(0).getValueType(),
2326 N0.getOperand(0), N1.getOperand(0));
2327 AddToWorkList(ORNode.getNode());
2328 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2329 ORNode, N0.getOperand(1));
2332 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2333 // Only perform this optimization after type legalization and before
2334 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2335 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2336 // we don't want to undo this promotion.
2337 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2339 if ((N0.getOpcode() == ISD::BITCAST || N0.getOpcode() == ISD::SCALAR_TO_VECTOR)
2340 && Level == AfterLegalizeVectorOps) {
2341 SDValue In0 = N0.getOperand(0);
2342 SDValue In1 = N1.getOperand(0);
2343 EVT In0Ty = In0.getValueType();
2344 EVT In1Ty = In1.getValueType();
2345 // If both incoming values are integers, and the original types are the same.
2346 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2347 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), In0Ty, In0, In1);
2348 SDValue BC = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, Op);
2349 AddToWorkList(Op.getNode());
2354 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2355 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2356 // If both shuffles use the same mask, and both shuffle within a single
2357 // vector, then it is worthwhile to move the swizzle after the operation.
2358 // The type-legalizer generates this pattern when loading illegal
2359 // vector types from memory. In many cases this allows additional shuffle
2361 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2362 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2363 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2364 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2365 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2367 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2368 "Inputs to shuffles are not the same type");
2370 unsigned NumElts = VT.getVectorNumElements();
2372 // Check that both shuffles use the same mask. The masks are known to be of
2373 // the same length because the result vector type is the same.
2374 bool SameMask = true;
2375 for (unsigned i = 0; i != NumElts; ++i) {
2376 int Idx0 = SVN0->getMaskElt(i);
2377 int Idx1 = SVN1->getMaskElt(i);
2385 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
2386 N0.getOperand(0), N1.getOperand(0));
2387 AddToWorkList(Op.getNode());
2388 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op,
2389 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2396 SDValue DAGCombiner::visitAND(SDNode *N) {
2397 SDValue N0 = N->getOperand(0);
2398 SDValue N1 = N->getOperand(1);
2399 SDValue LL, LR, RL, RR, CC0, CC1;
2400 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2401 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2402 EVT VT = N1.getValueType();
2403 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2406 if (VT.isVector()) {
2407 SDValue FoldedVOp = SimplifyVBinOp(N);
2408 if (FoldedVOp.getNode()) return FoldedVOp;
2411 // fold (and x, undef) -> 0
2412 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2413 return DAG.getConstant(0, VT);
2414 // fold (and c1, c2) -> c1&c2
2416 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2417 // canonicalize constant to RHS
2419 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2420 // fold (and x, -1) -> x
2421 if (N1C && N1C->isAllOnesValue())
2423 // if (and x, c) is known to be zero, return 0
2424 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2425 APInt::getAllOnesValue(BitWidth)))
2426 return DAG.getConstant(0, VT);
2428 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2429 if (RAND.getNode() != 0)
2431 // fold (and (or x, C), D) -> D if (C & D) == D
2432 if (N1C && N0.getOpcode() == ISD::OR)
2433 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2434 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2436 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2437 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2438 SDValue N0Op0 = N0.getOperand(0);
2439 APInt Mask = ~N1C->getAPIntValue();
2440 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2441 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2442 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2443 N0.getValueType(), N0Op0);
2445 // Replace uses of the AND with uses of the Zero extend node.
2448 // We actually want to replace all uses of the any_extend with the
2449 // zero_extend, to avoid duplicating things. This will later cause this
2450 // AND to be folded.
2451 CombineTo(N0.getNode(), Zext);
2452 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2455 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2456 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2457 // already be zero by virtue of the width of the base type of the load.
2459 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2461 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2462 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2463 N0.getOpcode() == ISD::LOAD) {
2464 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2465 N0 : N0.getOperand(0) );
2467 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2468 // This can be a pure constant or a vector splat, in which case we treat the
2469 // vector as a scalar and use the splat value.
2470 APInt Constant = APInt::getNullValue(1);
2471 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2472 Constant = C->getAPIntValue();
2473 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2474 APInt SplatValue, SplatUndef;
2475 unsigned SplatBitSize;
2477 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2478 SplatBitSize, HasAnyUndefs);
2480 // Undef bits can contribute to a possible optimisation if set, so
2482 SplatValue |= SplatUndef;
2484 // The splat value may be something like "0x00FFFFFF", which means 0 for
2485 // the first vector value and FF for the rest, repeating. We need a mask
2486 // that will apply equally to all members of the vector, so AND all the
2487 // lanes of the constant together.
2488 EVT VT = Vector->getValueType(0);
2489 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2490 Constant = APInt::getAllOnesValue(BitWidth);
2491 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i)
2492 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2496 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2497 // actually legal and isn't going to get expanded, else this is a false
2499 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2500 Load->getMemoryVT());
2502 // Resize the constant to the same size as the original memory access before
2503 // extension. If it is still the AllOnesValue then this AND is completely
2506 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2509 switch (Load->getExtensionType()) {
2510 default: B = false; break;
2511 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2513 case ISD::NON_EXTLOAD: B = true; break;
2516 if (B && Constant.isAllOnesValue()) {
2517 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2518 // preserve semantics once we get rid of the AND.
2519 SDValue NewLoad(Load, 0);
2520 if (Load->getExtensionType() == ISD::EXTLOAD) {
2521 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2522 Load->getValueType(0), Load->getDebugLoc(),
2523 Load->getChain(), Load->getBasePtr(),
2524 Load->getOffset(), Load->getMemoryVT(),
2525 Load->getMemOperand());
2526 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2527 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2530 // Fold the AND away, taking care not to fold to the old load node if we
2532 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2534 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2537 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2538 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2539 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2540 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2542 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2543 LL.getValueType().isInteger()) {
2544 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2545 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2546 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2547 LR.getValueType(), LL, RL);
2548 AddToWorkList(ORNode.getNode());
2549 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2551 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2552 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2553 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2554 LR.getValueType(), LL, RL);
2555 AddToWorkList(ANDNode.getNode());
2556 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2558 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2559 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2560 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2561 LR.getValueType(), LL, RL);
2562 AddToWorkList(ORNode.getNode());
2563 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2566 // canonicalize equivalent to ll == rl
2567 if (LL == RR && LR == RL) {
2568 Op1 = ISD::getSetCCSwappedOperands(Op1);
2571 if (LL == RL && LR == RR) {
2572 bool isInteger = LL.getValueType().isInteger();
2573 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2574 if (Result != ISD::SETCC_INVALID &&
2575 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2576 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2581 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2582 if (N0.getOpcode() == N1.getOpcode()) {
2583 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2584 if (Tmp.getNode()) return Tmp;
2587 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2588 // fold (and (sra)) -> (and (srl)) when possible.
2589 if (!VT.isVector() &&
2590 SimplifyDemandedBits(SDValue(N, 0)))
2591 return SDValue(N, 0);
2593 // fold (zext_inreg (extload x)) -> (zextload x)
2594 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2595 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2596 EVT MemVT = LN0->getMemoryVT();
2597 // If we zero all the possible extended bits, then we can turn this into
2598 // a zextload if we are running before legalize or the operation is legal.
2599 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2600 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2601 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2602 ((!LegalOperations && !LN0->isVolatile()) ||
2603 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2604 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2605 LN0->getChain(), LN0->getBasePtr(),
2606 LN0->getPointerInfo(), MemVT,
2607 LN0->isVolatile(), LN0->isNonTemporal(),
2608 LN0->getAlignment());
2610 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2611 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2614 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2615 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2617 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2618 EVT MemVT = LN0->getMemoryVT();
2619 // If we zero all the possible extended bits, then we can turn this into
2620 // a zextload if we are running before legalize or the operation is legal.
2621 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2622 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2623 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2624 ((!LegalOperations && !LN0->isVolatile()) ||
2625 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2626 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2628 LN0->getBasePtr(), LN0->getPointerInfo(),
2630 LN0->isVolatile(), LN0->isNonTemporal(),
2631 LN0->getAlignment());
2633 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2634 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2638 // fold (and (load x), 255) -> (zextload x, i8)
2639 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2640 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2641 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2642 (N0.getOpcode() == ISD::ANY_EXTEND &&
2643 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2644 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2645 LoadSDNode *LN0 = HasAnyExt
2646 ? cast<LoadSDNode>(N0.getOperand(0))
2647 : cast<LoadSDNode>(N0);
2648 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2649 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2650 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2651 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2652 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2653 EVT LoadedVT = LN0->getMemoryVT();
2655 if (ExtVT == LoadedVT &&
2656 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2657 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2660 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2661 LN0->getChain(), LN0->getBasePtr(),
2662 LN0->getPointerInfo(),
2663 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2664 LN0->getAlignment());
2666 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2667 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2670 // Do not change the width of a volatile load.
2671 // Do not generate loads of non-round integer types since these can
2672 // be expensive (and would be wrong if the type is not byte sized).
2673 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2674 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2675 EVT PtrType = LN0->getOperand(1).getValueType();
2677 unsigned Alignment = LN0->getAlignment();
2678 SDValue NewPtr = LN0->getBasePtr();
2680 // For big endian targets, we need to add an offset to the pointer
2681 // to load the correct bytes. For little endian systems, we merely
2682 // need to read fewer bytes from the same pointer.
2683 if (TLI.isBigEndian()) {
2684 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2685 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2686 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2687 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2688 NewPtr, DAG.getConstant(PtrOff, PtrType));
2689 Alignment = MinAlign(Alignment, PtrOff);
2692 AddToWorkList(NewPtr.getNode());
2694 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2696 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2697 LN0->getChain(), NewPtr,
2698 LN0->getPointerInfo(),
2699 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2702 CombineTo(LN0, Load, Load.getValue(1));
2703 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2712 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2714 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2715 bool DemandHighBits) {
2716 if (!LegalOperations)
2719 EVT VT = N->getValueType(0);
2720 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2722 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2725 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2726 bool LookPassAnd0 = false;
2727 bool LookPassAnd1 = false;
2728 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2730 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2732 if (N0.getOpcode() == ISD::AND) {
2733 if (!N0.getNode()->hasOneUse())
2735 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2736 if (!N01C || N01C->getZExtValue() != 0xFF00)
2738 N0 = N0.getOperand(0);
2739 LookPassAnd0 = true;
2742 if (N1.getOpcode() == ISD::AND) {
2743 if (!N1.getNode()->hasOneUse())
2745 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2746 if (!N11C || N11C->getZExtValue() != 0xFF)
2748 N1 = N1.getOperand(0);
2749 LookPassAnd1 = true;
2752 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2754 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2756 if (!N0.getNode()->hasOneUse() ||
2757 !N1.getNode()->hasOneUse())
2760 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2761 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2764 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2767 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2768 SDValue N00 = N0->getOperand(0);
2769 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2770 if (!N00.getNode()->hasOneUse())
2772 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2773 if (!N001C || N001C->getZExtValue() != 0xFF)
2775 N00 = N00.getOperand(0);
2776 LookPassAnd0 = true;
2779 SDValue N10 = N1->getOperand(0);
2780 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2781 if (!N10.getNode()->hasOneUse())
2783 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2784 if (!N101C || N101C->getZExtValue() != 0xFF00)
2786 N10 = N10.getOperand(0);
2787 LookPassAnd1 = true;
2793 // Make sure everything beyond the low halfword is zero since the SRL 16
2794 // will clear the top bits.
2795 unsigned OpSizeInBits = VT.getSizeInBits();
2796 if (DemandHighBits && OpSizeInBits > 16 &&
2797 (!LookPassAnd0 || !LookPassAnd1) &&
2798 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2801 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2802 if (OpSizeInBits > 16)
2803 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2804 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2808 /// isBSwapHWordElement - Return true if the specified node is an element
2809 /// that makes up a 32-bit packed halfword byteswap. i.e.
2810 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2811 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2812 if (!N.getNode()->hasOneUse())
2815 unsigned Opc = N.getOpcode();
2816 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2819 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2824 switch (N1C->getZExtValue()) {
2827 case 0xFF: Num = 0; break;
2828 case 0xFF00: Num = 1; break;
2829 case 0xFF0000: Num = 2; break;
2830 case 0xFF000000: Num = 3; break;
2833 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2834 SDValue N0 = N.getOperand(0);
2835 if (Opc == ISD::AND) {
2836 if (Num == 0 || Num == 2) {
2838 // (x >> 8) & 0xff0000
2839 if (N0.getOpcode() != ISD::SRL)
2841 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2842 if (!C || C->getZExtValue() != 8)
2845 // (x << 8) & 0xff00
2846 // (x << 8) & 0xff000000
2847 if (N0.getOpcode() != ISD::SHL)
2849 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2850 if (!C || C->getZExtValue() != 8)
2853 } else if (Opc == ISD::SHL) {
2855 // (x & 0xff0000) << 8
2856 if (Num != 0 && Num != 2)
2858 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2859 if (!C || C->getZExtValue() != 8)
2861 } else { // Opc == ISD::SRL
2862 // (x & 0xff00) >> 8
2863 // (x & 0xff000000) >> 8
2864 if (Num != 1 && Num != 3)
2866 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2867 if (!C || C->getZExtValue() != 8)
2874 Parts[Num] = N0.getOperand(0).getNode();
2878 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2879 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2880 /// => (rotl (bswap x), 16)
2881 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2882 if (!LegalOperations)
2885 EVT VT = N->getValueType(0);
2888 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2891 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2893 // (or (or (and), (and)), (or (and), (and)))
2894 // (or (or (or (and), (and)), (and)), (and))
2895 if (N0.getOpcode() != ISD::OR)
2897 SDValue N00 = N0.getOperand(0);
2898 SDValue N01 = N0.getOperand(1);
2900 if (N1.getOpcode() == ISD::OR) {
2901 // (or (or (and), (and)), (or (and), (and)))
2902 SDValue N000 = N00.getOperand(0);
2903 if (!isBSwapHWordElement(N000, Parts))
2906 SDValue N001 = N00.getOperand(1);
2907 if (!isBSwapHWordElement(N001, Parts))
2909 SDValue N010 = N01.getOperand(0);
2910 if (!isBSwapHWordElement(N010, Parts))
2912 SDValue N011 = N01.getOperand(1);
2913 if (!isBSwapHWordElement(N011, Parts))
2916 // (or (or (or (and), (and)), (and)), (and))
2917 if (!isBSwapHWordElement(N1, Parts))
2919 if (!isBSwapHWordElement(N01, Parts))
2921 if (N00.getOpcode() != ISD::OR)
2923 SDValue N000 = N00.getOperand(0);
2924 if (!isBSwapHWordElement(N000, Parts))
2926 SDValue N001 = N00.getOperand(1);
2927 if (!isBSwapHWordElement(N001, Parts))
2931 // Make sure the parts are all coming from the same node.
2932 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2935 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2936 SDValue(Parts[0],0));
2938 // Result of the bswap should be rotated by 16. If it's not legal, than
2939 // do (x << 16) | (x >> 16).
2940 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
2941 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2942 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2943 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2944 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
2945 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
2946 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
2947 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2950 SDValue DAGCombiner::visitOR(SDNode *N) {
2951 SDValue N0 = N->getOperand(0);
2952 SDValue N1 = N->getOperand(1);
2953 SDValue LL, LR, RL, RR, CC0, CC1;
2954 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2955 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2956 EVT VT = N1.getValueType();
2959 if (VT.isVector()) {
2960 SDValue FoldedVOp = SimplifyVBinOp(N);
2961 if (FoldedVOp.getNode()) return FoldedVOp;
2964 // fold (or x, undef) -> -1
2965 if (!LegalOperations &&
2966 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2967 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2968 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2970 // fold (or c1, c2) -> c1|c2
2972 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2973 // canonicalize constant to RHS
2975 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2976 // fold (or x, 0) -> x
2977 if (N1C && N1C->isNullValue())
2979 // fold (or x, -1) -> -1
2980 if (N1C && N1C->isAllOnesValue())
2982 // fold (or x, c) -> c iff (x & ~c) == 0
2983 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2986 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
2987 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
2988 if (BSwap.getNode() != 0)
2990 BSwap = MatchBSwapHWordLow(N, N0, N1);
2991 if (BSwap.getNode() != 0)
2995 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2996 if (ROR.getNode() != 0)
2998 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2999 // iff (c1 & c2) == 0.
3000 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3001 isa<ConstantSDNode>(N0.getOperand(1))) {
3002 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3003 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3004 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3005 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3006 N0.getOperand(0), N1),
3007 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3009 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3010 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3011 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3012 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3014 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3015 LL.getValueType().isInteger()) {
3016 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3017 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3018 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3019 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3020 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
3021 LR.getValueType(), LL, RL);
3022 AddToWorkList(ORNode.getNode());
3023 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
3025 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3026 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3027 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3028 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3029 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
3030 LR.getValueType(), LL, RL);
3031 AddToWorkList(ANDNode.getNode());
3032 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
3035 // canonicalize equivalent to ll == rl
3036 if (LL == RR && LR == RL) {
3037 Op1 = ISD::getSetCCSwappedOperands(Op1);
3040 if (LL == RL && LR == RR) {
3041 bool isInteger = LL.getValueType().isInteger();
3042 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3043 if (Result != ISD::SETCC_INVALID &&
3044 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
3045 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
3050 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3051 if (N0.getOpcode() == N1.getOpcode()) {
3052 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3053 if (Tmp.getNode()) return Tmp;
3056 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3057 if (N0.getOpcode() == ISD::AND &&
3058 N1.getOpcode() == ISD::AND &&
3059 N0.getOperand(1).getOpcode() == ISD::Constant &&
3060 N1.getOperand(1).getOpcode() == ISD::Constant &&
3061 // Don't increase # computations.
3062 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3063 // We can only do this xform if we know that bits from X that are set in C2
3064 // but not in C1 are already zero. Likewise for Y.
3065 const APInt &LHSMask =
3066 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3067 const APInt &RHSMask =
3068 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3070 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3071 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3072 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3073 N0.getOperand(0), N1.getOperand(0));
3074 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3075 DAG.getConstant(LHSMask | RHSMask, VT));
3079 // See if this is some rotate idiom.
3080 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3081 return SDValue(Rot, 0);
3083 // Simplify the operands using demanded-bits information.
3084 if (!VT.isVector() &&
3085 SimplifyDemandedBits(SDValue(N, 0)))
3086 return SDValue(N, 0);
3091 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3092 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3093 if (Op.getOpcode() == ISD::AND) {
3094 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3095 Mask = Op.getOperand(1);
3096 Op = Op.getOperand(0);
3102 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3110 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3111 // idioms for rotate, and if the target supports rotation instructions, generate
3113 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
3114 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3115 EVT VT = LHS.getValueType();
3116 if (!TLI.isTypeLegal(VT)) return 0;
3118 // The target must have at least one rotate flavor.
3119 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3120 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3121 if (!HasROTL && !HasROTR) return 0;
3123 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3124 SDValue LHSShift; // The shift.
3125 SDValue LHSMask; // AND value if any.
3126 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3127 return 0; // Not part of a rotate.
3129 SDValue RHSShift; // The shift.
3130 SDValue RHSMask; // AND value if any.
3131 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3132 return 0; // Not part of a rotate.
3134 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3135 return 0; // Not shifting the same value.
3137 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3138 return 0; // Shifts must disagree.
3140 // Canonicalize shl to left side in a shl/srl pair.
3141 if (RHSShift.getOpcode() == ISD::SHL) {
3142 std::swap(LHS, RHS);
3143 std::swap(LHSShift, RHSShift);
3144 std::swap(LHSMask , RHSMask );
3147 unsigned OpSizeInBits = VT.getSizeInBits();
3148 SDValue LHSShiftArg = LHSShift.getOperand(0);
3149 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3150 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3152 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3153 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3154 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3155 RHSShiftAmt.getOpcode() == ISD::Constant) {
3156 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3157 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3158 if ((LShVal + RShVal) != OpSizeInBits)
3163 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
3165 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
3167 // If there is an AND of either shifted operand, apply it to the result.
3168 if (LHSMask.getNode() || RHSMask.getNode()) {
3169 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3171 if (LHSMask.getNode()) {
3172 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3173 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3175 if (RHSMask.getNode()) {
3176 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3177 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3180 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3183 return Rot.getNode();
3186 // If there is a mask here, and we have a variable shift, we can't be sure
3187 // that we're masking out the right stuff.
3188 if (LHSMask.getNode() || RHSMask.getNode())
3191 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3192 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3193 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3194 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3195 if (ConstantSDNode *SUBC =
3196 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3197 if (SUBC->getAPIntValue() == OpSizeInBits) {
3199 return DAG.getNode(ISD::ROTL, DL, VT,
3200 LHSShiftArg, LHSShiftAmt).getNode();
3202 return DAG.getNode(ISD::ROTR, DL, VT,
3203 LHSShiftArg, RHSShiftAmt).getNode();
3208 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3209 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3210 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3211 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3212 if (ConstantSDNode *SUBC =
3213 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3214 if (SUBC->getAPIntValue() == OpSizeInBits) {
3216 return DAG.getNode(ISD::ROTR, DL, VT,
3217 LHSShiftArg, RHSShiftAmt).getNode();
3219 return DAG.getNode(ISD::ROTL, DL, VT,
3220 LHSShiftArg, LHSShiftAmt).getNode();
3225 // Look for sign/zext/any-extended or truncate cases:
3226 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3227 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3228 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3229 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3230 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3231 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3232 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3233 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3234 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3235 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3236 if (RExtOp0.getOpcode() == ISD::SUB &&
3237 RExtOp0.getOperand(1) == LExtOp0) {
3238 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3240 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3241 // (rotr x, (sub 32, y))
3242 if (ConstantSDNode *SUBC =
3243 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3244 if (SUBC->getAPIntValue() == OpSizeInBits) {
3245 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3247 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3250 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3251 RExtOp0 == LExtOp0.getOperand(1)) {
3252 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3254 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3255 // (rotl x, (sub 32, y))
3256 if (ConstantSDNode *SUBC =
3257 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3258 if (SUBC->getAPIntValue() == OpSizeInBits) {
3259 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3261 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3270 SDValue DAGCombiner::visitXOR(SDNode *N) {
3271 SDValue N0 = N->getOperand(0);
3272 SDValue N1 = N->getOperand(1);
3273 SDValue LHS, RHS, CC;
3274 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3275 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3276 EVT VT = N0.getValueType();
3279 if (VT.isVector()) {
3280 SDValue FoldedVOp = SimplifyVBinOp(N);
3281 if (FoldedVOp.getNode()) return FoldedVOp;
3284 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3285 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3286 return DAG.getConstant(0, VT);
3287 // fold (xor x, undef) -> undef
3288 if (N0.getOpcode() == ISD::UNDEF)
3290 if (N1.getOpcode() == ISD::UNDEF)
3292 // fold (xor c1, c2) -> c1^c2
3294 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3295 // canonicalize constant to RHS
3297 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3298 // fold (xor x, 0) -> x
3299 if (N1C && N1C->isNullValue())
3302 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3303 if (RXOR.getNode() != 0)
3306 // fold !(x cc y) -> (x !cc y)
3307 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3308 bool isInt = LHS.getValueType().isInteger();
3309 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3312 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3313 switch (N0.getOpcode()) {
3315 llvm_unreachable("Unhandled SetCC Equivalent!");
3317 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3318 case ISD::SELECT_CC:
3319 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3320 N0.getOperand(3), NotCC);
3325 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3326 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3327 N0.getNode()->hasOneUse() &&
3328 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3329 SDValue V = N0.getOperand(0);
3330 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3331 DAG.getConstant(1, V.getValueType()));
3332 AddToWorkList(V.getNode());
3333 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3336 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3337 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3338 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3339 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3340 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3341 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3342 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3343 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3344 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3345 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3348 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3349 if (N1C && N1C->isAllOnesValue() &&
3350 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3351 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3352 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3353 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3354 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3355 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3356 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3357 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3360 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3361 if (N1C && N0.getOpcode() == ISD::XOR) {
3362 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3363 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3365 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3366 DAG.getConstant(N1C->getAPIntValue() ^
3367 N00C->getAPIntValue(), VT));
3369 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3370 DAG.getConstant(N1C->getAPIntValue() ^
3371 N01C->getAPIntValue(), VT));
3373 // fold (xor x, x) -> 0
3375 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3377 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3378 if (N0.getOpcode() == N1.getOpcode()) {
3379 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3380 if (Tmp.getNode()) return Tmp;
3383 // Simplify the expression using non-local knowledge.
3384 if (!VT.isVector() &&
3385 SimplifyDemandedBits(SDValue(N, 0)))
3386 return SDValue(N, 0);
3391 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3392 /// the shift amount is a constant.
3393 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3394 SDNode *LHS = N->getOperand(0).getNode();
3395 if (!LHS->hasOneUse()) return SDValue();
3397 // We want to pull some binops through shifts, so that we have (and (shift))
3398 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3399 // thing happens with address calculations, so it's important to canonicalize
3401 bool HighBitSet = false; // Can we transform this if the high bit is set?
3403 switch (LHS->getOpcode()) {
3404 default: return SDValue();
3407 HighBitSet = false; // We can only transform sra if the high bit is clear.
3410 HighBitSet = true; // We can only transform sra if the high bit is set.
3413 if (N->getOpcode() != ISD::SHL)
3414 return SDValue(); // only shl(add) not sr[al](add).
3415 HighBitSet = false; // We can only transform sra if the high bit is clear.
3419 // We require the RHS of the binop to be a constant as well.
3420 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3421 if (!BinOpCst) return SDValue();
3423 // FIXME: disable this unless the input to the binop is a shift by a constant.
3424 // If it is not a shift, it pessimizes some common cases like:
3426 // void foo(int *X, int i) { X[i & 1235] = 1; }
3427 // int bar(int *X, int i) { return X[i & 255]; }
3428 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3429 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3430 BinOpLHSVal->getOpcode() != ISD::SRA &&
3431 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3432 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3435 EVT VT = N->getValueType(0);
3437 // If this is a signed shift right, and the high bit is modified by the
3438 // logical operation, do not perform the transformation. The highBitSet
3439 // boolean indicates the value of the high bit of the constant which would
3440 // cause it to be modified for this operation.
3441 if (N->getOpcode() == ISD::SRA) {
3442 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3443 if (BinOpRHSSignSet != HighBitSet)
3447 // Fold the constants, shifting the binop RHS by the shift amount.
3448 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3450 LHS->getOperand(1), N->getOperand(1));
3452 // Create the new shift.
3453 SDValue NewShift = DAG.getNode(N->getOpcode(),
3454 LHS->getOperand(0).getDebugLoc(),
3455 VT, LHS->getOperand(0), N->getOperand(1));
3457 // Create the new binop.
3458 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3461 SDValue DAGCombiner::visitSHL(SDNode *N) {
3462 SDValue N0 = N->getOperand(0);
3463 SDValue N1 = N->getOperand(1);
3464 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3465 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3466 EVT VT = N0.getValueType();
3467 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3469 // fold (shl c1, c2) -> c1<<c2
3471 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3472 // fold (shl 0, x) -> 0
3473 if (N0C && N0C->isNullValue())
3475 // fold (shl x, c >= size(x)) -> undef
3476 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3477 return DAG.getUNDEF(VT);
3478 // fold (shl x, 0) -> x
3479 if (N1C && N1C->isNullValue())
3481 // fold (shl undef, x) -> 0
3482 if (N0.getOpcode() == ISD::UNDEF)
3483 return DAG.getConstant(0, VT);
3484 // if (shl x, c) is known to be zero, return 0
3485 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3486 APInt::getAllOnesValue(OpSizeInBits)))
3487 return DAG.getConstant(0, VT);
3488 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3489 if (N1.getOpcode() == ISD::TRUNCATE &&
3490 N1.getOperand(0).getOpcode() == ISD::AND &&
3491 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3492 SDValue N101 = N1.getOperand(0).getOperand(1);
3493 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3494 EVT TruncVT = N1.getValueType();
3495 SDValue N100 = N1.getOperand(0).getOperand(0);
3496 APInt TruncC = N101C->getAPIntValue();
3497 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3498 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3499 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3500 DAG.getNode(ISD::TRUNCATE,
3503 DAG.getConstant(TruncC, TruncVT)));
3507 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3508 return SDValue(N, 0);
3510 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3511 if (N1C && N0.getOpcode() == ISD::SHL &&
3512 N0.getOperand(1).getOpcode() == ISD::Constant) {
3513 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3514 uint64_t c2 = N1C->getZExtValue();
3515 if (c1 + c2 >= OpSizeInBits)
3516 return DAG.getConstant(0, VT);
3517 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3518 DAG.getConstant(c1 + c2, N1.getValueType()));
3521 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3522 // For this to be valid, the second form must not preserve any of the bits
3523 // that are shifted out by the inner shift in the first form. This means
3524 // the outer shift size must be >= the number of bits added by the ext.
3525 // As a corollary, we don't care what kind of ext it is.
3526 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3527 N0.getOpcode() == ISD::ANY_EXTEND ||
3528 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3529 N0.getOperand(0).getOpcode() == ISD::SHL &&
3530 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3532 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3533 uint64_t c2 = N1C->getZExtValue();
3534 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3535 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3536 if (c2 >= OpSizeInBits - InnerShiftSize) {
3537 if (c1 + c2 >= OpSizeInBits)
3538 return DAG.getConstant(0, VT);
3539 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3540 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3541 N0.getOperand(0)->getOperand(0)),
3542 DAG.getConstant(c1 + c2, N1.getValueType()));
3546 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3547 // (and (srl x, (sub c1, c2), MASK)
3548 // Only fold this if the inner shift has no other uses -- if it does, folding
3549 // this will increase the total number of instructions.
3550 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3551 N0.getOperand(1).getOpcode() == ISD::Constant) {
3552 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3553 if (c1 < VT.getSizeInBits()) {
3554 uint64_t c2 = N1C->getZExtValue();
3555 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3556 VT.getSizeInBits() - c1);
3559 Mask = Mask.shl(c2-c1);
3560 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3561 DAG.getConstant(c2-c1, N1.getValueType()));
3563 Mask = Mask.lshr(c1-c2);
3564 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3565 DAG.getConstant(c1-c2, N1.getValueType()));
3567 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3568 DAG.getConstant(Mask, VT));
3571 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3572 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3573 SDValue HiBitsMask =
3574 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3575 VT.getSizeInBits() -
3576 N1C->getZExtValue()),
3578 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3583 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3584 if (NewSHL.getNode())
3591 SDValue DAGCombiner::visitSRA(SDNode *N) {
3592 SDValue N0 = N->getOperand(0);
3593 SDValue N1 = N->getOperand(1);
3594 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3595 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3596 EVT VT = N0.getValueType();
3597 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3599 // fold (sra c1, c2) -> (sra c1, c2)
3601 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3602 // fold (sra 0, x) -> 0
3603 if (N0C && N0C->isNullValue())
3605 // fold (sra -1, x) -> -1
3606 if (N0C && N0C->isAllOnesValue())
3608 // fold (sra x, (setge c, size(x))) -> undef
3609 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3610 return DAG.getUNDEF(VT);
3611 // fold (sra x, 0) -> x
3612 if (N1C && N1C->isNullValue())
3614 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3616 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3617 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3618 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3620 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3621 ExtVT, VT.getVectorNumElements());
3622 if ((!LegalOperations ||
3623 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3624 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3625 N0.getOperand(0), DAG.getValueType(ExtVT));
3628 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3629 if (N1C && N0.getOpcode() == ISD::SRA) {
3630 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3631 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3632 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3633 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3634 DAG.getConstant(Sum, N1C->getValueType(0)));
3638 // fold (sra (shl X, m), (sub result_size, n))
3639 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3640 // result_size - n != m.
3641 // If truncate is free for the target sext(shl) is likely to result in better
3643 if (N0.getOpcode() == ISD::SHL) {
3644 // Get the two constanst of the shifts, CN0 = m, CN = n.
3645 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3647 // Determine what the truncate's result bitsize and type would be.
3649 EVT::getIntegerVT(*DAG.getContext(),
3650 OpSizeInBits - N1C->getZExtValue());
3651 // Determine the residual right-shift amount.
3652 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3654 // If the shift is not a no-op (in which case this should be just a sign
3655 // extend already), the truncated to type is legal, sign_extend is legal
3656 // on that type, and the truncate to that type is both legal and free,
3657 // perform the transform.
3658 if ((ShiftAmt > 0) &&
3659 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3660 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3661 TLI.isTruncateFree(VT, TruncVT)) {
3663 SDValue Amt = DAG.getConstant(ShiftAmt,
3664 getShiftAmountTy(N0.getOperand(0).getValueType()));
3665 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3666 N0.getOperand(0), Amt);
3667 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3669 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3670 N->getValueType(0), Trunc);
3675 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3676 if (N1.getOpcode() == ISD::TRUNCATE &&
3677 N1.getOperand(0).getOpcode() == ISD::AND &&
3678 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3679 SDValue N101 = N1.getOperand(0).getOperand(1);
3680 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3681 EVT TruncVT = N1.getValueType();
3682 SDValue N100 = N1.getOperand(0).getOperand(0);
3683 APInt TruncC = N101C->getAPIntValue();
3684 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3685 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3686 DAG.getNode(ISD::AND, N->getDebugLoc(),
3688 DAG.getNode(ISD::TRUNCATE,
3691 DAG.getConstant(TruncC, TruncVT)));
3695 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3696 // if c1 is equal to the number of bits the trunc removes
3697 if (N0.getOpcode() == ISD::TRUNCATE &&
3698 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3699 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3700 N0.getOperand(0).hasOneUse() &&
3701 N0.getOperand(0).getOperand(1).hasOneUse() &&
3702 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3703 EVT LargeVT = N0.getOperand(0).getValueType();
3704 ConstantSDNode *LargeShiftAmt =
3705 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3707 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3708 LargeShiftAmt->getZExtValue()) {
3710 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3711 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3712 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3713 N0.getOperand(0).getOperand(0), Amt);
3714 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3718 // Simplify, based on bits shifted out of the LHS.
3719 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3720 return SDValue(N, 0);
3723 // If the sign bit is known to be zero, switch this to a SRL.
3724 if (DAG.SignBitIsZero(N0))
3725 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3728 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3729 if (NewSRA.getNode())
3736 SDValue DAGCombiner::visitSRL(SDNode *N) {
3737 SDValue N0 = N->getOperand(0);
3738 SDValue N1 = N->getOperand(1);
3739 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3740 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3741 EVT VT = N0.getValueType();
3742 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3744 // fold (srl c1, c2) -> c1 >>u c2
3746 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3747 // fold (srl 0, x) -> 0
3748 if (N0C && N0C->isNullValue())
3750 // fold (srl x, c >= size(x)) -> undef
3751 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3752 return DAG.getUNDEF(VT);
3753 // fold (srl x, 0) -> x
3754 if (N1C && N1C->isNullValue())
3756 // if (srl x, c) is known to be zero, return 0
3757 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3758 APInt::getAllOnesValue(OpSizeInBits)))
3759 return DAG.getConstant(0, VT);
3761 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3762 if (N1C && N0.getOpcode() == ISD::SRL &&
3763 N0.getOperand(1).getOpcode() == ISD::Constant) {
3764 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3765 uint64_t c2 = N1C->getZExtValue();
3766 if (c1 + c2 >= OpSizeInBits)
3767 return DAG.getConstant(0, VT);
3768 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3769 DAG.getConstant(c1 + c2, N1.getValueType()));
3772 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3773 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3774 N0.getOperand(0).getOpcode() == ISD::SRL &&
3775 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3777 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3778 uint64_t c2 = N1C->getZExtValue();
3779 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3780 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3781 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3782 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3783 if (c1 + OpSizeInBits == InnerShiftSize) {
3784 if (c1 + c2 >= InnerShiftSize)
3785 return DAG.getConstant(0, VT);
3786 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3787 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3788 N0.getOperand(0)->getOperand(0),
3789 DAG.getConstant(c1 + c2, ShiftCountVT)));
3793 // fold (srl (shl x, c), c) -> (and x, cst2)
3794 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3795 N0.getValueSizeInBits() <= 64) {
3796 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3797 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3798 DAG.getConstant(~0ULL >> ShAmt, VT));
3802 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3803 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3804 // Shifting in all undef bits?
3805 EVT SmallVT = N0.getOperand(0).getValueType();
3806 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3807 return DAG.getUNDEF(VT);
3809 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3810 uint64_t ShiftAmt = N1C->getZExtValue();
3811 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3813 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3814 AddToWorkList(SmallShift.getNode());
3815 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3819 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3820 // bit, which is unmodified by sra.
3821 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3822 if (N0.getOpcode() == ISD::SRA)
3823 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3826 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3827 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3828 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3829 APInt KnownZero, KnownOne;
3830 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
3832 // If any of the input bits are KnownOne, then the input couldn't be all
3833 // zeros, thus the result of the srl will always be zero.
3834 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3836 // If all of the bits input the to ctlz node are known to be zero, then
3837 // the result of the ctlz is "32" and the result of the shift is one.
3838 APInt UnknownBits = ~KnownZero;
3839 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3841 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3842 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3843 // Okay, we know that only that the single bit specified by UnknownBits
3844 // could be set on input to the CTLZ node. If this bit is set, the SRL
3845 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3846 // to an SRL/XOR pair, which is likely to simplify more.
3847 unsigned ShAmt = UnknownBits.countTrailingZeros();
3848 SDValue Op = N0.getOperand(0);
3851 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3852 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3853 AddToWorkList(Op.getNode());
3856 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3857 Op, DAG.getConstant(1, VT));
3861 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3862 if (N1.getOpcode() == ISD::TRUNCATE &&
3863 N1.getOperand(0).getOpcode() == ISD::AND &&
3864 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3865 SDValue N101 = N1.getOperand(0).getOperand(1);
3866 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3867 EVT TruncVT = N1.getValueType();
3868 SDValue N100 = N1.getOperand(0).getOperand(0);
3869 APInt TruncC = N101C->getAPIntValue();
3870 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3871 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3872 DAG.getNode(ISD::AND, N->getDebugLoc(),
3874 DAG.getNode(ISD::TRUNCATE,
3877 DAG.getConstant(TruncC, TruncVT)));
3881 // fold operands of srl based on knowledge that the low bits are not
3883 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3884 return SDValue(N, 0);
3887 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3888 if (NewSRL.getNode())
3892 // Attempt to convert a srl of a load into a narrower zero-extending load.
3893 SDValue NarrowLoad = ReduceLoadWidth(N);
3894 if (NarrowLoad.getNode())
3897 // Here is a common situation. We want to optimize:
3900 // %b = and i32 %a, 2
3901 // %c = srl i32 %b, 1
3902 // brcond i32 %c ...
3908 // %c = setcc eq %b, 0
3911 // However when after the source operand of SRL is optimized into AND, the SRL
3912 // itself may not be optimized further. Look for it and add the BRCOND into
3914 if (N->hasOneUse()) {
3915 SDNode *Use = *N->use_begin();
3916 if (Use->getOpcode() == ISD::BRCOND)
3918 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3919 // Also look pass the truncate.
3920 Use = *Use->use_begin();
3921 if (Use->getOpcode() == ISD::BRCOND)
3929 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3930 SDValue N0 = N->getOperand(0);
3931 EVT VT = N->getValueType(0);
3933 // fold (ctlz c1) -> c2
3934 if (isa<ConstantSDNode>(N0))
3935 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3939 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
3940 SDValue N0 = N->getOperand(0);
3941 EVT VT = N->getValueType(0);
3943 // fold (ctlz_zero_undef c1) -> c2
3944 if (isa<ConstantSDNode>(N0))
3945 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3949 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3950 SDValue N0 = N->getOperand(0);
3951 EVT VT = N->getValueType(0);
3953 // fold (cttz c1) -> c2
3954 if (isa<ConstantSDNode>(N0))
3955 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3959 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
3960 SDValue N0 = N->getOperand(0);
3961 EVT VT = N->getValueType(0);
3963 // fold (cttz_zero_undef c1) -> c2
3964 if (isa<ConstantSDNode>(N0))
3965 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3969 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3970 SDValue N0 = N->getOperand(0);
3971 EVT VT = N->getValueType(0);
3973 // fold (ctpop c1) -> c2
3974 if (isa<ConstantSDNode>(N0))
3975 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3979 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3980 SDValue N0 = N->getOperand(0);
3981 SDValue N1 = N->getOperand(1);
3982 SDValue N2 = N->getOperand(2);
3983 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3984 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3985 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3986 EVT VT = N->getValueType(0);
3987 EVT VT0 = N0.getValueType();
3989 // fold (select C, X, X) -> X
3992 // fold (select true, X, Y) -> X
3993 if (N0C && !N0C->isNullValue())
3995 // fold (select false, X, Y) -> Y
3996 if (N0C && N0C->isNullValue())
3998 // fold (select C, 1, X) -> (or C, X)
3999 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4000 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4001 // fold (select C, 0, 1) -> (xor C, 1)
4002 if (VT.isInteger() &&
4005 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
4006 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4009 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
4010 N0, DAG.getConstant(1, VT0));
4011 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
4012 N0, DAG.getConstant(1, VT0));
4013 AddToWorkList(XORNode.getNode());
4015 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
4016 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
4018 // fold (select C, 0, X) -> (and (not C), X)
4019 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4020 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4021 AddToWorkList(NOTNode.getNode());
4022 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
4024 // fold (select C, X, 1) -> (or (not C), X)
4025 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4026 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4027 AddToWorkList(NOTNode.getNode());
4028 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
4030 // fold (select C, X, 0) -> (and C, X)
4031 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4032 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4033 // fold (select X, X, Y) -> (or X, Y)
4034 // fold (select X, 1, Y) -> (or X, Y)
4035 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4036 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4037 // fold (select X, Y, X) -> (and X, Y)
4038 // fold (select X, Y, 0) -> (and X, Y)
4039 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4040 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4042 // If we can fold this based on the true/false value, do so.
4043 if (SimplifySelectOps(N, N1, N2))
4044 return SDValue(N, 0); // Don't revisit N.
4046 // fold selects based on a setcc into other things, such as min/max/abs
4047 if (N0.getOpcode() == ISD::SETCC) {
4049 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4050 // having to say they don't support SELECT_CC on every type the DAG knows
4051 // about, since there is no way to mark an opcode illegal at all value types
4052 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4053 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4054 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
4055 N0.getOperand(0), N0.getOperand(1),
4056 N1, N2, N0.getOperand(2));
4057 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
4063 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4064 SDValue N0 = N->getOperand(0);
4065 SDValue N1 = N->getOperand(1);
4066 SDValue N2 = N->getOperand(2);
4067 SDValue N3 = N->getOperand(3);
4068 SDValue N4 = N->getOperand(4);
4069 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4071 // fold select_cc lhs, rhs, x, x, cc -> x
4075 // Determine if the condition we're dealing with is constant
4076 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
4077 N0, N1, CC, N->getDebugLoc(), false);
4078 if (SCC.getNode()) AddToWorkList(SCC.getNode());
4080 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
4081 if (!SCCC->isNullValue())
4082 return N2; // cond always true -> true val
4084 return N3; // cond always false -> false val
4087 // Fold to a simpler select_cc
4088 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4089 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4090 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4093 // If we can fold this based on the true/false value, do so.
4094 if (SimplifySelectOps(N, N2, N3))
4095 return SDValue(N, 0); // Don't revisit N.
4097 // fold select_cc into other things, such as min/max/abs
4098 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
4101 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4102 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4103 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4107 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4108 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4109 // transformation. Returns true if extension are possible and the above
4110 // mentioned transformation is profitable.
4111 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4113 SmallVector<SDNode*, 4> &ExtendNodes,
4114 const TargetLowering &TLI) {
4115 bool HasCopyToRegUses = false;
4116 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4117 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4118 UE = N0.getNode()->use_end();
4123 if (UI.getUse().getResNo() != N0.getResNo())
4125 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4126 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4127 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4128 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4129 // Sign bits will be lost after a zext.
4132 for (unsigned i = 0; i != 2; ++i) {
4133 SDValue UseOp = User->getOperand(i);
4136 if (!isa<ConstantSDNode>(UseOp))
4141 ExtendNodes.push_back(User);
4144 // If truncates aren't free and there are users we can't
4145 // extend, it isn't worthwhile.
4148 // Remember if this value is live-out.
4149 if (User->getOpcode() == ISD::CopyToReg)
4150 HasCopyToRegUses = true;
4153 if (HasCopyToRegUses) {
4154 bool BothLiveOut = false;
4155 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4157 SDUse &Use = UI.getUse();
4158 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4164 // Both unextended and extended values are live out. There had better be
4165 // a good reason for the transformation.
4166 return ExtendNodes.size();
4171 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4172 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4173 ISD::NodeType ExtType) {
4174 // Extend SetCC uses if necessary.
4175 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4176 SDNode *SetCC = SetCCs[i];
4177 SmallVector<SDValue, 4> Ops;
4179 for (unsigned j = 0; j != 2; ++j) {
4180 SDValue SOp = SetCC->getOperand(j);
4182 Ops.push_back(ExtLoad);
4184 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4187 Ops.push_back(SetCC->getOperand(2));
4188 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4189 &Ops[0], Ops.size()));
4193 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4194 SDValue N0 = N->getOperand(0);
4195 EVT VT = N->getValueType(0);
4197 // fold (sext c1) -> c1
4198 if (isa<ConstantSDNode>(N0))
4199 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4201 // fold (sext (sext x)) -> (sext x)
4202 // fold (sext (aext x)) -> (sext x)
4203 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4204 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4207 if (N0.getOpcode() == ISD::TRUNCATE) {
4208 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4209 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4210 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4211 if (NarrowLoad.getNode()) {
4212 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4213 if (NarrowLoad.getNode() != N0.getNode()) {
4214 CombineTo(N0.getNode(), NarrowLoad);
4215 // CombineTo deleted the truncate, if needed, but not what's under it.
4218 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4221 // See if the value being truncated is already sign extended. If so, just
4222 // eliminate the trunc/sext pair.
4223 SDValue Op = N0.getOperand(0);
4224 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4225 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4226 unsigned DestBits = VT.getScalarType().getSizeInBits();
4227 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4229 if (OpBits == DestBits) {
4230 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4231 // bits, it is already ready.
4232 if (NumSignBits > DestBits-MidBits)
4234 } else if (OpBits < DestBits) {
4235 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4236 // bits, just sext from i32.
4237 if (NumSignBits > OpBits-MidBits)
4238 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4240 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4241 // bits, just truncate to i32.
4242 if (NumSignBits > OpBits-MidBits)
4243 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4246 // fold (sext (truncate x)) -> (sextinreg x).
4247 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4248 N0.getValueType())) {
4249 if (OpBits < DestBits)
4250 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4251 else if (OpBits > DestBits)
4252 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4253 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4254 DAG.getValueType(N0.getValueType()));
4258 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4259 // None of the supported targets knows how to perform load and sign extend
4260 // on vectors in one instruction. We only perform this transformation on
4262 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4263 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4264 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4265 bool DoXform = true;
4266 SmallVector<SDNode*, 4> SetCCs;
4267 if (!N0.hasOneUse())
4268 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4270 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4271 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4273 LN0->getBasePtr(), LN0->getPointerInfo(),
4275 LN0->isVolatile(), LN0->isNonTemporal(),
4276 LN0->getAlignment());
4277 CombineTo(N, ExtLoad);
4278 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4279 N0.getValueType(), ExtLoad);
4280 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4281 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4283 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4287 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4288 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4289 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4290 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4291 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4292 EVT MemVT = LN0->getMemoryVT();
4293 if ((!LegalOperations && !LN0->isVolatile()) ||
4294 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4295 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4297 LN0->getBasePtr(), LN0->getPointerInfo(),
4299 LN0->isVolatile(), LN0->isNonTemporal(),
4300 LN0->getAlignment());
4301 CombineTo(N, ExtLoad);
4302 CombineTo(N0.getNode(),
4303 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4304 N0.getValueType(), ExtLoad),
4305 ExtLoad.getValue(1));
4306 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4310 // fold (sext (and/or/xor (load x), cst)) ->
4311 // (and/or/xor (sextload x), (sext cst))
4312 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4313 N0.getOpcode() == ISD::XOR) &&
4314 isa<LoadSDNode>(N0.getOperand(0)) &&
4315 N0.getOperand(1).getOpcode() == ISD::Constant &&
4316 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4317 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4318 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4319 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4320 bool DoXform = true;
4321 SmallVector<SDNode*, 4> SetCCs;
4322 if (!N0.hasOneUse())
4323 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4326 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4327 LN0->getChain(), LN0->getBasePtr(),
4328 LN0->getPointerInfo(),
4331 LN0->isNonTemporal(),
4332 LN0->getAlignment());
4333 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4334 Mask = Mask.sext(VT.getSizeInBits());
4335 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4336 ExtLoad, DAG.getConstant(Mask, VT));
4337 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4338 N0.getOperand(0).getDebugLoc(),
4339 N0.getOperand(0).getValueType(), ExtLoad);
4341 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4342 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4344 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4349 if (N0.getOpcode() == ISD::SETCC) {
4350 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4351 // Only do this before legalize for now.
4352 if (VT.isVector() && !LegalOperations) {
4353 EVT N0VT = N0.getOperand(0).getValueType();
4354 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4355 // of the same size as the compared operands. Only optimize sext(setcc())
4356 // if this is the case.
4357 EVT SVT = TLI.getSetCCResultType(N0VT);
4359 // We know that the # elements of the results is the same as the
4360 // # elements of the compare (and the # elements of the compare result
4361 // for that matter). Check to see that they are the same size. If so,
4362 // we know that the element size of the sext'd result matches the
4363 // element size of the compare operands.
4364 if (VT.getSizeInBits() == SVT.getSizeInBits())
4365 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4367 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4368 // If the desired elements are smaller or larger than the source
4369 // elements we can use a matching integer vector type and then
4370 // truncate/sign extend
4372 EVT MatchingElementType =
4373 EVT::getIntegerVT(*DAG.getContext(),
4374 N0VT.getScalarType().getSizeInBits());
4375 EVT MatchingVectorType =
4376 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4377 N0VT.getVectorNumElements());
4379 if (SVT == MatchingVectorType) {
4380 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType,
4381 N0.getOperand(0), N0.getOperand(1),
4382 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4383 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4388 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4389 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4391 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4393 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4394 NegOne, DAG.getConstant(0, VT),
4395 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4396 if (SCC.getNode()) return SCC;
4397 if (!LegalOperations ||
4398 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4399 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4400 DAG.getSetCC(N->getDebugLoc(),
4401 TLI.getSetCCResultType(VT),
4402 N0.getOperand(0), N0.getOperand(1),
4403 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4404 NegOne, DAG.getConstant(0, VT));
4407 // fold (sext x) -> (zext x) if the sign bit is known zero.
4408 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4409 DAG.SignBitIsZero(N0))
4410 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4415 // isTruncateOf - If N is a truncate of some other value, return true, record
4416 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
4417 // This function computes KnownZero to avoid a duplicated call to
4418 // ComputeMaskedBits in the caller.
4419 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
4422 if (N->getOpcode() == ISD::TRUNCATE) {
4423 Op = N->getOperand(0);
4424 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4428 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4429 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4432 SDValue Op0 = N->getOperand(0);
4433 SDValue Op1 = N->getOperand(1);
4434 assert(Op0.getValueType() == Op1.getValueType());
4436 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
4437 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
4438 if (COp0 && COp0->isNullValue())
4440 else if (COp1 && COp1->isNullValue())
4445 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4447 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
4453 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4454 SDValue N0 = N->getOperand(0);
4455 EVT VT = N->getValueType(0);
4457 // fold (zext c1) -> c1
4458 if (isa<ConstantSDNode>(N0))
4459 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4460 // fold (zext (zext x)) -> (zext x)
4461 // fold (zext (aext x)) -> (zext x)
4462 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4463 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4466 // fold (zext (truncate x)) -> (zext x) or
4467 // (zext (truncate x)) -> (truncate x)
4468 // This is valid when the truncated bits of x are already zero.
4469 // FIXME: We should extend this to work for vectors too.
4472 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4473 APInt TruncatedBits =
4474 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4475 APInt(Op.getValueSizeInBits(), 0) :
4476 APInt::getBitsSet(Op.getValueSizeInBits(),
4477 N0.getValueSizeInBits(),
4478 std::min(Op.getValueSizeInBits(),
4479 VT.getSizeInBits()));
4480 if (TruncatedBits == (KnownZero & TruncatedBits)) {
4481 if (VT.bitsGT(Op.getValueType()))
4482 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4483 if (VT.bitsLT(Op.getValueType()))
4484 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4490 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4491 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4492 if (N0.getOpcode() == ISD::TRUNCATE) {
4493 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4494 if (NarrowLoad.getNode()) {
4495 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4496 if (NarrowLoad.getNode() != N0.getNode()) {
4497 CombineTo(N0.getNode(), NarrowLoad);
4498 // CombineTo deleted the truncate, if needed, but not what's under it.
4501 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4505 // fold (zext (truncate x)) -> (and x, mask)
4506 if (N0.getOpcode() == ISD::TRUNCATE &&
4507 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4509 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4510 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4511 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4512 if (NarrowLoad.getNode()) {
4513 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4514 if (NarrowLoad.getNode() != N0.getNode()) {
4515 CombineTo(N0.getNode(), NarrowLoad);
4516 // CombineTo deleted the truncate, if needed, but not what's under it.
4519 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4522 SDValue Op = N0.getOperand(0);
4523 if (Op.getValueType().bitsLT(VT)) {
4524 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4525 AddToWorkList(Op.getNode());
4526 } else if (Op.getValueType().bitsGT(VT)) {
4527 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4528 AddToWorkList(Op.getNode());
4530 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4531 N0.getValueType().getScalarType());
4534 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4535 // if either of the casts is not free.
4536 if (N0.getOpcode() == ISD::AND &&
4537 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4538 N0.getOperand(1).getOpcode() == ISD::Constant &&
4539 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4540 N0.getValueType()) ||
4541 !TLI.isZExtFree(N0.getValueType(), VT))) {
4542 SDValue X = N0.getOperand(0).getOperand(0);
4543 if (X.getValueType().bitsLT(VT)) {
4544 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4545 } else if (X.getValueType().bitsGT(VT)) {
4546 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4548 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4549 Mask = Mask.zext(VT.getSizeInBits());
4550 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4551 X, DAG.getConstant(Mask, VT));
4554 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4555 // None of the supported targets knows how to perform load and vector_zext
4556 // on vectors in one instruction. We only perform this transformation on
4558 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4559 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4560 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4561 bool DoXform = true;
4562 SmallVector<SDNode*, 4> SetCCs;
4563 if (!N0.hasOneUse())
4564 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4566 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4567 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4569 LN0->getBasePtr(), LN0->getPointerInfo(),
4571 LN0->isVolatile(), LN0->isNonTemporal(),
4572 LN0->getAlignment());
4573 CombineTo(N, ExtLoad);
4574 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4575 N0.getValueType(), ExtLoad);
4576 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4578 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4580 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4584 // fold (zext (and/or/xor (load x), cst)) ->
4585 // (and/or/xor (zextload x), (zext cst))
4586 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4587 N0.getOpcode() == ISD::XOR) &&
4588 isa<LoadSDNode>(N0.getOperand(0)) &&
4589 N0.getOperand(1).getOpcode() == ISD::Constant &&
4590 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4591 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4592 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4593 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4594 bool DoXform = true;
4595 SmallVector<SDNode*, 4> SetCCs;
4596 if (!N0.hasOneUse())
4597 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4600 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4601 LN0->getChain(), LN0->getBasePtr(),
4602 LN0->getPointerInfo(),
4605 LN0->isNonTemporal(),
4606 LN0->getAlignment());
4607 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4608 Mask = Mask.zext(VT.getSizeInBits());
4609 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4610 ExtLoad, DAG.getConstant(Mask, VT));
4611 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4612 N0.getOperand(0).getDebugLoc(),
4613 N0.getOperand(0).getValueType(), ExtLoad);
4615 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4616 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4618 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4623 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4624 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4625 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4626 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4627 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4628 EVT MemVT = LN0->getMemoryVT();
4629 if ((!LegalOperations && !LN0->isVolatile()) ||
4630 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4631 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4633 LN0->getBasePtr(), LN0->getPointerInfo(),
4635 LN0->isVolatile(), LN0->isNonTemporal(),
4636 LN0->getAlignment());
4637 CombineTo(N, ExtLoad);
4638 CombineTo(N0.getNode(),
4639 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4641 ExtLoad.getValue(1));
4642 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4646 if (N0.getOpcode() == ISD::SETCC) {
4647 if (!LegalOperations && VT.isVector()) {
4648 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4649 // Only do this before legalize for now.
4650 EVT N0VT = N0.getOperand(0).getValueType();
4651 EVT EltVT = VT.getVectorElementType();
4652 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4653 DAG.getConstant(1, EltVT));
4654 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4655 // We know that the # elements of the results is the same as the
4656 // # elements of the compare (and the # elements of the compare result
4657 // for that matter). Check to see that they are the same size. If so,
4658 // we know that the element size of the sext'd result matches the
4659 // element size of the compare operands.
4660 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4661 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4663 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4664 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4665 &OneOps[0], OneOps.size()));
4667 // If the desired elements are smaller or larger than the source
4668 // elements we can use a matching integer vector type and then
4669 // truncate/sign extend
4670 EVT MatchingElementType =
4671 EVT::getIntegerVT(*DAG.getContext(),
4672 N0VT.getScalarType().getSizeInBits());
4673 EVT MatchingVectorType =
4674 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4675 N0VT.getVectorNumElements());
4677 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4679 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4680 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4681 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4682 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4683 &OneOps[0], OneOps.size()));
4686 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4688 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4689 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4690 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4691 if (SCC.getNode()) return SCC;
4694 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4695 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4696 isa<ConstantSDNode>(N0.getOperand(1)) &&
4697 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4699 SDValue ShAmt = N0.getOperand(1);
4700 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4701 if (N0.getOpcode() == ISD::SHL) {
4702 SDValue InnerZExt = N0.getOperand(0);
4703 // If the original shl may be shifting out bits, do not perform this
4705 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4706 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4707 if (ShAmtVal > KnownZeroBits)
4711 DebugLoc DL = N->getDebugLoc();
4713 // Ensure that the shift amount is wide enough for the shifted value.
4714 if (VT.getSizeInBits() >= 256)
4715 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4717 return DAG.getNode(N0.getOpcode(), DL, VT,
4718 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4725 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4726 SDValue N0 = N->getOperand(0);
4727 EVT VT = N->getValueType(0);
4729 // fold (aext c1) -> c1
4730 if (isa<ConstantSDNode>(N0))
4731 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4732 // fold (aext (aext x)) -> (aext x)
4733 // fold (aext (zext x)) -> (zext x)
4734 // fold (aext (sext x)) -> (sext x)
4735 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4736 N0.getOpcode() == ISD::ZERO_EXTEND ||
4737 N0.getOpcode() == ISD::SIGN_EXTEND)
4738 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4740 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4741 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4742 if (N0.getOpcode() == ISD::TRUNCATE) {
4743 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4744 if (NarrowLoad.getNode()) {
4745 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4746 if (NarrowLoad.getNode() != N0.getNode()) {
4747 CombineTo(N0.getNode(), NarrowLoad);
4748 // CombineTo deleted the truncate, if needed, but not what's under it.
4751 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4755 // fold (aext (truncate x))
4756 if (N0.getOpcode() == ISD::TRUNCATE) {
4757 SDValue TruncOp = N0.getOperand(0);
4758 if (TruncOp.getValueType() == VT)
4759 return TruncOp; // x iff x size == zext size.
4760 if (TruncOp.getValueType().bitsGT(VT))
4761 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4762 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4765 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4766 // if the trunc is not free.
4767 if (N0.getOpcode() == ISD::AND &&
4768 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4769 N0.getOperand(1).getOpcode() == ISD::Constant &&
4770 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4771 N0.getValueType())) {
4772 SDValue X = N0.getOperand(0).getOperand(0);
4773 if (X.getValueType().bitsLT(VT)) {
4774 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4775 } else if (X.getValueType().bitsGT(VT)) {
4776 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4778 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4779 Mask = Mask.zext(VT.getSizeInBits());
4780 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4781 X, DAG.getConstant(Mask, VT));
4784 // fold (aext (load x)) -> (aext (truncate (extload x)))
4785 // None of the supported targets knows how to perform load and any_ext
4786 // on vectors in one instruction. We only perform this transformation on
4788 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4789 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4790 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4791 bool DoXform = true;
4792 SmallVector<SDNode*, 4> SetCCs;
4793 if (!N0.hasOneUse())
4794 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4796 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4797 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4799 LN0->getBasePtr(), LN0->getPointerInfo(),
4801 LN0->isVolatile(), LN0->isNonTemporal(),
4802 LN0->getAlignment());
4803 CombineTo(N, ExtLoad);
4804 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4805 N0.getValueType(), ExtLoad);
4806 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4807 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4809 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4813 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4814 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4815 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4816 if (N0.getOpcode() == ISD::LOAD &&
4817 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4819 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4820 EVT MemVT = LN0->getMemoryVT();
4821 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4822 VT, LN0->getChain(), LN0->getBasePtr(),
4823 LN0->getPointerInfo(), MemVT,
4824 LN0->isVolatile(), LN0->isNonTemporal(),
4825 LN0->getAlignment());
4826 CombineTo(N, ExtLoad);
4827 CombineTo(N0.getNode(),
4828 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4829 N0.getValueType(), ExtLoad),
4830 ExtLoad.getValue(1));
4831 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4834 if (N0.getOpcode() == ISD::SETCC) {
4835 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4836 // Only do this before legalize for now.
4837 if (VT.isVector() && !LegalOperations) {
4838 EVT N0VT = N0.getOperand(0).getValueType();
4839 // We know that the # elements of the results is the same as the
4840 // # elements of the compare (and the # elements of the compare result
4841 // for that matter). Check to see that they are the same size. If so,
4842 // we know that the element size of the sext'd result matches the
4843 // element size of the compare operands.
4844 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4845 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4847 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4848 // If the desired elements are smaller or larger than the source
4849 // elements we can use a matching integer vector type and then
4850 // truncate/sign extend
4852 EVT MatchingElementType =
4853 EVT::getIntegerVT(*DAG.getContext(),
4854 N0VT.getScalarType().getSizeInBits());
4855 EVT MatchingVectorType =
4856 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4857 N0VT.getVectorNumElements());
4859 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4861 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4862 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4866 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4868 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4869 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4870 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4878 /// GetDemandedBits - See if the specified operand can be simplified with the
4879 /// knowledge that only the bits specified by Mask are used. If so, return the
4880 /// simpler operand, otherwise return a null SDValue.
4881 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4882 switch (V.getOpcode()) {
4884 case ISD::Constant: {
4885 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4886 assert(CV != 0 && "Const value should be ConstSDNode.");
4887 const APInt &CVal = CV->getAPIntValue();
4888 APInt NewVal = CVal & Mask;
4889 if (NewVal != CVal) {
4890 return DAG.getConstant(NewVal, V.getValueType());
4896 // If the LHS or RHS don't contribute bits to the or, drop them.
4897 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4898 return V.getOperand(1);
4899 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4900 return V.getOperand(0);
4903 // Only look at single-use SRLs.
4904 if (!V.getNode()->hasOneUse())
4906 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4907 // See if we can recursively simplify the LHS.
4908 unsigned Amt = RHSC->getZExtValue();
4910 // Watch out for shift count overflow though.
4911 if (Amt >= Mask.getBitWidth()) break;
4912 APInt NewMask = Mask << Amt;
4913 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4914 if (SimplifyLHS.getNode())
4915 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4916 SimplifyLHS, V.getOperand(1));
4922 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4923 /// bits and then truncated to a narrower type and where N is a multiple
4924 /// of number of bits of the narrower type, transform it to a narrower load
4925 /// from address + N / num of bits of new type. If the result is to be
4926 /// extended, also fold the extension to form a extending load.
4927 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4928 unsigned Opc = N->getOpcode();
4930 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4931 SDValue N0 = N->getOperand(0);
4932 EVT VT = N->getValueType(0);
4935 // This transformation isn't valid for vector loads.
4939 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4941 if (Opc == ISD::SIGN_EXTEND_INREG) {
4942 ExtType = ISD::SEXTLOAD;
4943 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4944 } else if (Opc == ISD::SRL) {
4945 // Another special-case: SRL is basically zero-extending a narrower value.
4946 ExtType = ISD::ZEXTLOAD;
4948 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4949 if (!N01) return SDValue();
4950 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4951 VT.getSizeInBits() - N01->getZExtValue());
4953 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4956 unsigned EVTBits = ExtVT.getSizeInBits();
4958 // Do not generate loads of non-round integer types since these can
4959 // be expensive (and would be wrong if the type is not byte sized).
4960 if (!ExtVT.isRound())
4964 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4965 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4966 ShAmt = N01->getZExtValue();
4967 // Is the shift amount a multiple of size of VT?
4968 if ((ShAmt & (EVTBits-1)) == 0) {
4969 N0 = N0.getOperand(0);
4970 // Is the load width a multiple of size of VT?
4971 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4975 // At this point, we must have a load or else we can't do the transform.
4976 if (!isa<LoadSDNode>(N0)) return SDValue();
4978 // If the shift amount is larger than the input type then we're not
4979 // accessing any of the loaded bytes. If the load was a zextload/extload
4980 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4981 // If the load was a sextload then the result is a splat of the sign bit
4982 // of the extended byte. This is not worth optimizing for.
4983 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4988 // If the load is shifted left (and the result isn't shifted back right),
4989 // we can fold the truncate through the shift.
4990 unsigned ShLeftAmt = 0;
4991 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4992 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4993 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4994 ShLeftAmt = N01->getZExtValue();
4995 N0 = N0.getOperand(0);
4999 // If we haven't found a load, we can't narrow it. Don't transform one with
5000 // multiple uses, this would require adding a new load.
5001 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
5002 // Don't change the width of a volatile load.
5003 cast<LoadSDNode>(N0)->isVolatile())
5006 // Verify that we are actually reducing a load width here.
5007 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
5010 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5011 EVT PtrType = N0.getOperand(1).getValueType();
5013 // For big endian targets, we need to adjust the offset to the pointer to
5014 // load the correct bytes.
5015 if (TLI.isBigEndian()) {
5016 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5017 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5018 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5021 uint64_t PtrOff = ShAmt / 8;
5022 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5023 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
5024 PtrType, LN0->getBasePtr(),
5025 DAG.getConstant(PtrOff, PtrType));
5026 AddToWorkList(NewPtr.getNode());
5029 if (ExtType == ISD::NON_EXTLOAD)
5030 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
5031 LN0->getPointerInfo().getWithOffset(PtrOff),
5032 LN0->isVolatile(), LN0->isNonTemporal(),
5033 LN0->isInvariant(), NewAlign);
5035 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
5036 LN0->getPointerInfo().getWithOffset(PtrOff),
5037 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5040 // Replace the old load's chain with the new load's chain.
5041 WorkListRemover DeadNodes(*this);
5042 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5044 // Shift the result left, if we've swallowed a left shift.
5045 SDValue Result = Load;
5046 if (ShLeftAmt != 0) {
5047 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5048 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5050 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
5051 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5054 // Return the new loaded value.
5058 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5059 SDValue N0 = N->getOperand(0);
5060 SDValue N1 = N->getOperand(1);
5061 EVT VT = N->getValueType(0);
5062 EVT EVT = cast<VTSDNode>(N1)->getVT();
5063 unsigned VTBits = VT.getScalarType().getSizeInBits();
5064 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5066 // fold (sext_in_reg c1) -> c1
5067 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5068 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
5070 // If the input is already sign extended, just drop the extension.
5071 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5074 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5075 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5076 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
5077 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5078 N0.getOperand(0), N1);
5081 // fold (sext_in_reg (sext x)) -> (sext x)
5082 // fold (sext_in_reg (aext x)) -> (sext x)
5083 // if x is small enough.
5084 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5085 SDValue N00 = N0.getOperand(0);
5086 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5087 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5088 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
5091 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5092 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5093 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
5095 // fold operands of sext_in_reg based on knowledge that the top bits are not
5097 if (SimplifyDemandedBits(SDValue(N, 0)))
5098 return SDValue(N, 0);
5100 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5101 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5102 SDValue NarrowLoad = ReduceLoadWidth(N);
5103 if (NarrowLoad.getNode())
5106 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5107 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5108 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5109 if (N0.getOpcode() == ISD::SRL) {
5110 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5111 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5112 // We can turn this into an SRA iff the input to the SRL is already sign
5114 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5115 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5116 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5117 N0.getOperand(0), N0.getOperand(1));
5121 // fold (sext_inreg (extload x)) -> (sextload x)
5122 if (ISD::isEXTLoad(N0.getNode()) &&
5123 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5124 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5125 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5126 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5127 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5128 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5130 LN0->getBasePtr(), LN0->getPointerInfo(),
5132 LN0->isVolatile(), LN0->isNonTemporal(),
5133 LN0->getAlignment());
5134 CombineTo(N, ExtLoad);
5135 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5136 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5138 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5139 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5141 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5142 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5143 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5144 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5145 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5147 LN0->getBasePtr(), LN0->getPointerInfo(),
5149 LN0->isVolatile(), LN0->isNonTemporal(),
5150 LN0->getAlignment());
5151 CombineTo(N, ExtLoad);
5152 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5153 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5156 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5157 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5158 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5159 N0.getOperand(1), false);
5160 if (BSwap.getNode() != 0)
5161 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5168 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5169 SDValue N0 = N->getOperand(0);
5170 EVT VT = N->getValueType(0);
5171 bool isLE = TLI.isLittleEndian();
5174 if (N0.getValueType() == N->getValueType(0))
5176 // fold (truncate c1) -> c1
5177 if (isa<ConstantSDNode>(N0))
5178 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5179 // fold (truncate (truncate x)) -> (truncate x)
5180 if (N0.getOpcode() == ISD::TRUNCATE)
5181 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5182 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5183 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5184 N0.getOpcode() == ISD::SIGN_EXTEND ||
5185 N0.getOpcode() == ISD::ANY_EXTEND) {
5186 if (N0.getOperand(0).getValueType().bitsLT(VT))
5187 // if the source is smaller than the dest, we still need an extend
5188 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
5190 else if (N0.getOperand(0).getValueType().bitsGT(VT))
5191 // if the source is larger than the dest, than we just need the truncate
5192 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5194 // if the source and dest are the same type, we can drop both the extend
5195 // and the truncate.
5196 return N0.getOperand(0);
5199 // Fold extract-and-trunc into a narrow extract. For example:
5200 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5201 // i32 y = TRUNCATE(i64 x)
5203 // v16i8 b = BITCAST (v2i64 val)
5204 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5206 // Note: We only run this optimization after type legalization (which often
5207 // creates this pattern) and before operation legalization after which
5208 // we need to be more careful about the vector instructions that we generate.
5209 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5210 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5212 EVT VecTy = N0.getOperand(0).getValueType();
5213 EVT ExTy = N0.getValueType();
5214 EVT TrTy = N->getValueType(0);
5216 unsigned NumElem = VecTy.getVectorNumElements();
5217 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5219 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5220 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5222 SDValue EltNo = N0->getOperand(1);
5223 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5224 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5226 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5228 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5229 NVT, N0.getOperand(0));
5231 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5232 N->getDebugLoc(), TrTy, V,
5233 DAG.getConstant(Index, MVT::i32));
5237 // See if we can simplify the input to this truncate through knowledge that
5238 // only the low bits are being used.
5239 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5240 // Currently we only perform this optimization on scalars because vectors
5241 // may have different active low bits.
5242 if (!VT.isVector()) {
5244 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5245 VT.getSizeInBits()));
5246 if (Shorter.getNode())
5247 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5249 // fold (truncate (load x)) -> (smaller load x)
5250 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5251 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5252 SDValue Reduced = ReduceLoadWidth(N);
5253 if (Reduced.getNode())
5257 // Simplify the operands using demanded-bits information.
5258 if (!VT.isVector() &&
5259 SimplifyDemandedBits(SDValue(N, 0)))
5260 return SDValue(N, 0);
5265 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5266 SDValue Elt = N->getOperand(i);
5267 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5268 return Elt.getNode();
5269 return Elt.getOperand(Elt.getResNo()).getNode();
5272 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5273 /// if load locations are consecutive.
5274 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5275 assert(N->getOpcode() == ISD::BUILD_PAIR);
5277 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5278 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5279 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5280 LD1->getPointerInfo().getAddrSpace() !=
5281 LD2->getPointerInfo().getAddrSpace())
5283 EVT LD1VT = LD1->getValueType(0);
5285 if (ISD::isNON_EXTLoad(LD2) &&
5287 // If both are volatile this would reduce the number of volatile loads.
5288 // If one is volatile it might be ok, but play conservative and bail out.
5289 !LD1->isVolatile() &&
5290 !LD2->isVolatile() &&
5291 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5292 unsigned Align = LD1->getAlignment();
5293 unsigned NewAlign = TLI.getTargetData()->
5294 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5296 if (NewAlign <= Align &&
5297 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5298 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5299 LD1->getBasePtr(), LD1->getPointerInfo(),
5300 false, false, false, Align);
5306 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5307 SDValue N0 = N->getOperand(0);
5308 EVT VT = N->getValueType(0);
5310 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5311 // Only do this before legalize, since afterward the target may be depending
5312 // on the bitconvert.
5313 // First check to see if this is all constant.
5315 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5317 bool isSimple = true;
5318 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5319 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5320 N0.getOperand(i).getOpcode() != ISD::Constant &&
5321 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5326 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5327 assert(!DestEltVT.isVector() &&
5328 "Element type of vector ValueType must not be vector!");
5330 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5333 // If the input is a constant, let getNode fold it.
5334 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5335 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5336 if (Res.getNode() != N) {
5337 if (!LegalOperations ||
5338 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5341 // Folding it resulted in an illegal node, and it's too late to
5342 // do that. Clean up the old node and forego the transformation.
5343 // Ideally this won't happen very often, because instcombine
5344 // and the earlier dagcombine runs (where illegal nodes are
5345 // permitted) should have folded most of them already.
5346 DAG.DeleteNode(Res.getNode());
5350 // (conv (conv x, t1), t2) -> (conv x, t2)
5351 if (N0.getOpcode() == ISD::BITCAST)
5352 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5355 // fold (conv (load x)) -> (load (conv*)x)
5356 // If the resultant load doesn't need a higher alignment than the original!
5357 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5358 // Do not change the width of a volatile load.
5359 !cast<LoadSDNode>(N0)->isVolatile() &&
5360 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5361 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5362 unsigned Align = TLI.getTargetData()->
5363 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5364 unsigned OrigAlign = LN0->getAlignment();
5366 if (Align <= OrigAlign) {
5367 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5368 LN0->getBasePtr(), LN0->getPointerInfo(),
5369 LN0->isVolatile(), LN0->isNonTemporal(),
5370 LN0->isInvariant(), OrigAlign);
5372 CombineTo(N0.getNode(),
5373 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5374 N0.getValueType(), Load),
5380 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5381 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5382 // This often reduces constant pool loads.
5383 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5384 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
5385 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
5386 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5388 AddToWorkList(NewConv.getNode());
5390 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5391 if (N0.getOpcode() == ISD::FNEG)
5392 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5393 NewConv, DAG.getConstant(SignBit, VT));
5394 assert(N0.getOpcode() == ISD::FABS);
5395 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5396 NewConv, DAG.getConstant(~SignBit, VT));
5399 // fold (bitconvert (fcopysign cst, x)) ->
5400 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5401 // Note that we don't handle (copysign x, cst) because this can always be
5402 // folded to an fneg or fabs.
5403 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5404 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5405 VT.isInteger() && !VT.isVector()) {
5406 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5407 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5408 if (isTypeLegal(IntXVT)) {
5409 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5410 IntXVT, N0.getOperand(1));
5411 AddToWorkList(X.getNode());
5413 // If X has a different width than the result/lhs, sext it or truncate it.
5414 unsigned VTWidth = VT.getSizeInBits();
5415 if (OrigXWidth < VTWidth) {
5416 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5417 AddToWorkList(X.getNode());
5418 } else if (OrigXWidth > VTWidth) {
5419 // To get the sign bit in the right place, we have to shift it right
5420 // before truncating.
5421 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5422 X.getValueType(), X,
5423 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5424 AddToWorkList(X.getNode());
5425 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5426 AddToWorkList(X.getNode());
5429 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5430 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5431 X, DAG.getConstant(SignBit, VT));
5432 AddToWorkList(X.getNode());
5434 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5435 VT, N0.getOperand(0));
5436 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5437 Cst, DAG.getConstant(~SignBit, VT));
5438 AddToWorkList(Cst.getNode());
5440 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5444 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5445 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5446 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5447 if (CombineLD.getNode())
5454 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5455 EVT VT = N->getValueType(0);
5456 return CombineConsecutiveLoads(N, VT);
5459 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5460 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5461 /// destination element value type.
5462 SDValue DAGCombiner::
5463 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5464 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5466 // If this is already the right type, we're done.
5467 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5469 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5470 unsigned DstBitSize = DstEltVT.getSizeInBits();
5472 // If this is a conversion of N elements of one type to N elements of another
5473 // type, convert each element. This handles FP<->INT cases.
5474 if (SrcBitSize == DstBitSize) {
5475 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5476 BV->getValueType(0).getVectorNumElements());
5478 // Due to the FP element handling below calling this routine recursively,
5479 // we can end up with a scalar-to-vector node here.
5480 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5481 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5482 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5483 DstEltVT, BV->getOperand(0)));
5485 SmallVector<SDValue, 8> Ops;
5486 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5487 SDValue Op = BV->getOperand(i);
5488 // If the vector element type is not legal, the BUILD_VECTOR operands
5489 // are promoted and implicitly truncated. Make that explicit here.
5490 if (Op.getValueType() != SrcEltVT)
5491 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5492 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5494 AddToWorkList(Ops.back().getNode());
5496 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5497 &Ops[0], Ops.size());
5500 // Otherwise, we're growing or shrinking the elements. To avoid having to
5501 // handle annoying details of growing/shrinking FP values, we convert them to
5503 if (SrcEltVT.isFloatingPoint()) {
5504 // Convert the input float vector to a int vector where the elements are the
5506 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5507 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5508 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5512 // Now we know the input is an integer vector. If the output is a FP type,
5513 // convert to integer first, then to FP of the right size.
5514 if (DstEltVT.isFloatingPoint()) {
5515 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5516 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5517 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5519 // Next, convert to FP elements of the same size.
5520 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5523 // Okay, we know the src/dst types are both integers of differing types.
5524 // Handling growing first.
5525 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5526 if (SrcBitSize < DstBitSize) {
5527 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5529 SmallVector<SDValue, 8> Ops;
5530 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5531 i += NumInputsPerOutput) {
5532 bool isLE = TLI.isLittleEndian();
5533 APInt NewBits = APInt(DstBitSize, 0);
5534 bool EltIsUndef = true;
5535 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5536 // Shift the previously computed bits over.
5537 NewBits <<= SrcBitSize;
5538 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5539 if (Op.getOpcode() == ISD::UNDEF) continue;
5542 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5543 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5547 Ops.push_back(DAG.getUNDEF(DstEltVT));
5549 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5552 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5553 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5554 &Ops[0], Ops.size());
5557 // Finally, this must be the case where we are shrinking elements: each input
5558 // turns into multiple outputs.
5559 bool isS2V = ISD::isScalarToVector(BV);
5560 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5561 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5562 NumOutputsPerInput*BV->getNumOperands());
5563 SmallVector<SDValue, 8> Ops;
5565 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5566 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5567 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5568 Ops.push_back(DAG.getUNDEF(DstEltVT));
5572 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5573 getAPIntValue().zextOrTrunc(SrcBitSize);
5575 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5576 APInt ThisVal = OpVal.trunc(DstBitSize);
5577 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5578 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5579 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5580 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5582 OpVal = OpVal.lshr(DstBitSize);
5585 // For big endian targets, swap the order of the pieces of each element.
5586 if (TLI.isBigEndian())
5587 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5590 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5591 &Ops[0], Ops.size());
5594 SDValue DAGCombiner::visitFADD(SDNode *N) {
5595 SDValue N0 = N->getOperand(0);
5596 SDValue N1 = N->getOperand(1);
5597 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5598 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5599 EVT VT = N->getValueType(0);
5602 if (VT.isVector()) {
5603 SDValue FoldedVOp = SimplifyVBinOp(N);
5604 if (FoldedVOp.getNode()) return FoldedVOp;
5607 // fold (fadd c1, c2) -> (fadd c1, c2)
5608 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5609 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5610 // canonicalize constant to RHS
5611 if (N0CFP && !N1CFP)
5612 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5613 // fold (fadd A, 0) -> A
5614 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5615 N1CFP->getValueAPF().isZero())
5617 // fold (fadd A, (fneg B)) -> (fsub A, B)
5618 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5619 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5620 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5621 GetNegatedExpression(N1, DAG, LegalOperations));
5622 // fold (fadd (fneg A), B) -> (fsub B, A)
5623 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5624 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5625 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5626 GetNegatedExpression(N0, DAG, LegalOperations));
5628 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5629 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5630 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5631 isa<ConstantFPSDNode>(N0.getOperand(1)))
5632 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5633 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5634 N0.getOperand(1), N1));
5639 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5640 SDValue N0 = N->getOperand(0);
5641 SDValue N1 = N->getOperand(1);
5642 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5643 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5644 EVT VT = N->getValueType(0);
5647 if (VT.isVector()) {
5648 SDValue FoldedVOp = SimplifyVBinOp(N);
5649 if (FoldedVOp.getNode()) return FoldedVOp;
5652 // fold (fsub c1, c2) -> c1-c2
5653 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5654 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5655 // fold (fsub A, 0) -> A
5656 if (DAG.getTarget().Options.UnsafeFPMath &&
5657 N1CFP && N1CFP->getValueAPF().isZero())
5659 // fold (fsub 0, B) -> -B
5660 if (DAG.getTarget().Options.UnsafeFPMath &&
5661 N0CFP && N0CFP->getValueAPF().isZero()) {
5662 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5663 return GetNegatedExpression(N1, DAG, LegalOperations);
5664 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5665 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5667 // fold (fsub A, (fneg B)) -> (fadd A, B)
5668 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5669 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5670 GetNegatedExpression(N1, DAG, LegalOperations));
5672 // If 'unsafe math' is enabled, fold
5673 // (fsub x, x) -> 0.0 &
5674 // (fsub x, (fadd x, y)) -> (fneg y) &
5675 // (fsub x, (fadd y, x)) -> (fneg y)
5676 if (DAG.getTarget().Options.UnsafeFPMath) {
5678 return DAG.getConstantFP(0.0f, VT);
5680 if (N1.getOpcode() == ISD::FADD) {
5681 SDValue N10 = N1->getOperand(0);
5682 SDValue N11 = N1->getOperand(1);
5684 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
5685 &DAG.getTarget().Options))
5686 return GetNegatedExpression(N11, DAG, LegalOperations);
5687 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
5688 &DAG.getTarget().Options))
5689 return GetNegatedExpression(N10, DAG, LegalOperations);
5696 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5697 SDValue N0 = N->getOperand(0);
5698 SDValue N1 = N->getOperand(1);
5699 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5700 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5701 EVT VT = N->getValueType(0);
5702 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5705 if (VT.isVector()) {
5706 SDValue FoldedVOp = SimplifyVBinOp(N);
5707 if (FoldedVOp.getNode()) return FoldedVOp;
5710 // fold (fmul c1, c2) -> c1*c2
5711 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5712 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5713 // canonicalize constant to RHS
5714 if (N0CFP && !N1CFP)
5715 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5716 // fold (fmul A, 0) -> 0
5717 if (DAG.getTarget().Options.UnsafeFPMath &&
5718 N1CFP && N1CFP->getValueAPF().isZero())
5720 // fold (fmul A, 0) -> 0, vector edition.
5721 if (DAG.getTarget().Options.UnsafeFPMath &&
5722 ISD::isBuildVectorAllZeros(N1.getNode()))
5724 // fold (fmul A, 1.0) -> A
5725 if (N1CFP && N1CFP->isExactlyValue(1.0))
5727 // fold (fmul X, 2.0) -> (fadd X, X)
5728 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5729 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5730 // fold (fmul X, -1.0) -> (fneg X)
5731 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5732 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5733 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5735 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5736 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
5737 &DAG.getTarget().Options)) {
5738 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
5739 &DAG.getTarget().Options)) {
5740 // Both can be negated for free, check to see if at least one is cheaper
5742 if (LHSNeg == 2 || RHSNeg == 2)
5743 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5744 GetNegatedExpression(N0, DAG, LegalOperations),
5745 GetNegatedExpression(N1, DAG, LegalOperations));
5749 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5750 if (DAG.getTarget().Options.UnsafeFPMath &&
5751 N1CFP && N0.getOpcode() == ISD::FMUL &&
5752 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5753 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5754 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5755 N0.getOperand(1), N1));
5760 SDValue DAGCombiner::visitFMA(SDNode *N) {
5761 SDValue N0 = N->getOperand(0);
5762 SDValue N1 = N->getOperand(1);
5763 SDValue N2 = N->getOperand(2);
5764 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5765 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5766 EVT VT = N->getValueType(0);
5768 if (N0CFP && N0CFP->isExactlyValue(1.0))
5769 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2);
5770 if (N1CFP && N1CFP->isExactlyValue(1.0))
5771 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2);
5776 SDValue DAGCombiner::visitFDIV(SDNode *N) {
5777 SDValue N0 = N->getOperand(0);
5778 SDValue N1 = N->getOperand(1);
5779 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5780 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5781 EVT VT = N->getValueType(0);
5782 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5785 if (VT.isVector()) {
5786 SDValue FoldedVOp = SimplifyVBinOp(N);
5787 if (FoldedVOp.getNode()) return FoldedVOp;
5790 // fold (fdiv c1, c2) -> c1/c2
5791 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5792 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5794 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
5795 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) {
5796 // Compute the reciprocal 1.0 / c2.
5797 APFloat N1APF = N1CFP->getValueAPF();
5798 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
5799 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
5800 // Only do the transform if the reciprocal is a legal fp immediate that
5801 // isn't too nasty (eg NaN, denormal, ...).
5802 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
5803 (!LegalOperations ||
5804 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
5805 // backend)... we should handle this gracefully after Legalize.
5806 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
5807 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
5808 TLI.isFPImmLegal(Recip, VT)))
5809 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0,
5810 DAG.getConstantFP(Recip, VT));
5813 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5814 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
5815 &DAG.getTarget().Options)) {
5816 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
5817 &DAG.getTarget().Options)) {
5818 // Both can be negated for free, check to see if at least one is cheaper
5820 if (LHSNeg == 2 || RHSNeg == 2)
5821 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5822 GetNegatedExpression(N0, DAG, LegalOperations),
5823 GetNegatedExpression(N1, DAG, LegalOperations));
5830 SDValue DAGCombiner::visitFREM(SDNode *N) {
5831 SDValue N0 = N->getOperand(0);
5832 SDValue N1 = N->getOperand(1);
5833 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5834 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5835 EVT VT = N->getValueType(0);
5837 // fold (frem c1, c2) -> fmod(c1,c2)
5838 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5839 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5844 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5845 SDValue N0 = N->getOperand(0);
5846 SDValue N1 = N->getOperand(1);
5847 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5848 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5849 EVT VT = N->getValueType(0);
5851 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
5852 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5855 const APFloat& V = N1CFP->getValueAPF();
5856 // copysign(x, c1) -> fabs(x) iff ispos(c1)
5857 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5858 if (!V.isNegative()) {
5859 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5860 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5862 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5863 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5864 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5868 // copysign(fabs(x), y) -> copysign(x, y)
5869 // copysign(fneg(x), y) -> copysign(x, y)
5870 // copysign(copysign(x,z), y) -> copysign(x, y)
5871 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5872 N0.getOpcode() == ISD::FCOPYSIGN)
5873 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5874 N0.getOperand(0), N1);
5876 // copysign(x, abs(y)) -> abs(x)
5877 if (N1.getOpcode() == ISD::FABS)
5878 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5880 // copysign(x, copysign(y,z)) -> copysign(x, z)
5881 if (N1.getOpcode() == ISD::FCOPYSIGN)
5882 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5883 N0, N1.getOperand(1));
5885 // copysign(x, fp_extend(y)) -> copysign(x, y)
5886 // copysign(x, fp_round(y)) -> copysign(x, y)
5887 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5888 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5889 N0, N1.getOperand(0));
5894 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5895 SDValue N0 = N->getOperand(0);
5896 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5897 EVT VT = N->getValueType(0);
5898 EVT OpVT = N0.getValueType();
5900 // fold (sint_to_fp c1) -> c1fp
5901 if (N0C && OpVT != MVT::ppcf128 &&
5902 // ...but only if the target supports immediate floating-point values
5903 (!LegalOperations ||
5904 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5905 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5907 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5908 // but UINT_TO_FP is legal on this target, try to convert.
5909 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5910 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5911 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
5912 if (DAG.SignBitIsZero(N0))
5913 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5919 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5920 SDValue N0 = N->getOperand(0);
5921 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5922 EVT VT = N->getValueType(0);
5923 EVT OpVT = N0.getValueType();
5925 // fold (uint_to_fp c1) -> c1fp
5926 if (N0C && OpVT != MVT::ppcf128 &&
5927 // ...but only if the target supports immediate floating-point values
5928 (!LegalOperations ||
5929 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5930 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5932 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5933 // but SINT_TO_FP is legal on this target, try to convert.
5934 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5935 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5936 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5937 if (DAG.SignBitIsZero(N0))
5938 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5944 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5945 SDValue N0 = N->getOperand(0);
5946 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5947 EVT VT = N->getValueType(0);
5949 // fold (fp_to_sint c1fp) -> c1
5951 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5956 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5957 SDValue N0 = N->getOperand(0);
5958 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5959 EVT VT = N->getValueType(0);
5961 // fold (fp_to_uint c1fp) -> c1
5962 if (N0CFP && VT != MVT::ppcf128)
5963 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5968 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5969 SDValue N0 = N->getOperand(0);
5970 SDValue N1 = N->getOperand(1);
5971 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5972 EVT VT = N->getValueType(0);
5974 // fold (fp_round c1fp) -> c1fp
5975 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5976 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5978 // fold (fp_round (fp_extend x)) -> x
5979 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5980 return N0.getOperand(0);
5982 // fold (fp_round (fp_round x)) -> (fp_round x)
5983 if (N0.getOpcode() == ISD::FP_ROUND) {
5984 // This is a value preserving truncation if both round's are.
5985 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5986 N0.getNode()->getConstantOperandVal(1) == 1;
5987 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5988 DAG.getIntPtrConstant(IsTrunc));
5991 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5992 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5993 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5994 N0.getOperand(0), N1);
5995 AddToWorkList(Tmp.getNode());
5996 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5997 Tmp, N0.getOperand(1));
6003 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
6004 SDValue N0 = N->getOperand(0);
6005 EVT VT = N->getValueType(0);
6006 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6007 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6009 // fold (fp_round_inreg c1fp) -> c1fp
6010 if (N0CFP && isTypeLegal(EVT)) {
6011 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
6012 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
6018 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
6019 SDValue N0 = N->getOperand(0);
6020 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6021 EVT VT = N->getValueType(0);
6023 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
6024 if (N->hasOneUse() &&
6025 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6028 // fold (fp_extend c1fp) -> c1fp
6029 if (N0CFP && VT != MVT::ppcf128)
6030 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
6032 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
6034 if (N0.getOpcode() == ISD::FP_ROUND
6035 && N0.getNode()->getConstantOperandVal(1) == 1) {
6036 SDValue In = N0.getOperand(0);
6037 if (In.getValueType() == VT) return In;
6038 if (VT.bitsLT(In.getValueType()))
6039 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
6040 In, N0.getOperand(1));
6041 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
6044 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
6045 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6046 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6047 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6048 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6049 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
6051 LN0->getBasePtr(), LN0->getPointerInfo(),
6053 LN0->isVolatile(), LN0->isNonTemporal(),
6054 LN0->getAlignment());
6055 CombineTo(N, ExtLoad);
6056 CombineTo(N0.getNode(),
6057 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
6058 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6059 ExtLoad.getValue(1));
6060 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6066 SDValue DAGCombiner::visitFNEG(SDNode *N) {
6067 SDValue N0 = N->getOperand(0);
6068 EVT VT = N->getValueType(0);
6070 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6071 &DAG.getTarget().Options))
6072 return GetNegatedExpression(N0, DAG, LegalOperations);
6074 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
6075 // constant pool values.
6076 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6078 N0.getNode()->hasOneUse() &&
6079 N0.getOperand(0).getValueType().isInteger()) {
6080 SDValue Int = N0.getOperand(0);
6081 EVT IntVT = Int.getValueType();
6082 if (IntVT.isInteger() && !IntVT.isVector()) {
6083 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
6084 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6085 AddToWorkList(Int.getNode());
6086 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6094 SDValue DAGCombiner::visitFABS(SDNode *N) {
6095 SDValue N0 = N->getOperand(0);
6096 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6097 EVT VT = N->getValueType(0);
6099 // fold (fabs c1) -> fabs(c1)
6100 if (N0CFP && VT != MVT::ppcf128)
6101 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6102 // fold (fabs (fabs x)) -> (fabs x)
6103 if (N0.getOpcode() == ISD::FABS)
6104 return N->getOperand(0);
6105 // fold (fabs (fneg x)) -> (fabs x)
6106 // fold (fabs (fcopysign x, y)) -> (fabs x)
6107 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6108 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
6110 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
6111 // constant pool values.
6112 if (!TLI.isFAbsFree(VT) &&
6113 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6114 N0.getOperand(0).getValueType().isInteger() &&
6115 !N0.getOperand(0).getValueType().isVector()) {
6116 SDValue Int = N0.getOperand(0);
6117 EVT IntVT = Int.getValueType();
6118 if (IntVT.isInteger() && !IntVT.isVector()) {
6119 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
6120 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6121 AddToWorkList(Int.getNode());
6122 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6123 N->getValueType(0), Int);
6130 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
6131 SDValue Chain = N->getOperand(0);
6132 SDValue N1 = N->getOperand(1);
6133 SDValue N2 = N->getOperand(2);
6135 // If N is a constant we could fold this into a fallthrough or unconditional
6136 // branch. However that doesn't happen very often in normal code, because
6137 // Instcombine/SimplifyCFG should have handled the available opportunities.
6138 // If we did this folding here, it would be necessary to update the
6139 // MachineBasicBlock CFG, which is awkward.
6141 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6143 if (N1.getOpcode() == ISD::SETCC &&
6144 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
6145 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6146 Chain, N1.getOperand(2),
6147 N1.getOperand(0), N1.getOperand(1), N2);
6150 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6151 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6152 (N1.getOperand(0).hasOneUse() &&
6153 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6155 if (N1.getOpcode() == ISD::TRUNCATE) {
6156 // Look pass the truncate.
6157 Trunc = N1.getNode();
6158 N1 = N1.getOperand(0);
6161 // Match this pattern so that we can generate simpler code:
6164 // %b = and i32 %a, 2
6165 // %c = srl i32 %b, 1
6166 // brcond i32 %c ...
6171 // %b = and i32 %a, 2
6172 // %c = setcc eq %b, 0
6175 // This applies only when the AND constant value has one bit set and the
6176 // SRL constant is equal to the log2 of the AND constant. The back-end is
6177 // smart enough to convert the result into a TEST/JMP sequence.
6178 SDValue Op0 = N1.getOperand(0);
6179 SDValue Op1 = N1.getOperand(1);
6181 if (Op0.getOpcode() == ISD::AND &&
6182 Op1.getOpcode() == ISD::Constant) {
6183 SDValue AndOp1 = Op0.getOperand(1);
6185 if (AndOp1.getOpcode() == ISD::Constant) {
6186 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6188 if (AndConst.isPowerOf2() &&
6189 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6191 DAG.getSetCC(N->getDebugLoc(),
6192 TLI.getSetCCResultType(Op0.getValueType()),
6193 Op0, DAG.getConstant(0, Op0.getValueType()),
6196 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6197 MVT::Other, Chain, SetCC, N2);
6198 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6199 // will convert it back to (X & C1) >> C2.
6200 CombineTo(N, NewBRCond, false);
6201 // Truncate is dead.
6203 removeFromWorkList(Trunc);
6204 DAG.DeleteNode(Trunc);
6206 // Replace the uses of SRL with SETCC
6207 WorkListRemover DeadNodes(*this);
6208 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6209 removeFromWorkList(N1.getNode());
6210 DAG.DeleteNode(N1.getNode());
6211 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6217 // Restore N1 if the above transformation doesn't match.
6218 N1 = N->getOperand(1);
6221 // Transform br(xor(x, y)) -> br(x != y)
6222 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6223 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6224 SDNode *TheXor = N1.getNode();
6225 SDValue Op0 = TheXor->getOperand(0);
6226 SDValue Op1 = TheXor->getOperand(1);
6227 if (Op0.getOpcode() == Op1.getOpcode()) {
6228 // Avoid missing important xor optimizations.
6229 SDValue Tmp = visitXOR(TheXor);
6230 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
6231 DEBUG(dbgs() << "\nReplacing.8 ";
6233 dbgs() << "\nWith: ";
6234 Tmp.getNode()->dump(&DAG);
6236 WorkListRemover DeadNodes(*this);
6237 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
6238 removeFromWorkList(TheXor);
6239 DAG.DeleteNode(TheXor);
6240 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6241 MVT::Other, Chain, Tmp, N2);
6245 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6247 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6248 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6249 Op0.getOpcode() == ISD::XOR) {
6250 TheXor = Op0.getNode();
6254 EVT SetCCVT = N1.getValueType();
6256 SetCCVT = TLI.getSetCCResultType(SetCCVT);
6257 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
6260 Equal ? ISD::SETEQ : ISD::SETNE);
6261 // Replace the uses of XOR with SETCC
6262 WorkListRemover DeadNodes(*this);
6263 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6264 removeFromWorkList(N1.getNode());
6265 DAG.DeleteNode(N1.getNode());
6266 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6267 MVT::Other, Chain, SetCC, N2);
6274 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6276 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6277 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6278 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6280 // If N is a constant we could fold this into a fallthrough or unconditional
6281 // branch. However that doesn't happen very often in normal code, because
6282 // Instcombine/SimplifyCFG should have handled the available opportunities.
6283 // If we did this folding here, it would be necessary to update the
6284 // MachineBasicBlock CFG, which is awkward.
6286 // Use SimplifySetCC to simplify SETCC's.
6287 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6288 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6290 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6292 // fold to a simpler setcc
6293 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6294 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6295 N->getOperand(0), Simp.getOperand(2),
6296 Simp.getOperand(0), Simp.getOperand(1),
6302 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6303 /// uses N as its base pointer and that N may be folded in the load / store
6304 /// addressing mode.
6305 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6307 const TargetLowering &TLI) {
6309 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6310 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6312 VT = Use->getValueType(0);
6313 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6314 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6316 VT = ST->getValue().getValueType();
6320 TargetLowering::AddrMode AM;
6321 if (N->getOpcode() == ISD::ADD) {
6322 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6325 AM.BaseOffs = Offset->getSExtValue();
6329 } else if (N->getOpcode() == ISD::SUB) {
6330 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6333 AM.BaseOffs = -Offset->getSExtValue();
6340 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6343 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6344 /// pre-indexed load / store when the base pointer is an add or subtract
6345 /// and it has other uses besides the load / store. After the
6346 /// transformation, the new indexed load / store has effectively folded
6347 /// the add / subtract in and all of its other uses are redirected to the
6348 /// new load / store.
6349 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6350 if (Level < AfterLegalizeDAG)
6356 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6357 if (LD->isIndexed())
6359 VT = LD->getMemoryVT();
6360 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6361 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6363 Ptr = LD->getBasePtr();
6364 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6365 if (ST->isIndexed())
6367 VT = ST->getMemoryVT();
6368 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6369 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6371 Ptr = ST->getBasePtr();
6377 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6378 // out. There is no reason to make this a preinc/predec.
6379 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6380 Ptr.getNode()->hasOneUse())
6383 // Ask the target to do addressing mode selection.
6386 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6387 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6389 // Don't create a indexed load / store with zero offset.
6390 if (isa<ConstantSDNode>(Offset) &&
6391 cast<ConstantSDNode>(Offset)->isNullValue())
6394 // Try turning it into a pre-indexed load / store except when:
6395 // 1) The new base ptr is a frame index.
6396 // 2) If N is a store and the new base ptr is either the same as or is a
6397 // predecessor of the value being stored.
6398 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6399 // that would create a cycle.
6400 // 4) All uses are load / store ops that use it as old base ptr.
6402 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6403 // (plus the implicit offset) to a register to preinc anyway.
6404 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6409 SDValue Val = cast<StoreSDNode>(N)->getValue();
6410 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6414 // Now check for #3 and #4.
6415 bool RealUse = false;
6417 // Caches for hasPredecessorHelper
6418 SmallPtrSet<const SDNode *, 32> Visited;
6419 SmallVector<const SDNode *, 16> Worklist;
6421 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6422 E = Ptr.getNode()->use_end(); I != E; ++I) {
6426 if (N->hasPredecessorHelper(Use, Visited, Worklist))
6429 // If Ptr may be folded in addressing mode of other use, then it's
6430 // not profitable to do this transformation.
6431 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
6440 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6441 BasePtr, Offset, AM);
6443 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6444 BasePtr, Offset, AM);
6447 DEBUG(dbgs() << "\nReplacing.4 ";
6449 dbgs() << "\nWith: ";
6450 Result.getNode()->dump(&DAG);
6452 WorkListRemover DeadNodes(*this);
6454 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6455 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6457 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6460 // Finally, since the node is now dead, remove it from the graph.
6463 // Replace the uses of Ptr with uses of the updated base value.
6464 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
6465 removeFromWorkList(Ptr.getNode());
6466 DAG.DeleteNode(Ptr.getNode());
6471 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
6472 /// add / sub of the base pointer node into a post-indexed load / store.
6473 /// The transformation folded the add / subtract into the new indexed
6474 /// load / store effectively and all of its uses are redirected to the
6475 /// new load / store.
6476 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6477 if (Level < AfterLegalizeDAG)
6483 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6484 if (LD->isIndexed())
6486 VT = LD->getMemoryVT();
6487 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6488 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6490 Ptr = LD->getBasePtr();
6491 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6492 if (ST->isIndexed())
6494 VT = ST->getMemoryVT();
6495 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6496 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6498 Ptr = ST->getBasePtr();
6504 if (Ptr.getNode()->hasOneUse())
6507 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6508 E = Ptr.getNode()->use_end(); I != E; ++I) {
6511 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6516 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6517 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6518 // Don't create a indexed load / store with zero offset.
6519 if (isa<ConstantSDNode>(Offset) &&
6520 cast<ConstantSDNode>(Offset)->isNullValue())
6523 // Try turning it into a post-indexed load / store except when
6524 // 1) All uses are load / store ops that use it as base ptr (and
6525 // it may be folded as addressing mmode).
6526 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6527 // nor a successor of N. Otherwise, if Op is folded that would
6530 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6534 bool TryNext = false;
6535 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6536 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6538 if (Use == Ptr.getNode())
6541 // If all the uses are load / store addresses, then don't do the
6543 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6544 bool RealUse = false;
6545 for (SDNode::use_iterator III = Use->use_begin(),
6546 EEE = Use->use_end(); III != EEE; ++III) {
6547 SDNode *UseUse = *III;
6548 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
6563 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6564 SDValue Result = isLoad
6565 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6566 BasePtr, Offset, AM)
6567 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6568 BasePtr, Offset, AM);
6571 DEBUG(dbgs() << "\nReplacing.5 ";
6573 dbgs() << "\nWith: ";
6574 Result.getNode()->dump(&DAG);
6576 WorkListRemover DeadNodes(*this);
6578 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6579 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6581 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6584 // Finally, since the node is now dead, remove it from the graph.
6587 // Replace the uses of Use with uses of the updated base value.
6588 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6589 Result.getValue(isLoad ? 1 : 0));
6590 removeFromWorkList(Op);
6600 SDValue DAGCombiner::visitLOAD(SDNode *N) {
6601 LoadSDNode *LD = cast<LoadSDNode>(N);
6602 SDValue Chain = LD->getChain();
6603 SDValue Ptr = LD->getBasePtr();
6605 // If load is not volatile and there are no uses of the loaded value (and
6606 // the updated indexed value in case of indexed loads), change uses of the
6607 // chain value into uses of the chain input (i.e. delete the dead load).
6608 if (!LD->isVolatile()) {
6609 if (N->getValueType(1) == MVT::Other) {
6611 if (!N->hasAnyUseOfValue(0)) {
6612 // It's not safe to use the two value CombineTo variant here. e.g.
6613 // v1, chain2 = load chain1, loc
6614 // v2, chain3 = load chain2, loc
6616 // Now we replace use of chain2 with chain1. This makes the second load
6617 // isomorphic to the one we are deleting, and thus makes this load live.
6618 DEBUG(dbgs() << "\nReplacing.6 ";
6620 dbgs() << "\nWith chain: ";
6621 Chain.getNode()->dump(&DAG);
6623 WorkListRemover DeadNodes(*this);
6624 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
6626 if (N->use_empty()) {
6627 removeFromWorkList(N);
6631 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6635 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
6636 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
6637 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
6638 DEBUG(dbgs() << "\nReplacing.7 ";
6640 dbgs() << "\nWith: ";
6641 Undef.getNode()->dump(&DAG);
6642 dbgs() << " and 2 other values\n");
6643 WorkListRemover DeadNodes(*this);
6644 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
6645 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
6646 DAG.getUNDEF(N->getValueType(1)));
6647 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
6648 removeFromWorkList(N);
6650 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6655 // If this load is directly stored, replace the load value with the stored
6657 // TODO: Handle store large -> read small portion.
6658 // TODO: Handle TRUNCSTORE/LOADEXT
6659 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
6660 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
6661 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
6662 if (PrevST->getBasePtr() == Ptr &&
6663 PrevST->getValue().getValueType() == N->getValueType(0))
6664 return CombineTo(N, Chain.getOperand(1), Chain);
6668 // Try to infer better alignment information than the load already has.
6669 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
6670 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6671 if (Align > LD->getAlignment())
6672 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
6673 LD->getValueType(0),
6674 Chain, Ptr, LD->getPointerInfo(),
6676 LD->isVolatile(), LD->isNonTemporal(), Align);
6681 // Walk up chain skipping non-aliasing memory nodes.
6682 SDValue BetterChain = FindBetterChain(N, Chain);
6684 // If there is a better chain.
6685 if (Chain != BetterChain) {
6688 // Replace the chain to void dependency.
6689 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
6690 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
6691 BetterChain, Ptr, LD->getPointerInfo(),
6692 LD->isVolatile(), LD->isNonTemporal(),
6693 LD->isInvariant(), LD->getAlignment());
6695 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
6696 LD->getValueType(0),
6697 BetterChain, Ptr, LD->getPointerInfo(),
6700 LD->isNonTemporal(),
6701 LD->getAlignment());
6704 // Create token factor to keep old chain connected.
6705 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6706 MVT::Other, Chain, ReplLoad.getValue(1));
6708 // Make sure the new and old chains are cleaned up.
6709 AddToWorkList(Token.getNode());
6711 // Replace uses with load result and token factor. Don't add users
6713 return CombineTo(N, ReplLoad.getValue(0), Token, false);
6717 // Try transforming N to an indexed load.
6718 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6719 return SDValue(N, 0);
6724 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
6725 /// load is having specific bytes cleared out. If so, return the byte size
6726 /// being masked out and the shift amount.
6727 static std::pair<unsigned, unsigned>
6728 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
6729 std::pair<unsigned, unsigned> Result(0, 0);
6731 // Check for the structure we're looking for.
6732 if (V->getOpcode() != ISD::AND ||
6733 !isa<ConstantSDNode>(V->getOperand(1)) ||
6734 !ISD::isNormalLoad(V->getOperand(0).getNode()))
6737 // Check the chain and pointer.
6738 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
6739 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
6741 // The store should be chained directly to the load or be an operand of a
6743 if (LD == Chain.getNode())
6745 else if (Chain->getOpcode() != ISD::TokenFactor)
6746 return Result; // Fail.
6749 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
6750 if (Chain->getOperand(i).getNode() == LD) {
6754 if (!isOk) return Result;
6757 // This only handles simple types.
6758 if (V.getValueType() != MVT::i16 &&
6759 V.getValueType() != MVT::i32 &&
6760 V.getValueType() != MVT::i64)
6763 // Check the constant mask. Invert it so that the bits being masked out are
6764 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
6765 // follow the sign bit for uniformity.
6766 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
6767 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
6768 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
6769 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
6770 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
6771 if (NotMaskLZ == 64) return Result; // All zero mask.
6773 // See if we have a continuous run of bits. If so, we have 0*1+0*
6774 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
6777 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
6778 if (V.getValueType() != MVT::i64 && NotMaskLZ)
6779 NotMaskLZ -= 64-V.getValueSizeInBits();
6781 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
6782 switch (MaskedBytes) {
6786 default: return Result; // All one mask, or 5-byte mask.
6789 // Verify that the first bit starts at a multiple of mask so that the access
6790 // is aligned the same as the access width.
6791 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6793 Result.first = MaskedBytes;
6794 Result.second = NotMaskTZ/8;
6799 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6800 /// provides a value as specified by MaskInfo. If so, replace the specified
6801 /// store with a narrower store of truncated IVal.
6803 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6804 SDValue IVal, StoreSDNode *St,
6806 unsigned NumBytes = MaskInfo.first;
6807 unsigned ByteShift = MaskInfo.second;
6808 SelectionDAG &DAG = DC->getDAG();
6810 // Check to see if IVal is all zeros in the part being masked in by the 'or'
6811 // that uses this. If not, this is not a replacement.
6812 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6813 ByteShift*8, (ByteShift+NumBytes)*8);
6814 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6816 // Check that it is legal on the target to do this. It is legal if the new
6817 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6819 MVT VT = MVT::getIntegerVT(NumBytes*8);
6820 if (!DC->isTypeLegal(VT))
6823 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
6824 // shifted by ByteShift and truncated down to NumBytes.
6826 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6827 DAG.getConstant(ByteShift*8,
6828 DC->getShiftAmountTy(IVal.getValueType())));
6830 // Figure out the offset for the store and the alignment of the access.
6832 unsigned NewAlign = St->getAlignment();
6834 if (DAG.getTargetLoweringInfo().isLittleEndian())
6835 StOffset = ByteShift;
6837 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6839 SDValue Ptr = St->getBasePtr();
6841 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6842 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6843 NewAlign = MinAlign(NewAlign, StOffset);
6846 // Truncate down to the new size.
6847 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6850 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6851 St->getPointerInfo().getWithOffset(StOffset),
6852 false, false, NewAlign).getNode();
6856 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6857 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6858 /// of the loaded bits, try narrowing the load and store if it would end up
6859 /// being a win for performance or code size.
6860 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6861 StoreSDNode *ST = cast<StoreSDNode>(N);
6862 if (ST->isVolatile())
6865 SDValue Chain = ST->getChain();
6866 SDValue Value = ST->getValue();
6867 SDValue Ptr = ST->getBasePtr();
6868 EVT VT = Value.getValueType();
6870 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6873 unsigned Opc = Value.getOpcode();
6875 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
6876 // is a byte mask indicating a consecutive number of bytes, check to see if
6877 // Y is known to provide just those bytes. If so, we try to replace the
6878 // load + replace + store sequence with a single (narrower) store, which makes
6880 if (Opc == ISD::OR) {
6881 std::pair<unsigned, unsigned> MaskedLoad;
6882 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
6883 if (MaskedLoad.first)
6884 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6885 Value.getOperand(1), ST,this))
6886 return SDValue(NewST, 0);
6888 // Or is commutative, so try swapping X and Y.
6889 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
6890 if (MaskedLoad.first)
6891 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6892 Value.getOperand(0), ST,this))
6893 return SDValue(NewST, 0);
6896 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6897 Value.getOperand(1).getOpcode() != ISD::Constant)
6900 SDValue N0 = Value.getOperand(0);
6901 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6902 Chain == SDValue(N0.getNode(), 1)) {
6903 LoadSDNode *LD = cast<LoadSDNode>(N0);
6904 if (LD->getBasePtr() != Ptr ||
6905 LD->getPointerInfo().getAddrSpace() !=
6906 ST->getPointerInfo().getAddrSpace())
6909 // Find the type to narrow it the load / op / store to.
6910 SDValue N1 = Value.getOperand(1);
6911 unsigned BitWidth = N1.getValueSizeInBits();
6912 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
6913 if (Opc == ISD::AND)
6914 Imm ^= APInt::getAllOnesValue(BitWidth);
6915 if (Imm == 0 || Imm.isAllOnesValue())
6917 unsigned ShAmt = Imm.countTrailingZeros();
6918 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
6919 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
6920 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6921 while (NewBW < BitWidth &&
6922 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6923 TLI.isNarrowingProfitable(VT, NewVT))) {
6924 NewBW = NextPowerOf2(NewBW);
6925 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6927 if (NewBW >= BitWidth)
6930 // If the lsb changed does not start at the type bitwidth boundary,
6931 // start at the previous one.
6933 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
6934 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
6935 if ((Imm & Mask) == Imm) {
6936 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
6937 if (Opc == ISD::AND)
6938 NewImm ^= APInt::getAllOnesValue(NewBW);
6939 uint64_t PtrOff = ShAmt / 8;
6940 // For big endian targets, we need to adjust the offset to the pointer to
6941 // load the correct bytes.
6942 if (TLI.isBigEndian())
6943 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
6945 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
6946 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
6947 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
6950 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6951 Ptr.getValueType(), Ptr,
6952 DAG.getConstant(PtrOff, Ptr.getValueType()));
6953 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6954 LD->getChain(), NewPtr,
6955 LD->getPointerInfo().getWithOffset(PtrOff),
6956 LD->isVolatile(), LD->isNonTemporal(),
6957 LD->isInvariant(), NewAlign);
6958 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6959 DAG.getConstant(NewImm, NewVT));
6960 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6962 ST->getPointerInfo().getWithOffset(PtrOff),
6963 false, false, NewAlign);
6965 AddToWorkList(NewPtr.getNode());
6966 AddToWorkList(NewLD.getNode());
6967 AddToWorkList(NewVal.getNode());
6968 WorkListRemover DeadNodes(*this);
6969 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
6978 /// TransformFPLoadStorePair - For a given floating point load / store pair,
6979 /// if the load value isn't used by any other operations, then consider
6980 /// transforming the pair to integer load / store operations if the target
6981 /// deems the transformation profitable.
6982 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
6983 StoreSDNode *ST = cast<StoreSDNode>(N);
6984 SDValue Chain = ST->getChain();
6985 SDValue Value = ST->getValue();
6986 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6987 Value.hasOneUse() &&
6988 Chain == SDValue(Value.getNode(), 1)) {
6989 LoadSDNode *LD = cast<LoadSDNode>(Value);
6990 EVT VT = LD->getMemoryVT();
6991 if (!VT.isFloatingPoint() ||
6992 VT != ST->getMemoryVT() ||
6993 LD->isNonTemporal() ||
6994 ST->isNonTemporal() ||
6995 LD->getPointerInfo().getAddrSpace() != 0 ||
6996 ST->getPointerInfo().getAddrSpace() != 0)
6999 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7000 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
7001 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
7002 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
7003 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
7006 unsigned LDAlign = LD->getAlignment();
7007 unsigned STAlign = ST->getAlignment();
7008 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
7009 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
7010 if (LDAlign < ABIAlign || STAlign < ABIAlign)
7013 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
7014 LD->getChain(), LD->getBasePtr(),
7015 LD->getPointerInfo(),
7016 false, false, false, LDAlign);
7018 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
7019 NewLD, ST->getBasePtr(),
7020 ST->getPointerInfo(),
7021 false, false, STAlign);
7023 AddToWorkList(NewLD.getNode());
7024 AddToWorkList(NewST.getNode());
7025 WorkListRemover DeadNodes(*this);
7026 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
7034 SDValue DAGCombiner::visitSTORE(SDNode *N) {
7035 StoreSDNode *ST = cast<StoreSDNode>(N);
7036 SDValue Chain = ST->getChain();
7037 SDValue Value = ST->getValue();
7038 SDValue Ptr = ST->getBasePtr();
7040 // If this is a store of a bit convert, store the input value if the
7041 // resultant store does not need a higher alignment than the original.
7042 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
7043 ST->isUnindexed()) {
7044 unsigned OrigAlign = ST->getAlignment();
7045 EVT SVT = Value.getOperand(0).getValueType();
7046 unsigned Align = TLI.getTargetData()->
7047 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
7048 if (Align <= OrigAlign &&
7049 ((!LegalOperations && !ST->isVolatile()) ||
7050 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
7051 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
7052 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7053 ST->isNonTemporal(), OrigAlign);
7056 // Turn 'store undef, Ptr' -> nothing.
7057 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
7060 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
7061 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
7062 // NOTE: If the original store is volatile, this transform must not increase
7063 // the number of stores. For example, on x86-32 an f64 can be stored in one
7064 // processor operation but an i64 (which is not legal) requires two. So the
7065 // transform should not be done in this case.
7066 if (Value.getOpcode() != ISD::TargetConstantFP) {
7068 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
7069 default: llvm_unreachable("Unknown FP type");
7070 case MVT::f80: // We don't do this for these yet.
7075 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
7076 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
7077 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
7078 bitcastToAPInt().getZExtValue(), MVT::i32);
7079 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
7080 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7081 ST->isNonTemporal(), ST->getAlignment());
7085 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
7086 !ST->isVolatile()) ||
7087 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
7088 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
7089 getZExtValue(), MVT::i64);
7090 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
7091 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7092 ST->isNonTemporal(), ST->getAlignment());
7095 if (!ST->isVolatile() &&
7096 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
7097 // Many FP stores are not made apparent until after legalize, e.g. for
7098 // argument passing. Since this is so common, custom legalize the
7099 // 64-bit integer store into two 32-bit stores.
7100 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
7101 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
7102 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
7103 if (TLI.isBigEndian()) std::swap(Lo, Hi);
7105 unsigned Alignment = ST->getAlignment();
7106 bool isVolatile = ST->isVolatile();
7107 bool isNonTemporal = ST->isNonTemporal();
7109 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
7110 Ptr, ST->getPointerInfo(),
7111 isVolatile, isNonTemporal,
7112 ST->getAlignment());
7113 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
7114 DAG.getConstant(4, Ptr.getValueType()));
7115 Alignment = MinAlign(Alignment, 4U);
7116 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
7117 Ptr, ST->getPointerInfo().getWithOffset(4),
7118 isVolatile, isNonTemporal,
7120 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7129 // Try to infer better alignment information than the store already has.
7130 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
7131 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7132 if (Align > ST->getAlignment())
7133 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
7134 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7135 ST->isVolatile(), ST->isNonTemporal(), Align);
7139 // Try transforming a pair floating point load / store ops to integer
7140 // load / store ops.
7141 SDValue NewST = TransformFPLoadStorePair(N);
7142 if (NewST.getNode())
7146 // Walk up chain skipping non-aliasing memory nodes.
7147 SDValue BetterChain = FindBetterChain(N, Chain);
7149 // If there is a better chain.
7150 if (Chain != BetterChain) {
7153 // Replace the chain to avoid dependency.
7154 if (ST->isTruncatingStore()) {
7155 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
7156 ST->getPointerInfo(),
7157 ST->getMemoryVT(), ST->isVolatile(),
7158 ST->isNonTemporal(), ST->getAlignment());
7160 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
7161 ST->getPointerInfo(),
7162 ST->isVolatile(), ST->isNonTemporal(),
7163 ST->getAlignment());
7166 // Create token to keep both nodes around.
7167 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7168 MVT::Other, Chain, ReplStore);
7170 // Make sure the new and old chains are cleaned up.
7171 AddToWorkList(Token.getNode());
7173 // Don't add users to work list.
7174 return CombineTo(N, Token, false);
7178 // Try transforming N to an indexed store.
7179 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7180 return SDValue(N, 0);
7182 // FIXME: is there such a thing as a truncating indexed store?
7183 if (ST->isTruncatingStore() && ST->isUnindexed() &&
7184 Value.getValueType().isInteger()) {
7185 // See if we can simplify the input to this truncstore with knowledge that
7186 // only the low bits are being used. For example:
7187 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
7189 GetDemandedBits(Value,
7190 APInt::getLowBitsSet(
7191 Value.getValueType().getScalarType().getSizeInBits(),
7192 ST->getMemoryVT().getScalarType().getSizeInBits()));
7193 AddToWorkList(Value.getNode());
7194 if (Shorter.getNode())
7195 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
7196 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7197 ST->isVolatile(), ST->isNonTemporal(),
7198 ST->getAlignment());
7200 // Otherwise, see if we can simplify the operation with
7201 // SimplifyDemandedBits, which only works if the value has a single use.
7202 if (SimplifyDemandedBits(Value,
7203 APInt::getLowBitsSet(
7204 Value.getValueType().getScalarType().getSizeInBits(),
7205 ST->getMemoryVT().getScalarType().getSizeInBits())))
7206 return SDValue(N, 0);
7209 // If this is a load followed by a store to the same location, then the store
7211 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
7212 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
7213 ST->isUnindexed() && !ST->isVolatile() &&
7214 // There can't be any side effects between the load and store, such as
7216 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
7217 // The store is dead, remove it.
7222 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
7223 // truncating store. We can do this even if this is already a truncstore.
7224 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
7225 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
7226 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
7227 ST->getMemoryVT())) {
7228 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
7229 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7230 ST->isVolatile(), ST->isNonTemporal(),
7231 ST->getAlignment());
7234 return ReduceLoadOpStoreWidth(N);
7237 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
7238 SDValue InVec = N->getOperand(0);
7239 SDValue InVal = N->getOperand(1);
7240 SDValue EltNo = N->getOperand(2);
7241 DebugLoc dl = N->getDebugLoc();
7243 // If the inserted element is an UNDEF, just use the input vector.
7244 if (InVal.getOpcode() == ISD::UNDEF)
7247 EVT VT = InVec.getValueType();
7249 // If we can't generate a legal BUILD_VECTOR, exit
7250 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
7253 // Check that we know which element is being inserted
7254 if (!isa<ConstantSDNode>(EltNo))
7256 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7258 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
7259 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
7261 SmallVector<SDValue, 8> Ops;
7262 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
7263 Ops.append(InVec.getNode()->op_begin(),
7264 InVec.getNode()->op_end());
7265 } else if (InVec.getOpcode() == ISD::UNDEF) {
7266 unsigned NElts = VT.getVectorNumElements();
7267 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
7272 // Insert the element
7273 if (Elt < Ops.size()) {
7274 // All the operands of BUILD_VECTOR must have the same type;
7275 // we enforce that here.
7276 EVT OpVT = Ops[0].getValueType();
7277 if (InVal.getValueType() != OpVT)
7278 InVal = OpVT.bitsGT(InVal.getValueType()) ?
7279 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
7280 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
7284 // Return the new vector
7285 return DAG.getNode(ISD::BUILD_VECTOR, dl,
7286 VT, &Ops[0], Ops.size());
7289 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
7290 // (vextract (scalar_to_vector val, 0) -> val
7291 SDValue InVec = N->getOperand(0);
7292 EVT VT = InVec.getValueType();
7293 EVT NVT = N->getValueType(0);
7295 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
7296 // Check if the result type doesn't match the inserted element type. A
7297 // SCALAR_TO_VECTOR may truncate the inserted element and the
7298 // EXTRACT_VECTOR_ELT may widen the extracted vector.
7299 SDValue InOp = InVec.getOperand(0);
7300 if (InOp.getValueType() != NVT) {
7301 assert(InOp.getValueType().isInteger() && NVT.isInteger());
7302 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
7307 SDValue EltNo = N->getOperand(1);
7308 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
7310 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
7311 // We only perform this optimization before the op legalization phase because
7312 // we may introduce new vector instructions which are not backed by TD patterns.
7313 // For example on AVX, extracting elements from a wide vector without using
7314 // extract_subvector.
7315 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
7316 && ConstEltNo && !LegalOperations) {
7317 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7318 int NumElem = VT.getVectorNumElements();
7319 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
7320 // Find the new index to extract from.
7321 int OrigElt = SVOp->getMaskElt(Elt);
7323 // Extracting an undef index is undef.
7325 return DAG.getUNDEF(NVT);
7327 // Select the right vector half to extract from.
7328 if (OrigElt < NumElem) {
7329 InVec = InVec->getOperand(0);
7331 InVec = InVec->getOperand(1);
7335 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
7336 InVec, DAG.getConstant(OrigElt, MVT::i32));
7339 // Perform only after legalization to ensure build_vector / vector_shuffle
7340 // optimizations have already been done.
7341 if (!LegalOperations) return SDValue();
7343 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
7344 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
7345 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
7348 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7349 bool NewLoad = false;
7350 bool BCNumEltsChanged = false;
7351 EVT ExtVT = VT.getVectorElementType();
7354 // If the result of load has to be truncated, then it's not necessarily
7356 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
7359 if (InVec.getOpcode() == ISD::BITCAST) {
7360 // Don't duplicate a load with other uses.
7361 if (!InVec.hasOneUse())
7364 EVT BCVT = InVec.getOperand(0).getValueType();
7365 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
7367 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
7368 BCNumEltsChanged = true;
7369 InVec = InVec.getOperand(0);
7370 ExtVT = BCVT.getVectorElementType();
7374 LoadSDNode *LN0 = NULL;
7375 const ShuffleVectorSDNode *SVN = NULL;
7376 if (ISD::isNormalLoad(InVec.getNode())) {
7377 LN0 = cast<LoadSDNode>(InVec);
7378 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7379 InVec.getOperand(0).getValueType() == ExtVT &&
7380 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
7381 // Don't duplicate a load with other uses.
7382 if (!InVec.hasOneUse())
7385 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
7386 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
7387 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
7389 // (load $addr+1*size)
7391 // Don't duplicate a load with other uses.
7392 if (!InVec.hasOneUse())
7395 // If the bit convert changed the number of elements, it is unsafe
7396 // to examine the mask.
7397 if (BCNumEltsChanged)
7400 // Select the input vector, guarding against out of range extract vector.
7401 unsigned NumElems = VT.getVectorNumElements();
7402 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
7403 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
7405 if (InVec.getOpcode() == ISD::BITCAST) {
7406 // Don't duplicate a load with other uses.
7407 if (!InVec.hasOneUse())
7410 InVec = InVec.getOperand(0);
7412 if (ISD::isNormalLoad(InVec.getNode())) {
7413 LN0 = cast<LoadSDNode>(InVec);
7414 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
7418 // Make sure we found a non-volatile load and the extractelement is
7420 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
7423 // If Idx was -1 above, Elt is going to be -1, so just return undef.
7425 return DAG.getUNDEF(LVT);
7427 unsigned Align = LN0->getAlignment();
7429 // Check the resultant load doesn't need a higher alignment than the
7433 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
7435 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
7441 SDValue NewPtr = LN0->getBasePtr();
7442 unsigned PtrOff = 0;
7445 PtrOff = LVT.getSizeInBits() * Elt / 8;
7446 EVT PtrType = NewPtr.getValueType();
7447 if (TLI.isBigEndian())
7448 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
7449 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
7450 DAG.getConstant(PtrOff, PtrType));
7453 // The replacement we need to do here is a little tricky: we need to
7454 // replace an extractelement of a load with a load.
7455 // Use ReplaceAllUsesOfValuesWith to do the replacement.
7456 // Note that this replacement assumes that the extractvalue is the only
7457 // use of the load; that's okay because we don't want to perform this
7458 // transformation in other cases anyway.
7461 if (NVT.bitsGT(LVT)) {
7462 // If the result type of vextract is wider than the load, then issue an
7463 // extending load instead.
7464 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
7465 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
7466 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(),
7467 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
7468 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align);
7469 Chain = Load.getValue(1);
7471 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
7472 LN0->getPointerInfo().getWithOffset(PtrOff),
7473 LN0->isVolatile(), LN0->isNonTemporal(),
7474 LN0->isInvariant(), Align);
7475 Chain = Load.getValue(1);
7476 if (NVT.bitsLT(LVT))
7477 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load);
7479 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load);
7481 WorkListRemover DeadNodes(*this);
7482 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
7483 SDValue To[] = { Load, Chain };
7484 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7485 // Since we're explcitly calling ReplaceAllUses, add the new node to the
7486 // worklist explicitly as well.
7487 AddToWorkList(Load.getNode());
7488 AddUsersToWorkList(Load.getNode()); // Add users too
7489 // Make sure to revisit this node to clean it up; it will usually be dead.
7491 return SDValue(N, 0);
7497 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
7498 unsigned NumInScalars = N->getNumOperands();
7499 DebugLoc dl = N->getDebugLoc();
7500 EVT VT = N->getValueType(0);
7501 // Check to see if this is a BUILD_VECTOR of a bunch of values
7502 // which come from any_extend or zero_extend nodes. If so, we can create
7503 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
7504 // optimizations. We do not handle sign-extend because we can't fill the sign
7506 EVT SourceType = MVT::Other;
7507 bool AllAnyExt = true;
7508 bool AllUndef = true;
7509 for (unsigned i = 0; i != NumInScalars; ++i) {
7510 SDValue In = N->getOperand(i);
7511 // Ignore undef inputs.
7512 if (In.getOpcode() == ISD::UNDEF) continue;
7515 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
7516 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
7518 // Abort if the element is not an extension.
7519 if (!ZeroExt && !AnyExt) {
7520 SourceType = MVT::Other;
7524 // The input is a ZeroExt or AnyExt. Check the original type.
7525 EVT InTy = In.getOperand(0).getValueType();
7527 // Check that all of the widened source types are the same.
7528 if (SourceType == MVT::Other)
7531 else if (InTy != SourceType) {
7532 // Multiple income types. Abort.
7533 SourceType = MVT::Other;
7537 // Check if all of the extends are ANY_EXTENDs.
7538 AllAnyExt &= AnyExt;
7542 return DAG.getUNDEF(VT);
7544 // In order to have valid types, all of the inputs must be extended from the
7545 // same source type and all of the inputs must be any or zero extend.
7546 // Scalar sizes must be a power of two.
7547 EVT OutScalarTy = N->getValueType(0).getScalarType();
7548 bool ValidTypes = SourceType != MVT::Other &&
7549 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
7550 isPowerOf2_32(SourceType.getSizeInBits());
7552 // We perform this optimization post type-legalization because
7553 // the type-legalizer often scalarizes integer-promoted vectors.
7554 // Performing this optimization before may create bit-casts which
7555 // will be type-legalized to complex code sequences.
7556 // We perform this optimization only before the operation legalizer because we
7557 // may introduce illegal operations.
7558 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
7559 // turn into a single shuffle instruction.
7560 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) &&
7562 bool isLE = TLI.isLittleEndian();
7563 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
7564 assert(ElemRatio > 1 && "Invalid element size ratio");
7565 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
7566 DAG.getConstant(0, SourceType);
7568 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements();
7569 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
7571 // Populate the new build_vector
7572 for (unsigned i=0; i < N->getNumOperands(); ++i) {
7573 SDValue Cast = N->getOperand(i);
7574 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
7575 Cast.getOpcode() == ISD::ZERO_EXTEND ||
7576 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
7578 if (Cast.getOpcode() == ISD::UNDEF)
7579 In = DAG.getUNDEF(SourceType);
7581 In = Cast->getOperand(0);
7582 unsigned Index = isLE ? (i * ElemRatio) :
7583 (i * ElemRatio + (ElemRatio - 1));
7585 assert(Index < Ops.size() && "Invalid index");
7589 // The type of the new BUILD_VECTOR node.
7590 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
7591 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() &&
7592 "Invalid vector size");
7593 // Check if the new vector type is legal.
7594 if (!isTypeLegal(VecVT)) return SDValue();
7596 // Make the new BUILD_VECTOR.
7597 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7598 VecVT, &Ops[0], Ops.size());
7600 // The new BUILD_VECTOR node has the potential to be further optimized.
7601 AddToWorkList(BV.getNode());
7602 // Bitcast to the desired type.
7603 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
7606 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
7607 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
7608 // at most two distinct vectors, turn this into a shuffle node.
7610 // May only combine to shuffle after legalize if shuffle is legal.
7611 if (LegalOperations &&
7612 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
7615 SDValue VecIn1, VecIn2;
7616 for (unsigned i = 0; i != NumInScalars; ++i) {
7617 // Ignore undef inputs.
7618 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
7620 // If this input is something other than a EXTRACT_VECTOR_ELT with a
7621 // constant index, bail out.
7622 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7623 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
7624 VecIn1 = VecIn2 = SDValue(0, 0);
7628 // We allow up to two distinct input vectors.
7629 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
7630 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
7633 if (VecIn1.getNode() == 0) {
7634 VecIn1 = ExtractedFromVec;
7635 } else if (VecIn2.getNode() == 0) {
7636 VecIn2 = ExtractedFromVec;
7639 VecIn1 = VecIn2 = SDValue(0, 0);
7644 // If everything is good, we can make a shuffle operation.
7645 if (VecIn1.getNode()) {
7646 SmallVector<int, 8> Mask;
7647 for (unsigned i = 0; i != NumInScalars; ++i) {
7648 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
7653 // If extracting from the first vector, just use the index directly.
7654 SDValue Extract = N->getOperand(i);
7655 SDValue ExtVal = Extract.getOperand(1);
7656 if (Extract.getOperand(0) == VecIn1) {
7657 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7658 if (ExtIndex > VT.getVectorNumElements())
7661 Mask.push_back(ExtIndex);
7665 // Otherwise, use InIdx + VecSize
7666 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7667 Mask.push_back(Idx+NumInScalars);
7670 // We can't generate a shuffle node with mismatched input and output types.
7671 // Attempt to transform a single input vector to the correct type.
7672 if ((VT != VecIn1.getValueType())) {
7673 // We don't support shuffeling between TWO values of different types.
7674 if (VecIn2.getNode() != 0)
7677 // We only support widening of vectors which are half the size of the
7678 // output registers. For example XMM->YMM widening on X86 with AVX.
7679 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
7682 // Widen the input vector by adding undef values.
7683 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
7684 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
7687 // If VecIn2 is unused then change it to undef.
7688 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
7690 // Check that we were able to transform all incoming values to the same type.
7691 if (VecIn2.getValueType() != VecIn1.getValueType() ||
7692 VecIn1.getValueType() != VT)
7695 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
7696 if (!isTypeLegal(VT))
7699 // Return the new VECTOR_SHUFFLE node.
7703 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
7709 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
7710 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
7711 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
7712 // inputs come from at most two distinct vectors, turn this into a shuffle
7715 // If we only have one input vector, we don't need to do any concatenation.
7716 if (N->getNumOperands() == 1)
7717 return N->getOperand(0);
7722 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
7723 EVT NVT = N->getValueType(0);
7724 SDValue V = N->getOperand(0);
7726 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
7727 // Handle only simple case where vector being inserted and vector
7728 // being extracted are of same type, and are half size of larger vectors.
7729 EVT BigVT = V->getOperand(0).getValueType();
7730 EVT SmallVT = V->getOperand(1).getValueType();
7731 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
7734 // Only handle cases where both indexes are constants with the same type.
7735 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
7736 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
7738 if (InsIdx && ExtIdx &&
7739 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
7740 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
7742 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
7744 // indices are equal => V1
7745 // otherwise => (extract_subvec V1, ExtIdx)
7746 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
7747 return V->getOperand(1);
7748 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
7749 V->getOperand(0), N->getOperand(1));
7756 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
7757 EVT VT = N->getValueType(0);
7758 unsigned NumElts = VT.getVectorNumElements();
7760 SDValue N0 = N->getOperand(0);
7761 SDValue N1 = N->getOperand(1);
7763 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
7765 // Canonicalize shuffle undef, undef -> undef
7766 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
7767 return DAG.getUNDEF(VT);
7769 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7771 // Canonicalize shuffle v, v -> v, undef
7773 SmallVector<int, 8> NewMask;
7774 for (unsigned i = 0; i != NumElts; ++i) {
7775 int Idx = SVN->getMaskElt(i);
7776 if (Idx >= (int)NumElts) Idx -= NumElts;
7777 NewMask.push_back(Idx);
7779 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
7783 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
7784 if (N0.getOpcode() == ISD::UNDEF) {
7785 SmallVector<int, 8> NewMask;
7786 for (unsigned i = 0; i != NumElts; ++i) {
7787 int Idx = SVN->getMaskElt(i);
7789 if (Idx < (int)NumElts)
7794 NewMask.push_back(Idx);
7796 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
7800 // Remove references to rhs if it is undef
7801 if (N1.getOpcode() == ISD::UNDEF) {
7802 bool Changed = false;
7803 SmallVector<int, 8> NewMask;
7804 for (unsigned i = 0; i != NumElts; ++i) {
7805 int Idx = SVN->getMaskElt(i);
7806 if (Idx >= (int)NumElts) {
7810 NewMask.push_back(Idx);
7813 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
7816 // If it is a splat, check if the argument vector is another splat or a
7817 // build_vector with all scalar elements the same.
7818 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
7819 SDNode *V = N0.getNode();
7821 // If this is a bit convert that changes the element type of the vector but
7822 // not the number of vector elements, look through it. Be careful not to
7823 // look though conversions that change things like v4f32 to v2f64.
7824 if (V->getOpcode() == ISD::BITCAST) {
7825 SDValue ConvInput = V->getOperand(0);
7826 if (ConvInput.getValueType().isVector() &&
7827 ConvInput.getValueType().getVectorNumElements() == NumElts)
7828 V = ConvInput.getNode();
7831 if (V->getOpcode() == ISD::BUILD_VECTOR) {
7832 assert(V->getNumOperands() == NumElts &&
7833 "BUILD_VECTOR has wrong number of operands");
7835 bool AllSame = true;
7836 for (unsigned i = 0; i != NumElts; ++i) {
7837 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
7838 Base = V->getOperand(i);
7842 // Splat of <u, u, u, u>, return <u, u, u, u>
7843 if (!Base.getNode())
7845 for (unsigned i = 0; i != NumElts; ++i) {
7846 if (V->getOperand(i) != Base) {
7851 // Splat of <x, x, x, x>, return <x, x, x, x>
7857 // If this shuffle node is simply a swizzle of another shuffle node,
7858 // and it reverses the swizzle of the previous shuffle then we can
7859 // optimize shuffle(shuffle(x, undef), undef) -> x.
7860 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
7861 N1.getOpcode() == ISD::UNDEF) {
7863 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
7865 // Shuffle nodes can only reverse shuffles with a single non-undef value.
7866 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
7869 // The incoming shuffle must be of the same type as the result of the
7871 assert(OtherSV->getOperand(0).getValueType() == VT &&
7872 "Shuffle types don't match");
7874 for (unsigned i = 0; i != NumElts; ++i) {
7875 int Idx = SVN->getMaskElt(i);
7876 assert(Idx < (int)NumElts && "Index references undef operand");
7877 // Next, this index comes from the first value, which is the incoming
7878 // shuffle. Adopt the incoming index.
7880 Idx = OtherSV->getMaskElt(Idx);
7882 // The combined shuffle must map each index to itself.
7883 if (Idx >= 0 && (unsigned)Idx != i)
7887 return OtherSV->getOperand(0);
7893 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
7894 if (!TLI.getShouldFoldAtomicFences())
7897 SDValue atomic = N->getOperand(0);
7898 switch (atomic.getOpcode()) {
7899 case ISD::ATOMIC_CMP_SWAP:
7900 case ISD::ATOMIC_SWAP:
7901 case ISD::ATOMIC_LOAD_ADD:
7902 case ISD::ATOMIC_LOAD_SUB:
7903 case ISD::ATOMIC_LOAD_AND:
7904 case ISD::ATOMIC_LOAD_OR:
7905 case ISD::ATOMIC_LOAD_XOR:
7906 case ISD::ATOMIC_LOAD_NAND:
7907 case ISD::ATOMIC_LOAD_MIN:
7908 case ISD::ATOMIC_LOAD_MAX:
7909 case ISD::ATOMIC_LOAD_UMIN:
7910 case ISD::ATOMIC_LOAD_UMAX:
7916 SDValue fence = atomic.getOperand(0);
7917 if (fence.getOpcode() != ISD::MEMBARRIER)
7920 switch (atomic.getOpcode()) {
7921 case ISD::ATOMIC_CMP_SWAP:
7922 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7923 fence.getOperand(0),
7924 atomic.getOperand(1), atomic.getOperand(2),
7925 atomic.getOperand(3)), atomic.getResNo());
7926 case ISD::ATOMIC_SWAP:
7927 case ISD::ATOMIC_LOAD_ADD:
7928 case ISD::ATOMIC_LOAD_SUB:
7929 case ISD::ATOMIC_LOAD_AND:
7930 case ISD::ATOMIC_LOAD_OR:
7931 case ISD::ATOMIC_LOAD_XOR:
7932 case ISD::ATOMIC_LOAD_NAND:
7933 case ISD::ATOMIC_LOAD_MIN:
7934 case ISD::ATOMIC_LOAD_MAX:
7935 case ISD::ATOMIC_LOAD_UMIN:
7936 case ISD::ATOMIC_LOAD_UMAX:
7937 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7938 fence.getOperand(0),
7939 atomic.getOperand(1), atomic.getOperand(2)),
7946 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
7947 /// an AND to a vector_shuffle with the destination vector and a zero vector.
7948 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
7949 /// vector_shuffle V, Zero, <0, 4, 2, 4>
7950 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
7951 EVT VT = N->getValueType(0);
7952 DebugLoc dl = N->getDebugLoc();
7953 SDValue LHS = N->getOperand(0);
7954 SDValue RHS = N->getOperand(1);
7955 if (N->getOpcode() == ISD::AND) {
7956 if (RHS.getOpcode() == ISD::BITCAST)
7957 RHS = RHS.getOperand(0);
7958 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
7959 SmallVector<int, 8> Indices;
7960 unsigned NumElts = RHS.getNumOperands();
7961 for (unsigned i = 0; i != NumElts; ++i) {
7962 SDValue Elt = RHS.getOperand(i);
7963 if (!isa<ConstantSDNode>(Elt))
7966 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
7967 Indices.push_back(i);
7968 else if (cast<ConstantSDNode>(Elt)->isNullValue())
7969 Indices.push_back(NumElts);
7974 // Let's see if the target supports this vector_shuffle.
7975 EVT RVT = RHS.getValueType();
7976 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
7979 // Return the new VECTOR_SHUFFLE node.
7980 EVT EltVT = RVT.getVectorElementType();
7981 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
7982 DAG.getConstant(0, EltVT));
7983 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7984 RVT, &ZeroOps[0], ZeroOps.size());
7985 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
7986 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
7987 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
7994 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
7995 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
7996 // After legalize, the target may be depending on adds and other
7997 // binary ops to provide legal ways to construct constants or other
7998 // things. Simplifying them may result in a loss of legality.
7999 if (LegalOperations) return SDValue();
8001 assert(N->getValueType(0).isVector() &&
8002 "SimplifyVBinOp only works on vectors!");
8004 SDValue LHS = N->getOperand(0);
8005 SDValue RHS = N->getOperand(1);
8006 SDValue Shuffle = XformToShuffleWithZero(N);
8007 if (Shuffle.getNode()) return Shuffle;
8009 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
8011 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
8012 RHS.getOpcode() == ISD::BUILD_VECTOR) {
8013 SmallVector<SDValue, 8> Ops;
8014 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
8015 SDValue LHSOp = LHS.getOperand(i);
8016 SDValue RHSOp = RHS.getOperand(i);
8017 // If these two elements can't be folded, bail out.
8018 if ((LHSOp.getOpcode() != ISD::UNDEF &&
8019 LHSOp.getOpcode() != ISD::Constant &&
8020 LHSOp.getOpcode() != ISD::ConstantFP) ||
8021 (RHSOp.getOpcode() != ISD::UNDEF &&
8022 RHSOp.getOpcode() != ISD::Constant &&
8023 RHSOp.getOpcode() != ISD::ConstantFP))
8026 // Can't fold divide by zero.
8027 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
8028 N->getOpcode() == ISD::FDIV) {
8029 if ((RHSOp.getOpcode() == ISD::Constant &&
8030 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
8031 (RHSOp.getOpcode() == ISD::ConstantFP &&
8032 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
8036 EVT VT = LHSOp.getValueType();
8037 EVT RVT = RHSOp.getValueType();
8039 // Integer BUILD_VECTOR operands may have types larger than the element
8040 // size (e.g., when the element type is not legal). Prior to type
8041 // legalization, the types may not match between the two BUILD_VECTORS.
8042 // Truncate one of the operands to make them match.
8043 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
8044 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
8046 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
8050 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
8052 if (FoldOp.getOpcode() != ISD::UNDEF &&
8053 FoldOp.getOpcode() != ISD::Constant &&
8054 FoldOp.getOpcode() != ISD::ConstantFP)
8056 Ops.push_back(FoldOp);
8057 AddToWorkList(FoldOp.getNode());
8060 if (Ops.size() == LHS.getNumOperands())
8061 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8062 LHS.getValueType(), &Ops[0], Ops.size());
8068 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
8069 SDValue N1, SDValue N2){
8070 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
8072 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
8073 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8075 // If we got a simplified select_cc node back from SimplifySelectCC, then
8076 // break it down into a new SETCC node, and a new SELECT node, and then return
8077 // the SELECT node, since we were called with a SELECT node.
8078 if (SCC.getNode()) {
8079 // Check to see if we got a select_cc back (to turn into setcc/select).
8080 // Otherwise, just return whatever node we got back, like fabs.
8081 if (SCC.getOpcode() == ISD::SELECT_CC) {
8082 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
8084 SCC.getOperand(0), SCC.getOperand(1),
8086 AddToWorkList(SETCC.getNode());
8087 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
8088 SCC.getOperand(2), SCC.getOperand(3), SETCC);
8096 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
8097 /// are the two values being selected between, see if we can simplify the
8098 /// select. Callers of this should assume that TheSelect is deleted if this
8099 /// returns true. As such, they should return the appropriate thing (e.g. the
8100 /// node) back to the top-level of the DAG combiner loop to avoid it being
8102 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
8105 // Cannot simplify select with vector condition
8106 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
8108 // If this is a select from two identical things, try to pull the operation
8109 // through the select.
8110 if (LHS.getOpcode() != RHS.getOpcode() ||
8111 !LHS.hasOneUse() || !RHS.hasOneUse())
8114 // If this is a load and the token chain is identical, replace the select
8115 // of two loads with a load through a select of the address to load from.
8116 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
8117 // constants have been dropped into the constant pool.
8118 if (LHS.getOpcode() == ISD::LOAD) {
8119 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
8120 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
8122 // Token chains must be identical.
8123 if (LHS.getOperand(0) != RHS.getOperand(0) ||
8124 // Do not let this transformation reduce the number of volatile loads.
8125 LLD->isVolatile() || RLD->isVolatile() ||
8126 // If this is an EXTLOAD, the VT's must match.
8127 LLD->getMemoryVT() != RLD->getMemoryVT() ||
8128 // If this is an EXTLOAD, the kind of extension must match.
8129 (LLD->getExtensionType() != RLD->getExtensionType() &&
8130 // The only exception is if one of the extensions is anyext.
8131 LLD->getExtensionType() != ISD::EXTLOAD &&
8132 RLD->getExtensionType() != ISD::EXTLOAD) ||
8133 // FIXME: this discards src value information. This is
8134 // over-conservative. It would be beneficial to be able to remember
8135 // both potential memory locations. Since we are discarding
8136 // src value info, don't do the transformation if the memory
8137 // locations are not in the default address space.
8138 LLD->getPointerInfo().getAddrSpace() != 0 ||
8139 RLD->getPointerInfo().getAddrSpace() != 0)
8142 // Check that the select condition doesn't reach either load. If so,
8143 // folding this will induce a cycle into the DAG. If not, this is safe to
8144 // xform, so create a select of the addresses.
8146 if (TheSelect->getOpcode() == ISD::SELECT) {
8147 SDNode *CondNode = TheSelect->getOperand(0).getNode();
8148 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
8149 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
8151 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
8152 LLD->getBasePtr().getValueType(),
8153 TheSelect->getOperand(0), LLD->getBasePtr(),
8155 } else { // Otherwise SELECT_CC
8156 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
8157 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
8159 if ((LLD->hasAnyUseOfValue(1) &&
8160 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
8161 (RLD->hasAnyUseOfValue(1) &&
8162 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
8165 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
8166 LLD->getBasePtr().getValueType(),
8167 TheSelect->getOperand(0),
8168 TheSelect->getOperand(1),
8169 LLD->getBasePtr(), RLD->getBasePtr(),
8170 TheSelect->getOperand(4));
8174 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
8175 Load = DAG.getLoad(TheSelect->getValueType(0),
8176 TheSelect->getDebugLoc(),
8177 // FIXME: Discards pointer info.
8178 LLD->getChain(), Addr, MachinePointerInfo(),
8179 LLD->isVolatile(), LLD->isNonTemporal(),
8180 LLD->isInvariant(), LLD->getAlignment());
8182 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
8183 RLD->getExtensionType() : LLD->getExtensionType(),
8184 TheSelect->getDebugLoc(),
8185 TheSelect->getValueType(0),
8186 // FIXME: Discards pointer info.
8187 LLD->getChain(), Addr, MachinePointerInfo(),
8188 LLD->getMemoryVT(), LLD->isVolatile(),
8189 LLD->isNonTemporal(), LLD->getAlignment());
8192 // Users of the select now use the result of the load.
8193 CombineTo(TheSelect, Load);
8195 // Users of the old loads now use the new load's chain. We know the
8196 // old-load value is dead now.
8197 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
8198 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
8205 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
8206 /// where 'cond' is the comparison specified by CC.
8207 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
8208 SDValue N2, SDValue N3,
8209 ISD::CondCode CC, bool NotExtCompare) {
8210 // (x ? y : y) -> y.
8211 if (N2 == N3) return N2;
8213 EVT VT = N2.getValueType();
8214 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
8215 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
8216 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
8218 // Determine if the condition we're dealing with is constant
8219 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
8220 N0, N1, CC, DL, false);
8221 if (SCC.getNode()) AddToWorkList(SCC.getNode());
8222 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
8224 // fold select_cc true, x, y -> x
8225 if (SCCC && !SCCC->isNullValue())
8227 // fold select_cc false, x, y -> y
8228 if (SCCC && SCCC->isNullValue())
8231 // Check to see if we can simplify the select into an fabs node
8232 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
8233 // Allow either -0.0 or 0.0
8234 if (CFP->getValueAPF().isZero()) {
8235 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
8236 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
8237 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
8238 N2 == N3.getOperand(0))
8239 return DAG.getNode(ISD::FABS, DL, VT, N0);
8241 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
8242 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
8243 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
8244 N2.getOperand(0) == N3)
8245 return DAG.getNode(ISD::FABS, DL, VT, N3);
8249 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
8250 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
8251 // in it. This is a win when the constant is not otherwise available because
8252 // it replaces two constant pool loads with one. We only do this if the FP
8253 // type is known to be legal, because if it isn't, then we are before legalize
8254 // types an we want the other legalization to happen first (e.g. to avoid
8255 // messing with soft float) and if the ConstantFP is not legal, because if
8256 // it is legal, we may not need to store the FP constant in a constant pool.
8257 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
8258 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
8259 if (TLI.isTypeLegal(N2.getValueType()) &&
8260 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
8261 TargetLowering::Legal) &&
8262 // If both constants have multiple uses, then we won't need to do an
8263 // extra load, they are likely around in registers for other users.
8264 (TV->hasOneUse() || FV->hasOneUse())) {
8265 Constant *Elts[] = {
8266 const_cast<ConstantFP*>(FV->getConstantFPValue()),
8267 const_cast<ConstantFP*>(TV->getConstantFPValue())
8269 Type *FPTy = Elts[0]->getType();
8270 const TargetData &TD = *TLI.getTargetData();
8272 // Create a ConstantArray of the two constants.
8273 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
8274 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
8275 TD.getPrefTypeAlignment(FPTy));
8276 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8278 // Get the offsets to the 0 and 1 element of the array so that we can
8279 // select between them.
8280 SDValue Zero = DAG.getIntPtrConstant(0);
8281 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
8282 SDValue One = DAG.getIntPtrConstant(EltSize);
8284 SDValue Cond = DAG.getSetCC(DL,
8285 TLI.getSetCCResultType(N0.getValueType()),
8287 AddToWorkList(Cond.getNode());
8288 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
8290 AddToWorkList(CstOffset.getNode());
8291 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
8293 AddToWorkList(CPIdx.getNode());
8294 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
8295 MachinePointerInfo::getConstantPool(), false,
8296 false, false, Alignment);
8301 // Check to see if we can perform the "gzip trick", transforming
8302 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
8303 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
8304 (N1C->isNullValue() || // (a < 0) ? b : 0
8305 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
8306 EVT XType = N0.getValueType();
8307 EVT AType = N2.getValueType();
8308 if (XType.bitsGE(AType)) {
8309 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
8310 // single-bit constant.
8311 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
8312 unsigned ShCtV = N2C->getAPIntValue().logBase2();
8313 ShCtV = XType.getSizeInBits()-ShCtV-1;
8314 SDValue ShCt = DAG.getConstant(ShCtV,
8315 getShiftAmountTy(N0.getValueType()));
8316 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
8318 AddToWorkList(Shift.getNode());
8320 if (XType.bitsGT(AType)) {
8321 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8322 AddToWorkList(Shift.getNode());
8325 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8328 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
8330 DAG.getConstant(XType.getSizeInBits()-1,
8331 getShiftAmountTy(N0.getValueType())));
8332 AddToWorkList(Shift.getNode());
8334 if (XType.bitsGT(AType)) {
8335 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8336 AddToWorkList(Shift.getNode());
8339 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8343 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
8344 // where y is has a single bit set.
8345 // A plaintext description would be, we can turn the SELECT_CC into an AND
8346 // when the condition can be materialized as an all-ones register. Any
8347 // single bit-test can be materialized as an all-ones register with
8348 // shift-left and shift-right-arith.
8349 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
8350 N0->getValueType(0) == VT &&
8351 N1C && N1C->isNullValue() &&
8352 N2C && N2C->isNullValue()) {
8353 SDValue AndLHS = N0->getOperand(0);
8354 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
8355 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
8356 // Shift the tested bit over the sign bit.
8357 APInt AndMask = ConstAndRHS->getAPIntValue();
8359 DAG.getConstant(AndMask.countLeadingZeros(),
8360 getShiftAmountTy(AndLHS.getValueType()));
8361 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
8363 // Now arithmetic right shift it all the way over, so the result is either
8364 // all-ones, or zero.
8366 DAG.getConstant(AndMask.getBitWidth()-1,
8367 getShiftAmountTy(Shl.getValueType()));
8368 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
8370 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
8374 // fold select C, 16, 0 -> shl C, 4
8375 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
8376 TLI.getBooleanContents(N0.getValueType().isVector()) ==
8377 TargetLowering::ZeroOrOneBooleanContent) {
8379 // If the caller doesn't want us to simplify this into a zext of a compare,
8381 if (NotExtCompare && N2C->getAPIntValue() == 1)
8384 // Get a SetCC of the condition
8385 // FIXME: Should probably make sure that setcc is legal if we ever have a
8386 // target where it isn't.
8388 // cast from setcc result type to select result type
8390 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
8392 if (N2.getValueType().bitsLT(SCC.getValueType()))
8393 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
8395 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8396 N2.getValueType(), SCC);
8398 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
8399 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8400 N2.getValueType(), SCC);
8403 AddToWorkList(SCC.getNode());
8404 AddToWorkList(Temp.getNode());
8406 if (N2C->getAPIntValue() == 1)
8409 // shl setcc result by log2 n2c
8410 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
8411 DAG.getConstant(N2C->getAPIntValue().logBase2(),
8412 getShiftAmountTy(Temp.getValueType())));
8415 // Check to see if this is the equivalent of setcc
8416 // FIXME: Turn all of these into setcc if setcc if setcc is legal
8417 // otherwise, go ahead with the folds.
8418 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
8419 EVT XType = N0.getValueType();
8420 if (!LegalOperations ||
8421 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
8422 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
8423 if (Res.getValueType() != VT)
8424 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
8428 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
8429 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
8430 (!LegalOperations ||
8431 TLI.isOperationLegal(ISD::CTLZ, XType))) {
8432 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
8433 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
8434 DAG.getConstant(Log2_32(XType.getSizeInBits()),
8435 getShiftAmountTy(Ctlz.getValueType())));
8437 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
8438 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
8439 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
8440 XType, DAG.getConstant(0, XType), N0);
8441 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
8442 return DAG.getNode(ISD::SRL, DL, XType,
8443 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
8444 DAG.getConstant(XType.getSizeInBits()-1,
8445 getShiftAmountTy(XType)));
8447 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
8448 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
8449 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
8450 DAG.getConstant(XType.getSizeInBits()-1,
8451 getShiftAmountTy(N0.getValueType())));
8452 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
8456 // Check to see if this is an integer abs.
8457 // select_cc setg[te] X, 0, X, -X ->
8458 // select_cc setgt X, -1, X, -X ->
8459 // select_cc setl[te] X, 0, -X, X ->
8460 // select_cc setlt X, 1, -X, X ->
8461 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
8463 ConstantSDNode *SubC = NULL;
8464 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
8465 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
8466 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
8467 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
8468 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
8469 (N1C->isOne() && CC == ISD::SETLT)) &&
8470 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
8471 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
8473 EVT XType = N0.getValueType();
8474 if (SubC && SubC->isNullValue() && XType.isInteger()) {
8475 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
8477 DAG.getConstant(XType.getSizeInBits()-1,
8478 getShiftAmountTy(N0.getValueType())));
8479 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
8481 AddToWorkList(Shift.getNode());
8482 AddToWorkList(Add.getNode());
8483 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
8490 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
8491 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
8492 SDValue N1, ISD::CondCode Cond,
8493 DebugLoc DL, bool foldBooleans) {
8494 TargetLowering::DAGCombinerInfo
8495 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
8496 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
8499 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
8500 /// return a DAG expression to select that will generate the same value by
8501 /// multiplying by a magic number. See:
8502 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8503 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
8504 std::vector<SDNode*> Built;
8505 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
8507 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8513 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
8514 /// return a DAG expression to select that will generate the same value by
8515 /// multiplying by a magic number. See:
8516 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8517 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
8518 std::vector<SDNode*> Built;
8519 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
8521 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8527 /// FindBaseOffset - Return true if base is a frame index, which is known not
8528 // to alias with anything but itself. Provides base object and offset as
8530 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
8531 const GlobalValue *&GV, void *&CV) {
8532 // Assume it is a primitive operation.
8533 Base = Ptr; Offset = 0; GV = 0; CV = 0;
8535 // If it's an adding a simple constant then integrate the offset.
8536 if (Base.getOpcode() == ISD::ADD) {
8537 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
8538 Base = Base.getOperand(0);
8539 Offset += C->getZExtValue();
8543 // Return the underlying GlobalValue, and update the Offset. Return false
8544 // for GlobalAddressSDNode since the same GlobalAddress may be represented
8545 // by multiple nodes with different offsets.
8546 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
8547 GV = G->getGlobal();
8548 Offset += G->getOffset();
8552 // Return the underlying Constant value, and update the Offset. Return false
8553 // for ConstantSDNodes since the same constant pool entry may be represented
8554 // by multiple nodes with different offsets.
8555 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
8556 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
8557 : (void *)C->getConstVal();
8558 Offset += C->getOffset();
8561 // If it's any of the following then it can't alias with anything but itself.
8562 return isa<FrameIndexSDNode>(Base);
8565 /// isAlias - Return true if there is any possibility that the two addresses
8567 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
8568 const Value *SrcValue1, int SrcValueOffset1,
8569 unsigned SrcValueAlign1,
8570 const MDNode *TBAAInfo1,
8571 SDValue Ptr2, int64_t Size2,
8572 const Value *SrcValue2, int SrcValueOffset2,
8573 unsigned SrcValueAlign2,
8574 const MDNode *TBAAInfo2) const {
8575 // If they are the same then they must be aliases.
8576 if (Ptr1 == Ptr2) return true;
8578 // Gather base node and offset information.
8579 SDValue Base1, Base2;
8580 int64_t Offset1, Offset2;
8581 const GlobalValue *GV1, *GV2;
8583 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
8584 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
8586 // If they have a same base address then check to see if they overlap.
8587 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
8588 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
8590 // It is possible for different frame indices to alias each other, mostly
8591 // when tail call optimization reuses return address slots for arguments.
8592 // To catch this case, look up the actual index of frame indices to compute
8593 // the real alias relationship.
8594 if (isFrameIndex1 && isFrameIndex2) {
8595 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8596 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
8597 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
8598 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
8601 // Otherwise, if we know what the bases are, and they aren't identical, then
8602 // we know they cannot alias.
8603 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
8606 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
8607 // compared to the size and offset of the access, we may be able to prove they
8608 // do not alias. This check is conservative for now to catch cases created by
8609 // splitting vector types.
8610 if ((SrcValueAlign1 == SrcValueAlign2) &&
8611 (SrcValueOffset1 != SrcValueOffset2) &&
8612 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
8613 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
8614 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
8616 // There is no overlap between these relatively aligned accesses of similar
8617 // size, return no alias.
8618 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
8622 if (CombinerGlobalAA) {
8623 // Use alias analysis information.
8624 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
8625 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
8626 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
8627 AliasAnalysis::AliasResult AAResult =
8628 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
8629 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
8630 if (AAResult == AliasAnalysis::NoAlias)
8634 // Otherwise we have to assume they alias.
8638 /// FindAliasInfo - Extracts the relevant alias information from the memory
8639 /// node. Returns true if the operand was a load.
8640 bool DAGCombiner::FindAliasInfo(SDNode *N,
8641 SDValue &Ptr, int64_t &Size,
8642 const Value *&SrcValue,
8643 int &SrcValueOffset,
8644 unsigned &SrcValueAlign,
8645 const MDNode *&TBAAInfo) const {
8646 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
8648 Ptr = LS->getBasePtr();
8649 Size = LS->getMemoryVT().getSizeInBits() >> 3;
8650 SrcValue = LS->getSrcValue();
8651 SrcValueOffset = LS->getSrcValueOffset();
8652 SrcValueAlign = LS->getOriginalAlignment();
8653 TBAAInfo = LS->getTBAAInfo();
8654 return isa<LoadSDNode>(LS);
8657 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
8658 /// looking for aliasing nodes and adding them to the Aliases vector.
8659 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
8660 SmallVector<SDValue, 8> &Aliases) {
8661 SmallVector<SDValue, 8> Chains; // List of chains to visit.
8662 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
8664 // Get alias information for node.
8667 const Value *SrcValue;
8669 unsigned SrcValueAlign;
8670 const MDNode *SrcTBAAInfo;
8671 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
8672 SrcValueAlign, SrcTBAAInfo);
8675 Chains.push_back(OriginalChain);
8678 // Look at each chain and determine if it is an alias. If so, add it to the
8679 // aliases list. If not, then continue up the chain looking for the next
8681 while (!Chains.empty()) {
8682 SDValue Chain = Chains.back();
8685 // For TokenFactor nodes, look at each operand and only continue up the
8686 // chain until we find two aliases. If we've seen two aliases, assume we'll
8687 // find more and revert to original chain since the xform is unlikely to be
8690 // FIXME: The depth check could be made to return the last non-aliasing
8691 // chain we found before we hit a tokenfactor rather than the original
8693 if (Depth > 6 || Aliases.size() == 2) {
8695 Aliases.push_back(OriginalChain);
8699 // Don't bother if we've been before.
8700 if (!Visited.insert(Chain.getNode()))
8703 switch (Chain.getOpcode()) {
8704 case ISD::EntryToken:
8705 // Entry token is ideal chain operand, but handled in FindBetterChain.
8710 // Get alias information for Chain.
8713 const Value *OpSrcValue;
8714 int OpSrcValueOffset;
8715 unsigned OpSrcValueAlign;
8716 const MDNode *OpSrcTBAAInfo;
8717 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
8718 OpSrcValue, OpSrcValueOffset,
8722 // If chain is alias then stop here.
8723 if (!(IsLoad && IsOpLoad) &&
8724 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
8726 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
8727 OpSrcValueAlign, OpSrcTBAAInfo)) {
8728 Aliases.push_back(Chain);
8730 // Look further up the chain.
8731 Chains.push_back(Chain.getOperand(0));
8737 case ISD::TokenFactor:
8738 // We have to check each of the operands of the token factor for "small"
8739 // token factors, so we queue them up. Adding the operands to the queue
8740 // (stack) in reverse order maintains the original order and increases the
8741 // likelihood that getNode will find a matching token factor (CSE.)
8742 if (Chain.getNumOperands() > 16) {
8743 Aliases.push_back(Chain);
8746 for (unsigned n = Chain.getNumOperands(); n;)
8747 Chains.push_back(Chain.getOperand(--n));
8752 // For all other instructions we will just have to take what we can get.
8753 Aliases.push_back(Chain);
8759 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
8760 /// for a better chain (aliasing node.)
8761 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
8762 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
8764 // Accumulate all the aliases to this node.
8765 GatherAllAliases(N, OldChain, Aliases);
8767 // If no operands then chain to entry token.
8768 if (Aliases.size() == 0)
8769 return DAG.getEntryNode();
8771 // If a single operand then chain to it. We don't need to revisit it.
8772 if (Aliases.size() == 1)
8775 // Construct a custom tailored token factor.
8776 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8777 &Aliases[0], Aliases.size());
8780 // SelectionDAG::Combine - This is the entry point for the file.
8782 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
8783 CodeGenOpt::Level OptLevel) {
8784 /// run - This is the main entry point to this class.
8786 DAGCombiner(*this, AA, OptLevel).Run(Level);