1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef SCHEDULEDAGINSTRS_H
16 #define SCHEDULEDAGINSTRS_H
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineLoopInfo.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/SparseSet.h"
28 class MachineLoopInfo;
29 class MachineDominatorTree;
32 /// LoopDependencies - This class analyzes loop-oriented register
33 /// dependencies, which are used to guide scheduling decisions.
34 /// For example, loop induction variable increments should be
35 /// scheduled as soon as possible after the variable's last use.
37 class LLVM_LIBRARY_VISIBILITY LoopDependencies {
38 const MachineLoopInfo &MLI;
39 const MachineDominatorTree &MDT;
42 typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
46 LoopDependencies(const MachineLoopInfo &mli,
47 const MachineDominatorTree &mdt) :
50 /// VisitLoop - Clear out any previous state and analyze the given loop.
52 void VisitLoop(const MachineLoop *Loop) {
53 assert(Deps.empty() && "stale loop dependencies");
55 MachineBasicBlock *Header = Loop->getHeader();
56 SmallSet<unsigned, 8> LoopLiveIns;
57 for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
58 LE = Header->livein_end(); LI != LE; ++LI)
59 LoopLiveIns.insert(*LI);
61 const MachineDomTreeNode *Node = MDT.getNode(Header);
62 const MachineBasicBlock *MBB = Node->getBlock();
63 assert(Loop->contains(MBB) &&
64 "Loop does not contain header!");
65 VisitRegion(Node, MBB, Loop, LoopLiveIns);
69 void VisitRegion(const MachineDomTreeNode *Node,
70 const MachineBasicBlock *MBB,
71 const MachineLoop *Loop,
72 const SmallSet<unsigned, 8> &LoopLiveIns) {
74 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
76 const MachineInstr *MI = I;
77 if (MI->isDebugValue())
79 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
80 const MachineOperand &MO = MI->getOperand(i);
81 if (!MO.isReg() || !MO.isUse())
83 unsigned MOReg = MO.getReg();
84 if (LoopLiveIns.count(MOReg))
85 Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
87 ++Count; // Not every iteration due to dbg_value above.
90 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
91 for (std::vector<MachineDomTreeNode*>::const_iterator I =
92 Children.begin(), E = Children.end(); I != E; ++I) {
93 const MachineDomTreeNode *ChildNode = *I;
94 MachineBasicBlock *ChildBlock = ChildNode->getBlock();
95 if (Loop->contains(ChildBlock))
96 VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
101 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
103 class LLVM_LIBRARY_VISIBILITY ScheduleDAGInstrs : public ScheduleDAG {
104 const MachineLoopInfo &MLI;
105 const MachineDominatorTree &MDT;
106 const MachineFrameInfo *MFI;
107 const InstrItineraryData *InstrItins;
109 /// isPostRA flag indicates vregs cannot be present.
112 /// Live Intervals provides reaching defs in preRA scheduling.
115 /// After calling BuildSchedGraph, each machine instruction in the current
116 /// scheduling region is mapped to an SUnit.
117 DenseMap<MachineInstr*, SUnit*> MISUnitMap;
119 /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
120 /// the def-side latency only.
123 /// Combine a SparseSet with a 1x1 vector to track physical registers.
124 /// The SparseSet allows iterating over the (few) live registers for quickly
125 /// comparing against a regmask or clearing the set.
127 /// Storage for the map is allocated once for the pass. The map can be
128 /// cleared between scheduling regions without freeing unused entries.
129 class Reg2SUnitsMap {
130 SparseSet<unsigned> PhysRegSet;
131 std::vector<std::vector<SUnit*> > SUnits;
133 typedef SparseSet<unsigned>::const_iterator const_iterator;
135 // Allow iteration over register numbers (keys) in the map. If needed, we
136 // can provide an iterator over SUnits (values) as well.
137 const_iterator reg_begin() const { return PhysRegSet.begin(); }
138 const_iterator reg_end() const { return PhysRegSet.end(); }
140 /// Initialize the map with the number of registers.
141 /// If the map is already large enough, no allocation occurs.
142 /// For simplicity we expect the map to be empty().
143 void setRegLimit(unsigned Limit);
145 /// Returns true if the map is empty.
146 bool empty() const { return PhysRegSet.empty(); }
148 /// Clear the map without deallocating storage.
151 bool contains(unsigned Reg) const { return PhysRegSet.count(Reg); }
153 /// If this register is mapped, return its existing SUnits vector.
154 /// Otherwise map the register and return an empty SUnits vector.
155 std::vector<SUnit *> &operator[](unsigned Reg) {
156 bool New = PhysRegSet.insert(Reg).second;
157 assert((!New || SUnits[Reg].empty()) && "stale SUnits vector");
162 /// Erase an existing element without freeing memory.
163 void erase(unsigned Reg) {
164 PhysRegSet.erase(Reg);
168 /// Defs, Uses - Remember where defs and uses of each register are as we
169 /// iterate upward through the instructions. This is allocated here instead
170 /// of inside BuildSchedGraph to avoid the need for it to be initialized and
171 /// destructed for each block.
175 /// An individual mapping from virtual register number to SUnit.
180 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
182 unsigned getSparseSetKey() const {
183 return TargetRegisterInfo::virtReg2Index(VirtReg);
186 /// Use SparseSet as a SparseMap by relying on the fact that it never
187 /// compares ValueT's, only unsigned keys. This allows the set to be cleared
188 /// between scheduling regions in constant time as long as ValueT does not
189 /// require a destructor.
190 typedef SparseSet<VReg2SUnit> VReg2SUnitMap;
191 /// Track the last instructon in this region defining each virtual register.
192 VReg2SUnitMap VRegDefs;
194 /// PendingLoads - Remember where unknown loads are after the most recent
195 /// unknown store, as we iterate. As with Defs and Uses, this is here
196 /// to minimize construction/destruction.
197 std::vector<SUnit *> PendingLoads;
199 /// LoopRegs - Track which registers are used for loop-carried dependencies.
201 LoopDependencies LoopRegs;
205 /// DbgValues - Remember instruction that preceeds DBG_VALUE.
206 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
208 DbgValueVector DbgValues;
209 MachineInstr *FirstDbgValue;
212 MachineBasicBlock::iterator Begin; // The beginning of the range to
213 // be scheduled. The range extends
215 unsigned InsertPosIndex; // The index in BB of InsertPos.
217 explicit ScheduleDAGInstrs(MachineFunction &mf,
218 const MachineLoopInfo &mli,
219 const MachineDominatorTree &mdt,
221 LiveIntervals *LIS = 0);
223 virtual ~ScheduleDAGInstrs() {}
225 /// NewSUnit - Creates a new SUnit and return a ptr to it.
227 SUnit *NewSUnit(MachineInstr *MI) {
229 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
231 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
232 assert((Addr == 0 || Addr == &SUnits[0]) &&
233 "SUnits std::vector reallocated on the fly!");
234 SUnits.back().OrigNode = &SUnits.back();
235 return &SUnits.back();
239 /// Run - perform scheduling.
241 void Run(MachineBasicBlock *bb,
242 MachineBasicBlock::iterator begin,
243 MachineBasicBlock::iterator end,
246 /// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
248 void BuildSchedGraph(AliasAnalysis *AA);
250 /// AddSchedBarrierDeps - Add dependencies from instructions in the current
251 /// list of instructions being scheduled to scheduling barrier. We want to
252 /// make sure instructions which define registers that are either used by
253 /// the terminator or are live-out are properly scheduled. This is
254 /// especially important when the definition latency of the return value(s)
255 /// are too high to be hidden by the branch or when the liveout registers
256 /// used by instructions in the fallthrough block.
257 void AddSchedBarrierDeps();
259 /// ComputeLatency - Compute node latency.
261 virtual void ComputeLatency(SUnit *SU);
263 /// ComputeOperandLatency - Override dependence edge latency using
264 /// operand use/def information
266 virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
269 virtual MachineBasicBlock *EmitSchedule();
271 /// StartBlock - Prepare to perform scheduling in the given block.
273 virtual void StartBlock(MachineBasicBlock *BB);
275 /// Schedule - Order nodes according to selected style, filling
276 /// in the Sequence member.
278 virtual void Schedule() = 0;
280 /// FinishBlock - Clean up after scheduling in the given block.
282 virtual void FinishBlock();
284 virtual void dumpNode(const SUnit *SU) const;
286 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
288 virtual std::string getDAGName() const;
291 SUnit *getSUnit(MachineInstr *MI) const {
292 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
293 if (I == MISUnitMap.end())
299 void addPhysRegDataDeps(SUnit *SU, const MachineOperand &MO);
300 void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
301 void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
302 void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
304 VReg2SUnitMap::iterator findVRegDef(unsigned VirtReg) {
305 return VRegDefs.find(TargetRegisterInfo::virtReg2Index(VirtReg));