1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/Compiler.h"
46 STATISTIC(NumIters , "Number of iterations performed");
47 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
48 STATISTIC(NumCoalesce, "Number of copies coalesced");
49 STATISTIC(NumDowngrade, "Number of registers downgraded");
52 NewHeuristic("new-spilling-heuristic",
53 cl::desc("Use new spilling heuristic"),
54 cl::init(false), cl::Hidden);
57 PreSplitIntervals("pre-alloc-split",
58 cl::desc("Pre-register allocation live interval splitting"),
59 cl::init(false), cl::Hidden);
62 NewSpillFramework("new-spill-framework",
63 cl::desc("New spilling framework"),
64 cl::init(false), cl::Hidden);
66 static RegisterRegAlloc
67 linearscanRegAlloc("linearscan", "linear scan register allocator",
68 createLinearScanRegisterAllocator);
71 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
73 RALinScan() : MachineFunctionPass(&ID) {}
75 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
76 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
78 /// RelatedRegClasses - This structure is built the first time a function is
79 /// compiled, and keeps track of which register classes have registers that
80 /// belong to multiple classes or have aliases that are in other classes.
81 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
82 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
84 // NextReloadMap - For each register in the map, it maps to the another
85 // register which is defined by a reload from the same stack slot and
86 // both reloads are in the same basic block.
87 DenseMap<unsigned, unsigned> NextReloadMap;
89 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
90 // un-favored for allocation.
91 SmallSet<unsigned, 8> DowngradedRegs;
93 // DowngradeMap - A map from virtual registers to physical registers being
94 // downgraded for the virtual registers.
95 DenseMap<unsigned, unsigned> DowngradeMap;
98 MachineRegisterInfo* mri_;
99 const TargetMachine* tm_;
100 const TargetRegisterInfo* tri_;
101 const TargetInstrInfo* tii_;
102 BitVector allocatableRegs_;
105 const MachineLoopInfo *loopInfo;
107 /// handled_ - Intervals are added to the handled_ set in the order of their
108 /// start value. This is uses for backtracking.
109 std::vector<LiveInterval*> handled_;
111 /// fixed_ - Intervals that correspond to machine registers.
115 /// active_ - Intervals that are currently being processed, and which have a
116 /// live range active for the current point.
117 IntervalPtrs active_;
119 /// inactive_ - Intervals that are currently being processed, but which have
120 /// a hold at the current point.
121 IntervalPtrs inactive_;
123 typedef std::priority_queue<LiveInterval*,
124 SmallVector<LiveInterval*, 64>,
125 greater_ptr<LiveInterval> > IntervalHeap;
126 IntervalHeap unhandled_;
128 /// regUse_ - Tracks register usage.
129 SmallVector<unsigned, 32> regUse_;
130 SmallVector<unsigned, 32> regUseBackUp_;
132 /// vrm_ - Tracks register assignments.
135 std::auto_ptr<VirtRegRewriter> rewriter_;
137 std::auto_ptr<Spiller> spiller_;
140 virtual const char* getPassName() const {
141 return "Linear Scan Register Allocator";
144 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
145 AU.addRequired<LiveIntervals>();
147 AU.addRequiredID(StrongPHIEliminationID);
148 // Make sure PassManager knows which analyses to make available
149 // to coalescing and which analyses coalescing invalidates.
150 AU.addRequiredTransitive<RegisterCoalescer>();
151 if (PreSplitIntervals)
152 AU.addRequiredID(PreAllocSplittingID);
153 AU.addRequired<LiveStacks>();
154 AU.addPreserved<LiveStacks>();
155 AU.addRequired<MachineLoopInfo>();
156 AU.addPreserved<MachineLoopInfo>();
157 AU.addRequired<VirtRegMap>();
158 AU.addPreserved<VirtRegMap>();
159 AU.addPreservedID(MachineDominatorsID);
160 MachineFunctionPass::getAnalysisUsage(AU);
163 /// runOnMachineFunction - register allocate the whole function
164 bool runOnMachineFunction(MachineFunction&);
167 /// linearScan - the linear scan algorithm
170 /// initIntervalSets - initialize the interval sets.
172 void initIntervalSets();
174 /// processActiveIntervals - expire old intervals and move non-overlapping
175 /// ones to the inactive list.
176 void processActiveIntervals(unsigned CurPoint);
178 /// processInactiveIntervals - expire old intervals and move overlapping
179 /// ones to the active list.
180 void processInactiveIntervals(unsigned CurPoint);
182 /// hasNextReloadInterval - Return the next liveinterval that's being
183 /// defined by a reload from the same SS as the specified one.
184 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
186 /// DowngradeRegister - Downgrade a register for allocation.
187 void DowngradeRegister(LiveInterval *li, unsigned Reg);
189 /// UpgradeRegister - Upgrade a register for allocation.
190 void UpgradeRegister(unsigned Reg);
192 /// assignRegOrStackSlotAtInterval - assign a register if one
193 /// is available, or spill.
194 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
196 void updateSpillWeights(std::vector<float> &Weights,
197 unsigned reg, float weight,
198 const TargetRegisterClass *RC);
200 /// findIntervalsToSpill - Determine the intervals to spill for the
201 /// specified interval. It's passed the physical registers whose spill
202 /// weight is the lowest among all the registers whose live intervals
203 /// conflict with the interval.
204 void findIntervalsToSpill(LiveInterval *cur,
205 std::vector<std::pair<unsigned,float> > &Candidates,
207 SmallVector<LiveInterval*, 8> &SpillIntervals);
209 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
210 /// try allocate the definition the same register as the source register
211 /// if the register is not defined during live time of the interval. This
212 /// eliminate a copy. This is used to coalesce copies which were not
213 /// coalesced away before allocation either due to dest and src being in
214 /// different register classes or because the coalescer was overly
216 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
219 /// Register usage / availability tracking helpers.
223 regUse_.resize(tri_->getNumRegs(), 0);
224 regUseBackUp_.resize(tri_->getNumRegs(), 0);
227 void finalizeRegUses() {
229 // Verify all the registers are "freed".
231 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
232 if (regUse_[i] != 0) {
233 cerr << tri_->getName(i) << " is still in use!\n";
241 regUseBackUp_.clear();
244 void addRegUse(unsigned physReg) {
245 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
246 "should be physical register!");
248 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
252 void delRegUse(unsigned physReg) {
253 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
254 "should be physical register!");
255 assert(regUse_[physReg] != 0);
257 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
258 assert(regUse_[*as] != 0);
263 bool isRegAvail(unsigned physReg) const {
264 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
265 "should be physical register!");
266 return regUse_[physReg] == 0;
269 void backUpRegUses() {
270 regUseBackUp_ = regUse_;
273 void restoreRegUses() {
274 regUse_ = regUseBackUp_;
278 /// Register handling helpers.
281 /// getFreePhysReg - return a free physical register for this virtual
282 /// register interval if we have one, otherwise return 0.
283 unsigned getFreePhysReg(LiveInterval* cur);
284 unsigned getFreePhysReg(const TargetRegisterClass *RC,
285 unsigned MaxInactiveCount,
286 SmallVector<unsigned, 256> &inactiveCounts,
289 /// assignVirt2StackSlot - assigns this virtual register to a
290 /// stack slot. returns the stack slot
291 int assignVirt2StackSlot(unsigned virtReg);
293 void ComputeRelatedRegClasses();
295 template <typename ItTy>
296 void printIntervals(const char* const str, ItTy i, ItTy e) const {
297 if (str) DOUT << str << " intervals:\n";
298 for (; i != e; ++i) {
299 DOUT << "\t" << *i->first << " -> ";
300 unsigned reg = i->first->reg;
301 if (TargetRegisterInfo::isVirtualRegister(reg)) {
302 reg = vrm_->getPhys(reg);
304 DOUT << tri_->getName(reg) << '\n';
308 char RALinScan::ID = 0;
311 static RegisterPass<RALinScan>
312 X("linearscan-regalloc", "Linear Scan Register Allocator");
314 void RALinScan::ComputeRelatedRegClasses() {
315 // First pass, add all reg classes to the union, and determine at least one
316 // reg class that each register is in.
317 bool HasAliases = false;
318 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
319 E = tri_->regclass_end(); RCI != E; ++RCI) {
320 RelatedRegClasses.insert(*RCI);
321 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
323 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
325 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
327 // Already processed this register. Just make sure we know that
328 // multiple register classes share a register.
329 RelatedRegClasses.unionSets(PRC, *RCI);
336 // Second pass, now that we know conservatively what register classes each reg
337 // belongs to, add info about aliases. We don't need to do this for targets
338 // without register aliases.
340 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
341 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
343 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
344 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
347 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
348 /// try allocate the definition the same register as the source register
349 /// if the register is not defined during live time of the interval. This
350 /// eliminate a copy. This is used to coalesce copies which were not
351 /// coalesced away before allocation either due to dest and src being in
352 /// different register classes or because the coalescer was overly
354 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
355 if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
358 VNInfo *vni = cur.begin()->valno;
359 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
361 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
362 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
364 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
367 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
368 if (!vrm_->isAssignedReg(SrcReg))
370 PhysReg = vrm_->getPhys(SrcReg);
375 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
376 if (!RC->contains(PhysReg))
380 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
381 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
383 vrm_->clearVirt(cur.reg);
384 vrm_->assignVirt2Phys(cur.reg, PhysReg);
386 // Remove unnecessary kills since a copy does not clobber the register.
387 if (li_->hasInterval(SrcReg)) {
388 LiveInterval &SrcLI = li_->getInterval(SrcReg);
389 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
390 E = mri_->reg_end(); I != E; ++I) {
391 MachineOperand &O = I.getOperand();
392 if (!O.isUse() || !O.isKill())
394 MachineInstr *MI = &*I;
395 if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
407 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
409 mri_ = &fn.getRegInfo();
410 tm_ = &fn.getTarget();
411 tri_ = tm_->getRegisterInfo();
412 tii_ = tm_->getInstrInfo();
413 allocatableRegs_ = tri_->getAllocatableSet(fn);
414 li_ = &getAnalysis<LiveIntervals>();
415 ls_ = &getAnalysis<LiveStacks>();
416 loopInfo = &getAnalysis<MachineLoopInfo>();
418 // We don't run the coalescer here because we have no reason to
419 // interact with it. If the coalescer requires interaction, it
420 // won't do anything. If it doesn't require interaction, we assume
421 // it was run as a separate pass.
423 // If this is the first function compiled, compute the related reg classes.
424 if (RelatedRegClasses.empty())
425 ComputeRelatedRegClasses();
427 // Also resize register usage trackers.
430 vrm_ = &getAnalysis<VirtRegMap>();
431 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
433 if (NewSpillFramework) {
434 spiller_.reset(createSpiller(mf_, li_, ls_, vrm_));
441 // Rewrite spill code and update the PhysRegsUsed set.
442 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
444 assert(unhandled_.empty() && "Unhandled live intervals remain!");
452 NextReloadMap.clear();
453 DowngradedRegs.clear();
454 DowngradeMap.clear();
460 /// initIntervalSets - initialize the interval sets.
462 void RALinScan::initIntervalSets()
464 assert(unhandled_.empty() && fixed_.empty() &&
465 active_.empty() && inactive_.empty() &&
466 "interval sets should be empty on initialization");
468 handled_.reserve(li_->getNumIntervals());
470 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
471 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
472 mri_->setPhysRegUsed(i->second->reg);
473 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
475 unhandled_.push(i->second);
479 void RALinScan::linearScan()
481 // linear scan algorithm
482 DOUT << "********** LINEAR SCAN **********\n";
483 DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
485 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
487 while (!unhandled_.empty()) {
488 // pick the interval with the earliest start point
489 LiveInterval* cur = unhandled_.top();
492 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
495 processActiveIntervals(cur->beginNumber());
496 processInactiveIntervals(cur->beginNumber());
498 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
499 "Can only allocate virtual registers!");
502 // Allocating a virtual register. try to find a free
503 // physical register or spill an interval (possibly this one) in order to
505 assignRegOrStackSlotAtInterval(cur);
507 DEBUG(printIntervals("active", active_.begin(), active_.end()));
508 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
511 // Expire any remaining active intervals
512 while (!active_.empty()) {
513 IntervalPtr &IP = active_.back();
514 unsigned reg = IP.first->reg;
515 DOUT << "\tinterval " << *IP.first << " expired\n";
516 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
517 "Can only allocate virtual registers!");
518 reg = vrm_->getPhys(reg);
523 // Expire any remaining inactive intervals
524 DEBUG(for (IntervalPtrs::reverse_iterator
525 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
526 DOUT << "\tinterval " << *i->first << " expired\n");
529 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
530 MachineFunction::iterator EntryMBB = mf_->begin();
531 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
532 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
533 LiveInterval &cur = *i->second;
535 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
538 else if (vrm_->isAssignedReg(cur.reg))
539 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
542 // Ignore splited live intervals.
543 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
546 // A register defined by an implicit_def can be liveout the def BB and livein
547 // to a use BB. Add it to the livein set of the use BB's.
548 if (!isPhys && cur.empty()) {
549 if (MachineInstr *DefMI = mri_->getVRegDef(cur.reg)) {
550 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
551 MachineBasicBlock *DefMBB = DefMI->getParent();
552 SmallPtrSet<MachineBasicBlock*, 4> Seen;
554 for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(cur.reg),
555 re = mri_->reg_end(); ri != re; ++ri) {
556 MachineInstr *UseMI = &*ri;
557 MachineBasicBlock *UseMBB = UseMI->getParent();
558 if (Seen.insert(UseMBB))
559 UseMBB->addLiveIn(Reg);
563 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
565 const LiveRange &LR = *I;
566 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
567 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
568 if (LiveInMBBs[i] != EntryMBB)
569 LiveInMBBs[i]->addLiveIn(Reg);
577 // Look for physical registers that end up not being allocated even though
578 // register allocator had to spill other registers in its register class.
579 if (ls_->getNumIntervals() == 0)
581 if (!vrm_->FindUnusedRegisters(tri_, li_))
585 /// processActiveIntervals - expire old intervals and move non-overlapping ones
586 /// to the inactive list.
587 void RALinScan::processActiveIntervals(unsigned CurPoint)
589 DOUT << "\tprocessing active intervals:\n";
591 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
592 LiveInterval *Interval = active_[i].first;
593 LiveInterval::iterator IntervalPos = active_[i].second;
594 unsigned reg = Interval->reg;
596 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
598 if (IntervalPos == Interval->end()) { // Remove expired intervals.
599 DOUT << "\t\tinterval " << *Interval << " expired\n";
600 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
601 "Can only allocate virtual registers!");
602 reg = vrm_->getPhys(reg);
605 // Pop off the end of the list.
606 active_[i] = active_.back();
610 } else if (IntervalPos->start > CurPoint) {
611 // Move inactive intervals to inactive list.
612 DOUT << "\t\tinterval " << *Interval << " inactive\n";
613 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
614 "Can only allocate virtual registers!");
615 reg = vrm_->getPhys(reg);
618 inactive_.push_back(std::make_pair(Interval, IntervalPos));
620 // Pop off the end of the list.
621 active_[i] = active_.back();
625 // Otherwise, just update the iterator position.
626 active_[i].second = IntervalPos;
631 /// processInactiveIntervals - expire old intervals and move overlapping
632 /// ones to the active list.
633 void RALinScan::processInactiveIntervals(unsigned CurPoint)
635 DOUT << "\tprocessing inactive intervals:\n";
637 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
638 LiveInterval *Interval = inactive_[i].first;
639 LiveInterval::iterator IntervalPos = inactive_[i].second;
640 unsigned reg = Interval->reg;
642 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
644 if (IntervalPos == Interval->end()) { // remove expired intervals.
645 DOUT << "\t\tinterval " << *Interval << " expired\n";
647 // Pop off the end of the list.
648 inactive_[i] = inactive_.back();
649 inactive_.pop_back();
651 } else if (IntervalPos->start <= CurPoint) {
652 // move re-activated intervals in active list
653 DOUT << "\t\tinterval " << *Interval << " active\n";
654 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
655 "Can only allocate virtual registers!");
656 reg = vrm_->getPhys(reg);
659 active_.push_back(std::make_pair(Interval, IntervalPos));
661 // Pop off the end of the list.
662 inactive_[i] = inactive_.back();
663 inactive_.pop_back();
666 // Otherwise, just update the iterator position.
667 inactive_[i].second = IntervalPos;
672 /// updateSpillWeights - updates the spill weights of the specifed physical
673 /// register and its weight.
674 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
675 unsigned reg, float weight,
676 const TargetRegisterClass *RC) {
677 SmallSet<unsigned, 4> Processed;
678 SmallSet<unsigned, 4> SuperAdded;
679 SmallVector<unsigned, 4> Supers;
680 Weights[reg] += weight;
681 Processed.insert(reg);
682 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
683 Weights[*as] += weight;
684 Processed.insert(*as);
685 if (tri_->isSubRegister(*as, reg) &&
686 SuperAdded.insert(*as) &&
688 Supers.push_back(*as);
692 // If the alias is a super-register, and the super-register is in the
693 // register class we are trying to allocate. Then add the weight to all
694 // sub-registers of the super-register even if they are not aliases.
695 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
696 // bl should get the same spill weight otherwise it will be choosen
697 // as a spill candidate since spilling bh doesn't make ebx available.
698 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
699 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
700 if (!Processed.count(*sr))
701 Weights[*sr] += weight;
706 RALinScan::IntervalPtrs::iterator
707 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
708 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
710 if (I->first == LI) return I;
714 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
715 for (unsigned i = 0, e = V.size(); i != e; ++i) {
716 RALinScan::IntervalPtr &IP = V[i];
717 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
719 if (I != IP.first->begin()) --I;
724 /// addStackInterval - Create a LiveInterval for stack if the specified live
725 /// interval has been spilled.
726 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
728 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
729 int SS = vrm_.getStackSlot(cur->reg);
730 if (SS == VirtRegMap::NO_STACK_SLOT)
733 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
734 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
737 if (SI.hasAtLeastOneValue())
738 VNI = SI.getValNumInfo(0);
740 VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator());
742 LiveInterval &RI = li_->getInterval(cur->reg);
743 // FIXME: This may be overly conservative.
744 SI.MergeRangesInAsValue(RI, VNI);
747 /// getConflictWeight - Return the number of conflicts between cur
748 /// live interval and defs and uses of Reg weighted by loop depthes.
750 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
751 MachineRegisterInfo *mri_,
752 const MachineLoopInfo *loopInfo) {
754 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
755 E = mri_->reg_end(); I != E; ++I) {
756 MachineInstr *MI = &*I;
757 if (cur->liveAt(li_->getInstructionIndex(MI))) {
758 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
759 Conflicts += powf(10.0f, (float)loopDepth);
765 /// findIntervalsToSpill - Determine the intervals to spill for the
766 /// specified interval. It's passed the physical registers whose spill
767 /// weight is the lowest among all the registers whose live intervals
768 /// conflict with the interval.
769 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
770 std::vector<std::pair<unsigned,float> > &Candidates,
772 SmallVector<LiveInterval*, 8> &SpillIntervals) {
773 // We have figured out the *best* register to spill. But there are other
774 // registers that are pretty good as well (spill weight within 3%). Spill
775 // the one that has fewest defs and uses that conflict with cur.
776 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
777 SmallVector<LiveInterval*, 8> SLIs[3];
779 DOUT << "\tConsidering " << NumCands << " candidates: ";
780 DEBUG(for (unsigned i = 0; i != NumCands; ++i)
781 DOUT << tri_->getName(Candidates[i].first) << " ";
784 // Calculate the number of conflicts of each candidate.
785 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
786 unsigned Reg = i->first->reg;
787 unsigned PhysReg = vrm_->getPhys(Reg);
788 if (!cur->overlapsFrom(*i->first, i->second))
790 for (unsigned j = 0; j < NumCands; ++j) {
791 unsigned Candidate = Candidates[j].first;
792 if (tri_->regsOverlap(PhysReg, Candidate)) {
794 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
795 SLIs[j].push_back(i->first);
800 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
801 unsigned Reg = i->first->reg;
802 unsigned PhysReg = vrm_->getPhys(Reg);
803 if (!cur->overlapsFrom(*i->first, i->second-1))
805 for (unsigned j = 0; j < NumCands; ++j) {
806 unsigned Candidate = Candidates[j].first;
807 if (tri_->regsOverlap(PhysReg, Candidate)) {
809 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
810 SLIs[j].push_back(i->first);
815 // Which is the best candidate?
816 unsigned BestCandidate = 0;
817 float MinConflicts = Conflicts[0];
818 for (unsigned i = 1; i != NumCands; ++i) {
819 if (Conflicts[i] < MinConflicts) {
821 MinConflicts = Conflicts[i];
825 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
826 std::back_inserter(SpillIntervals));
830 struct WeightCompare {
831 typedef std::pair<unsigned, float> RegWeightPair;
832 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
833 return LHS.second < RHS.second;
838 static bool weightsAreClose(float w1, float w2) {
842 float diff = w1 - w2;
843 if (diff <= 0.02f) // Within 0.02f
845 return (diff / w2) <= 0.05f; // Within 5%.
848 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
849 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
850 if (I == NextReloadMap.end())
852 return &li_->getInterval(I->second);
855 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
856 bool isNew = DowngradedRegs.insert(Reg);
857 isNew = isNew; // Silence compiler warning.
858 assert(isNew && "Multiple reloads holding the same register?");
859 DowngradeMap.insert(std::make_pair(li->reg, Reg));
860 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
861 isNew = DowngradedRegs.insert(*AS);
862 isNew = isNew; // Silence compiler warning.
863 assert(isNew && "Multiple reloads holding the same register?");
864 DowngradeMap.insert(std::make_pair(li->reg, *AS));
869 void RALinScan::UpgradeRegister(unsigned Reg) {
871 DowngradedRegs.erase(Reg);
872 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
873 DowngradedRegs.erase(*AS);
879 bool operator()(LiveInterval* A, LiveInterval* B) {
880 return A->beginNumber() < B->beginNumber();
885 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
887 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
889 DOUT << "\tallocating current interval: ";
891 // This is an implicitly defined live interval, just assign any register.
892 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
894 unsigned physReg = cur->preference;
896 physReg = *RC->allocation_order_begin(*mf_);
897 DOUT << tri_->getName(physReg) << '\n';
898 // Note the register is not really in use.
899 vrm_->assignVirt2Phys(cur->reg, physReg);
905 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
906 unsigned StartPosition = cur->beginNumber();
907 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
909 // If start of this live interval is defined by a move instruction and its
910 // source is assigned a physical register that is compatible with the target
911 // register class, then we should try to assign it the same register.
912 // This can happen when the move is from a larger register class to a smaller
913 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
914 if (!cur->preference && cur->hasAtLeastOneValue()) {
915 VNInfo *vni = cur->begin()->valno;
916 if (vni->def && vni->def != ~1U && vni->def != ~0U) {
917 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
918 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
920 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
922 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
924 else if (vrm_->isAssignedReg(SrcReg))
925 Reg = vrm_->getPhys(SrcReg);
928 Reg = tri_->getSubReg(Reg, SrcSubReg);
930 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
931 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
932 cur->preference = Reg;
938 // For every interval in inactive we overlap with, mark the
939 // register as not free and update spill weights.
940 for (IntervalPtrs::const_iterator i = inactive_.begin(),
941 e = inactive_.end(); i != e; ++i) {
942 unsigned Reg = i->first->reg;
943 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
944 "Can only allocate virtual registers!");
945 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
946 // If this is not in a related reg class to the register we're allocating,
948 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
949 cur->overlapsFrom(*i->first, i->second-1)) {
950 Reg = vrm_->getPhys(Reg);
952 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
956 // Speculatively check to see if we can get a register right now. If not,
957 // we know we won't be able to by adding more constraints. If so, we can
958 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
959 // is very bad (it contains all callee clobbered registers for any functions
960 // with a call), so we want to avoid doing that if possible.
961 unsigned physReg = getFreePhysReg(cur);
962 unsigned BestPhysReg = physReg;
964 // We got a register. However, if it's in the fixed_ list, we might
965 // conflict with it. Check to see if we conflict with it or any of its
967 SmallSet<unsigned, 8> RegAliases;
968 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
969 RegAliases.insert(*AS);
971 bool ConflictsWithFixed = false;
972 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
973 IntervalPtr &IP = fixed_[i];
974 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
975 // Okay, this reg is on the fixed list. Check to see if we actually
977 LiveInterval *I = IP.first;
978 if (I->endNumber() > StartPosition) {
979 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
981 if (II != I->begin() && II->start > StartPosition)
983 if (cur->overlapsFrom(*I, II)) {
984 ConflictsWithFixed = true;
991 // Okay, the register picked by our speculative getFreePhysReg call turned
992 // out to be in use. Actually add all of the conflicting fixed registers to
993 // regUse_ so we can do an accurate query.
994 if (ConflictsWithFixed) {
995 // For every interval in fixed we overlap with, mark the register as not
996 // free and update spill weights.
997 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
998 IntervalPtr &IP = fixed_[i];
999 LiveInterval *I = IP.first;
1001 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1002 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1003 I->endNumber() > StartPosition) {
1004 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1006 if (II != I->begin() && II->start > StartPosition)
1008 if (cur->overlapsFrom(*I, II)) {
1009 unsigned reg = I->reg;
1011 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1016 // Using the newly updated regUse_ object, which includes conflicts in the
1017 // future, see if there are any registers available.
1018 physReg = getFreePhysReg(cur);
1022 // Restore the physical register tracker, removing information about the
1026 // If we find a free register, we are done: assign this virtual to
1027 // the free physical register and add this interval to the active
1030 DOUT << tri_->getName(physReg) << '\n';
1031 vrm_->assignVirt2Phys(cur->reg, physReg);
1033 active_.push_back(std::make_pair(cur, cur->begin()));
1034 handled_.push_back(cur);
1036 // "Upgrade" the physical register since it has been allocated.
1037 UpgradeRegister(physReg);
1038 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1039 // "Downgrade" physReg to try to keep physReg from being allocated until
1040 // the next reload from the same SS is allocated.
1041 NextReloadLI->preference = physReg;
1042 DowngradeRegister(cur, physReg);
1046 DOUT << "no free registers\n";
1048 // Compile the spill weights into an array that is better for scanning.
1049 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1050 for (std::vector<std::pair<unsigned, float> >::iterator
1051 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1052 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1054 // for each interval in active, update spill weights.
1055 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1057 unsigned reg = i->first->reg;
1058 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1059 "Can only allocate virtual registers!");
1060 reg = vrm_->getPhys(reg);
1061 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1064 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
1066 // Find a register to spill.
1067 float minWeight = HUGE_VALF;
1068 unsigned minReg = 0; /*cur->preference*/; // Try the pref register first.
1071 std::vector<std::pair<unsigned,float> > RegsWeights;
1072 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1073 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1074 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1076 float regWeight = SpillWeights[reg];
1077 if (minWeight > regWeight)
1079 RegsWeights.push_back(std::make_pair(reg, regWeight));
1082 // If we didn't find a register that is spillable, try aliases?
1084 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1085 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1087 // No need to worry about if the alias register size < regsize of RC.
1088 // We are going to spill all registers that alias it anyway.
1089 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1090 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1094 // Sort all potential spill candidates by weight.
1095 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
1096 minReg = RegsWeights[0].first;
1097 minWeight = RegsWeights[0].second;
1098 if (minWeight == HUGE_VALF) {
1099 // All registers must have inf weight. Just grab one!
1100 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1101 if (cur->weight == HUGE_VALF ||
1102 li_->getApproximateInstructionCount(*cur) == 0) {
1103 // Spill a physical register around defs and uses.
1104 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1105 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1106 // in fixed_. Reset them.
1107 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1108 IntervalPtr &IP = fixed_[i];
1109 LiveInterval *I = IP.first;
1110 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1111 IP.second = I->advanceTo(I->begin(), StartPosition);
1114 DowngradedRegs.clear();
1115 assignRegOrStackSlotAtInterval(cur);
1117 cerr << "Ran out of registers during register allocation!\n";
1124 // Find up to 3 registers to consider as spill candidates.
1125 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1126 while (LastCandidate > 1) {
1127 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1132 DOUT << "\t\tregister(s) with min weight(s): ";
1133 DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
1134 DOUT << tri_->getName(RegsWeights[i].first)
1135 << " (" << RegsWeights[i].second << ")\n");
1137 // If the current has the minimum weight, we need to spill it and
1138 // add any added intervals back to unhandled, and restart
1140 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1141 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
1142 SmallVector<LiveInterval*, 8> spillIs;
1143 std::vector<LiveInterval*> added;
1145 if (!NewSpillFramework) {
1146 added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
1148 added = spiller_->spill(cur);
1151 std::sort(added.begin(), added.end(), LISorter());
1152 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1154 return; // Early exit if all spills were folded.
1156 // Merge added with unhandled. Note that we have already sorted
1157 // intervals returned by addIntervalsForSpills by their starting
1159 // This also update the NextReloadMap. That is, it adds mapping from a
1160 // register defined by a reload from SS to the next reload from SS in the
1161 // same basic block.
1162 MachineBasicBlock *LastReloadMBB = 0;
1163 LiveInterval *LastReload = 0;
1164 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1165 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1166 LiveInterval *ReloadLi = added[i];
1167 if (ReloadLi->weight == HUGE_VALF &&
1168 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1169 unsigned ReloadIdx = ReloadLi->beginNumber();
1170 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1171 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1172 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1173 // Last reload of same SS is in the same MBB. We want to try to
1174 // allocate both reloads the same register and make sure the reg
1175 // isn't clobbered in between if at all possible.
1176 assert(LastReload->beginNumber() < ReloadIdx);
1177 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1179 LastReloadMBB = ReloadMBB;
1180 LastReload = ReloadLi;
1181 LastReloadSS = ReloadSS;
1183 unhandled_.push(ReloadLi);
1190 // Push the current interval back to unhandled since we are going
1191 // to re-run at least this iteration. Since we didn't modify it it
1192 // should go back right in the front of the list
1193 unhandled_.push(cur);
1195 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1196 "did not choose a register to spill?");
1198 // We spill all intervals aliasing the register with
1199 // minimum weight, rollback to the interval with the earliest
1200 // start point and let the linear scan algorithm run again
1201 SmallVector<LiveInterval*, 8> spillIs;
1203 // Determine which intervals have to be spilled.
1204 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1206 // Set of spilled vregs (used later to rollback properly)
1207 SmallSet<unsigned, 8> spilled;
1209 // The earliest start of a Spilled interval indicates up to where
1210 // in handled we need to roll back
1212 LiveInterval *earliestStartInterval = cur;
1214 // Spill live intervals of virtual regs mapped to the physical register we
1215 // want to clear (and its aliases). We only spill those that overlap with the
1216 // current interval as the rest do not affect its allocation. we also keep
1217 // track of the earliest start of all spilled live intervals since this will
1218 // mark our rollback point.
1219 std::vector<LiveInterval*> added;
1220 while (!spillIs.empty()) {
1221 bool epicFail = false;
1222 LiveInterval *sli = spillIs.back();
1224 DOUT << "\t\t\tspilling(a): " << *sli << '\n';
1225 earliestStartInterval =
1226 (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
1227 earliestStartInterval : sli;
1229 std::vector<LiveInterval*> newIs;
1230 if (!NewSpillFramework) {
1231 newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
1233 newIs = spiller_->spill(sli);
1235 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1236 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1237 spilled.insert(sli->reg);
1244 unsigned earliestStart = earliestStartInterval->beginNumber();
1246 DOUT << "\t\trolling back to: " << earliestStart << '\n';
1248 // Scan handled in reverse order up to the earliest start of a
1249 // spilled live interval and undo each one, restoring the state of
1251 while (!handled_.empty()) {
1252 LiveInterval* i = handled_.back();
1253 // If this interval starts before t we are done.
1254 if (i->beginNumber() < earliestStart)
1256 DOUT << "\t\t\tundo changes for: " << *i << '\n';
1257 handled_.pop_back();
1259 // When undoing a live interval allocation we must know if it is active or
1260 // inactive to properly update regUse_ and the VirtRegMap.
1261 IntervalPtrs::iterator it;
1262 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1264 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1265 if (!spilled.count(i->reg))
1267 delRegUse(vrm_->getPhys(i->reg));
1268 vrm_->clearVirt(i->reg);
1269 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1270 inactive_.erase(it);
1271 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1272 if (!spilled.count(i->reg))
1274 vrm_->clearVirt(i->reg);
1276 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1277 "Can only allocate virtual registers!");
1278 vrm_->clearVirt(i->reg);
1282 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1283 if (ii == DowngradeMap.end())
1284 // It interval has a preference, it must be defined by a copy. Clear the
1285 // preference now since the source interval allocation may have been
1289 UpgradeRegister(ii->second);
1293 // Rewind the iterators in the active, inactive, and fixed lists back to the
1294 // point we reverted to.
1295 RevertVectorIteratorsTo(active_, earliestStart);
1296 RevertVectorIteratorsTo(inactive_, earliestStart);
1297 RevertVectorIteratorsTo(fixed_, earliestStart);
1299 // Scan the rest and undo each interval that expired after t and
1300 // insert it in active (the next iteration of the algorithm will
1301 // put it in inactive if required)
1302 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1303 LiveInterval *HI = handled_[i];
1304 if (!HI->expiredAt(earliestStart) &&
1305 HI->expiredAt(cur->beginNumber())) {
1306 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
1307 active_.push_back(std::make_pair(HI, HI->begin()));
1308 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1309 addRegUse(vrm_->getPhys(HI->reg));
1313 // Merge added with unhandled.
1314 // This also update the NextReloadMap. That is, it adds mapping from a
1315 // register defined by a reload from SS to the next reload from SS in the
1316 // same basic block.
1317 MachineBasicBlock *LastReloadMBB = 0;
1318 LiveInterval *LastReload = 0;
1319 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1320 std::sort(added.begin(), added.end(), LISorter());
1321 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1322 LiveInterval *ReloadLi = added[i];
1323 if (ReloadLi->weight == HUGE_VALF &&
1324 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1325 unsigned ReloadIdx = ReloadLi->beginNumber();
1326 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1327 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1328 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1329 // Last reload of same SS is in the same MBB. We want to try to
1330 // allocate both reloads the same register and make sure the reg
1331 // isn't clobbered in between if at all possible.
1332 assert(LastReload->beginNumber() < ReloadIdx);
1333 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1335 LastReloadMBB = ReloadMBB;
1336 LastReload = ReloadLi;
1337 LastReloadSS = ReloadSS;
1339 unhandled_.push(ReloadLi);
1343 unsigned RALinScan::getFreePhysReg(const TargetRegisterClass *RC,
1344 unsigned MaxInactiveCount,
1345 SmallVector<unsigned, 256> &inactiveCounts,
1347 unsigned FreeReg = 0;
1348 unsigned FreeRegInactiveCount = 0;
1350 TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
1351 TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
1352 assert(I != E && "No allocatable register in this register class!");
1354 // Scan for the first available register.
1355 for (; I != E; ++I) {
1357 // Ignore "downgraded" registers.
1358 if (SkipDGRegs && DowngradedRegs.count(Reg))
1360 if (isRegAvail(Reg)) {
1362 if (FreeReg < inactiveCounts.size())
1363 FreeRegInactiveCount = inactiveCounts[FreeReg];
1365 FreeRegInactiveCount = 0;
1370 // If there are no free regs, or if this reg has the max inactive count,
1371 // return this register.
1372 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount)
1375 // Continue scanning the registers, looking for the one with the highest
1376 // inactive count. Alkis found that this reduced register pressure very
1377 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1379 for (; I != E; ++I) {
1381 // Ignore "downgraded" registers.
1382 if (SkipDGRegs && DowngradedRegs.count(Reg))
1384 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1385 FreeRegInactiveCount < inactiveCounts[Reg]) {
1387 FreeRegInactiveCount = inactiveCounts[Reg];
1388 if (FreeRegInactiveCount == MaxInactiveCount)
1389 break; // We found the one with the max inactive count.
1396 /// getFreePhysReg - return a free physical register for this virtual register
1397 /// interval if we have one, otherwise return 0.
1398 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1399 SmallVector<unsigned, 256> inactiveCounts;
1400 unsigned MaxInactiveCount = 0;
1402 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1403 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1405 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1407 unsigned reg = i->first->reg;
1408 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1409 "Can only allocate virtual registers!");
1411 // If this is not in a related reg class to the register we're allocating,
1413 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1414 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1415 reg = vrm_->getPhys(reg);
1416 if (inactiveCounts.size() <= reg)
1417 inactiveCounts.resize(reg+1);
1418 ++inactiveCounts[reg];
1419 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1423 // If copy coalescer has assigned a "preferred" register, check if it's
1425 if (cur->preference) {
1426 DOUT << "(preferred: " << tri_->getName(cur->preference) << ") ";
1427 if (isRegAvail(cur->preference) &&
1428 RC->contains(cur->preference))
1429 return cur->preference;
1432 if (!DowngradedRegs.empty()) {
1433 unsigned FreeReg = getFreePhysReg(RC, MaxInactiveCount, inactiveCounts,
1438 return getFreePhysReg(RC, MaxInactiveCount, inactiveCounts, false);
1441 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1442 return new RALinScan();