1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/CodeGen/Passes.h"
17 #include "AllocationOrder.h"
18 #include "InterferenceCache.h"
19 #include "LiveDebugVariables.h"
20 #include "RegAllocBase.h"
21 #include "SpillPlacement.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/CodeGen/CalcSpillWeights.h"
27 #include "llvm/CodeGen/EdgeBundles.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveRangeEdit.h"
30 #include "llvm/CodeGen/LiveRegMatrix.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
33 #include "llvm/CodeGen/MachineDominators.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineLoopInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/RegAllocRegistry.h"
38 #include "llvm/CodeGen/RegisterClassInfo.h"
39 #include "llvm/CodeGen/VirtRegMap.h"
40 #include "llvm/PassAnalysisSupport.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/Timer.h"
45 #include "llvm/Support/raw_ostream.h"
50 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
51 STATISTIC(NumLocalSplits, "Number of split local live ranges");
52 STATISTIC(NumEvicted, "Number of interferences evicted");
54 static cl::opt<SplitEditor::ComplementSpillMode>
55 SplitSpillMode("split-spill-mode", cl::Hidden,
56 cl::desc("Spill mode for splitting live ranges"),
57 cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"),
58 clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"),
59 clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed"),
61 cl::init(SplitEditor::SM_Partition));
63 static cl::opt<unsigned>
64 LastChanceRecoloringMaxDepth("lcr-max-depth", cl::Hidden,
65 cl::desc("Last chance recoloring max depth"),
68 static cl::opt<unsigned> LastChanceRecoloringMaxInterference(
69 "lcr-max-interf", cl::Hidden,
70 cl::desc("Last chance recoloring maximum number of considered"
71 " interference at a time"),
74 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
75 createGreedyRegisterAllocator);
78 class RAGreedy : public MachineFunctionPass,
80 private LiveRangeEdit::Delegate {
81 // Convenient shortcuts.
82 typedef std::priority_queue<std::pair<unsigned, unsigned> > PQueue;
83 typedef SmallPtrSet<LiveInterval *, 4> SmallLISet;
84 typedef SmallSet<unsigned, 16> SmallVirtRegSet;
89 // Shortcuts to some useful interface.
90 const TargetInstrInfo *TII;
91 const TargetRegisterInfo *TRI;
92 RegisterClassInfo RCI;
96 MachineBlockFrequencyInfo *MBFI;
97 MachineDominatorTree *DomTree;
98 MachineLoopInfo *Loops;
100 SpillPlacement *SpillPlacer;
101 LiveDebugVariables *DebugVars;
104 std::unique_ptr<Spiller> SpillerInstance;
106 unsigned NextCascade;
108 // Live ranges pass through a number of stages as we try to allocate them.
109 // Some of the stages may also create new live ranges:
111 // - Region splitting.
112 // - Per-block splitting.
113 // - Local splitting.
116 // Ranges produced by one of the stages skip the previous stages when they are
117 // dequeued. This improves performance because we can skip interference checks
118 // that are unlikely to give any results. It also guarantees that the live
119 // range splitting algorithm terminates, something that is otherwise hard to
121 enum LiveRangeStage {
122 /// Newly created live range that has never been queued.
125 /// Only attempt assignment and eviction. Then requeue as RS_Split.
128 /// Attempt live range splitting if assignment is impossible.
131 /// Attempt more aggressive live range splitting that is guaranteed to make
132 /// progress. This is used for split products that may not be making
136 /// Live range will be spilled. No more splitting will be attempted.
139 /// There is nothing more we can do to this live range. Abort compilation
140 /// if it can't be assigned.
145 static const char *const StageName[];
148 // RegInfo - Keep additional information about each live range.
150 LiveRangeStage Stage;
152 // Cascade - Eviction loop prevention. See canEvictInterference().
155 RegInfo() : Stage(RS_New), Cascade(0) {}
158 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
160 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
161 return ExtraRegInfo[VirtReg.reg].Stage;
164 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
165 ExtraRegInfo.resize(MRI->getNumVirtRegs());
166 ExtraRegInfo[VirtReg.reg].Stage = Stage;
169 template<typename Iterator>
170 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
171 ExtraRegInfo.resize(MRI->getNumVirtRegs());
172 for (;Begin != End; ++Begin) {
173 unsigned Reg = *Begin;
174 if (ExtraRegInfo[Reg].Stage == RS_New)
175 ExtraRegInfo[Reg].Stage = NewStage;
179 /// Cost of evicting interference.
180 struct EvictionCost {
181 unsigned BrokenHints; ///< Total number of broken hints.
182 float MaxWeight; ///< Maximum spill weight evicted.
184 EvictionCost(): BrokenHints(0), MaxWeight(0) {}
186 bool isMax() const { return BrokenHints == ~0u; }
188 void setMax() { BrokenHints = ~0u; }
190 void setBrokenHints(unsigned NHints) { BrokenHints = NHints; }
192 bool operator<(const EvictionCost &O) const {
193 return std::tie(BrokenHints, MaxWeight) <
194 std::tie(O.BrokenHints, O.MaxWeight);
199 std::unique_ptr<SplitAnalysis> SA;
200 std::unique_ptr<SplitEditor> SE;
202 /// Cached per-block interference maps
203 InterferenceCache IntfCache;
205 /// All basic blocks where the current register has uses.
206 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
208 /// Global live range splitting candidate info.
209 struct GlobalSplitCandidate {
210 // Register intended for assignment, or 0.
213 // SplitKit interval index for this candidate.
216 // Interference for PhysReg.
217 InterferenceCache::Cursor Intf;
219 // Bundles where this candidate should be live.
220 BitVector LiveBundles;
221 SmallVector<unsigned, 8> ActiveBlocks;
223 void reset(InterferenceCache &Cache, unsigned Reg) {
226 Intf.setPhysReg(Cache, Reg);
228 ActiveBlocks.clear();
231 // Set B[i] = C for every live bundle where B[i] was NoCand.
232 unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {
234 for (int i = LiveBundles.find_first(); i >= 0;
235 i = LiveBundles.find_next(i))
236 if (B[i] == NoCand) {
244 /// Candidate info for each PhysReg in AllocationOrder.
245 /// This vector never shrinks, but grows to the size of the largest register
247 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
249 enum : unsigned { NoCand = ~0u };
251 /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
252 /// NoCand which indicates the stack interval.
253 SmallVector<unsigned, 32> BundleCand;
258 /// Return the pass name.
259 const char* getPassName() const override {
260 return "Greedy Register Allocator";
263 /// RAGreedy analysis usage.
264 void getAnalysisUsage(AnalysisUsage &AU) const override;
265 void releaseMemory() override;
266 Spiller &spiller() override { return *SpillerInstance; }
267 void enqueue(LiveInterval *LI) override;
268 LiveInterval *dequeue() override;
269 unsigned selectOrSplit(LiveInterval&, SmallVectorImpl<unsigned>&) override;
271 /// Perform register allocation.
272 bool runOnMachineFunction(MachineFunction &mf) override;
277 unsigned selectOrSplitImpl(LiveInterval &, SmallVectorImpl<unsigned> &,
278 SmallVirtRegSet &, unsigned = 0);
280 bool LRE_CanEraseVirtReg(unsigned) override;
281 void LRE_WillShrinkVirtReg(unsigned) override;
282 void LRE_DidCloneVirtReg(unsigned, unsigned) override;
283 void enqueue(PQueue &CurQueue, LiveInterval *LI);
284 LiveInterval *dequeue(PQueue &CurQueue);
286 BlockFrequency calcSpillCost();
287 bool addSplitConstraints(InterferenceCache::Cursor, BlockFrequency&);
288 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
289 void growRegion(GlobalSplitCandidate &Cand);
290 BlockFrequency calcGlobalSplitCost(GlobalSplitCandidate&);
291 bool calcCompactRegion(GlobalSplitCandidate&);
292 void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
293 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
294 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
295 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
296 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
297 void evictInterference(LiveInterval&, unsigned,
298 SmallVectorImpl<unsigned>&);
299 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
300 SmallLISet &RecoloringCandidates,
301 const SmallVirtRegSet &FixedRegisters);
303 unsigned tryAssign(LiveInterval&, AllocationOrder&,
304 SmallVectorImpl<unsigned>&);
305 unsigned tryEvict(LiveInterval&, AllocationOrder&,
306 SmallVectorImpl<unsigned>&, unsigned = ~0u);
307 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
308 SmallVectorImpl<unsigned>&);
309 /// Calculate cost of region splitting.
310 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
311 AllocationOrder &Order,
312 BlockFrequency &BestCost,
314 /// Perform region splitting.
315 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
317 SmallVectorImpl<unsigned> &NewVRegs);
318 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
319 SmallVectorImpl<unsigned>&);
320 unsigned tryInstructionSplit(LiveInterval&, AllocationOrder&,
321 SmallVectorImpl<unsigned>&);
322 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
323 SmallVectorImpl<unsigned>&);
324 unsigned trySplit(LiveInterval&, AllocationOrder&,
325 SmallVectorImpl<unsigned>&);
326 unsigned tryLastChanceRecoloring(LiveInterval &, AllocationOrder &,
327 SmallVectorImpl<unsigned> &,
328 SmallVirtRegSet &, unsigned);
329 bool tryRecoloringCandidates(PQueue &, SmallVectorImpl<unsigned> &,
330 SmallVirtRegSet &, unsigned);
332 } // end anonymous namespace
334 char RAGreedy::ID = 0;
337 const char *const RAGreedy::StageName[] = {
347 // Hysteresis to use when comparing floats.
348 // This helps stabilize decisions based on float comparisons.
349 const float Hysteresis = (2007 / 2048.0f); // 0.97998046875
352 FunctionPass* llvm::createGreedyRegisterAllocator() {
353 return new RAGreedy();
356 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
357 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
358 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
359 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
360 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
361 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
362 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
363 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
364 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
365 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
366 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
367 initializeLiveRegMatrixPass(*PassRegistry::getPassRegistry());
368 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
369 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
372 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
373 AU.setPreservesCFG();
374 AU.addRequired<MachineBlockFrequencyInfo>();
375 AU.addPreserved<MachineBlockFrequencyInfo>();
376 AU.addRequired<AliasAnalysis>();
377 AU.addPreserved<AliasAnalysis>();
378 AU.addRequired<LiveIntervals>();
379 AU.addPreserved<LiveIntervals>();
380 AU.addRequired<SlotIndexes>();
381 AU.addPreserved<SlotIndexes>();
382 AU.addRequired<LiveDebugVariables>();
383 AU.addPreserved<LiveDebugVariables>();
384 AU.addRequired<LiveStacks>();
385 AU.addPreserved<LiveStacks>();
386 AU.addRequired<MachineDominatorTree>();
387 AU.addPreserved<MachineDominatorTree>();
388 AU.addRequired<MachineLoopInfo>();
389 AU.addPreserved<MachineLoopInfo>();
390 AU.addRequired<VirtRegMap>();
391 AU.addPreserved<VirtRegMap>();
392 AU.addRequired<LiveRegMatrix>();
393 AU.addPreserved<LiveRegMatrix>();
394 AU.addRequired<EdgeBundles>();
395 AU.addRequired<SpillPlacement>();
396 MachineFunctionPass::getAnalysisUsage(AU);
400 //===----------------------------------------------------------------------===//
401 // LiveRangeEdit delegate methods
402 //===----------------------------------------------------------------------===//
404 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
405 if (VRM->hasPhys(VirtReg)) {
406 Matrix->unassign(LIS->getInterval(VirtReg));
409 // Unassigned virtreg is probably in the priority queue.
410 // RegAllocBase will erase it after dequeueing.
414 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
415 if (!VRM->hasPhys(VirtReg))
418 // Register is assigned, put it back on the queue for reassignment.
419 LiveInterval &LI = LIS->getInterval(VirtReg);
420 Matrix->unassign(LI);
424 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
425 // Cloning a register we haven't even heard about yet? Just ignore it.
426 if (!ExtraRegInfo.inBounds(Old))
429 // LRE may clone a virtual register because dead code elimination causes it to
430 // be split into connected components. The new components are much smaller
431 // than the original, so they should get a new chance at being assigned.
432 // same stage as the parent.
433 ExtraRegInfo[Old].Stage = RS_Assign;
434 ExtraRegInfo.grow(New);
435 ExtraRegInfo[New] = ExtraRegInfo[Old];
438 void RAGreedy::releaseMemory() {
439 SpillerInstance.reset(0);
440 ExtraRegInfo.clear();
444 void RAGreedy::enqueue(LiveInterval *LI) { enqueue(Queue, LI); }
446 void RAGreedy::enqueue(PQueue &CurQueue, LiveInterval *LI) {
447 // Prioritize live ranges by size, assigning larger ranges first.
448 // The queue holds (size, reg) pairs.
449 const unsigned Size = LI->getSize();
450 const unsigned Reg = LI->reg;
451 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
452 "Can only enqueue virtual registers");
455 ExtraRegInfo.grow(Reg);
456 if (ExtraRegInfo[Reg].Stage == RS_New)
457 ExtraRegInfo[Reg].Stage = RS_Assign;
459 if (ExtraRegInfo[Reg].Stage == RS_Split) {
460 // Unsplit ranges that couldn't be allocated immediately are deferred until
461 // everything else has been allocated.
464 // Giant live ranges fall back to the global assignment heuristic, which
465 // prevents excessive spilling in pathological cases.
466 bool ReverseLocal = TRI->reverseLocalAssignment();
467 bool ForceGlobal = !ReverseLocal && TRI->mayOverrideLocalAssignment() &&
468 (Size / SlotIndex::InstrDist) > (2 * MRI->getRegClass(Reg)->getNumRegs());
470 if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
471 LIS->intervalIsInOneMBB(*LI)) {
472 // Allocate original local ranges in linear instruction order. Since they
473 // are singly defined, this produces optimal coloring in the absence of
474 // global interference and other constraints.
476 Prio = LI->beginIndex().getInstrDistance(Indexes->getLastIndex());
478 // Allocating bottom up may allow many short LRGs to be assigned first
479 // to one of the cheap registers. This could be much faster for very
480 // large blocks on targets with many physical registers.
481 Prio = Indexes->getZeroIndex().getInstrDistance(LI->beginIndex());
485 // Allocate global and split ranges in long->short order. Long ranges that
486 // don't fit should be spilled (or split) ASAP so they don't create
487 // interference. Mark a bit to prioritize global above local ranges.
488 Prio = (1u << 29) + Size;
490 // Mark a higher bit to prioritize global and local above RS_Split.
493 // Boost ranges that have a physical register hint.
494 if (VRM->hasKnownPreference(Reg))
497 // The virtual register number is a tie breaker for same-sized ranges.
498 // Give lower vreg numbers higher priority to assign them first.
499 CurQueue.push(std::make_pair(Prio, ~Reg));
502 LiveInterval *RAGreedy::dequeue() { return dequeue(Queue); }
504 LiveInterval *RAGreedy::dequeue(PQueue &CurQueue) {
505 if (CurQueue.empty())
507 LiveInterval *LI = &LIS->getInterval(~CurQueue.top().second);
513 //===----------------------------------------------------------------------===//
515 //===----------------------------------------------------------------------===//
517 /// tryAssign - Try to assign VirtReg to an available register.
518 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
519 AllocationOrder &Order,
520 SmallVectorImpl<unsigned> &NewVRegs) {
523 while ((PhysReg = Order.next()))
524 if (!Matrix->checkInterference(VirtReg, PhysReg))
526 if (!PhysReg || Order.isHint())
529 // PhysReg is available, but there may be a better choice.
531 // If we missed a simple hint, try to cheaply evict interference from the
532 // preferred register.
533 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
534 if (Order.isHint(Hint)) {
535 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
536 EvictionCost MaxCost;
537 MaxCost.setBrokenHints(1);
538 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
539 evictInterference(VirtReg, Hint, NewVRegs);
544 // Try to evict interference from a cheaper alternative.
545 unsigned Cost = TRI->getCostPerUse(PhysReg);
547 // Most registers have 0 additional cost.
551 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
553 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
554 return CheapReg ? CheapReg : PhysReg;
558 //===----------------------------------------------------------------------===//
559 // Interference eviction
560 //===----------------------------------------------------------------------===//
562 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) {
563 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
565 while ((PhysReg = Order.next())) {
566 if (PhysReg == PrevReg)
569 MCRegUnitIterator Units(PhysReg, TRI);
570 for (; Units.isValid(); ++Units) {
571 // Instantiate a "subquery", not to be confused with the Queries array.
572 LiveIntervalUnion::Query subQ(&VirtReg, &Matrix->getLiveUnions()[*Units]);
573 if (subQ.checkInterference())
576 // If no units have interference, break out with the current PhysReg.
577 if (!Units.isValid())
581 DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
582 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
587 /// shouldEvict - determine if A should evict the assigned live range B. The
588 /// eviction policy defined by this function together with the allocation order
589 /// defined by enqueue() decides which registers ultimately end up being split
592 /// Cascade numbers are used to prevent infinite loops if this function is a
595 /// @param A The live range to be assigned.
596 /// @param IsHint True when A is about to be assigned to its preferred
598 /// @param B The live range to be evicted.
599 /// @param BreaksHint True when B is already assigned to its preferred register.
600 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
601 LiveInterval &B, bool BreaksHint) {
602 bool CanSplit = getStage(B) < RS_Spill;
604 // Be fairly aggressive about following hints as long as the evictee can be
606 if (CanSplit && IsHint && !BreaksHint)
609 if (A.weight > B.weight) {
610 DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight << '\n');
616 /// canEvictInterference - Return true if all interferences between VirtReg and
617 /// PhysReg can be evicted.
619 /// @param VirtReg Live range that is about to be assigned.
620 /// @param PhysReg Desired register for assignment.
621 /// @param IsHint True when PhysReg is VirtReg's preferred register.
622 /// @param MaxCost Only look for cheaper candidates and update with new cost
623 /// when returning true.
624 /// @returns True when interference can be evicted cheaper than MaxCost.
625 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
626 bool IsHint, EvictionCost &MaxCost) {
627 // It is only possible to evict virtual register interference.
628 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
631 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg);
633 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
634 // involved in an eviction before. If a cascade number was assigned, deny
635 // evicting anything with the same or a newer cascade number. This prevents
636 // infinite eviction loops.
638 // This works out so a register without a cascade number is allowed to evict
639 // anything, and it can be evicted by anything.
640 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
642 Cascade = NextCascade;
645 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
646 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
647 // If there is 10 or more interferences, chances are one is heavier.
648 if (Q.collectInterferingVRegs(10) >= 10)
651 // Check if any interfering live range is heavier than MaxWeight.
652 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
653 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
654 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
655 "Only expecting virtual register interference from query");
656 // Never evict spill products. They cannot split or spill.
657 if (getStage(*Intf) == RS_Done)
659 // Once a live range becomes small enough, it is urgent that we find a
660 // register for it. This is indicated by an infinite spill weight. These
661 // urgent live ranges get to evict almost anything.
663 // Also allow urgent evictions of unspillable ranges from a strictly
664 // larger allocation order.
665 bool Urgent = !VirtReg.isSpillable() &&
666 (Intf->isSpillable() ||
667 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
668 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
669 // Only evict older cascades or live ranges without a cascade.
670 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
671 if (Cascade <= IntfCascade) {
674 // We permit breaking cascades for urgent evictions. It should be the
675 // last resort, though, so make it really expensive.
676 Cost.BrokenHints += 10;
678 // Would this break a satisfied hint?
679 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
680 // Update eviction cost.
681 Cost.BrokenHints += BreaksHint;
682 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
683 // Abort if this would be too expensive.
684 if (!(Cost < MaxCost))
688 // Apply the eviction policy for non-urgent evictions.
689 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
691 // If !MaxCost.isMax(), then we're just looking for a cheap register.
692 // Evicting another local live range in this case could lead to suboptimal
694 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
695 !canReassign(*Intf, PhysReg)) {
704 /// evictInterference - Evict any interferring registers that prevent VirtReg
705 /// from being assigned to Physreg. This assumes that canEvictInterference
707 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
708 SmallVectorImpl<unsigned> &NewVRegs) {
709 // Make sure that VirtReg has a cascade number, and assign that cascade
710 // number to every evicted register. These live ranges than then only be
711 // evicted by a newer cascade, preventing infinite loops.
712 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
714 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
716 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
717 << " interference: Cascade " << Cascade << '\n');
719 // Collect all interfering virtregs first.
720 SmallVector<LiveInterval*, 8> Intfs;
721 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
722 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
723 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
724 ArrayRef<LiveInterval*> IVR = Q.interferingVRegs();
725 Intfs.append(IVR.begin(), IVR.end());
728 // Evict them second. This will invalidate the queries.
729 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
730 LiveInterval *Intf = Intfs[i];
731 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
732 if (!VRM->hasPhys(Intf->reg))
734 Matrix->unassign(*Intf);
735 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
736 VirtReg.isSpillable() < Intf->isSpillable()) &&
737 "Cannot decrease cascade number, illegal eviction");
738 ExtraRegInfo[Intf->reg].Cascade = Cascade;
740 NewVRegs.push_back(Intf->reg);
744 /// tryEvict - Try to evict all interferences for a physreg.
745 /// @param VirtReg Currently unassigned virtual register.
746 /// @param Order Physregs to try.
747 /// @return Physreg to assign VirtReg, or 0.
748 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
749 AllocationOrder &Order,
750 SmallVectorImpl<unsigned> &NewVRegs,
751 unsigned CostPerUseLimit) {
752 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
754 // Keep track of the cheapest interference seen so far.
755 EvictionCost BestCost;
757 unsigned BestPhys = 0;
758 unsigned OrderLimit = Order.getOrder().size();
760 // When we are just looking for a reduced cost per use, don't break any
761 // hints, and only evict smaller spill weights.
762 if (CostPerUseLimit < ~0u) {
763 BestCost.BrokenHints = 0;
764 BestCost.MaxWeight = VirtReg.weight;
766 // Check of any registers in RC are below CostPerUseLimit.
767 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
768 unsigned MinCost = RegClassInfo.getMinCost(RC);
769 if (MinCost >= CostPerUseLimit) {
770 DEBUG(dbgs() << RC->getName() << " minimum cost = " << MinCost
771 << ", no cheaper registers to be found.\n");
775 // It is normal for register classes to have a long tail of registers with
776 // the same cost. We don't need to look at them if they're too expensive.
777 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) {
778 OrderLimit = RegClassInfo.getLastCostChange(RC);
779 DEBUG(dbgs() << "Only trying the first " << OrderLimit << " regs.\n");
784 while (unsigned PhysReg = Order.next(OrderLimit)) {
785 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
787 // The first use of a callee-saved register in a function has cost 1.
788 // Don't start using a CSR when the CostPerUseLimit is low.
789 if (CostPerUseLimit == 1)
790 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
791 if (!MRI->isPhysRegUsed(CSR)) {
792 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
793 << PrintReg(CSR, TRI) << '\n');
797 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
803 // Stop if the hint can be used.
811 evictInterference(VirtReg, BestPhys, NewVRegs);
816 //===----------------------------------------------------------------------===//
818 //===----------------------------------------------------------------------===//
820 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
821 /// interference pattern in Physreg and its aliases. Add the constraints to
822 /// SpillPlacement and return the static cost of this split in Cost, assuming
823 /// that all preferences in SplitConstraints are met.
824 /// Return false if there are no bundles with positive bias.
825 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
826 BlockFrequency &Cost) {
827 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
829 // Reset interference dependent info.
830 SplitConstraints.resize(UseBlocks.size());
831 BlockFrequency StaticCost = 0;
832 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
833 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
834 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
836 BC.Number = BI.MBB->getNumber();
837 Intf.moveToBlock(BC.Number);
838 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
839 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
840 BC.ChangesValue = BI.FirstDef.isValid();
842 if (!Intf.hasInterference())
845 // Number of spill code instructions to insert.
848 // Interference for the live-in value.
850 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
851 BC.Entry = SpillPlacement::MustSpill, ++Ins;
852 else if (Intf.first() < BI.FirstInstr)
853 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
854 else if (Intf.first() < BI.LastInstr)
858 // Interference for the live-out value.
860 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
861 BC.Exit = SpillPlacement::MustSpill, ++Ins;
862 else if (Intf.last() > BI.LastInstr)
863 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
864 else if (Intf.last() > BI.FirstInstr)
868 // Accumulate the total frequency of inserted spill code.
870 StaticCost += SpillPlacer->getBlockFrequency(BC.Number);
874 // Add constraints for use-blocks. Note that these are the only constraints
875 // that may add a positive bias, it is downhill from here.
876 SpillPlacer->addConstraints(SplitConstraints);
877 return SpillPlacer->scanActiveBundles();
881 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
882 /// live-through blocks in Blocks.
883 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
884 ArrayRef<unsigned> Blocks) {
885 const unsigned GroupSize = 8;
886 SpillPlacement::BlockConstraint BCS[GroupSize];
887 unsigned TBS[GroupSize];
888 unsigned B = 0, T = 0;
890 for (unsigned i = 0; i != Blocks.size(); ++i) {
891 unsigned Number = Blocks[i];
892 Intf.moveToBlock(Number);
894 if (!Intf.hasInterference()) {
895 assert(T < GroupSize && "Array overflow");
897 if (++T == GroupSize) {
898 SpillPlacer->addLinks(makeArrayRef(TBS, T));
904 assert(B < GroupSize && "Array overflow");
905 BCS[B].Number = Number;
907 // Interference for the live-in value.
908 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
909 BCS[B].Entry = SpillPlacement::MustSpill;
911 BCS[B].Entry = SpillPlacement::PrefSpill;
913 // Interference for the live-out value.
914 if (Intf.last() >= SA->getLastSplitPoint(Number))
915 BCS[B].Exit = SpillPlacement::MustSpill;
917 BCS[B].Exit = SpillPlacement::PrefSpill;
919 if (++B == GroupSize) {
920 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
921 SpillPlacer->addConstraints(Array);
926 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
927 SpillPlacer->addConstraints(Array);
928 SpillPlacer->addLinks(makeArrayRef(TBS, T));
931 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
932 // Keep track of through blocks that have not been added to SpillPlacer.
933 BitVector Todo = SA->getThroughBlocks();
934 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
935 unsigned AddedTo = 0;
937 unsigned Visited = 0;
941 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
942 // Find new through blocks in the periphery of PrefRegBundles.
943 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
944 unsigned Bundle = NewBundles[i];
945 // Look at all blocks connected to Bundle in the full graph.
946 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
947 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
950 if (!Todo.test(Block))
953 // This is a new through block. Add it to SpillPlacer later.
954 ActiveBlocks.push_back(Block);
960 // Any new blocks to add?
961 if (ActiveBlocks.size() == AddedTo)
964 // Compute through constraints from the interference, or assume that all
965 // through blocks prefer spilling when forming compact regions.
966 ArrayRef<unsigned> NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo);
968 addThroughConstraints(Cand.Intf, NewBlocks);
970 // Provide a strong negative bias on through blocks to prevent unwanted
971 // liveness on loop backedges.
972 SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true);
973 AddedTo = ActiveBlocks.size();
975 // Perhaps iterating can enable more bundles?
976 SpillPlacer->iterate();
978 DEBUG(dbgs() << ", v=" << Visited);
981 /// calcCompactRegion - Compute the set of edge bundles that should be live
982 /// when splitting the current live range into compact regions. Compact
983 /// regions can be computed without looking at interference. They are the
984 /// regions formed by removing all the live-through blocks from the live range.
986 /// Returns false if the current live range is already compact, or if the
987 /// compact regions would form single block regions anyway.
988 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
989 // Without any through blocks, the live range is already compact.
990 if (!SA->getNumThroughBlocks())
993 // Compact regions don't correspond to any physreg.
994 Cand.reset(IntfCache, 0);
996 DEBUG(dbgs() << "Compact region bundles");
998 // Use the spill placer to determine the live bundles. GrowRegion pretends
999 // that all the through blocks have interference when PhysReg is unset.
1000 SpillPlacer->prepare(Cand.LiveBundles);
1002 // The static split cost will be zero since Cand.Intf reports no interference.
1003 BlockFrequency Cost;
1004 if (!addSplitConstraints(Cand.Intf, Cost)) {
1005 DEBUG(dbgs() << ", none.\n");
1010 SpillPlacer->finish();
1012 if (!Cand.LiveBundles.any()) {
1013 DEBUG(dbgs() << ", none.\n");
1018 for (int i = Cand.LiveBundles.find_first(); i>=0;
1019 i = Cand.LiveBundles.find_next(i))
1020 dbgs() << " EB#" << i;
1026 /// calcSpillCost - Compute how expensive it would be to split the live range in
1027 /// SA around all use blocks instead of forming bundle regions.
1028 BlockFrequency RAGreedy::calcSpillCost() {
1029 BlockFrequency Cost = 0;
1030 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1031 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1032 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1033 unsigned Number = BI.MBB->getNumber();
1034 // We normally only need one spill instruction - a load or a store.
1035 Cost += SpillPlacer->getBlockFrequency(Number);
1037 // Unless the value is redefined in the block.
1038 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
1039 Cost += SpillPlacer->getBlockFrequency(Number);
1044 /// calcGlobalSplitCost - Return the global split cost of following the split
1045 /// pattern in LiveBundles. This cost should be added to the local cost of the
1046 /// interference pattern in SplitConstraints.
1048 BlockFrequency RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) {
1049 BlockFrequency GlobalCost = 0;
1050 const BitVector &LiveBundles = Cand.LiveBundles;
1051 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1052 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1053 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1054 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
1055 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
1056 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
1060 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
1062 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
1064 GlobalCost += SpillPlacer->getBlockFrequency(BC.Number);
1067 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
1068 unsigned Number = Cand.ActiveBlocks[i];
1069 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
1070 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
1071 if (!RegIn && !RegOut)
1073 if (RegIn && RegOut) {
1074 // We need double spill code if this block has interference.
1075 Cand.Intf.moveToBlock(Number);
1076 if (Cand.Intf.hasInterference()) {
1077 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1078 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1082 // live-in / stack-out or stack-in live-out.
1083 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1088 /// splitAroundRegion - Split the current live range around the regions
1089 /// determined by BundleCand and GlobalCand.
1091 /// Before calling this function, GlobalCand and BundleCand must be initialized
1092 /// so each bundle is assigned to a valid candidate, or NoCand for the
1093 /// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor
1094 /// objects must be initialized for the current live range, and intervals
1095 /// created for the used candidates.
1097 /// @param LREdit The LiveRangeEdit object handling the current split.
1098 /// @param UsedCands List of used GlobalCand entries. Every BundleCand value
1099 /// must appear in this list.
1100 void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
1101 ArrayRef<unsigned> UsedCands) {
1102 // These are the intervals created for new global ranges. We may create more
1103 // intervals for local ranges.
1104 const unsigned NumGlobalIntvs = LREdit.size();
1105 DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n");
1106 assert(NumGlobalIntvs && "No global intervals configured");
1108 // Isolate even single instructions when dealing with a proper sub-class.
1109 // That guarantees register class inflation for the stack interval because it
1111 unsigned Reg = SA->getParent().reg;
1112 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1114 // First handle all the blocks with uses.
1115 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1116 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1117 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1118 unsigned Number = BI.MBB->getNumber();
1119 unsigned IntvIn = 0, IntvOut = 0;
1120 SlotIndex IntfIn, IntfOut;
1122 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1123 if (CandIn != NoCand) {
1124 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1125 IntvIn = Cand.IntvIdx;
1126 Cand.Intf.moveToBlock(Number);
1127 IntfIn = Cand.Intf.first();
1131 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1132 if (CandOut != NoCand) {
1133 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1134 IntvOut = Cand.IntvIdx;
1135 Cand.Intf.moveToBlock(Number);
1136 IntfOut = Cand.Intf.last();
1140 // Create separate intervals for isolated blocks with multiple uses.
1141 if (!IntvIn && !IntvOut) {
1142 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
1143 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1144 SE->splitSingleBlock(BI);
1148 if (IntvIn && IntvOut)
1149 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1151 SE->splitRegInBlock(BI, IntvIn, IntfIn);
1153 SE->splitRegOutBlock(BI, IntvOut, IntfOut);
1156 // Handle live-through blocks. The relevant live-through blocks are stored in
1157 // the ActiveBlocks list with each candidate. We need to filter out
1159 BitVector Todo = SA->getThroughBlocks();
1160 for (unsigned c = 0; c != UsedCands.size(); ++c) {
1161 ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
1162 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
1163 unsigned Number = Blocks[i];
1164 if (!Todo.test(Number))
1168 unsigned IntvIn = 0, IntvOut = 0;
1169 SlotIndex IntfIn, IntfOut;
1171 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1172 if (CandIn != NoCand) {
1173 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1174 IntvIn = Cand.IntvIdx;
1175 Cand.Intf.moveToBlock(Number);
1176 IntfIn = Cand.Intf.first();
1179 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1180 if (CandOut != NoCand) {
1181 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1182 IntvOut = Cand.IntvIdx;
1183 Cand.Intf.moveToBlock(Number);
1184 IntfOut = Cand.Intf.last();
1186 if (!IntvIn && !IntvOut)
1188 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1194 SmallVector<unsigned, 8> IntvMap;
1195 SE->finish(&IntvMap);
1196 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1198 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1199 unsigned OrigBlocks = SA->getNumLiveBlocks();
1201 // Sort out the new intervals created by splitting. We get four kinds:
1202 // - Remainder intervals should not be split again.
1203 // - Candidate intervals can be assigned to Cand.PhysReg.
1204 // - Block-local splits are candidates for local splitting.
1205 // - DCE leftovers should go back on the queue.
1206 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1207 LiveInterval &Reg = LIS->getInterval(LREdit.get(i));
1209 // Ignore old intervals from DCE.
1210 if (getStage(Reg) != RS_New)
1213 // Remainder interval. Don't try splitting again, spill if it doesn't
1215 if (IntvMap[i] == 0) {
1216 setStage(Reg, RS_Spill);
1220 // Global intervals. Allow repeated splitting as long as the number of live
1221 // blocks is strictly decreasing.
1222 if (IntvMap[i] < NumGlobalIntvs) {
1223 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
1224 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1225 << " blocks as original.\n");
1226 // Don't allow repeated splitting as a safe guard against looping.
1227 setStage(Reg, RS_Split2);
1232 // Other intervals are treated as new. This includes local intervals created
1233 // for blocks with multiple uses, and anything created by DCE.
1237 MF->verify(this, "After splitting live range around region");
1240 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1241 SmallVectorImpl<unsigned> &NewVRegs) {
1242 unsigned NumCands = 0;
1243 BlockFrequency BestCost;
1245 // Check if we can split this live range around a compact region.
1246 bool HasCompact = calcCompactRegion(GlobalCand.front());
1248 // Yes, keep GlobalCand[0] as the compact region candidate.
1250 BestCost = BlockFrequency::getMaxFrequency();
1252 // No benefit from the compact region, our fallback will be per-block
1253 // splitting. Make sure we find a solution that is cheaper than spilling.
1254 BestCost = calcSpillCost();
1255 DEBUG(dbgs() << "Cost of isolating all blocks = ";
1256 MBFI->printBlockFreq(dbgs(), BestCost) << '\n');
1260 calculateRegionSplitCost(VirtReg, Order, BestCost, NumCands);
1262 // No solutions found, fall back to single block splitting.
1263 if (!HasCompact && BestCand == NoCand)
1266 return doRegionSplit(VirtReg, BestCand, HasCompact, NewVRegs);
1269 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg,
1270 AllocationOrder &Order,
1271 BlockFrequency &BestCost,
1272 unsigned &NumCands) {
1273 unsigned BestCand = NoCand;
1275 while (unsigned PhysReg = Order.next()) {
1276 // Discard bad candidates before we run out of interference cache cursors.
1277 // This will only affect register classes with a lot of registers (>32).
1278 if (NumCands == IntfCache.getMaxCursors()) {
1279 unsigned WorstCount = ~0u;
1281 for (unsigned i = 0; i != NumCands; ++i) {
1282 if (i == BestCand || !GlobalCand[i].PhysReg)
1284 unsigned Count = GlobalCand[i].LiveBundles.count();
1285 if (Count < WorstCount)
1286 Worst = i, WorstCount = Count;
1289 GlobalCand[Worst] = GlobalCand[NumCands];
1290 if (BestCand == NumCands)
1294 if (GlobalCand.size() <= NumCands)
1295 GlobalCand.resize(NumCands+1);
1296 GlobalSplitCandidate &Cand = GlobalCand[NumCands];
1297 Cand.reset(IntfCache, PhysReg);
1299 SpillPlacer->prepare(Cand.LiveBundles);
1300 BlockFrequency Cost;
1301 if (!addSplitConstraints(Cand.Intf, Cost)) {
1302 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1305 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = ";
1306 MBFI->printBlockFreq(dbgs(), Cost));
1307 if (Cost >= BestCost) {
1309 if (BestCand == NoCand)
1310 dbgs() << " worse than no bundles\n";
1312 dbgs() << " worse than "
1313 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1319 SpillPlacer->finish();
1321 // No live bundles, defer to splitSingleBlocks().
1322 if (!Cand.LiveBundles.any()) {
1323 DEBUG(dbgs() << " no bundles.\n");
1327 Cost += calcGlobalSplitCost(Cand);
1329 dbgs() << ", total = "; MBFI->printBlockFreq(dbgs(), Cost)
1331 for (int i = Cand.LiveBundles.find_first(); i>=0;
1332 i = Cand.LiveBundles.find_next(i))
1333 dbgs() << " EB#" << i;
1336 if (Cost < BestCost) {
1337 BestCand = NumCands;
1345 unsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
1347 SmallVectorImpl<unsigned> &NewVRegs) {
1348 SmallVector<unsigned, 8> UsedCands;
1349 // Prepare split editor.
1350 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1351 SE->reset(LREdit, SplitSpillMode);
1353 // Assign all edge bundles to the preferred candidate, or NoCand.
1354 BundleCand.assign(Bundles->getNumBundles(), NoCand);
1356 // Assign bundles for the best candidate region.
1357 if (BestCand != NoCand) {
1358 GlobalSplitCandidate &Cand = GlobalCand[BestCand];
1359 if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
1360 UsedCands.push_back(BestCand);
1361 Cand.IntvIdx = SE->openIntv();
1362 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1363 << B << " bundles, intv " << Cand.IntvIdx << ".\n");
1368 // Assign bundles for the compact region.
1370 GlobalSplitCandidate &Cand = GlobalCand.front();
1371 assert(!Cand.PhysReg && "Compact region has no physreg");
1372 if (unsigned B = Cand.getBundles(BundleCand, 0)) {
1373 UsedCands.push_back(0);
1374 Cand.IntvIdx = SE->openIntv();
1375 DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv "
1376 << Cand.IntvIdx << ".\n");
1381 splitAroundRegion(LREdit, UsedCands);
1386 //===----------------------------------------------------------------------===//
1387 // Per-Block Splitting
1388 //===----------------------------------------------------------------------===//
1390 /// tryBlockSplit - Split a global live range around every block with uses. This
1391 /// creates a lot of local live ranges, that will be split by tryLocalSplit if
1392 /// they don't allocate.
1393 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1394 SmallVectorImpl<unsigned> &NewVRegs) {
1395 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1396 unsigned Reg = VirtReg.reg;
1397 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1398 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1399 SE->reset(LREdit, SplitSpillMode);
1400 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1401 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1402 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1403 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1404 SE->splitSingleBlock(BI);
1406 // No blocks were split.
1410 // We did split for some blocks.
1411 SmallVector<unsigned, 8> IntvMap;
1412 SE->finish(&IntvMap);
1414 // Tell LiveDebugVariables about the new ranges.
1415 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1417 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1419 // Sort out the new intervals created by splitting. The remainder interval
1420 // goes straight to spilling, the new local ranges get to stay RS_New.
1421 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1422 LiveInterval &LI = LIS->getInterval(LREdit.get(i));
1423 if (getStage(LI) == RS_New && IntvMap[i] == 0)
1424 setStage(LI, RS_Spill);
1428 MF->verify(this, "After splitting live range around basic blocks");
1433 //===----------------------------------------------------------------------===//
1434 // Per-Instruction Splitting
1435 //===----------------------------------------------------------------------===//
1437 /// Get the number of allocatable registers that match the constraints of \p Reg
1438 /// on \p MI and that are also in \p SuperRC.
1439 static unsigned getNumAllocatableRegsForConstraints(
1440 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC,
1441 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1442 const RegisterClassInfo &RCI) {
1443 assert(SuperRC && "Invalid register class");
1445 const TargetRegisterClass *ConstrainedRC =
1446 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI,
1447 /* ExploreBundle */ true);
1450 return RCI.getNumAllocatableRegs(ConstrainedRC);
1453 /// tryInstructionSplit - Split a live range around individual instructions.
1454 /// This is normally not worthwhile since the spiller is doing essentially the
1455 /// same thing. However, when the live range is in a constrained register
1456 /// class, it may help to insert copies such that parts of the live range can
1457 /// be moved to a larger register class.
1459 /// This is similar to spilling to a larger register class.
1461 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1462 SmallVectorImpl<unsigned> &NewVRegs) {
1463 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1464 // There is no point to this if there are no larger sub-classes.
1465 if (!RegClassInfo.isProperSubClass(CurRC))
1468 // Always enable split spill mode, since we're effectively spilling to a
1470 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1471 SE->reset(LREdit, SplitEditor::SM_Size);
1473 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1474 if (Uses.size() <= 1)
1477 DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n");
1479 const TargetRegisterClass *SuperRC = TRI->getLargestLegalSuperClass(CurRC);
1480 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
1481 // Split around every non-copy instruction if this split will relax
1482 // the constraints on the virtual register.
1483 // Otherwise, splitting just inserts uncoalescable copies that do not help
1485 for (unsigned i = 0; i != Uses.size(); ++i) {
1486 if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]))
1487 if (MI->isFullCopy() ||
1488 SuperRCNumAllocatableRegs ==
1489 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII,
1491 DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI);
1495 SlotIndex SegStart = SE->enterIntvBefore(Uses[i]);
1496 SlotIndex SegStop = SE->leaveIntvAfter(Uses[i]);
1497 SE->useIntv(SegStart, SegStop);
1500 if (LREdit.empty()) {
1501 DEBUG(dbgs() << "All uses were copies.\n");
1505 SmallVector<unsigned, 8> IntvMap;
1506 SE->finish(&IntvMap);
1507 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1508 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1510 // Assign all new registers to RS_Spill. This was the last chance.
1511 setStage(LREdit.begin(), LREdit.end(), RS_Spill);
1516 //===----------------------------------------------------------------------===//
1518 //===----------------------------------------------------------------------===//
1521 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
1522 /// in order to use PhysReg between two entries in SA->UseSlots.
1524 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
1526 void RAGreedy::calcGapWeights(unsigned PhysReg,
1527 SmallVectorImpl<float> &GapWeight) {
1528 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1529 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1530 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1531 const unsigned NumGaps = Uses.size()-1;
1533 // Start and end points for the interference check.
1534 SlotIndex StartIdx =
1535 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
1537 BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr;
1539 GapWeight.assign(NumGaps, 0.0f);
1541 // Add interference from each overlapping register.
1542 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1543 if (!Matrix->query(const_cast<LiveInterval&>(SA->getParent()), *Units)
1544 .checkInterference())
1547 // We know that VirtReg is a continuous interval from FirstInstr to
1548 // LastInstr, so we don't need InterferenceQuery.
1550 // Interference that overlaps an instruction is counted in both gaps
1551 // surrounding the instruction. The exception is interference before
1552 // StartIdx and after StopIdx.
1554 LiveIntervalUnion::SegmentIter IntI =
1555 Matrix->getLiveUnions()[*Units] .find(StartIdx);
1556 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
1557 // Skip the gaps before IntI.
1558 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
1559 if (++Gap == NumGaps)
1564 // Update the gaps covered by IntI.
1565 const float weight = IntI.value()->weight;
1566 for (; Gap != NumGaps; ++Gap) {
1567 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1568 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1576 // Add fixed interference.
1577 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1578 const LiveRange &LR = LIS->getRegUnit(*Units);
1579 LiveRange::const_iterator I = LR.find(StartIdx);
1580 LiveRange::const_iterator E = LR.end();
1582 // Same loop as above. Mark any overlapped gaps as HUGE_VALF.
1583 for (unsigned Gap = 0; I != E && I->start < StopIdx; ++I) {
1584 while (Uses[Gap+1].getBoundaryIndex() < I->start)
1585 if (++Gap == NumGaps)
1590 for (; Gap != NumGaps; ++Gap) {
1591 GapWeight[Gap] = llvm::huge_valf;
1592 if (Uses[Gap+1].getBaseIndex() >= I->end)
1601 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1604 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1605 SmallVectorImpl<unsigned> &NewVRegs) {
1606 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1607 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1609 // Note that it is possible to have an interval that is live-in or live-out
1610 // while only covering a single block - A phi-def can use undef values from
1611 // predecessors, and the block could be a single-block loop.
1612 // We don't bother doing anything clever about such a case, we simply assume
1613 // that the interval is continuous from FirstInstr to LastInstr. We should
1614 // make sure that we don't do anything illegal to such an interval, though.
1616 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1617 if (Uses.size() <= 2)
1619 const unsigned NumGaps = Uses.size()-1;
1622 dbgs() << "tryLocalSplit: ";
1623 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1624 dbgs() << ' ' << Uses[i];
1628 // If VirtReg is live across any register mask operands, compute a list of
1629 // gaps with register masks.
1630 SmallVector<unsigned, 8> RegMaskGaps;
1631 if (Matrix->checkRegMaskInterference(VirtReg)) {
1632 // Get regmask slots for the whole block.
1633 ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber());
1634 DEBUG(dbgs() << RMS.size() << " regmasks in block:");
1635 // Constrain to VirtReg's live range.
1636 unsigned ri = std::lower_bound(RMS.begin(), RMS.end(),
1637 Uses.front().getRegSlot()) - RMS.begin();
1638 unsigned re = RMS.size();
1639 for (unsigned i = 0; i != NumGaps && ri != re; ++i) {
1640 // Look for Uses[i] <= RMS <= Uses[i+1].
1641 assert(!SlotIndex::isEarlierInstr(RMS[ri], Uses[i]));
1642 if (SlotIndex::isEarlierInstr(Uses[i+1], RMS[ri]))
1644 // Skip a regmask on the same instruction as the last use. It doesn't
1645 // overlap the live range.
1646 if (SlotIndex::isSameInstr(Uses[i+1], RMS[ri]) && i+1 == NumGaps)
1648 DEBUG(dbgs() << ' ' << RMS[ri] << ':' << Uses[i] << '-' << Uses[i+1]);
1649 RegMaskGaps.push_back(i);
1650 // Advance ri to the next gap. A regmask on one of the uses counts in
1652 while (ri != re && SlotIndex::isEarlierInstr(RMS[ri], Uses[i+1]))
1655 DEBUG(dbgs() << '\n');
1658 // Since we allow local split results to be split again, there is a risk of
1659 // creating infinite loops. It is tempting to require that the new live
1660 // ranges have less instructions than the original. That would guarantee
1661 // convergence, but it is too strict. A live range with 3 instructions can be
1662 // split 2+3 (including the COPY), and we want to allow that.
1664 // Instead we use these rules:
1666 // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
1667 // noop split, of course).
1668 // 2. Require progress be made for ranges with getStage() == RS_Split2. All
1669 // the new ranges must have fewer instructions than before the split.
1670 // 3. New ranges with the same number of instructions are marked RS_Split2,
1671 // smaller ranges are marked RS_New.
1673 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
1674 // excessive splitting and infinite loops.
1676 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
1678 // Best split candidate.
1679 unsigned BestBefore = NumGaps;
1680 unsigned BestAfter = 0;
1683 const float blockFreq =
1684 SpillPlacer->getBlockFrequency(BI.MBB->getNumber()).getFrequency() *
1685 (1.0f / MBFI->getEntryFreq());
1686 SmallVector<float, 8> GapWeight;
1689 while (unsigned PhysReg = Order.next()) {
1690 // Keep track of the largest spill weight that would need to be evicted in
1691 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1692 calcGapWeights(PhysReg, GapWeight);
1694 // Remove any gaps with regmask clobbers.
1695 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1696 for (unsigned i = 0, e = RegMaskGaps.size(); i != e; ++i)
1697 GapWeight[RegMaskGaps[i]] = llvm::huge_valf;
1699 // Try to find the best sequence of gaps to close.
1700 // The new spill weight must be larger than any gap interference.
1702 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1703 unsigned SplitBefore = 0, SplitAfter = 1;
1705 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1706 // It is the spill weight that needs to be evicted.
1707 float MaxGap = GapWeight[0];
1710 // Live before/after split?
1711 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1712 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1714 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1715 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1716 << " i=" << MaxGap);
1718 // Stop before the interval gets so big we wouldn't be making progress.
1719 if (!LiveBefore && !LiveAfter) {
1720 DEBUG(dbgs() << " all\n");
1723 // Should the interval be extended or shrunk?
1726 // How many gaps would the new range have?
1727 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
1729 // Legally, without causing looping?
1730 bool Legal = !ProgressRequired || NewGaps < NumGaps;
1732 if (Legal && MaxGap < llvm::huge_valf) {
1733 // Estimate the new spill weight. Each instruction reads or writes the
1734 // register. Conservatively assume there are no read-modify-write
1737 // Try to guess the size of the new interval.
1738 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1),
1739 Uses[SplitBefore].distance(Uses[SplitAfter]) +
1740 (LiveBefore + LiveAfter)*SlotIndex::InstrDist);
1741 // Would this split be possible to allocate?
1742 // Never allocate all gaps, we wouldn't be making progress.
1743 DEBUG(dbgs() << " w=" << EstWeight);
1744 if (EstWeight * Hysteresis >= MaxGap) {
1746 float Diff = EstWeight - MaxGap;
1747 if (Diff > BestDiff) {
1748 DEBUG(dbgs() << " (best)");
1749 BestDiff = Hysteresis * Diff;
1750 BestBefore = SplitBefore;
1751 BestAfter = SplitAfter;
1758 if (++SplitBefore < SplitAfter) {
1759 DEBUG(dbgs() << " shrink\n");
1760 // Recompute the max when necessary.
1761 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1762 MaxGap = GapWeight[SplitBefore];
1763 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1764 MaxGap = std::max(MaxGap, GapWeight[i]);
1771 // Try to extend the interval.
1772 if (SplitAfter >= NumGaps) {
1773 DEBUG(dbgs() << " end\n");
1777 DEBUG(dbgs() << " extend\n");
1778 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
1782 // Didn't find any candidates?
1783 if (BestBefore == NumGaps)
1786 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1787 << '-' << Uses[BestAfter] << ", " << BestDiff
1788 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1790 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1794 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1795 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1796 SE->useIntv(SegStart, SegStop);
1797 SmallVector<unsigned, 8> IntvMap;
1798 SE->finish(&IntvMap);
1799 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1801 // If the new range has the same number of instructions as before, mark it as
1802 // RS_Split2 so the next split will be forced to make progress. Otherwise,
1803 // leave the new intervals as RS_New so they can compete.
1804 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
1805 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
1806 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
1807 if (NewGaps >= NumGaps) {
1808 DEBUG(dbgs() << "Tagging non-progress ranges: ");
1809 assert(!ProgressRequired && "Didn't make progress when it was required.");
1810 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
1811 if (IntvMap[i] == 1) {
1812 setStage(LIS->getInterval(LREdit.get(i)), RS_Split2);
1813 DEBUG(dbgs() << PrintReg(LREdit.get(i)));
1815 DEBUG(dbgs() << '\n');
1822 //===----------------------------------------------------------------------===//
1823 // Live Range Splitting
1824 //===----------------------------------------------------------------------===//
1826 /// trySplit - Try to split VirtReg or one of its interferences, making it
1828 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1829 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1830 SmallVectorImpl<unsigned>&NewVRegs) {
1831 // Ranges must be Split2 or less.
1832 if (getStage(VirtReg) >= RS_Spill)
1835 // Local intervals are handled separately.
1836 if (LIS->intervalIsInOneMBB(VirtReg)) {
1837 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1838 SA->analyze(&VirtReg);
1839 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1840 if (PhysReg || !NewVRegs.empty())
1842 return tryInstructionSplit(VirtReg, Order, NewVRegs);
1845 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1847 SA->analyze(&VirtReg);
1849 // FIXME: SplitAnalysis may repair broken live ranges coming from the
1850 // coalescer. That may cause the range to become allocatable which means that
1851 // tryRegionSplit won't be making progress. This check should be replaced with
1852 // an assertion when the coalescer is fixed.
1853 if (SA->didRepairRange()) {
1854 // VirtReg has changed, so all cached queries are invalid.
1855 Matrix->invalidateVirtRegs();
1856 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1860 // First try to split around a region spanning multiple blocks. RS_Split2
1861 // ranges already made dubious progress with region splitting, so they go
1862 // straight to single block splitting.
1863 if (getStage(VirtReg) < RS_Split2) {
1864 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1865 if (PhysReg || !NewVRegs.empty())
1869 // Then isolate blocks.
1870 return tryBlockSplit(VirtReg, Order, NewVRegs);
1873 //===----------------------------------------------------------------------===//
1874 // Last Chance Recoloring
1875 //===----------------------------------------------------------------------===//
1877 /// mayRecolorAllInterferences - Check if the virtual registers that
1878 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
1879 /// recolored to free \p PhysReg.
1880 /// When true is returned, \p RecoloringCandidates has been augmented with all
1881 /// the live intervals that need to be recolored in order to free \p PhysReg
1883 /// \p FixedRegisters contains all the virtual registers that cannot be
1886 RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
1887 SmallLISet &RecoloringCandidates,
1888 const SmallVirtRegSet &FixedRegisters) {
1889 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1891 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1892 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
1893 // If there is LastChanceRecoloringMaxInterference or more interferences,
1894 // chances are one would not be recolorable.
1895 if (Q.collectInterferingVRegs(LastChanceRecoloringMaxInterference) >=
1896 LastChanceRecoloringMaxInterference) {
1897 DEBUG(dbgs() << "Early abort: too many interferences.\n");
1900 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
1901 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
1902 // If Intf is done and sit on the same register class as VirtReg,
1903 // it would not be recolorable as it is in the same state as VirtReg.
1904 if ((getStage(*Intf) == RS_Done &&
1905 MRI->getRegClass(Intf->reg) == CurRC) ||
1906 FixedRegisters.count(Intf->reg)) {
1907 DEBUG(dbgs() << "Early abort: the inteference is not recolorable.\n");
1910 RecoloringCandidates.insert(Intf);
1916 /// tryLastChanceRecoloring - Try to assign a color to \p VirtReg by recoloring
1917 /// its interferences.
1918 /// Last chance recoloring chooses a color for \p VirtReg and recolors every
1919 /// virtual register that was using it. The recoloring process may recursively
1920 /// use the last chance recoloring. Therefore, when a virtual register has been
1921 /// assigned a color by this mechanism, it is marked as Fixed, i.e., it cannot
1922 /// be last-chance-recolored again during this recoloring "session".
1925 /// vA can use {R1, R2 }
1926 /// vB can use { R2, R3}
1927 /// vC can use {R1 }
1928 /// Where vA, vB, and vC cannot be split anymore (they are reloads for
1929 /// instance) and they all interfere.
1931 /// vA is assigned R1
1932 /// vB is assigned R2
1933 /// vC tries to evict vA but vA is already done.
1934 /// Regular register allocation fails.
1936 /// Last chance recoloring kicks in:
1937 /// vC does as if vA was evicted => vC uses R1.
1938 /// vC is marked as fixed.
1939 /// vA needs to find a color.
1940 /// None are available.
1941 /// vA cannot evict vC: vC is a fixed virtual register now.
1942 /// vA does as if vB was evicted => vA uses R2.
1943 /// vB needs to find a color.
1944 /// R3 is available.
1945 /// Recoloring => vC = R1, vA = R2, vB = R3
1947 /// \p Order defines the preferred allocation order for \p VirtReg.
1948 /// \p NewRegs will contain any new virtual register that have been created
1949 /// (split, spill) during the process and that must be assigned.
1950 /// \p FixedRegisters contains all the virtual registers that cannot be
1952 /// \p Depth gives the current depth of the last chance recoloring.
1953 /// \return a physical register that can be used for VirtReg or ~0u if none
1955 unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg,
1956 AllocationOrder &Order,
1957 SmallVectorImpl<unsigned> &NewVRegs,
1958 SmallVirtRegSet &FixedRegisters,
1960 DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n');
1961 // Ranges must be Done.
1962 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&
1963 "Last chance recoloring should really be last chance");
1964 // Set the max depth to LastChanceRecoloringMaxDepth.
1965 // We may want to reconsider that if we end up with a too large search space
1966 // for target with hundreds of registers.
1967 // Indeed, in that case we may want to cut the search space earlier.
1968 if (Depth >= LastChanceRecoloringMaxDepth) {
1969 DEBUG(dbgs() << "Abort because max depth has been reached.\n");
1973 // Set of Live intervals that will need to be recolored.
1974 SmallLISet RecoloringCandidates;
1975 // Record the original mapping virtual register to physical register in case
1976 // the recoloring fails.
1977 DenseMap<unsigned, unsigned> VirtRegToPhysReg;
1978 // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in
1979 // this recoloring "session".
1980 FixedRegisters.insert(VirtReg.reg);
1983 while (unsigned PhysReg = Order.next()) {
1984 DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
1985 << PrintReg(PhysReg, TRI) << '\n');
1986 RecoloringCandidates.clear();
1987 VirtRegToPhysReg.clear();
1989 // It is only possible to recolor virtual register interference.
1990 if (Matrix->checkInterference(VirtReg, PhysReg) >
1991 LiveRegMatrix::IK_VirtReg) {
1992 DEBUG(dbgs() << "Some inteferences are not with virtual registers.\n");
1997 // Early give up on this PhysReg if it is obvious we cannot recolor all
1998 // the interferences.
1999 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2001 DEBUG(dbgs() << "Some inteferences cannot be recolored.\n");
2005 // RecoloringCandidates contains all the virtual registers that interfer
2006 // with VirtReg on PhysReg (or one of its aliases).
2007 // Enqueue them for recoloring and perform the actual recoloring.
2008 PQueue RecoloringQueue;
2009 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
2010 EndIt = RecoloringCandidates.end();
2011 It != EndIt; ++It) {
2012 unsigned ItVirtReg = (*It)->reg;
2013 enqueue(RecoloringQueue, *It);
2014 assert(VRM->hasPhys(ItVirtReg) &&
2015 "Interferences are supposed to be with allocated vairables");
2017 // Record the current allocation.
2018 VirtRegToPhysReg[ItVirtReg] = VRM->getPhys(ItVirtReg);
2019 // unset the related struct.
2020 Matrix->unassign(**It);
2023 // Do as if VirtReg was assigned to PhysReg so that the underlying
2024 // recoloring has the right information about the interferes and
2025 // available colors.
2026 Matrix->assign(VirtReg, PhysReg);
2028 // Save the current recoloring state.
2029 // If we cannot recolor all the interferences, we will have to start again
2030 // at this point for the next physical register.
2031 SmallVirtRegSet SaveFixedRegisters(FixedRegisters);
2032 if (tryRecoloringCandidates(RecoloringQueue, NewVRegs, FixedRegisters,
2034 // Do not mess up with the global assignment process.
2035 // I.e., VirtReg must be unassigned.
2036 Matrix->unassign(VirtReg);
2040 DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
2041 << PrintReg(PhysReg, TRI) << '\n');
2043 // The recoloring attempt failed, undo the changes.
2044 FixedRegisters = SaveFixedRegisters;
2045 Matrix->unassign(VirtReg);
2047 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
2048 EndIt = RecoloringCandidates.end();
2049 It != EndIt; ++It) {
2050 unsigned ItVirtReg = (*It)->reg;
2051 if (VRM->hasPhys(ItVirtReg))
2052 Matrix->unassign(**It);
2053 Matrix->assign(**It, VirtRegToPhysReg[ItVirtReg]);
2057 // Last chance recoloring did not worked either, give up.
2061 /// tryRecoloringCandidates - Try to assign a new color to every register
2062 /// in \RecoloringQueue.
2063 /// \p NewRegs will contain any new virtual register created during the
2064 /// recoloring process.
2065 /// \p FixedRegisters[in/out] contains all the registers that have been
2067 /// \return true if all virtual registers in RecoloringQueue were successfully
2068 /// recolored, false otherwise.
2069 bool RAGreedy::tryRecoloringCandidates(PQueue &RecoloringQueue,
2070 SmallVectorImpl<unsigned> &NewVRegs,
2071 SmallVirtRegSet &FixedRegisters,
2073 while (!RecoloringQueue.empty()) {
2074 LiveInterval *LI = dequeue(RecoloringQueue);
2075 DEBUG(dbgs() << "Try to recolor: " << *LI << '\n');
2077 PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, Depth + 1);
2078 if (PhysReg == ~0u || !PhysReg)
2080 DEBUG(dbgs() << "Recoloring of " << *LI
2081 << " succeeded with: " << PrintReg(PhysReg, TRI) << '\n');
2082 Matrix->assign(*LI, PhysReg);
2083 FixedRegisters.insert(LI->reg);
2088 //===----------------------------------------------------------------------===//
2090 //===----------------------------------------------------------------------===//
2092 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
2093 SmallVectorImpl<unsigned> &NewVRegs) {
2094 SmallVirtRegSet FixedRegisters;
2095 return selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters);
2098 unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
2099 SmallVectorImpl<unsigned> &NewVRegs,
2100 SmallVirtRegSet &FixedRegisters,
2102 // First try assigning a free register.
2103 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
2104 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
2107 LiveRangeStage Stage = getStage(VirtReg);
2108 DEBUG(dbgs() << StageName[Stage]
2109 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
2111 // Try to evict a less worthy live range, but only for ranges from the primary
2112 // queue. The RS_Split ranges already failed to do this, and they should not
2113 // get a second chance until they have been split.
2114 if (Stage != RS_Split)
2115 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
2118 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
2120 // The first time we see a live range, don't try to split or spill.
2121 // Wait until the second time, when all smaller ranges have been allocated.
2122 // This gives a better picture of the interference to split around.
2123 if (Stage < RS_Split) {
2124 setStage(VirtReg, RS_Split);
2125 DEBUG(dbgs() << "wait for second round\n");
2126 NewVRegs.push_back(VirtReg.reg);
2130 // If we couldn't allocate a register from spilling, there is probably some
2131 // invalid inline assembly. The base class wil report it.
2132 if (Stage >= RS_Done || !VirtReg.isSpillable())
2133 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,
2136 // Try splitting VirtReg or interferences.
2137 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
2138 if (PhysReg || !NewVRegs.empty())
2141 // Finally spill VirtReg itself.
2142 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
2143 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
2144 spiller().spill(LRE);
2145 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
2148 MF->verify(this, "After spilling");
2150 // The live virtual register requesting allocation was spilled, so tell
2151 // the caller not to allocate anything during this round.
2155 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
2156 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
2157 << "********** Function: " << mf.getName() << '\n');
2160 TRI = MF->getTarget().getRegisterInfo();
2161 TII = MF->getTarget().getInstrInfo();
2162 RCI.runOnMachineFunction(mf);
2164 MF->verify(this, "Before greedy register allocator");
2166 RegAllocBase::init(getAnalysis<VirtRegMap>(),
2167 getAnalysis<LiveIntervals>(),
2168 getAnalysis<LiveRegMatrix>());
2169 Indexes = &getAnalysis<SlotIndexes>();
2170 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
2171 DomTree = &getAnalysis<MachineDominatorTree>();
2172 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
2173 Loops = &getAnalysis<MachineLoopInfo>();
2174 Bundles = &getAnalysis<EdgeBundles>();
2175 SpillPlacer = &getAnalysis<SpillPlacement>();
2176 DebugVars = &getAnalysis<LiveDebugVariables>();
2178 calculateSpillWeightsAndHints(*LIS, mf, *Loops, *MBFI);
2182 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
2183 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree, *MBFI));
2184 ExtraRegInfo.clear();
2185 ExtraRegInfo.resize(MRI->getNumVirtRegs());
2187 IntfCache.init(MF, Matrix->getLiveUnions(), Indexes, LIS, TRI);
2188 GlobalCand.resize(32); // This will grow as needed.