1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "LiveIntervalUnion.h"
18 #include "LiveRangeEdit.h"
19 #include "RegAllocBase.h"
21 #include "SpillPlacement.h"
23 #include "VirtRegMap.h"
24 #include "VirtRegRewriter.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Function.h"
27 #include "llvm/PassAnalysisSupport.h"
28 #include "llvm/CodeGen/CalcSpillWeights.h"
29 #include "llvm/CodeGen/EdgeBundles.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineDominators.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineLoopRanges.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/CodeGen/RegisterCoalescer.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Support/Timer.h"
48 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
49 createGreedyRegisterAllocator);
52 class RAGreedy : public MachineFunctionPass, public RegAllocBase {
55 BitVector ReservedRegs;
60 MachineDominatorTree *DomTree;
61 MachineLoopInfo *Loops;
62 MachineLoopRanges *LoopRanges;
64 SpillPlacement *SpillPlacer;
67 std::auto_ptr<Spiller> SpillerInstance;
68 std::auto_ptr<SplitAnalysis> SA;
72 /// All basic blocks where the current register is live.
73 SmallVector<SpillPlacement::BlockConstraint, 8> SpillConstraints;
75 /// Additional information about basic blocks where the current variable is
76 /// live. Such a block will look like one of these templates:
78 /// 1. | o---x | Internal to block. Variable is only live in this block.
79 /// 2. |---x | Live-in, kill.
80 /// 3. | o---| Def, live-out.
81 /// 4. |---x o---| Live-in, kill, def, live-out.
82 /// 5. |---o---o---| Live-through with uses or defs.
83 /// 6. |-----------| Live-through without uses. Transparent.
86 MachineBasicBlock *MBB;
87 SlotIndex FirstUse; ///< First instr using current reg.
88 SlotIndex LastUse; ///< Last instr using current reg.
89 SlotIndex Kill; ///< Interval end point inside block.
90 SlotIndex Def; ///< Interval start point inside block.
91 /// Last possible point for splitting live ranges.
92 SlotIndex LastSplitPoint;
93 bool Uses; ///< Current reg has uses or defs in block.
94 bool LiveThrough; ///< Live in whole block (Templ 5. or 6. above).
95 bool LiveIn; ///< Current reg is live in.
96 bool LiveOut; ///< Current reg is live out.
98 // Per-interference pattern scratch data.
99 bool OverlapEntry; ///< Interference overlaps entering interval.
100 bool OverlapExit; ///< Interference overlaps exiting interval.
103 /// Basic blocks where var is live. This array is parallel to
104 /// SpillConstraints.
105 SmallVector<BlockInfo, 8> LiveBlocks;
110 /// Return the pass name.
111 virtual const char* getPassName() const {
112 return "Greedy Register Allocator";
115 /// RAGreedy analysis usage.
116 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
118 virtual void releaseMemory();
120 virtual Spiller &spiller() { return *SpillerInstance; }
122 virtual float getPriority(LiveInterval *LI);
124 virtual unsigned selectOrSplit(LiveInterval&,
125 SmallVectorImpl<LiveInterval*>&);
127 /// Perform register allocation.
128 virtual bool runOnMachineFunction(MachineFunction &mf);
133 bool checkUncachedInterference(LiveInterval&, unsigned);
134 LiveInterval *getSingleInterference(LiveInterval&, unsigned);
135 bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
136 bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
137 float calcInterferenceWeight(LiveInterval&, unsigned);
138 void calcLiveBlockInfo(LiveInterval&);
139 float calcInterferenceInfo(LiveInterval&, unsigned);
140 float calcGlobalSplitCost(const BitVector&);
141 void splitAroundRegion(LiveInterval&, unsigned, const BitVector&,
142 SmallVectorImpl<LiveInterval*>&);
144 unsigned tryReassign(LiveInterval&, AllocationOrder&);
145 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
146 SmallVectorImpl<LiveInterval*>&);
147 unsigned trySplit(LiveInterval&, AllocationOrder&,
148 SmallVectorImpl<LiveInterval*>&);
149 unsigned trySpillInterferences(LiveInterval&, AllocationOrder&,
150 SmallVectorImpl<LiveInterval*>&);
152 } // end anonymous namespace
154 char RAGreedy::ID = 0;
156 FunctionPass* llvm::createGreedyRegisterAllocator() {
157 return new RAGreedy();
160 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
161 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
162 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
163 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
164 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
165 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
166 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
167 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
168 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
169 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
170 initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
171 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
172 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
173 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
176 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
177 AU.setPreservesCFG();
178 AU.addRequired<AliasAnalysis>();
179 AU.addPreserved<AliasAnalysis>();
180 AU.addRequired<LiveIntervals>();
181 AU.addRequired<SlotIndexes>();
182 AU.addPreserved<SlotIndexes>();
184 AU.addRequiredID(StrongPHIEliminationID);
185 AU.addRequiredTransitive<RegisterCoalescer>();
186 AU.addRequired<CalculateSpillWeights>();
187 AU.addRequired<LiveStacks>();
188 AU.addPreserved<LiveStacks>();
189 AU.addRequired<MachineDominatorTree>();
190 AU.addPreserved<MachineDominatorTree>();
191 AU.addRequired<MachineLoopInfo>();
192 AU.addPreserved<MachineLoopInfo>();
193 AU.addRequired<MachineLoopRanges>();
194 AU.addPreserved<MachineLoopRanges>();
195 AU.addRequired<VirtRegMap>();
196 AU.addPreserved<VirtRegMap>();
197 AU.addRequired<EdgeBundles>();
198 AU.addRequired<SpillPlacement>();
199 MachineFunctionPass::getAnalysisUsage(AU);
202 void RAGreedy::releaseMemory() {
203 SpillerInstance.reset(0);
204 RegAllocBase::releaseMemory();
207 float RAGreedy::getPriority(LiveInterval *LI) {
208 float Priority = LI->weight;
210 // Prioritize hinted registers so they are allocated first.
211 std::pair<unsigned, unsigned> Hint;
212 if (Hint.first || Hint.second) {
213 // The hint can be target specific, a virtual register, or a physreg.
216 // Prefer physreg hints above anything else.
217 if (Hint.first == 0 && TargetRegisterInfo::isPhysicalRegister(Hint.second))
224 //===----------------------------------------------------------------------===//
225 // Register Reassignment
226 //===----------------------------------------------------------------------===//
228 // Check interference without using the cache.
229 bool RAGreedy::checkUncachedInterference(LiveInterval &VirtReg,
231 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
232 LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[*AliasI]);
233 if (subQ.checkInterference())
239 /// getSingleInterference - Return the single interfering virtual register
240 /// assigned to PhysReg. Return 0 if more than one virtual register is
242 LiveInterval *RAGreedy::getSingleInterference(LiveInterval &VirtReg,
244 // Check physreg and aliases.
245 LiveInterval *Interference = 0;
246 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
247 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
248 if (Q.checkInterference()) {
251 Q.collectInterferingVRegs(1);
252 if (!Q.seenAllInterferences())
254 Interference = Q.interferingVRegs().front();
260 // Attempt to reassign this virtual register to a different physical register.
262 // FIXME: we are not yet caching these "second-level" interferences discovered
263 // in the sub-queries. These interferences can change with each call to
264 // selectOrSplit. However, we could implement a "may-interfere" cache that
265 // could be conservatively dirtied when we reassign or split.
267 // FIXME: This may result in a lot of alias queries. We could summarize alias
268 // live intervals in their parent register's live union, but it's messy.
269 bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
270 unsigned WantedPhysReg) {
271 assert(TargetRegisterInfo::isVirtualRegister(InterferingVReg.reg) &&
272 "Can only reassign virtual registers");
273 assert(TRI->regsOverlap(WantedPhysReg, VRM->getPhys(InterferingVReg.reg)) &&
274 "inconsistent phys reg assigment");
276 AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
277 while (unsigned PhysReg = Order.next()) {
278 // Don't reassign to a WantedPhysReg alias.
279 if (TRI->regsOverlap(PhysReg, WantedPhysReg))
282 if (checkUncachedInterference(InterferingVReg, PhysReg))
285 // Reassign the interfering virtual reg to this physical reg.
286 unsigned OldAssign = VRM->getPhys(InterferingVReg.reg);
287 DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
288 TRI->getName(OldAssign) << " to " << TRI->getName(PhysReg) << '\n');
289 PhysReg2LiveUnion[OldAssign].extract(InterferingVReg);
290 VRM->clearVirt(InterferingVReg.reg);
291 VRM->assignVirt2Phys(InterferingVReg.reg, PhysReg);
292 PhysReg2LiveUnion[PhysReg].unify(InterferingVReg);
299 /// reassignInterferences - Reassign all interferences to different physical
300 /// registers such that Virtreg can be assigned to PhysReg.
301 /// Currently this only works with a single interference.
302 /// @param VirtReg Currently unassigned virtual register.
303 /// @param PhysReg Physical register to be cleared.
304 /// @return True on success, false if nothing was changed.
305 bool RAGreedy::reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg) {
306 LiveInterval *InterferingVReg = getSingleInterference(VirtReg, PhysReg);
307 if (!InterferingVReg)
309 if (TargetRegisterInfo::isPhysicalRegister(InterferingVReg->reg))
311 return reassignVReg(*InterferingVReg, PhysReg);
314 /// tryReassign - Try to reassign interferences to different physregs.
315 /// @param VirtReg Currently unassigned virtual register.
316 /// @param Order Physregs to try.
317 /// @return Physreg to assign VirtReg, or 0.
318 unsigned RAGreedy::tryReassign(LiveInterval &VirtReg, AllocationOrder &Order) {
319 NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
321 while (unsigned PhysReg = Order.next())
322 if (reassignInterferences(VirtReg, PhysReg))
328 //===----------------------------------------------------------------------===//
330 //===----------------------------------------------------------------------===//
332 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
333 /// where VirtReg is live.
334 /// The SpillConstraints array is minimally initialized with MBB->getNumber().
335 void RAGreedy::calcLiveBlockInfo(LiveInterval &VirtReg) {
337 SpillConstraints.clear();
339 assert(!VirtReg.empty() && "Cannot allocate an empty interval");
340 LiveInterval::const_iterator LVI = VirtReg.begin();
341 LiveInterval::const_iterator LVE = VirtReg.end();
343 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
344 UseI = SA->UseSlots.begin();
345 UseE = SA->UseSlots.end();
347 // Loop over basic blocks where VirtReg is live.
348 MachineFunction::iterator MFI = Indexes->getMBBFromIndex(LVI->start);
350 // Block constraints depend on the interference pattern.
351 // Just allocate them here, don't compute anything.
352 SpillPlacement::BlockConstraint BC;
353 BC.Number = MFI->getNumber();
354 SpillConstraints.push_back(BC);
358 SlotIndex Start, Stop;
359 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
361 // The last split point is the latest possible insertion point that dominates
362 // all successor blocks. If interference reaches LastSplitPoint, it is not
363 // possible to insert a split or reload that makes VirtReg live in the
365 MachineBasicBlock::iterator LSP = LIS->getLastSplitPoint(VirtReg, BI.MBB);
366 if (LSP == BI.MBB->end())
367 BI.LastSplitPoint = Stop;
369 BI.LastSplitPoint = Indexes->getInstructionIndex(LSP);
371 // LVI is the first live segment overlapping MBB.
372 BI.LiveIn = LVI->start <= Start;
376 // Find the first and last uses in the block.
377 BI.Uses = SA->hasUses(MFI);
378 if (BI.Uses && UseI != UseE) {
380 assert(BI.FirstUse >= Start);
382 while (UseI != UseE && *UseI < Stop);
383 BI.LastUse = UseI[-1];
384 assert(BI.LastUse < Stop);
387 // Look for gaps in the live range.
390 while (LVI->end < Stop) {
391 SlotIndex LastStop = LVI->end;
392 if (++LVI == LVE || LVI->start >= Stop) {
397 if (LastStop < LVI->start) {
404 // Don't set LiveThrough when the block has a gap.
405 BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
406 LiveBlocks.push_back(BI);
408 // LVI is now at LVE or LVI->end >= Stop.
412 // Live segment ends exactly at Stop. Move to the next segment.
413 if (LVI->end == Stop && ++LVI == LVE)
416 // Pick the next basic block.
417 if (LVI->start < Stop)
420 MFI = Indexes->getMBBFromIndex(LVI->start);
424 /// calcInterferenceInfo - Compute per-block outgoing and ingoing constraints
425 /// when considering interference from PhysReg. Also compute an optimistic local
426 /// cost of this interference pattern.
428 /// The final cost of a split is the local cost + global cost of preferences
429 /// broken by SpillPlacement.
431 float RAGreedy::calcInterferenceInfo(LiveInterval &VirtReg, unsigned PhysReg) {
432 // Reset interference dependent info.
433 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
434 BlockInfo &BI = LiveBlocks[i];
435 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
436 BC.Entry = (BI.Uses && BI.LiveIn) ?
437 SpillPlacement::PrefReg : SpillPlacement::DontCare;
438 BC.Exit = (BI.Uses && BI.LiveOut) ?
439 SpillPlacement::PrefReg : SpillPlacement::DontCare;
440 BI.OverlapEntry = BI.OverlapExit = false;
443 // Add interference info from each PhysReg alias.
444 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
445 if (!query(VirtReg, *AI).checkInterference())
447 LiveIntervalUnion::SegmentIter IntI =
448 PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
452 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
453 BlockInfo &BI = LiveBlocks[i];
454 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
455 SlotIndex Start, Stop;
456 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
458 // Skip interference-free blocks.
459 if (IntI.start() >= Stop)
462 // Handle transparent blocks with interference separately.
463 // Transparent blocks never incur any fixed cost.
464 if (BI.LiveThrough && !BI.Uses) {
465 // Check if interference is live-in - force spill.
466 if (BC.Entry != SpillPlacement::MustSpill) {
467 BC.Entry = SpillPlacement::PrefSpill;
468 IntI.advanceTo(Start);
469 if (IntI.valid() && IntI.start() <= Start)
470 BC.Entry = SpillPlacement::MustSpill;
473 // Check if interference is live-out - force spill.
474 if (BC.Exit != SpillPlacement::MustSpill) {
475 BC.Exit = SpillPlacement::PrefSpill;
476 // Any interference overlapping [LastSplitPoint;Stop) forces a spill.
477 IntI.advanceTo(BI.LastSplitPoint.getPrevSlot());
478 if (IntI.valid() && IntI.start() < Stop)
479 BC.Exit = SpillPlacement::MustSpill;
482 // Nothing more to do for this transparent block.
488 // Now we only have blocks with uses left.
489 // Check if the interference overlaps the uses.
490 assert(BI.Uses && "Non-transparent block without any uses");
492 // Check interference on entry.
493 if (BI.LiveIn && BC.Entry != SpillPlacement::MustSpill) {
494 IntI.advanceTo(Start);
498 // Interference is live-in - force spill.
499 if (IntI.start() <= Start)
500 BC.Entry = SpillPlacement::MustSpill;
501 // Not live in, but before the first use.
502 else if (IntI.start() < BI.FirstUse)
503 BC.Entry = SpillPlacement::PrefSpill;
506 // Does interference overlap the uses in the entry segment
508 if (BI.LiveIn && !BI.OverlapEntry) {
509 IntI.advanceTo(BI.FirstUse);
512 // A live-through interval has no kill.
513 // Check [FirstUse;LastUse) instead.
514 if (IntI.start() < (BI.LiveThrough ? BI.LastUse : BI.Kill))
515 BI.OverlapEntry = true;
518 // Does interference overlap the uses in the exit segment [Def;LastUse)?
519 if (BI.LiveOut && !BI.LiveThrough && !BI.OverlapExit) {
520 IntI.advanceTo(BI.Def);
523 if (IntI.start() < BI.LastUse)
524 BI.OverlapExit = true;
527 // Check interference on exit.
528 if (BI.LiveOut && BC.Exit != SpillPlacement::MustSpill) {
529 // Check interference between LastUse and Stop.
530 if (BC.Exit != SpillPlacement::PrefSpill) {
531 IntI.advanceTo(BI.LastUse);
534 if (IntI.start() < Stop)
535 BC.Exit = SpillPlacement::PrefSpill;
537 // Is the interference overlapping the last split point?
538 IntI.advanceTo(BI.LastSplitPoint.getPrevSlot());
541 if (IntI.start() < Stop)
542 BC.Exit = SpillPlacement::MustSpill;
547 // Accumulate a local cost of this interference pattern.
549 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
550 BlockInfo &BI = LiveBlocks[i];
553 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
554 unsigned Inserts = 0;
556 // Do we need spill code for the entry segment?
558 Inserts += BI.OverlapEntry || BC.Entry != SpillPlacement::PrefReg;
560 // For the exit segment?
562 Inserts += BI.OverlapExit || BC.Exit != SpillPlacement::PrefReg;
564 // The local cost of spill code in this block is the block frequency times
565 // the number of spill instructions inserted.
567 LocalCost += Inserts * SpillPlacer->getBlockFrequency(BI.MBB);
569 DEBUG(dbgs() << "Local cost of " << PrintReg(PhysReg, TRI) << " = "
570 << LocalCost << '\n');
574 /// calcGlobalSplitCost - Return the global split cost of following the split
575 /// pattern in LiveBundles. This cost should be added to the local cost of the
576 /// interference pattern in SpillConstraints.
578 float RAGreedy::calcGlobalSplitCost(const BitVector &LiveBundles) {
579 float GlobalCost = 0;
580 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
581 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
582 unsigned Inserts = 0;
583 // Broken entry preference?
584 Inserts += LiveBundles[Bundles->getBundle(BC.Number, 0)] !=
585 (BC.Entry == SpillPlacement::PrefReg);
586 // Broken exit preference?
587 Inserts += LiveBundles[Bundles->getBundle(BC.Number, 1)] !=
588 (BC.Exit == SpillPlacement::PrefReg);
590 GlobalCost += Inserts * SpillPlacer->getBlockFrequency(LiveBlocks[i].MBB);
592 DEBUG(dbgs() << "Global cost = " << GlobalCost << '\n');
596 /// splitAroundRegion - Split VirtReg around the region determined by
597 /// LiveBundles. Make an effort to avoid interference from PhysReg.
599 /// The 'register' interval is going to contain as many uses as possible while
600 /// avoiding interference. The 'stack' interval is the complement constructed by
601 /// SplitEditor. It will contain the rest.
603 void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
604 const BitVector &LiveBundles,
605 SmallVectorImpl<LiveInterval*> &NewVRegs) {
607 dbgs() << "Splitting around region for " << PrintReg(PhysReg, TRI)
609 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
610 dbgs() << " EB#" << i;
614 // First compute interference ranges in the live blocks.
615 typedef std::pair<SlotIndex, SlotIndex> IndexPair;
616 SmallVector<IndexPair, 8> InterferenceRanges;
617 InterferenceRanges.resize(LiveBlocks.size());
618 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
619 if (!query(VirtReg, *AI).checkInterference())
621 LiveIntervalUnion::SegmentIter IntI =
622 PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
625 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
626 const BlockInfo &BI = LiveBlocks[i];
627 IndexPair &IP = InterferenceRanges[i];
628 SlotIndex Start, Stop;
629 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
630 // Skip interference-free blocks.
631 if (IntI.start() >= Stop)
634 // First interference in block.
636 IntI.advanceTo(Start);
639 if (IntI.start() >= Stop)
641 if (!IP.first.isValid() || IntI.start() < IP.first)
642 IP.first = IntI.start();
645 // Last interference in block.
647 IntI.advanceTo(Stop);
648 if (!IntI.valid() || IntI.start() >= Stop)
650 if (IntI.stop() <= Start)
652 if (!IP.second.isValid() || IntI.stop() > IP.second)
653 IP.second = IntI.stop();
658 SmallVector<LiveInterval*, 4> SpillRegs;
659 LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
660 SplitEditor SE(*SA, *LIS, *VRM, *DomTree, LREdit);
662 // Create the main cross-block interval.
665 // First add all defs that are live out of a block.
666 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
667 BlockInfo &BI = LiveBlocks[i];
668 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
669 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
671 // Should the register be live out?
672 if (!BI.LiveOut || !RegOut)
675 IndexPair &IP = InterferenceRanges[i];
676 SlotIndex Start, Stop;
677 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
679 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
680 << Bundles->getBundle(BI.MBB->getNumber(), 1)
681 << " intf [" << IP.first << ';' << IP.second << ')');
683 // The interference interval should either be invalid or overlap MBB.
684 assert((!IP.first.isValid() || IP.first < Stop) && "Bad interference");
685 assert((!IP.second.isValid() || IP.second > Start) && "Bad interference");
687 // Check interference leaving the block.
688 if (!IP.second.isValid()) {
689 // Block is interference-free.
690 DEBUG(dbgs() << ", no interference");
692 assert(BI.LiveThrough && "No uses, but not live through block?");
693 // Block is live-through without interference.
694 DEBUG(dbgs() << ", no uses"
695 << (RegIn ? ", live-through.\n" : ", stack in.\n"));
697 SE.enterIntvAtEnd(*BI.MBB);
700 if (!BI.LiveThrough) {
701 DEBUG(dbgs() << ", not live-through.\n");
702 SE.useIntv(SE.enterIntvBefore(BI.Def), Stop);
706 // Block is live-through, but entry bundle is on the stack.
707 // Reload just before the first use.
708 DEBUG(dbgs() << ", not live-in, enter before first use.\n");
709 SE.useIntv(SE.enterIntvBefore(BI.FirstUse), Stop);
712 DEBUG(dbgs() << ", live-through.\n");
716 // Block has interference.
717 DEBUG(dbgs() << ", interference to " << IP.second);
719 if (!BI.LiveThrough && IP.second <= BI.Def) {
720 // The interference doesn't reach the outgoing segment.
721 DEBUG(dbgs() << " doesn't affect def from " << BI.Def << '\n');
722 SE.useIntv(BI.Def, Stop);
728 // No uses in block, avoid interference by reloading as late as possible.
729 DEBUG(dbgs() << ", no uses.\n");
730 SlotIndex SegStart = SE.enterIntvAtEnd(*BI.MBB);
731 assert(SegStart >= IP.second && "Couldn't avoid interference");
735 if (IP.second.getBoundaryIndex() < BI.LastUse &&
736 IP.second.getBoundaryIndex() <= BI.LastSplitPoint) {
737 // There are interference-free uses at the end of the block.
738 // Find the first use that can get the live-out register.
739 SmallVectorImpl<SlotIndex>::const_iterator UI =
740 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
741 IP.second.getBoundaryIndex());
742 assert(UI != SA->UseSlots.end() && "Couldn't find last use");
744 DEBUG(dbgs() << ", free use at " << Use << ".\n");
745 assert(Use <= BI.LastUse && "Couldn't find last use");
746 SlotIndex SegStart = SE.enterIntvBefore(Use);
747 assert(SegStart >= IP.second && "Couldn't avoid interference");
748 assert(SegStart < BI.LastSplitPoint && "Impossible split point");
749 SE.useIntv(SegStart, Stop);
753 // Interference is after the last use.
754 DEBUG(dbgs() << " after last use.\n");
755 SlotIndex SegStart = SE.enterIntvAtEnd(*BI.MBB);
756 assert(SegStart >= IP.second && "Couldn't avoid interference");
759 // Now all defs leading to live bundles are handled, do everything else.
760 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
761 BlockInfo &BI = LiveBlocks[i];
762 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
763 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
765 // Is the register live-in?
766 if (!BI.LiveIn || !RegIn)
769 // We have an incoming register. Check for interference.
770 IndexPair &IP = InterferenceRanges[i];
771 SlotIndex Start, Stop;
772 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
774 DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
775 << " -> BB#" << BI.MBB->getNumber());
777 // Check interference entering the block.
778 if (!IP.first.isValid()) {
779 // Block is interference-free.
780 DEBUG(dbgs() << ", no interference");
782 assert(BI.LiveThrough && "No uses, but not live through block?");
783 // Block is live-through without interference.
785 DEBUG(dbgs() << ", no uses, live-through.\n");
786 SE.useIntv(Start, Stop);
788 DEBUG(dbgs() << ", no uses, stack-out.\n");
789 SE.leaveIntvAtTop(*BI.MBB);
793 if (!BI.LiveThrough) {
794 DEBUG(dbgs() << ", killed in block.\n");
795 SE.useIntv(Start, SE.leaveIntvAfter(BI.Kill));
799 // Block is live-through, but exit bundle is on the stack.
800 // Spill immediately after the last use.
801 if (BI.LastUse < BI.LastSplitPoint) {
802 DEBUG(dbgs() << ", uses, stack-out.\n");
803 SE.useIntv(Start, SE.leaveIntvAfter(BI.LastUse));
806 // The last use is after the last split point, it is probably an
808 DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point "
809 << BI.LastSplitPoint << ", stack-out.\n");
811 // Find the last real instruction before the split point.
812 MachineBasicBlock::iterator SplitI =
813 LIS->getInstructionFromIndex(BI.LastSplitPoint);
814 MachineBasicBlock::iterator I = SplitI, B = BI.MBB->begin();
815 while (I != B && (--I)->isDebugValue())
818 SegEnd = SE.leaveIntvAtTop(*BI.MBB);
820 SegEnd = SE.leaveIntvAfter(LIS->getInstructionIndex(I));
821 SE.useIntv(Start, SegEnd);
823 // Run a double interval from the split to the last use.
824 // This makes it possible to spill the complement without affecting the
826 SE.overlapIntv(SegEnd, BI.LastUse);
829 // Register is live-through.
830 DEBUG(dbgs() << ", uses, live-through.\n");
831 SE.useIntv(Start, Stop);
835 // Block has interference.
836 DEBUG(dbgs() << ", interference from " << IP.first);
838 if (!BI.LiveThrough && IP.first >= BI.Kill) {
839 // The interference doesn't reach the outgoing segment.
840 DEBUG(dbgs() << " doesn't affect kill at " << BI.Kill << '\n');
841 SE.useIntv(Start, BI.Kill);
846 // No uses in block, avoid interference by spilling as soon as possible.
847 DEBUG(dbgs() << ", no uses.\n");
848 SlotIndex SegEnd = SE.leaveIntvAtTop(*BI.MBB);
849 assert(SegEnd <= IP.first && "Couldn't avoid interference");
852 if (IP.first.getBaseIndex() > BI.FirstUse) {
853 // There are interference-free uses at the beginning of the block.
854 // Find the last use that can get the register.
855 SmallVectorImpl<SlotIndex>::const_iterator UI =
856 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
857 IP.first.getBaseIndex());
858 assert(UI != SA->UseSlots.begin() && "Couldn't find first use");
859 SlotIndex Use = (--UI)->getBoundaryIndex();
860 DEBUG(dbgs() << ", free use at " << *UI << ".\n");
861 SlotIndex SegEnd = SE.leaveIntvAfter(Use);
862 assert(SegEnd <= IP.first && "Couldn't avoid interference");
863 SE.useIntv(Start, SegEnd);
867 // Interference is before the first use.
868 DEBUG(dbgs() << " before first use.\n");
869 SlotIndex SegEnd = SE.leaveIntvAtTop(*BI.MBB);
870 assert(SegEnd <= IP.first && "Couldn't avoid interference");
875 // FIXME: Should we be more aggressive about splitting the stack region into
876 // per-block segments? The current approach allows the stack region to
877 // separate into connected components. Some components may be allocatable.
881 MF->verify(this, "After splitting live range around region");
884 // Make sure that at least one of the new intervals can allocate to PhysReg.
885 // That was the whole point of splitting the live range.
887 for (LiveRangeEdit::iterator I = LREdit.begin(), E = LREdit.end(); I != E;
889 if (!checkUncachedInterference(**I, PhysReg)) {
893 assert(found && "No allocatable intervals after pointless splitting");
898 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
899 SmallVectorImpl<LiveInterval*> &NewVRegs) {
900 calcLiveBlockInfo(VirtReg);
901 BitVector LiveBundles, BestBundles;
903 unsigned BestReg = 0;
905 while (unsigned PhysReg = Order.next()) {
906 float Cost = calcInterferenceInfo(VirtReg, PhysReg);
907 if (BestReg && Cost >= BestCost)
910 SpillPlacer->placeSpills(SpillConstraints, LiveBundles);
911 // No live bundles, defer to splitSingleBlocks().
912 if (!LiveBundles.any())
915 Cost += calcGlobalSplitCost(LiveBundles);
916 if (!BestReg || Cost < BestCost) {
919 BestBundles.swap(LiveBundles);
926 splitAroundRegion(VirtReg, BestReg, BestBundles, NewVRegs);
931 //===----------------------------------------------------------------------===//
932 // Live Range Splitting
933 //===----------------------------------------------------------------------===//
935 /// trySplit - Try to split VirtReg or one of its interferences, making it
937 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
938 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
939 SmallVectorImpl<LiveInterval*>&NewVRegs) {
940 NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
941 SA->analyze(&VirtReg);
943 // Don't attempt splitting on local intervals for now. TBD.
944 if (LIS->intervalIsInOneMBB(VirtReg))
947 // First try to split around a region spanning multiple blocks.
948 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
949 if (PhysReg || !NewVRegs.empty())
952 // Then isolate blocks with multiple uses.
953 SplitAnalysis::BlockPtrSet Blocks;
954 if (SA->getMultiUseBlocks(Blocks)) {
955 SmallVector<LiveInterval*, 4> SpillRegs;
956 LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
957 SplitEditor(*SA, *LIS, *VRM, *DomTree, LREdit).splitSingleBlocks(Blocks);
959 MF->verify(this, "After splitting live range around basic blocks");
962 // Don't assign any physregs.
967 //===----------------------------------------------------------------------===//
969 //===----------------------------------------------------------------------===//
971 /// calcInterferenceWeight - Calculate the combined spill weight of
972 /// interferences when assigning VirtReg to PhysReg.
973 float RAGreedy::calcInterferenceWeight(LiveInterval &VirtReg, unsigned PhysReg){
975 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
976 LiveIntervalUnion::Query &Q = query(VirtReg, *AI);
977 Q.collectInterferingVRegs();
978 if (Q.seenUnspillableVReg())
980 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i)
981 Sum += Q.interferingVRegs()[i]->weight;
986 /// trySpillInterferences - Try to spill interfering registers instead of the
987 /// current one. Only do it if the accumulated spill weight is smaller than the
988 /// current spill weight.
989 unsigned RAGreedy::trySpillInterferences(LiveInterval &VirtReg,
990 AllocationOrder &Order,
991 SmallVectorImpl<LiveInterval*> &NewVRegs) {
992 NamedRegionTimer T("Spill Interference", TimerGroupName, TimePassesIsEnabled);
993 unsigned BestPhys = 0;
994 float BestWeight = 0;
997 while (unsigned PhysReg = Order.next()) {
998 float Weight = calcInterferenceWeight(VirtReg, PhysReg);
999 if (Weight == HUGE_VALF || Weight >= VirtReg.weight)
1001 if (!BestPhys || Weight < BestWeight)
1002 BestPhys = PhysReg, BestWeight = Weight;
1005 // No candidates found.
1009 // Collect all interfering registers.
1010 SmallVector<LiveInterval*, 8> Spills;
1011 for (const unsigned *AI = TRI->getOverlaps(BestPhys); *AI; ++AI) {
1012 LiveIntervalUnion::Query &Q = query(VirtReg, *AI);
1013 Spills.append(Q.interferingVRegs().begin(), Q.interferingVRegs().end());
1014 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
1015 LiveInterval *VReg = Q.interferingVRegs()[i];
1016 PhysReg2LiveUnion[*AI].extract(*VReg);
1017 VRM->clearVirt(VReg->reg);
1022 DEBUG(dbgs() << "spilling " << Spills.size() << " interferences with weight "
1023 << BestWeight << '\n');
1024 for (unsigned i = 0, e = Spills.size(); i != e; ++i)
1025 spiller().spill(Spills[i], NewVRegs, Spills);
1030 //===----------------------------------------------------------------------===//
1032 //===----------------------------------------------------------------------===//
1034 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1035 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1036 // First try assigning a free register.
1037 AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
1038 while (unsigned PhysReg = Order.next()) {
1039 if (!checkPhysRegInterference(VirtReg, PhysReg))
1043 // Try to reassign interferences.
1044 if (unsigned PhysReg = tryReassign(VirtReg, Order))
1047 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1049 // Try splitting VirtReg or interferences.
1050 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1051 if (PhysReg || !NewVRegs.empty())
1054 // Try to spill another interfering reg with less spill weight.
1055 PhysReg = trySpillInterferences(VirtReg, Order, NewVRegs);
1059 // Finally spill VirtReg itself.
1060 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1061 SmallVector<LiveInterval*, 1> pendingSpills;
1062 spiller().spill(&VirtReg, NewVRegs, pendingSpills);
1064 // The live virtual register requesting allocation was spilled, so tell
1065 // the caller not to allocate anything during this round.
1069 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1070 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1071 << "********** Function: "
1072 << ((Value*)mf.getFunction())->getName() << '\n');
1076 MF->verify(this, "Before greedy register allocator");
1078 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1079 Indexes = &getAnalysis<SlotIndexes>();
1080 DomTree = &getAnalysis<MachineDominatorTree>();
1081 ReservedRegs = TRI->getReservedRegs(*MF);
1082 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1083 Loops = &getAnalysis<MachineLoopInfo>();
1084 LoopRanges = &getAnalysis<MachineLoopRanges>();
1085 Bundles = &getAnalysis<EdgeBundles>();
1086 SpillPlacer = &getAnalysis<SpillPlacement>();
1088 SA.reset(new SplitAnalysis(*MF, *LIS, *Loops));
1092 LIS->addKillFlags();
1096 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1097 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
1098 rewriter->runOnMachineFunction(*MF, *VRM, LIS);
1101 // The pass output is in VirtRegMap. Release all the transient data.