1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "RegAllocBase.h"
17 #include "LiveDebugVariables.h"
18 #include "LiveIntervalUnion.h"
19 #include "LiveRangeEdit.h"
20 #include "RenderMachineFunction.h"
22 #include "VirtRegMap.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Function.h"
27 #include "llvm/PassAnalysisSupport.h"
28 #include "llvm/CodeGen/CalcSpillWeights.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/CodeGen/LiveStackAnalysis.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/RegAllocRegistry.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/ADT/SparseBitVector.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/Support/Timer.h"
53 STATISTIC(NumAssigned , "Number of registers assigned");
54 STATISTIC(NumUnassigned , "Number of registers unassigned");
55 STATISTIC(NumNewQueued , "Number of new live ranges queued");
57 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
58 createBasicRegisterAllocator);
60 // Temporary verification option until we can put verification inside
62 static cl::opt<bool, true>
63 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
64 cl::desc("Verify during register allocation"));
66 const char *RegAllocBase::TimerGroupName = "Register Allocation";
67 bool RegAllocBase::VerifyEnabled = false;
70 struct CompSpillWeight {
71 bool operator()(LiveInterval *A, LiveInterval *B) const {
72 return A->weight < B->weight;
78 /// RABasic provides a minimal implementation of the basic register allocation
79 /// algorithm. It prioritizes live virtual registers by spill weight and spills
80 /// whenever a register is unavailable. This is not practical in production but
81 /// provides a useful baseline both for measuring other allocators and comparing
82 /// the speed of the basic algorithm against other styles of allocators.
83 class RABasic : public MachineFunctionPass, public RegAllocBase
90 RenderMachineFunction *RMF;
93 std::auto_ptr<Spiller> SpillerInstance;
94 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
95 CompSpillWeight> Queue;
99 /// Return the pass name.
100 virtual const char* getPassName() const {
101 return "Basic Register Allocator";
104 /// RABasic analysis usage.
105 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
107 virtual void releaseMemory();
109 virtual Spiller &spiller() { return *SpillerInstance; }
111 virtual float getPriority(LiveInterval *LI) { return LI->weight; }
113 virtual void enqueue(LiveInterval *LI) {
117 virtual LiveInterval *dequeue() {
120 LiveInterval *LI = Queue.top();
125 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
126 SmallVectorImpl<LiveInterval*> &SplitVRegs);
128 /// Perform register allocation.
129 virtual bool runOnMachineFunction(MachineFunction &mf);
134 char RABasic::ID = 0;
136 } // end anonymous namespace
138 RABasic::RABasic(): MachineFunctionPass(ID) {
139 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
140 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
141 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
142 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
143 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
144 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
145 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
146 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
147 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
148 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
149 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
152 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
153 AU.setPreservesCFG();
154 AU.addRequired<AliasAnalysis>();
155 AU.addPreserved<AliasAnalysis>();
156 AU.addRequired<LiveIntervals>();
157 AU.addPreserved<SlotIndexes>();
158 AU.addRequired<LiveDebugVariables>();
159 AU.addPreserved<LiveDebugVariables>();
161 AU.addRequiredID(StrongPHIEliminationID);
162 AU.addRequiredTransitiveID(RegisterCoalescerPassID);
163 AU.addRequired<CalculateSpillWeights>();
164 AU.addRequired<LiveStacks>();
165 AU.addPreserved<LiveStacks>();
166 AU.addRequiredID(MachineDominatorsID);
167 AU.addPreservedID(MachineDominatorsID);
168 AU.addRequired<MachineLoopInfo>();
169 AU.addPreserved<MachineLoopInfo>();
170 AU.addRequired<VirtRegMap>();
171 AU.addPreserved<VirtRegMap>();
172 DEBUG(AU.addRequired<RenderMachineFunction>());
173 MachineFunctionPass::getAnalysisUsage(AU);
176 void RABasic::releaseMemory() {
177 SpillerInstance.reset(0);
178 RegAllocBase::releaseMemory();
182 // Verify each LiveIntervalUnion.
183 void RegAllocBase::verify() {
184 LiveVirtRegBitSet VisitedVRegs;
185 OwningArrayPtr<LiveVirtRegBitSet>
186 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
188 // Verify disjoint unions.
189 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
190 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
191 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
192 PhysReg2LiveUnion[PhysReg].verify(VRegs);
193 // Union + intersection test could be done efficiently in one pass, but
194 // don't add a method to SparseBitVector unless we really need it.
195 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
196 VisitedVRegs |= VRegs;
199 // Verify vreg coverage.
200 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
201 liItr != liEnd; ++liItr) {
202 unsigned reg = liItr->first;
203 if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
204 if (!VRM->hasPhys(reg)) continue; // spilled?
205 unsigned PhysReg = VRM->getPhys(reg);
206 if (!unionVRegs[PhysReg].test(reg)) {
207 dbgs() << "LiveVirtReg " << reg << " not in union " <<
208 TRI->getName(PhysReg) << "\n";
209 llvm_unreachable("unallocated live vreg");
212 // FIXME: I'm not sure how to verify spilled intervals.
216 //===----------------------------------------------------------------------===//
217 // RegAllocBase Implementation
218 //===----------------------------------------------------------------------===//
220 // Instantiate a LiveIntervalUnion for each physical register.
221 void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
225 static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
226 for (unsigned r = 0; r != NRegs; ++r)
227 new(Array + r) LiveIntervalUnion(r, allocator);
230 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
231 NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
232 TRI = &vrm.getTargetRegInfo();
233 MRI = &vrm.getRegInfo();
236 MRI->freezeReservedRegs(vrm.getMachineFunction());
237 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
239 const unsigned NumRegs = TRI->getNumRegs();
240 if (NumRegs != PhysReg2LiveUnion.numRegs()) {
241 PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
242 // Cache an interferece query for each physical reg
243 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
247 void RegAllocBase::LiveUnionArray::clear() {
250 for (unsigned r = 0; r != NumRegs; ++r)
251 Array[r].~LiveIntervalUnion();
257 void RegAllocBase::releaseMemory() {
258 for (unsigned r = 0, e = PhysReg2LiveUnion.numRegs(); r != e; ++r)
259 PhysReg2LiveUnion[r].clear();
262 // Visit all the live registers. If they are already assigned to a physical
263 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
264 // them on the priority queue for later assignment.
265 void RegAllocBase::seedLiveRegs() {
266 NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled);
267 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
268 unsigned RegNum = I->first;
269 LiveInterval &VirtReg = *I->second;
270 if (TargetRegisterInfo::isPhysicalRegister(RegNum))
271 PhysReg2LiveUnion[RegNum].unify(VirtReg);
277 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
278 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
279 << " to " << PrintReg(PhysReg, TRI) << '\n');
280 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
281 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
282 MRI->setPhysRegUsed(PhysReg);
283 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
287 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
288 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
289 << " from " << PrintReg(PhysReg, TRI) << '\n');
290 assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
291 PhysReg2LiveUnion[PhysReg].extract(VirtReg);
292 VRM->clearVirt(VirtReg.reg);
296 // Top-level driver to manage the queue of unassigned VirtRegs and call the
297 // selectOrSplit implementation.
298 void RegAllocBase::allocatePhysRegs() {
301 // Continue assigning vregs one at a time to available physical registers.
302 while (LiveInterval *VirtReg = dequeue()) {
303 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
305 // Unused registers can appear when the spiller coalesces snippets.
306 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
307 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
308 LIS->removeInterval(VirtReg->reg);
312 // Invalidate all interference queries, live ranges could have changed.
313 invalidateVirtRegs();
315 // selectOrSplit requests the allocator to return an available physical
316 // register if possible and populate a list of new live intervals that
317 // result from splitting.
318 DEBUG(dbgs() << "\nselectOrSplit "
319 << MRI->getRegClass(VirtReg->reg)->getName()
320 << ':' << *VirtReg << '\n');
321 typedef SmallVector<LiveInterval*, 4> VirtRegVec;
322 VirtRegVec SplitVRegs;
323 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
325 if (AvailablePhysReg == ~0u) {
326 // selectOrSplit failed to find a register!
327 const char *Msg = "ran out of registers during register allocation";
328 // Probably caused by an inline asm.
330 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
331 (MI = I.skipInstruction());)
332 if (MI->isInlineAsm())
337 report_fatal_error(Msg);
338 // Keep going after reporting the error.
339 VRM->assignVirt2Phys(VirtReg->reg,
340 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
344 if (AvailablePhysReg)
345 assign(*VirtReg, AvailablePhysReg);
347 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
349 LiveInterval *SplitVirtReg = *I;
350 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
351 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
352 DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
353 LIS->removeInterval(SplitVirtReg->reg);
356 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
357 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
358 "expect split value in virtual register");
359 enqueue(SplitVirtReg);
365 // Check if this live virtual register interferes with a physical register. If
366 // not, then check for interference on each register that aliases with the
367 // physical register. Return the interfering register.
368 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
370 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
371 if (query(VirtReg, *AliasI).checkInterference())
376 // Helper for spillInteferences() that spills all interfering vregs currently
377 // assigned to this physical register.
378 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
379 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
380 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
381 assert(Q.seenAllInterferences() && "need collectInterferences()");
382 const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
384 for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
385 E = PendingSpills.end(); I != E; ++I) {
386 LiveInterval &SpilledVReg = **I;
387 DEBUG(dbgs() << "extracting from " <<
388 TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
390 // Deallocate the interfering vreg by removing it from the union.
391 // A LiveInterval instance may not be in a union during modification!
392 unassign(SpilledVReg, PhysReg);
394 // Spill the extracted interval.
395 LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills);
396 spiller().spill(LRE);
398 // After extracting segments, the query's results are invalid. But keep the
399 // contents valid until we're done accessing pendingSpills.
403 // Spill or split all live virtual registers currently unified under PhysReg
404 // that interfere with VirtReg. The newly spilled or split live intervals are
405 // returned by appending them to SplitVRegs.
407 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
408 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
409 // Record each interference and determine if all are spillable before mutating
410 // either the union or live intervals.
411 unsigned NumInterferences = 0;
412 // Collect interferences assigned to any alias of the physical register.
413 for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
414 LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
415 NumInterferences += QAlias.collectInterferingVRegs();
416 if (QAlias.seenUnspillableVReg()) {
420 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
421 " interferences with " << VirtReg << "\n");
422 assert(NumInterferences > 0 && "expect interference");
424 // Spill each interfering vreg allocated to PhysReg or an alias.
425 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
426 spillReg(VirtReg, *AliasI, SplitVRegs);
430 // Add newly allocated physical registers to the MBB live in sets.
431 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
432 NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
433 SlotIndexes *Indexes = LIS->getSlotIndexes();
437 LiveIntervalUnion::SegmentIter SI;
438 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
439 LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
440 if (LiveUnion.empty())
442 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " live-in:");
443 MachineFunction::iterator MBB = llvm::next(MF->begin());
444 MachineFunction::iterator MFE = MF->end();
445 SlotIndex Start, Stop;
446 tie(Start, Stop) = Indexes->getMBBRange(MBB);
447 SI.setMap(LiveUnion.getMap());
450 if (SI.start() <= Start) {
451 if (!MBB->isLiveIn(PhysReg))
452 MBB->addLiveIn(PhysReg);
453 DEBUG(dbgs() << "\tBB#" << MBB->getNumber() << ':'
454 << PrintReg(SI.value()->reg, TRI));
455 } else if (SI.start() > Stop)
456 MBB = Indexes->getMBBFromIndex(SI.start().getPrevIndex());
459 tie(Start, Stop) = Indexes->getMBBRange(MBB);
462 DEBUG(dbgs() << '\n');
467 //===----------------------------------------------------------------------===//
468 // RABasic Implementation
469 //===----------------------------------------------------------------------===//
471 // Driver for the register assignment and splitting heuristics.
472 // Manages iteration over the LiveIntervalUnions.
474 // This is a minimal implementation of register assignment and splitting that
475 // spills whenever we run out of registers.
477 // selectOrSplit can only be called once per live virtual register. We then do a
478 // single interference test for each register the correct class until we find an
479 // available register. So, the number of interference tests in the worst case is
480 // |vregs| * |machineregs|. And since the number of interference tests is
481 // minimal, there is no value in caching them outside the scope of
483 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
484 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
485 // Populate a list of physical register spill candidates.
486 SmallVector<unsigned, 8> PhysRegSpillCands;
488 // Check for an available register in this class.
489 ArrayRef<unsigned> Order =
490 RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg));
491 for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E;
493 unsigned PhysReg = *I;
495 // Check interference and as a side effect, intialize queries for this
496 // VirtReg and its aliases.
497 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
498 if (interfReg == 0) {
499 // Found an available register.
502 Queries[interfReg].collectInterferingVRegs(1);
503 LiveInterval *interferingVirtReg =
504 Queries[interfReg].interferingVRegs().front();
506 // The current VirtReg must either be spillable, or one of its interferences
507 // must have less spill weight.
508 if (interferingVirtReg->weight < VirtReg.weight ) {
509 PhysRegSpillCands.push_back(PhysReg);
512 // Try to spill another interfering reg with less spill weight.
513 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
514 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
516 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
518 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
519 "Interference after spill.");
520 // Tell the caller to allocate to this newly freed physical register.
524 // No other spill candidates were found, so spill the current VirtReg.
525 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
526 if (!VirtReg.isSpillable())
528 LiveRangeEdit LRE(VirtReg, SplitVRegs);
529 spiller().spill(LRE);
531 // The live virtual register requesting allocation was spilled, so tell
532 // the caller not to allocate anything during this round.
536 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
537 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
538 << "********** Function: "
539 << ((Value*)mf.getFunction())->getName() << '\n');
542 DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
544 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
545 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
551 // Diagnostic output before rewriting
552 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
554 // optional HTML output
555 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
557 // FIXME: Verification currently must run before VirtRegRewriter. We should
558 // make the rewriter a separate pass and override verifyAnalysis instead. When
559 // that happens, verification naturally falls under VerifyMachineCode.
562 // Verify accuracy of LiveIntervals. The standard machine code verifier
563 // ensures that each LiveIntervals covers all uses of the virtual reg.
565 // FIXME: MachineVerifier is badly broken when using the standard
566 // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
567 // inline spiller, some tests fail to verify because the coalescer does not
568 // always generate verifiable code.
569 MF->verify(this, "In RABasic::verify");
571 // Verify that LiveIntervals are partitioned into unions and disjoint within
578 VRM->rewrite(LIS->getSlotIndexes());
580 // Write out new DBG_VALUE instructions.
581 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
583 // The pass output is in VirtRegMap. Release all the transient data.
589 FunctionPass* llvm::createBasicRegisterAllocator()
591 return new RABasic();