1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "LiveDebugVariables.h"
17 #include "LiveIntervalUnion.h"
18 #include "LiveRangeEdit.h"
19 #include "RegAllocBase.h"
20 #include "RenderMachineFunction.h"
22 #include "VirtRegMap.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Function.h"
27 #include "llvm/PassAnalysisSupport.h"
28 #include "llvm/CodeGen/CalcSpillWeights.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/CodeGen/LiveStackAnalysis.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/RegAllocRegistry.h"
37 #include "llvm/CodeGen/RegisterCoalescer.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/ADT/SparseBitVector.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/raw_ostream.h"
47 #include "llvm/Support/Timer.h"
54 STATISTIC(NumAssigned , "Number of registers assigned");
55 STATISTIC(NumUnassigned , "Number of registers unassigned");
56 STATISTIC(NumNewQueued , "Number of new live ranges queued");
58 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
59 createBasicRegisterAllocator);
61 // Temporary verification option until we can put verification inside
63 static cl::opt<bool, true>
64 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
65 cl::desc("Verify during register allocation"));
67 const char *RegAllocBase::TimerGroupName = "Register Allocation";
68 bool RegAllocBase::VerifyEnabled = false;
71 struct CompSpillWeight {
72 bool operator()(LiveInterval *A, LiveInterval *B) const {
73 return A->weight < B->weight;
79 /// RABasic provides a minimal implementation of the basic register allocation
80 /// algorithm. It prioritizes live virtual registers by spill weight and spills
81 /// whenever a register is unavailable. This is not practical in production but
82 /// provides a useful baseline both for measuring other allocators and comparing
83 /// the speed of the basic algorithm against other styles of allocators.
84 class RABasic : public MachineFunctionPass, public RegAllocBase
88 BitVector ReservedRegs;
92 RenderMachineFunction *RMF;
95 std::auto_ptr<Spiller> SpillerInstance;
96 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
97 CompSpillWeight> Queue;
101 /// Return the pass name.
102 virtual const char* getPassName() const {
103 return "Basic Register Allocator";
106 /// RABasic analysis usage.
107 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
109 virtual void releaseMemory();
111 virtual Spiller &spiller() { return *SpillerInstance; }
113 virtual float getPriority(LiveInterval *LI) { return LI->weight; }
115 virtual void enqueue(LiveInterval *LI) {
119 virtual LiveInterval *dequeue() {
122 LiveInterval *LI = Queue.top();
127 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
128 SmallVectorImpl<LiveInterval*> &SplitVRegs);
130 /// Perform register allocation.
131 virtual bool runOnMachineFunction(MachineFunction &mf);
136 char RABasic::ID = 0;
138 } // end anonymous namespace
140 RABasic::RABasic(): MachineFunctionPass(ID) {
141 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
142 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
143 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
144 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
145 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
146 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
147 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
148 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
149 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
150 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
151 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
154 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
155 AU.setPreservesCFG();
156 AU.addRequired<AliasAnalysis>();
157 AU.addPreserved<AliasAnalysis>();
158 AU.addRequired<LiveIntervals>();
159 AU.addPreserved<SlotIndexes>();
160 AU.addRequired<LiveDebugVariables>();
161 AU.addPreserved<LiveDebugVariables>();
163 AU.addRequiredID(StrongPHIEliminationID);
164 AU.addRequiredTransitive<RegisterCoalescer>();
165 AU.addRequired<CalculateSpillWeights>();
166 AU.addRequired<LiveStacks>();
167 AU.addPreserved<LiveStacks>();
168 AU.addRequiredID(MachineDominatorsID);
169 AU.addPreservedID(MachineDominatorsID);
170 AU.addRequired<MachineLoopInfo>();
171 AU.addPreserved<MachineLoopInfo>();
172 AU.addRequired<VirtRegMap>();
173 AU.addPreserved<VirtRegMap>();
174 DEBUG(AU.addRequired<RenderMachineFunction>());
175 MachineFunctionPass::getAnalysisUsage(AU);
178 void RABasic::releaseMemory() {
179 SpillerInstance.reset(0);
180 RegAllocBase::releaseMemory();
184 // Verify each LiveIntervalUnion.
185 void RegAllocBase::verify() {
186 LiveVirtRegBitSet VisitedVRegs;
187 OwningArrayPtr<LiveVirtRegBitSet>
188 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
190 // Verify disjoint unions.
191 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
192 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
193 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
194 PhysReg2LiveUnion[PhysReg].verify(VRegs);
195 // Union + intersection test could be done efficiently in one pass, but
196 // don't add a method to SparseBitVector unless we really need it.
197 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
198 VisitedVRegs |= VRegs;
201 // Verify vreg coverage.
202 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
203 liItr != liEnd; ++liItr) {
204 unsigned reg = liItr->first;
205 if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
206 if (!VRM->hasPhys(reg)) continue; // spilled?
207 unsigned PhysReg = VRM->getPhys(reg);
208 if (!unionVRegs[PhysReg].test(reg)) {
209 dbgs() << "LiveVirtReg " << reg << " not in union " <<
210 TRI->getName(PhysReg) << "\n";
211 llvm_unreachable("unallocated live vreg");
214 // FIXME: I'm not sure how to verify spilled intervals.
218 //===----------------------------------------------------------------------===//
219 // RegAllocBase Implementation
220 //===----------------------------------------------------------------------===//
222 // Instantiate a LiveIntervalUnion for each physical register.
223 void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
227 static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
228 for (unsigned r = 0; r != NRegs; ++r)
229 new(Array + r) LiveIntervalUnion(r, allocator);
232 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
233 NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
234 TRI = &vrm.getTargetRegInfo();
235 MRI = &vrm.getRegInfo();
238 PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
239 // Cache an interferece query for each physical reg
240 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
243 void RegAllocBase::LiveUnionArray::clear() {
246 for (unsigned r = 0; r != NumRegs; ++r)
247 Array[r].~LiveIntervalUnion();
253 void RegAllocBase::releaseMemory() {
254 PhysReg2LiveUnion.clear();
257 // Visit all the live registers. If they are already assigned to a physical
258 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
259 // them on the priority queue for later assignment.
260 void RegAllocBase::seedLiveRegs() {
261 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
262 unsigned RegNum = I->first;
263 LiveInterval &VirtReg = *I->second;
264 if (TargetRegisterInfo::isPhysicalRegister(RegNum))
265 PhysReg2LiveUnion[RegNum].unify(VirtReg);
271 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
272 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
273 << " to " << PrintReg(PhysReg, TRI) << '\n');
274 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
275 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
276 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
280 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
281 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
282 << " from " << PrintReg(PhysReg, TRI) << '\n');
283 assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
284 PhysReg2LiveUnion[PhysReg].extract(VirtReg);
285 VRM->clearVirt(VirtReg.reg);
289 // Top-level driver to manage the queue of unassigned VirtRegs and call the
290 // selectOrSplit implementation.
291 void RegAllocBase::allocatePhysRegs() {
294 // Continue assigning vregs one at a time to available physical registers.
295 while (LiveInterval *VirtReg = dequeue()) {
296 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
298 // Unused registers can appear when the spiller coalesces snippets.
299 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
300 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
301 LIS->removeInterval(VirtReg->reg);
305 // Invalidate all interference queries, live ranges could have changed.
308 // selectOrSplit requests the allocator to return an available physical
309 // register if possible and populate a list of new live intervals that
310 // result from splitting.
311 DEBUG(dbgs() << "\nselectOrSplit "
312 << MRI->getRegClass(VirtReg->reg)->getName()
313 << ':' << *VirtReg << '\n');
314 typedef SmallVector<LiveInterval*, 4> VirtRegVec;
315 VirtRegVec SplitVRegs;
316 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
318 if (AvailablePhysReg)
319 assign(*VirtReg, AvailablePhysReg);
321 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
323 LiveInterval *SplitVirtReg = *I;
324 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
325 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
326 DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
327 LIS->removeInterval(SplitVirtReg->reg);
330 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
331 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
332 "expect split value in virtual register");
333 enqueue(SplitVirtReg);
339 // Check if this live virtual register interferes with a physical register. If
340 // not, then check for interference on each register that aliases with the
341 // physical register. Return the interfering register.
342 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
344 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
345 if (query(VirtReg, *AliasI).checkInterference())
350 // Helper for spillInteferences() that spills all interfering vregs currently
351 // assigned to this physical register.
352 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
353 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
354 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
355 assert(Q.seenAllInterferences() && "need collectInterferences()");
356 const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
358 for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
359 E = PendingSpills.end(); I != E; ++I) {
360 LiveInterval &SpilledVReg = **I;
361 DEBUG(dbgs() << "extracting from " <<
362 TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
364 // Deallocate the interfering vreg by removing it from the union.
365 // A LiveInterval instance may not be in a union during modification!
366 unassign(SpilledVReg, PhysReg);
368 // Spill the extracted interval.
369 LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills);
370 spiller().spill(LRE);
372 // After extracting segments, the query's results are invalid. But keep the
373 // contents valid until we're done accessing pendingSpills.
377 // Spill or split all live virtual registers currently unified under PhysReg
378 // that interfere with VirtReg. The newly spilled or split live intervals are
379 // returned by appending them to SplitVRegs.
381 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
382 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
383 // Record each interference and determine if all are spillable before mutating
384 // either the union or live intervals.
385 unsigned NumInterferences = 0;
386 // Collect interferences assigned to any alias of the physical register.
387 for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
388 LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
389 NumInterferences += QAlias.collectInterferingVRegs();
390 if (QAlias.seenUnspillableVReg()) {
394 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
395 " interferences with " << VirtReg << "\n");
396 assert(NumInterferences > 0 && "expect interference");
398 // Spill each interfering vreg allocated to PhysReg or an alias.
399 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
400 spillReg(VirtReg, *AliasI, SplitVRegs);
404 // Add newly allocated physical registers to the MBB live in sets.
405 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
406 NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
407 typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
409 MachineBasicBlock &entryMBB = *MF->begin();
411 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
412 LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
413 if (LiveUnion.empty())
415 for (LiveIntervalUnion::SegmentIter SI = LiveUnion.begin(); SI.valid();
418 // Find the set of basic blocks which this range is live into...
420 if (!LIS->findLiveInMBBs(SI.start(), SI.stop(), liveInMBBs)) continue;
422 // And add the physreg for this interval to their live-in sets.
423 for (MBBVec::iterator I = liveInMBBs.begin(), E = liveInMBBs.end();
425 MachineBasicBlock *MBB = *I;
426 if (MBB == &entryMBB) continue;
427 if (MBB->isLiveIn(PhysReg)) continue;
428 MBB->addLiveIn(PhysReg);
435 //===----------------------------------------------------------------------===//
436 // RABasic Implementation
437 //===----------------------------------------------------------------------===//
439 // Driver for the register assignment and splitting heuristics.
440 // Manages iteration over the LiveIntervalUnions.
442 // This is a minimal implementation of register assignment and splitting that
443 // spills whenever we run out of registers.
445 // selectOrSplit can only be called once per live virtual register. We then do a
446 // single interference test for each register the correct class until we find an
447 // available register. So, the number of interference tests in the worst case is
448 // |vregs| * |machineregs|. And since the number of interference tests is
449 // minimal, there is no value in caching them outside the scope of
451 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
452 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
453 // Populate a list of physical register spill candidates.
454 SmallVector<unsigned, 8> PhysRegSpillCands;
456 // Check for an available register in this class.
457 const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
459 for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
460 E = TRC->allocation_order_end(*MF);
463 unsigned PhysReg = *I;
464 if (ReservedRegs.test(PhysReg)) continue;
466 // Check interference and as a side effect, intialize queries for this
467 // VirtReg and its aliases.
468 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
469 if (interfReg == 0) {
470 // Found an available register.
473 LiveInterval *interferingVirtReg =
474 Queries[interfReg].firstInterference().liveUnionPos().value();
476 // The current VirtReg must either be spillable, or one of its interferences
477 // must have less spill weight.
478 if (interferingVirtReg->weight < VirtReg.weight ) {
479 PhysRegSpillCands.push_back(PhysReg);
482 // Try to spill another interfering reg with less spill weight.
483 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
484 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
486 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
488 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
489 "Interference after spill.");
490 // Tell the caller to allocate to this newly freed physical register.
493 // No other spill candidates were found, so spill the current VirtReg.
494 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
495 LiveRangeEdit LRE(VirtReg, SplitVRegs);
496 spiller().spill(LRE);
498 // The live virtual register requesting allocation was spilled, so tell
499 // the caller not to allocate anything during this round.
503 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
504 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
505 << "********** Function: "
506 << ((Value*)mf.getFunction())->getName() << '\n');
509 DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
511 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
513 ReservedRegs = TRI->getReservedRegs(*MF);
515 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
521 // Diagnostic output before rewriting
522 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
524 // optional HTML output
525 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
527 // FIXME: Verification currently must run before VirtRegRewriter. We should
528 // make the rewriter a separate pass and override verifyAnalysis instead. When
529 // that happens, verification naturally falls under VerifyMachineCode.
532 // Verify accuracy of LiveIntervals. The standard machine code verifier
533 // ensures that each LiveIntervals covers all uses of the virtual reg.
535 // FIXME: MachineVerifier is badly broken when using the standard
536 // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
537 // inline spiller, some tests fail to verify because the coalescer does not
538 // always generate verifiable code.
539 MF->verify(this, "In RABasic::verify");
541 // Verify that LiveIntervals are partitioned into unions and disjoint within
548 VRM->rewrite(LIS->getSlotIndexes());
550 // Write out new DBG_VALUE instructions.
551 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
553 // The pass output is in VirtRegMap. Release all the transient data.
559 FunctionPass* llvm::createBasicRegisterAllocator()
561 return new RABasic();