1 //===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "RegAllocBase.h"
18 #include "LiveDebugVariables.h"
19 #include "RenderMachineFunction.h"
21 #include "VirtRegMap.h"
22 #include "LiveRegMatrix.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Function.h"
25 #include "llvm/PassAnalysisSupport.h"
26 #include "llvm/CodeGen/CalcSpillWeights.h"
27 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
28 #include "llvm/CodeGen/LiveRangeEdit.h"
29 #include "llvm/CodeGen/LiveStackAnalysis.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/CodeGen/RegAllocRegistry.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/raw_ostream.h"
47 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
48 createBasicRegisterAllocator);
51 struct CompSpillWeight {
52 bool operator()(LiveInterval *A, LiveInterval *B) const {
53 return A->weight < B->weight;
59 /// RABasic provides a minimal implementation of the basic register allocation
60 /// algorithm. It prioritizes live virtual registers by spill weight and spills
61 /// whenever a register is unavailable. This is not practical in production but
62 /// provides a useful baseline both for measuring other allocators and comparing
63 /// the speed of the basic algorithm against other styles of allocators.
64 class RABasic : public MachineFunctionPass, public RegAllocBase
71 RenderMachineFunction *RMF;
75 std::auto_ptr<Spiller> SpillerInstance;
76 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
77 CompSpillWeight> Queue;
79 // Scratch space. Allocated here to avoid repeated malloc calls in
86 /// Return the pass name.
87 virtual const char* getPassName() const {
88 return "Basic Register Allocator";
91 /// RABasic analysis usage.
92 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
94 virtual void releaseMemory();
96 virtual Spiller &spiller() { return *SpillerInstance; }
98 virtual float getPriority(LiveInterval *LI) { return LI->weight; }
100 virtual void enqueue(LiveInterval *LI) {
104 virtual LiveInterval *dequeue() {
107 LiveInterval *LI = Queue.top();
112 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
113 SmallVectorImpl<LiveInterval*> &SplitVRegs);
115 /// Perform register allocation.
116 virtual bool runOnMachineFunction(MachineFunction &mf);
118 // Helper for spilling all live virtual registers currently unified under preg
119 // that interfere with the most recently queried lvr. Return true if spilling
120 // was successful, and append any new spilled/split intervals to splitLVRs.
121 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
122 SmallVectorImpl<LiveInterval*> &SplitVRegs);
127 char RABasic::ID = 0;
129 } // end anonymous namespace
131 RABasic::RABasic(): MachineFunctionPass(ID) {
132 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
133 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
134 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
135 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
136 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
137 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
138 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
139 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
140 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
141 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
142 initializeLiveRegMatrixPass(*PassRegistry::getPassRegistry());
143 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
146 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
147 AU.setPreservesCFG();
148 AU.addRequired<AliasAnalysis>();
149 AU.addPreserved<AliasAnalysis>();
150 AU.addRequired<LiveIntervals>();
151 AU.addPreserved<LiveIntervals>();
152 AU.addPreserved<SlotIndexes>();
153 AU.addRequired<LiveDebugVariables>();
154 AU.addPreserved<LiveDebugVariables>();
155 AU.addRequired<CalculateSpillWeights>();
156 AU.addRequired<LiveStacks>();
157 AU.addPreserved<LiveStacks>();
158 AU.addRequiredID(MachineDominatorsID);
159 AU.addPreservedID(MachineDominatorsID);
160 AU.addRequired<MachineLoopInfo>();
161 AU.addPreserved<MachineLoopInfo>();
162 AU.addRequired<VirtRegMap>();
163 AU.addPreserved<VirtRegMap>();
164 AU.addRequired<LiveRegMatrix>();
165 AU.addPreserved<LiveRegMatrix>();
166 DEBUG(AU.addRequired<RenderMachineFunction>());
167 MachineFunctionPass::getAnalysisUsage(AU);
170 void RABasic::releaseMemory() {
171 SpillerInstance.reset(0);
172 RegAllocBase::releaseMemory();
176 // Spill or split all live virtual registers currently unified under PhysReg
177 // that interfere with VirtReg. The newly spilled or split live intervals are
178 // returned by appending them to SplitVRegs.
179 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
180 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
181 // Record each interference and determine if all are spillable before mutating
182 // either the union or live intervals.
183 SmallVector<LiveInterval*, 8> Intfs;
185 // Collect interferences assigned to any alias of the physical register.
186 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
187 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
188 Q.collectInterferingVRegs();
189 if (Q.seenUnspillableVReg())
191 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
192 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
193 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
195 Intfs.push_back(Intf);
198 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
199 " interferences with " << VirtReg << "\n");
200 assert(!Intfs.empty() && "expected interference");
202 // Spill each interfering vreg allocated to PhysReg or an alias.
203 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
204 LiveInterval &Spill = *Intfs[i];
207 if (!VRM->hasPhys(Spill.reg))
210 // Deallocate the interfering vreg by removing it from the union.
211 // A LiveInterval instance may not be in a union during modification!
212 Matrix->unassign(Spill);
214 // Spill the extracted interval.
215 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM);
216 spiller().spill(LRE);
221 // Driver for the register assignment and splitting heuristics.
222 // Manages iteration over the LiveIntervalUnions.
224 // This is a minimal implementation of register assignment and splitting that
225 // spills whenever we run out of registers.
227 // selectOrSplit can only be called once per live virtual register. We then do a
228 // single interference test for each register the correct class until we find an
229 // available register. So, the number of interference tests in the worst case is
230 // |vregs| * |machineregs|. And since the number of interference tests is
231 // minimal, there is no value in caching them outside the scope of
233 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
234 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
235 // Populate a list of physical register spill candidates.
236 SmallVector<unsigned, 8> PhysRegSpillCands;
238 // Check for an available register in this class.
239 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
240 while (unsigned PhysReg = Order.next()) {
241 // Check for interference in PhysReg
242 switch (Matrix->checkInterference(VirtReg, PhysReg)) {
243 case LiveRegMatrix::IK_Free:
244 // PhysReg is available, allocate it.
247 case LiveRegMatrix::IK_VirtReg:
248 // Only virtual registers in the way, we may be able to spill them.
249 PhysRegSpillCands.push_back(PhysReg);
253 // RegMask or RegUnit interference.
258 // Try to spill another interfering reg with less spill weight.
259 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
260 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
261 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
264 assert(!Matrix->checkInterference(VirtReg, *PhysRegI) &&
265 "Interference after spill.");
266 // Tell the caller to allocate to this newly freed physical register.
270 // No other spill candidates were found, so spill the current VirtReg.
271 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
272 if (!VirtReg.isSpillable())
274 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM);
275 spiller().spill(LRE);
277 // The live virtual register requesting allocation was spilled, so tell
278 // the caller not to allocate anything during this round.
282 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
283 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
284 << "********** Function: "
285 << ((Value*)mf.getFunction())->getName() << '\n');
288 DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
290 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
291 Matrix = &getAnalysis<LiveRegMatrix>();
292 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
296 // Diagnostic output before rewriting
297 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
299 // optional HTML output
300 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
306 FunctionPass* llvm::createBasicRegisterAllocator()
308 return new RABasic();