1 //===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RABasic function pass, which provides a minimal
11 // implementation of the basic register allocator.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "LiveIntervalUnion.h"
17 #include "LiveRangeEdit.h"
18 #include "RegAllocBase.h"
19 #include "RenderMachineFunction.h"
21 #include "VirtRegMap.h"
22 #include "llvm/ADT/OwningPtr.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassAnalysisSupport.h"
27 #include "llvm/CodeGen/CalcSpillWeights.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveStackAnalysis.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/CodeGen/RegAllocRegistry.h"
36 #include "llvm/CodeGen/RegisterCoalescer.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/ADT/SparseBitVector.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/Support/Timer.h"
53 STATISTIC(NumAssigned , "Number of registers assigned");
54 STATISTIC(NumUnassigned , "Number of registers unassigned");
55 STATISTIC(NumNewQueued , "Number of new live ranges queued");
57 static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
58 createBasicRegisterAllocator);
60 // Temporary verification option until we can put verification inside
62 static cl::opt<bool, true>
63 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
64 cl::desc("Verify during register allocation"));
66 const char *RegAllocBase::TimerGroupName = "Register Allocation";
67 bool RegAllocBase::VerifyEnabled = false;
70 struct CompSpillWeight {
71 bool operator()(LiveInterval *A, LiveInterval *B) const {
72 return A->weight < B->weight;
78 /// RABasic provides a minimal implementation of the basic register allocation
79 /// algorithm. It prioritizes live virtual registers by spill weight and spills
80 /// whenever a register is unavailable. This is not practical in production but
81 /// provides a useful baseline both for measuring other allocators and comparing
82 /// the speed of the basic algorithm against other styles of allocators.
83 class RABasic : public MachineFunctionPass, public RegAllocBase
87 BitVector ReservedRegs;
91 RenderMachineFunction *RMF;
94 std::auto_ptr<Spiller> SpillerInstance;
95 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
96 CompSpillWeight> Queue;
100 /// Return the pass name.
101 virtual const char* getPassName() const {
102 return "Basic Register Allocator";
105 /// RABasic analysis usage.
106 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
108 virtual void releaseMemory();
110 virtual Spiller &spiller() { return *SpillerInstance; }
112 virtual float getPriority(LiveInterval *LI) { return LI->weight; }
114 virtual void enqueue(LiveInterval *LI) {
118 virtual LiveInterval *dequeue() {
121 LiveInterval *LI = Queue.top();
126 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
127 SmallVectorImpl<LiveInterval*> &SplitVRegs);
129 /// Perform register allocation.
130 virtual bool runOnMachineFunction(MachineFunction &mf);
135 char RABasic::ID = 0;
137 } // end anonymous namespace
139 RABasic::RABasic(): MachineFunctionPass(ID) {
140 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
141 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
142 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
143 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
144 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
145 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
146 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
147 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
148 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
149 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
152 void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
153 AU.setPreservesCFG();
154 AU.addRequired<AliasAnalysis>();
155 AU.addPreserved<AliasAnalysis>();
156 AU.addRequired<LiveIntervals>();
157 AU.addPreserved<SlotIndexes>();
159 AU.addRequiredID(StrongPHIEliminationID);
160 AU.addRequiredTransitive<RegisterCoalescer>();
161 AU.addRequired<CalculateSpillWeights>();
162 AU.addRequired<LiveStacks>();
163 AU.addPreserved<LiveStacks>();
164 AU.addRequiredID(MachineDominatorsID);
165 AU.addPreservedID(MachineDominatorsID);
166 AU.addRequired<MachineLoopInfo>();
167 AU.addPreserved<MachineLoopInfo>();
168 AU.addRequired<VirtRegMap>();
169 AU.addPreserved<VirtRegMap>();
170 DEBUG(AU.addRequired<RenderMachineFunction>());
171 MachineFunctionPass::getAnalysisUsage(AU);
174 void RABasic::releaseMemory() {
175 SpillerInstance.reset(0);
176 RegAllocBase::releaseMemory();
180 // Verify each LiveIntervalUnion.
181 void RegAllocBase::verify() {
182 LiveVirtRegBitSet VisitedVRegs;
183 OwningArrayPtr<LiveVirtRegBitSet>
184 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]);
186 // Verify disjoint unions.
187 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
188 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
189 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
190 PhysReg2LiveUnion[PhysReg].verify(VRegs);
191 // Union + intersection test could be done efficiently in one pass, but
192 // don't add a method to SparseBitVector unless we really need it.
193 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
194 VisitedVRegs |= VRegs;
197 // Verify vreg coverage.
198 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
199 liItr != liEnd; ++liItr) {
200 unsigned reg = liItr->first;
201 if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
202 if (!VRM->hasPhys(reg)) continue; // spilled?
203 unsigned PhysReg = VRM->getPhys(reg);
204 if (!unionVRegs[PhysReg].test(reg)) {
205 dbgs() << "LiveVirtReg " << reg << " not in union " <<
206 TRI->getName(PhysReg) << "\n";
207 llvm_unreachable("unallocated live vreg");
210 // FIXME: I'm not sure how to verify spilled intervals.
214 //===----------------------------------------------------------------------===//
215 // RegAllocBase Implementation
216 //===----------------------------------------------------------------------===//
218 // Instantiate a LiveIntervalUnion for each physical register.
219 void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator,
223 static_cast<LiveIntervalUnion*>(malloc(sizeof(LiveIntervalUnion)*NRegs));
224 for (unsigned r = 0; r != NRegs; ++r)
225 new(Array + r) LiveIntervalUnion(r, allocator);
228 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
229 NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
230 TRI = &vrm.getTargetRegInfo();
231 MRI = &vrm.getRegInfo();
234 PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
235 // Cache an interferece query for each physical reg
236 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]);
239 void RegAllocBase::LiveUnionArray::clear() {
242 for (unsigned r = 0; r != NumRegs; ++r)
243 Array[r].~LiveIntervalUnion();
249 void RegAllocBase::releaseMemory() {
250 PhysReg2LiveUnion.clear();
253 // Visit all the live registers. If they are already assigned to a physical
254 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
255 // them on the priority queue for later assignment.
256 void RegAllocBase::seedLiveRegs() {
257 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
258 unsigned RegNum = I->first;
259 LiveInterval &VirtReg = *I->second;
260 if (TargetRegisterInfo::isPhysicalRegister(RegNum))
261 PhysReg2LiveUnion[RegNum].unify(VirtReg);
267 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
268 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
269 << " to " << PrintReg(PhysReg, TRI) << '\n');
270 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
271 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
272 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
276 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
277 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
278 << " from " << PrintReg(PhysReg, TRI) << '\n');
279 assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
280 PhysReg2LiveUnion[PhysReg].extract(VirtReg);
281 VRM->clearVirt(VirtReg.reg);
285 // Top-level driver to manage the queue of unassigned VirtRegs and call the
286 // selectOrSplit implementation.
287 void RegAllocBase::allocatePhysRegs() {
290 // Continue assigning vregs one at a time to available physical registers.
291 while (LiveInterval *VirtReg = dequeue()) {
292 // Unused registers can appear when the spiller coalesces snippets.
293 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
294 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
295 LIS->removeInterval(VirtReg->reg);
299 // Invalidate all interference queries, live ranges could have changed.
302 // selectOrSplit requests the allocator to return an available physical
303 // register if possible and populate a list of new live intervals that
304 // result from splitting.
305 DEBUG(dbgs() << "\nselectOrSplit "
306 << MRI->getRegClass(VirtReg->reg)->getName()
307 << ':' << *VirtReg << '\n');
308 typedef SmallVector<LiveInterval*, 4> VirtRegVec;
309 VirtRegVec SplitVRegs;
310 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
312 if (AvailablePhysReg)
313 assign(*VirtReg, AvailablePhysReg);
315 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
317 LiveInterval *SplitVirtReg = *I;
318 if (SplitVirtReg->empty()) continue;
319 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
320 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
321 "expect split value in virtual register");
322 enqueue(SplitVirtReg);
328 // Check if this live virtual register interferes with a physical register. If
329 // not, then check for interference on each register that aliases with the
330 // physical register. Return the interfering register.
331 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
333 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
334 if (query(VirtReg, *AliasI).checkInterference())
339 // Helper for spillInteferences() that spills all interfering vregs currently
340 // assigned to this physical register.
341 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
342 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
343 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
344 assert(Q.seenAllInterferences() && "need collectInterferences()");
345 const SmallVectorImpl<LiveInterval*> &PendingSpills = Q.interferingVRegs();
347 for (SmallVectorImpl<LiveInterval*>::const_iterator I = PendingSpills.begin(),
348 E = PendingSpills.end(); I != E; ++I) {
349 LiveInterval &SpilledVReg = **I;
350 DEBUG(dbgs() << "extracting from " <<
351 TRI->getName(PhysReg) << " " << SpilledVReg << '\n');
353 // Deallocate the interfering vreg by removing it from the union.
354 // A LiveInterval instance may not be in a union during modification!
355 unassign(SpilledVReg, PhysReg);
357 // Spill the extracted interval.
358 LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills);
359 spiller().spill(LRE);
361 // After extracting segments, the query's results are invalid. But keep the
362 // contents valid until we're done accessing pendingSpills.
366 // Spill or split all live virtual registers currently unified under PhysReg
367 // that interfere with VirtReg. The newly spilled or split live intervals are
368 // returned by appending them to SplitVRegs.
370 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
371 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
372 // Record each interference and determine if all are spillable before mutating
373 // either the union or live intervals.
374 unsigned NumInterferences = 0;
375 // Collect interferences assigned to any alias of the physical register.
376 for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
377 LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
378 NumInterferences += QAlias.collectInterferingVRegs();
379 if (QAlias.seenUnspillableVReg()) {
383 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
384 " interferences with " << VirtReg << "\n");
385 assert(NumInterferences > 0 && "expect interference");
387 // Spill each interfering vreg allocated to PhysReg or an alias.
388 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
389 spillReg(VirtReg, *AliasI, SplitVRegs);
393 // Add newly allocated physical registers to the MBB live in sets.
394 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
395 NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
396 typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
398 MachineBasicBlock &entryMBB = *MF->begin();
400 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
401 LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg];
402 if (LiveUnion.empty())
404 for (LiveIntervalUnion::SegmentIter SI = LiveUnion.begin(); SI.valid();
407 // Find the set of basic blocks which this range is live into...
409 if (!LIS->findLiveInMBBs(SI.start(), SI.stop(), liveInMBBs)) continue;
411 // And add the physreg for this interval to their live-in sets.
412 for (MBBVec::iterator I = liveInMBBs.begin(), E = liveInMBBs.end();
414 MachineBasicBlock *MBB = *I;
415 if (MBB == &entryMBB) continue;
416 if (MBB->isLiveIn(PhysReg)) continue;
417 MBB->addLiveIn(PhysReg);
424 //===----------------------------------------------------------------------===//
425 // RABasic Implementation
426 //===----------------------------------------------------------------------===//
428 // Driver for the register assignment and splitting heuristics.
429 // Manages iteration over the LiveIntervalUnions.
431 // This is a minimal implementation of register assignment and splitting that
432 // spills whenever we run out of registers.
434 // selectOrSplit can only be called once per live virtual register. We then do a
435 // single interference test for each register the correct class until we find an
436 // available register. So, the number of interference tests in the worst case is
437 // |vregs| * |machineregs|. And since the number of interference tests is
438 // minimal, there is no value in caching them outside the scope of
440 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
441 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
442 // Populate a list of physical register spill candidates.
443 SmallVector<unsigned, 8> PhysRegSpillCands;
445 // Check for an available register in this class.
446 const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
448 for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
449 E = TRC->allocation_order_end(*MF);
452 unsigned PhysReg = *I;
453 if (ReservedRegs.test(PhysReg)) continue;
455 // Check interference and as a side effect, intialize queries for this
456 // VirtReg and its aliases.
457 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
458 if (interfReg == 0) {
459 // Found an available register.
462 LiveInterval *interferingVirtReg =
463 Queries[interfReg].firstInterference().liveUnionPos().value();
465 // The current VirtReg must either be spillable, or one of its interferences
466 // must have less spill weight.
467 if (interferingVirtReg->weight < VirtReg.weight ) {
468 PhysRegSpillCands.push_back(PhysReg);
471 // Try to spill another interfering reg with less spill weight.
472 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
473 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
475 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
477 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
478 "Interference after spill.");
479 // Tell the caller to allocate to this newly freed physical register.
482 // No other spill candidates were found, so spill the current VirtReg.
483 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
484 LiveRangeEdit LRE(VirtReg, SplitVRegs);
485 spiller().spill(LRE);
487 // The live virtual register requesting allocation was spilled, so tell
488 // the caller not to allocate anything during this round.
492 bool RABasic::runOnMachineFunction(MachineFunction &mf) {
493 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
494 << "********** Function: "
495 << ((Value*)mf.getFunction())->getName() << '\n');
498 DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
500 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
502 ReservedRegs = TRI->getReservedRegs(*MF);
504 SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
510 // Diagnostic output before rewriting
511 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
513 // optional HTML output
514 DEBUG(RMF->renderMachineFunction("After basic register allocation.", VRM));
516 // FIXME: Verification currently must run before VirtRegRewriter. We should
517 // make the rewriter a separate pass and override verifyAnalysis instead. When
518 // that happens, verification naturally falls under VerifyMachineCode.
521 // Verify accuracy of LiveIntervals. The standard machine code verifier
522 // ensures that each LiveIntervals covers all uses of the virtual reg.
524 // FIXME: MachineVerifier is badly broken when using the standard
525 // spiller. Always use -spiller=inline with -verify-regalloc. Even with the
526 // inline spiller, some tests fail to verify because the coalescer does not
527 // always generate verifiable code.
528 MF->verify(this, "In RABasic::verify");
530 // Verify that LiveIntervals are partitioned into unions and disjoint within
537 VRM->rewrite(LIS->getSlotIndexes());
539 // The pass output is in VirtRegMap. Release all the transient data.
545 FunctionPass* llvm::createBasicRegisterAllocator()
547 return new RABasic();