1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "llvm/CodeGen/Passes.h"
18 #include "PHIEliminationUtils.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
39 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
40 cl::Hidden, cl::desc("Disable critical edge splitting "
41 "during PHI elimination"));
44 class PHIElimination : public MachineFunctionPass {
45 MachineRegisterInfo *MRI; // Machine register information
50 static char ID; // Pass identification, replacement for typeid
51 PHIElimination() : MachineFunctionPass(ID) {
52 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
55 virtual bool runOnMachineFunction(MachineFunction &Fn);
56 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
59 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
60 /// in predecessor basic blocks.
62 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
63 void LowerPHINode(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator AfterPHIsIt);
66 /// analyzePHINodes - Gather information about the PHI nodes in
67 /// here. In particular, we want to map the number of uses of a virtual
68 /// register which is used in a PHI node. We map that to the BB the
69 /// vreg is coming from. This is used later to determine when the vreg
70 /// is killed in the BB.
72 void analyzePHINodes(const MachineFunction& Fn);
74 /// Split critical edges where necessary for good coalescer performance.
75 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
76 MachineLoopInfo *MLI);
78 // These functions are temporary abstractions around LiveVariables and
79 // LiveIntervals, so they can go away when LiveVariables does.
80 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
81 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
83 typedef std::pair<unsigned, unsigned> BBVRegPair;
84 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
86 VRegPHIUse VRegPHIUseCount;
88 // Defs of PHI sources which are implicit_def.
89 SmallPtrSet<MachineInstr*, 4> ImpDefs;
91 // Map reusable lowered PHI node -> incoming join register.
92 typedef DenseMap<MachineInstr*, unsigned,
93 MachineInstrExpressionTrait> LoweredPHIMap;
94 LoweredPHIMap LoweredPHIs;
98 STATISTIC(NumLowered, "Number of phis lowered");
99 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
100 STATISTIC(NumReused, "Number of reused lowered phis");
102 char PHIElimination::ID = 0;
103 char& llvm::PHIEliminationID = PHIElimination::ID;
105 INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
106 "Eliminate PHI nodes for register allocation",
108 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
109 INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
110 "Eliminate PHI nodes for register allocation", false, false)
112 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
113 AU.addPreserved<LiveVariables>();
114 AU.addPreserved<LiveIntervals>();
115 AU.addPreserved<MachineDominatorTree>();
116 AU.addPreserved<MachineLoopInfo>();
117 MachineFunctionPass::getAnalysisUsage(AU);
120 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
121 MRI = &MF.getRegInfo();
122 LV = getAnalysisIfAvailable<LiveVariables>();
123 LIS = getAnalysisIfAvailable<LiveIntervals>();
125 bool Changed = false;
127 // This pass takes the function out of SSA form.
130 // Split critical edges to help the coalescer. This does not yet support
131 // updating LiveIntervals, so we disable it.
132 if (!DisableEdgeSplitting && LV && !LIS) {
133 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
134 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
135 Changed |= SplitPHIEdges(MF, *I, MLI);
138 // Populate VRegPHIUseCount
141 // Eliminate PHI instructions by inserting copies into predecessor blocks.
142 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
143 Changed |= EliminatePHINodes(MF, *I);
145 // Remove dead IMPLICIT_DEF instructions.
146 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(),
147 E = ImpDefs.end(); I != E; ++I) {
148 MachineInstr *DefMI = *I;
149 unsigned DefReg = DefMI->getOperand(0).getReg();
150 if (MRI->use_nodbg_empty(DefReg)) {
152 LIS->RemoveMachineInstrFromMaps(DefMI);
153 DefMI->eraseFromParent();
157 // Clean up the lowered PHI instructions.
158 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
161 LIS->RemoveMachineInstrFromMaps(I->first);
162 MF.DeleteMachineInstr(I->first);
167 VRegPHIUseCount.clear();
170 MF.verify(this, "After PHI elimination");
175 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
176 /// predecessor basic blocks.
178 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
179 MachineBasicBlock &MBB) {
180 if (MBB.empty() || !MBB.front().isPHI())
181 return false; // Quick exit for basic blocks without PHIs.
183 // Get an iterator to the first instruction after the last PHI node (this may
184 // also be the end of the basic block).
185 MachineBasicBlock::iterator AfterPHIsIt = MBB.SkipPHIsAndLabels(MBB.begin());
187 while (MBB.front().isPHI())
188 LowerPHINode(MBB, AfterPHIsIt);
193 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
194 /// This includes registers with no defs.
195 static bool isImplicitlyDefined(unsigned VirtReg,
196 const MachineRegisterInfo *MRI) {
197 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg),
198 DE = MRI->def_end(); DI != DE; ++DI)
199 if (!DI->isImplicitDef())
204 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
205 /// are implicit_def's.
206 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
207 const MachineRegisterInfo *MRI) {
208 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
209 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
215 /// LowerPHINode - Lower the PHI node at the top of the specified block,
217 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
218 MachineBasicBlock::iterator AfterPHIsIt) {
220 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
221 MachineInstr *MPhi = MBB.remove(MBB.begin());
223 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
224 unsigned DestReg = MPhi->getOperand(0).getReg();
225 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
226 bool isDead = MPhi->getOperand(0).isDead();
228 // Create a new register for the incoming PHI arguments.
229 MachineFunction &MF = *MBB.getParent();
230 unsigned IncomingReg = 0;
231 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
233 // Insert a register to register copy at the top of the current block (but
234 // after any remaining phi nodes) which copies the new incoming register
235 // into the phi node destination.
236 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
237 if (isSourceDefinedByImplicitDef(MPhi, MRI))
238 // If all sources of a PHI node are implicit_def, just emit an
239 // implicit_def instead of a copy.
240 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
241 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
243 // Can we reuse an earlier PHI node? This only happens for critical edges,
244 // typically those created by tail duplication.
245 unsigned &entry = LoweredPHIs[MPhi];
247 // An identical PHI node was already lowered. Reuse the incoming register.
249 reusedIncoming = true;
251 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
253 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
254 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
256 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
257 TII->get(TargetOpcode::COPY), DestReg)
258 .addReg(IncomingReg);
261 // Update live variable information if there is any.
263 MachineInstr *PHICopy = prior(AfterPHIsIt);
266 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
268 // Increment use count of the newly created virtual register.
269 LV->setPHIJoin(IncomingReg);
271 // When we are reusing the incoming register, it may already have been
272 // killed in this block. The old kill will also have been inserted at
273 // AfterPHIsIt, so it appears before the current PHICopy.
275 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
276 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
277 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
281 // Add information to LiveVariables to know that the incoming value is
282 // killed. Note that because the value is defined in several places (once
283 // each for each incoming block), the "def" block and instruction fields
284 // for the VarInfo is not filled in.
285 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
288 // Since we are going to be deleting the PHI node, if it is the last use of
289 // any registers, or if the value itself is dead, we need to move this
290 // information over to the new copy we just inserted.
291 LV->removeVirtualRegistersKilled(MPhi);
293 // If the result is dead, update LV.
295 LV->addVirtualRegisterDead(DestReg, PHICopy);
296 LV->removeVirtualRegisterDead(DestReg, MPhi);
300 // Update LiveIntervals for the new copy or implicit def.
302 MachineInstr *NewInstr = prior(AfterPHIsIt);
303 LIS->InsertMachineInstrInMaps(NewInstr);
305 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
306 SlotIndex DestCopyIndex = LIS->getInstructionIndex(NewInstr);
308 // Add the region from the beginning of MBB to the copy instruction to
309 // IncomingReg's live interval.
310 LiveInterval &IncomingLI = LIS->getOrCreateInterval(IncomingReg);
311 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
313 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
314 LIS->getVNInfoAllocator());
315 IncomingLI.addRange(LiveRange(MBBStartIndex,
316 DestCopyIndex.getRegSlot(),
320 LiveInterval &DestLI = LIS->getOrCreateInterval(DestReg);
321 if (NewInstr->getOperand(0).isDead()) {
322 // A dead PHI's live range begins and ends at the start of the MBB, but
323 // the lowered copy, which will still be dead, needs to begin and end at
324 // the copy instruction.
325 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
326 assert(OrigDestVNI && "PHI destination should be live at block entry.");
327 DestLI.removeRange(MBBStartIndex, MBBStartIndex.getDeadSlot());
328 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
329 LIS->getVNInfoAllocator());
330 DestLI.removeValNo(OrigDestVNI);
332 // Otherwise, remove the region from the beginning of MBB to the copy
333 // instruction from DestReg's live interval.
334 DestLI.removeRange(MBBStartIndex, DestCopyIndex.getRegSlot());
335 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
336 assert(DestVNI && "PHI destination should be live at its definition.");
337 DestVNI->def = DestCopyIndex.getRegSlot();
341 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
342 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
343 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
344 MPhi->getOperand(i).getReg())];
346 // Now loop over all of the incoming arguments, changing them to copy into the
347 // IncomingReg register in the corresponding predecessor basic block.
348 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
349 for (int i = NumSrcs - 1; i >= 0; --i) {
350 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
351 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
352 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
353 isImplicitlyDefined(SrcReg, MRI);
354 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
355 "Machine PHI Operands must all be virtual registers!");
357 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
359 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
361 // Check to make sure we haven't already emitted the copy for this block.
362 // This can happen because PHI nodes may have multiple entries for the same
364 if (!MBBsInsertedInto.insert(&opBlock))
365 continue; // If the copy has already been emitted, we're done.
367 // Find a safe location to insert the copy, this may be the first terminator
368 // in the block (or end()).
369 MachineBasicBlock::iterator InsertPos =
370 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
373 MachineInstr *NewSrcInstr = 0;
374 if (!reusedIncoming && IncomingReg) {
376 // The source register is undefined, so there is no need for a real
377 // COPY, but we still need to ensure joint dominance by defs.
378 // Insert an IMPLICIT_DEF instruction.
379 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
380 TII->get(TargetOpcode::IMPLICIT_DEF),
383 // Clean up the old implicit-def, if there even was one.
384 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
385 if (DefMI->isImplicitDef())
386 ImpDefs.insert(DefMI);
388 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
389 TII->get(TargetOpcode::COPY), IncomingReg)
390 .addReg(SrcReg, 0, SrcSubReg);
394 // We only need to update the LiveVariables kill of SrcReg if this was the
395 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
396 // out of the predecessor. We can also ignore undef sources.
397 if (LV && !SrcUndef &&
398 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
399 !LV->isLiveOut(SrcReg, opBlock)) {
400 // We want to be able to insert a kill of the register if this PHI (aka,
401 // the copy we just inserted) is the last use of the source value. Live
402 // variable analysis conservatively handles this by saying that the value
403 // is live until the end of the block the PHI entry lives in. If the value
404 // really is dead at the PHI copy, there will be no successor blocks which
405 // have the value live-in.
407 // Okay, if we now know that the value is not live out of the block, we
408 // can add a kill marker in this block saying that it kills the incoming
411 // In our final twist, we have to decide which instruction kills the
412 // register. In most cases this is the copy, however, terminator
413 // instructions at the end of the block may also use the value. In this
414 // case, we should mark the last such terminator as being the killing
415 // block, not the copy.
416 MachineBasicBlock::iterator KillInst = opBlock.end();
417 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
418 for (MachineBasicBlock::iterator Term = FirstTerm;
419 Term != opBlock.end(); ++Term) {
420 if (Term->readsRegister(SrcReg))
424 if (KillInst == opBlock.end()) {
425 // No terminator uses the register.
427 if (reusedIncoming || !IncomingReg) {
428 // We may have to rewind a bit if we didn't insert a copy this time.
429 KillInst = FirstTerm;
430 while (KillInst != opBlock.begin()) {
432 if (KillInst->isDebugValue())
434 if (KillInst->readsRegister(SrcReg))
438 // We just inserted this copy.
439 KillInst = prior(InsertPos);
442 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
444 // Finally, mark it killed.
445 LV->addVirtualRegisterKilled(SrcReg, KillInst);
447 // This vreg no longer lives all of the way through opBlock.
448 unsigned opBlockNum = opBlock.getNumber();
449 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
454 LIS->InsertMachineInstrInMaps(NewSrcInstr);
455 LIS->addLiveRangeToEndOfBlock(IncomingReg, NewSrcInstr);
459 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
460 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
462 bool isLiveOut = false;
463 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
464 SE = opBlock.succ_end(); SI != SE; ++SI) {
465 if (SrcLI.liveAt(LIS->getMBBStartIdx(*SI))) {
472 MachineBasicBlock::iterator KillInst = opBlock.end();
473 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
474 for (MachineBasicBlock::iterator Term = FirstTerm;
475 Term != opBlock.end(); ++Term) {
476 if (Term->readsRegister(SrcReg))
480 if (KillInst == opBlock.end()) {
481 // No terminator uses the register.
483 if (reusedIncoming || !IncomingReg) {
484 // We may have to rewind a bit if we didn't just insert a copy.
485 KillInst = FirstTerm;
486 while (KillInst != opBlock.begin()) {
488 if (KillInst->isDebugValue())
490 if (KillInst->readsRegister(SrcReg))
494 // We just inserted this copy.
495 KillInst = prior(InsertPos);
498 assert(KillInst->readsRegister(SrcReg) &&
499 "Cannot find kill instruction");
501 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
502 SrcLI.removeRange(LastUseIndex.getRegSlot(),
503 LIS->getMBBEndIdx(&opBlock));
509 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
510 if (reusedIncoming || !IncomingReg) {
512 LIS->RemoveMachineInstrFromMaps(MPhi);
513 MF.DeleteMachineInstr(MPhi);
517 /// analyzePHINodes - Gather information about the PHI nodes in here. In
518 /// particular, we want to map the number of uses of a virtual register which is
519 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
520 /// used later to determine when the vreg is killed in the BB.
522 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
523 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
525 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
526 BBI != BBE && BBI->isPHI(); ++BBI)
527 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
528 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(),
529 BBI->getOperand(i).getReg())];
532 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
533 MachineBasicBlock &MBB,
534 MachineLoopInfo *MLI) {
535 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
536 return false; // Quick exit for basic blocks without PHIs.
538 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : 0;
539 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
541 bool Changed = false;
542 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
543 BBI != BBE && BBI->isPHI(); ++BBI) {
544 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
545 unsigned Reg = BBI->getOperand(i).getReg();
546 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
547 // Is there a critical edge from PreMBB to MBB?
548 if (PreMBB->succ_size() == 1)
551 // Avoid splitting backedges of loops. It would introduce small
552 // out-of-line blocks into the loop which is very bad for code placement.
555 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : 0;
556 if (IsLoopHeader && PreLoop == CurLoop)
559 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
560 // when the source register is live-out for some other reason than a phi
561 // use. That means the copy we will insert in PreMBB won't be a kill, and
562 // there is a risk it may not be coalesced away.
564 // If the copy would be a kill, there is no need to split the edge.
565 if (!isLiveOutPastPHIs(Reg, PreMBB))
568 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
569 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
572 // If Reg is not live-in to MBB, it means it must be live-in to some
573 // other PreMBB successor, and we can avoid the interference by splitting
576 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
577 // is likely to be left after coalescing. If we are looking at a loop
578 // exiting edge, split it so we won't insert code in the loop, otherwise
580 bool ShouldSplit = !isLiveIn(Reg, &MBB);
582 // Check for a loop exiting edge.
583 if (!ShouldSplit && CurLoop != PreLoop) {
585 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
586 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
587 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
589 // This edge could be entering a loop, exiting a loop, or it could be
590 // both: Jumping directly form one loop to the header of a sibling
592 // Split unless this edge is entering CurLoop from an outer loop.
593 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
597 if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
598 DEBUG(dbgs() << "Failed to split ciritcal edge.\n");
602 ++NumCriticalEdgesSplit;
608 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) {
609 assert((LV || LIS) &&
610 "isLiveIn() requires either LiveVariables or LiveIntervals");
612 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
614 return LV->isLiveIn(Reg, *MBB);
617 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) {
618 assert((LV || LIS) &&
619 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
620 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
621 // so that a register used only in a PHI is not live out of the block. In
622 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
623 // in the predecessor basic block, so that a register used only in a PHI is live
626 const LiveInterval &LI = LIS->getInterval(Reg);
627 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
628 SE = MBB->succ_end(); SI != SE; ++SI) {
629 if (LI.liveAt(LIS->getMBBStartIdx(*SI)))
634 return LV->isLiveOut(Reg, *MBB);