1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "PHIElimination.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Function.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
37 STATISTIC(NumAtomic, "Number of atomic phis lowered");
38 STATISTIC(NumSplits, "Number of critical edges split on demand");
39 STATISTIC(NumReused, "Number of reused lowered phis");
41 char PHIElimination::ID = 0;
42 static RegisterPass<PHIElimination>
43 X("phi-node-elimination", "Eliminate PHI nodes for register allocation");
45 const PassInfo *const llvm::PHIEliminationID = &X;
47 void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
48 AU.addPreserved<LiveVariables>();
49 AU.addPreserved<MachineDominatorTree>();
50 // rdar://7401784 This would be nice:
51 // AU.addPreservedID(MachineLoopInfoID);
52 MachineFunctionPass::getAnalysisUsage(AU);
55 bool llvm::PHIElimination::runOnMachineFunction(MachineFunction &MF) {
56 MRI = &MF.getRegInfo();
60 // Split critical edges to help the coalescer
61 if (LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>())
62 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
63 Changed |= SplitPHIEdges(MF, *I, *LV);
65 // Populate VRegPHIUseCount
68 // Eliminate PHI instructions by inserting copies into predecessor blocks.
69 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
70 Changed |= EliminatePHINodes(MF, *I);
72 // Remove dead IMPLICIT_DEF instructions.
73 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(),
74 E = ImpDefs.end(); I != E; ++I) {
75 MachineInstr *DefMI = *I;
76 unsigned DefReg = DefMI->getOperand(0).getReg();
77 if (MRI->use_nodbg_empty(DefReg))
78 DefMI->eraseFromParent();
81 // Clean up the lowered PHI instructions.
82 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
84 MF.DeleteMachineInstr(I->first);
88 VRegPHIUseCount.clear();
93 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
94 /// predecessor basic blocks.
96 bool llvm::PHIElimination::EliminatePHINodes(MachineFunction &MF,
97 MachineBasicBlock &MBB) {
98 if (MBB.empty() || !MBB.front().isPHI())
99 return false; // Quick exit for basic blocks without PHIs.
101 // Get an iterator to the first instruction after the last PHI node (this may
102 // also be the end of the basic block).
103 MachineBasicBlock::iterator AfterPHIsIt = SkipPHIsAndLabels(MBB, MBB.begin());
105 while (MBB.front().isPHI())
106 LowerAtomicPHINode(MBB, AfterPHIsIt);
111 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
112 /// are implicit_def's.
113 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
114 const MachineRegisterInfo *MRI) {
115 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
116 unsigned SrcReg = MPhi->getOperand(i).getReg();
117 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
118 if (!DefMI || !DefMI->isImplicitDef())
124 // FindCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
125 // when following the CFG edge to SuccMBB. This needs to be after any def of
126 // SrcReg, but before any subsequent point where control flow might jump out of
128 MachineBasicBlock::iterator
129 llvm::PHIElimination::FindCopyInsertPoint(MachineBasicBlock &MBB,
130 MachineBasicBlock &SuccMBB,
132 // Handle the trivial case trivially.
136 // Usually, we just want to insert the copy before the first terminator
137 // instruction. However, for the edge going to a landing pad, we must insert
138 // the copy before the call/invoke instruction.
139 if (!SuccMBB.isLandingPad())
140 return MBB.getFirstTerminator();
142 // Discover any defs/uses in this basic block.
143 SmallPtrSet<MachineInstr*, 8> DefUsesInMBB;
144 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
145 RE = MRI->reg_end(); RI != RE; ++RI) {
146 MachineInstr *DefUseMI = &*RI;
147 if (DefUseMI->getParent() == &MBB)
148 DefUsesInMBB.insert(DefUseMI);
151 MachineBasicBlock::iterator InsertPoint;
152 if (DefUsesInMBB.empty()) {
153 // No defs. Insert the copy at the start of the basic block.
154 InsertPoint = MBB.begin();
155 } else if (DefUsesInMBB.size() == 1) {
156 // Insert the copy immediately after the def/use.
157 InsertPoint = *DefUsesInMBB.begin();
160 // Insert the copy immediately after the last def/use.
161 InsertPoint = MBB.end();
162 while (!DefUsesInMBB.count(&*--InsertPoint)) {}
166 // Make sure the copy goes after any phi nodes however.
167 return SkipPHIsAndLabels(MBB, InsertPoint);
170 /// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
171 /// under the assuption that it needs to be lowered in a way that supports
172 /// atomic execution of PHIs. This lowering method is always correct all of the
175 void llvm::PHIElimination::LowerAtomicPHINode(
176 MachineBasicBlock &MBB,
177 MachineBasicBlock::iterator AfterPHIsIt) {
179 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
180 MachineInstr *MPhi = MBB.remove(MBB.begin());
182 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
183 unsigned DestReg = MPhi->getOperand(0).getReg();
184 bool isDead = MPhi->getOperand(0).isDead();
186 // Create a new register for the incoming PHI arguments.
187 MachineFunction &MF = *MBB.getParent();
188 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
189 unsigned IncomingReg = 0;
190 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
192 // Insert a register to register copy at the top of the current block (but
193 // after any remaining phi nodes) which copies the new incoming register
194 // into the phi node destination.
195 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
196 if (isSourceDefinedByImplicitDef(MPhi, MRI))
197 // If all sources of a PHI node are implicit_def, just emit an
198 // implicit_def instead of a copy.
199 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
200 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
202 // Can we reuse an earlier PHI node? This only happens for critical edges,
203 // typically those created by tail duplication.
204 unsigned &entry = LoweredPHIs[MPhi];
206 // An identical PHI node was already lowered. Reuse the incoming register.
208 reusedIncoming = true;
210 DEBUG(dbgs() << "Reusing %reg" << IncomingReg << " for " << *MPhi);
212 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
214 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
217 // Update live variable information if there is any.
218 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>();
220 MachineInstr *PHICopy = prior(AfterPHIsIt);
223 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
225 // Increment use count of the newly created virtual register.
227 LV->setPHIJoin(IncomingReg);
229 // When we are reusing the incoming register, it may already have been
230 // killed in this block. The old kill will also have been inserted at
231 // AfterPHIsIt, so it appears before the current PHICopy.
233 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
234 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
235 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
239 // Add information to LiveVariables to know that the incoming value is
240 // killed. Note that because the value is defined in several places (once
241 // each for each incoming block), the "def" block and instruction fields
242 // for the VarInfo is not filled in.
243 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
246 // Since we are going to be deleting the PHI node, if it is the last use of
247 // any registers, or if the value itself is dead, we need to move this
248 // information over to the new copy we just inserted.
249 LV->removeVirtualRegistersKilled(MPhi);
251 // If the result is dead, update LV.
253 LV->addVirtualRegisterDead(DestReg, PHICopy);
254 LV->removeVirtualRegisterDead(DestReg, MPhi);
258 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
259 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
260 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
261 MPhi->getOperand(i).getReg())];
263 // Now loop over all of the incoming arguments, changing them to copy into the
264 // IncomingReg register in the corresponding predecessor basic block.
265 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
266 for (int i = NumSrcs - 1; i >= 0; --i) {
267 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
268 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
269 "Machine PHI Operands must all be virtual registers!");
271 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
273 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
275 // If source is defined by an implicit def, there is no need to insert a
277 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
278 if (DefMI->isImplicitDef()) {
279 ImpDefs.insert(DefMI);
283 // Check to make sure we haven't already emitted the copy for this block.
284 // This can happen because PHI nodes may have multiple entries for the same
286 if (!MBBsInsertedInto.insert(&opBlock))
287 continue; // If the copy has already been emitted, we're done.
289 // Find a safe location to insert the copy, this may be the first terminator
290 // in the block (or end()).
291 MachineBasicBlock::iterator InsertPos =
292 FindCopyInsertPoint(opBlock, MBB, SrcReg);
295 if (!reusedIncoming && IncomingReg)
296 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
298 // Now update live variable information if we have it. Otherwise we're done
301 // We want to be able to insert a kill of the register if this PHI (aka, the
302 // copy we just inserted) is the last use of the source value. Live
303 // variable analysis conservatively handles this by saying that the value is
304 // live until the end of the block the PHI entry lives in. If the value
305 // really is dead at the PHI copy, there will be no successor blocks which
306 // have the value live-in.
308 // Also check to see if this register is in use by another PHI node which
309 // has not yet been eliminated. If so, it will be killed at an appropriate
312 // Is it used by any PHI instructions in this block?
313 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)];
315 // Okay, if we now know that the value is not live out of the block, we can
316 // add a kill marker in this block saying that it kills the incoming value!
317 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) {
318 // In our final twist, we have to decide which instruction kills the
319 // register. In most cases this is the copy, however, the first
320 // terminator instruction at the end of the block may also use the value.
321 // In this case, we should mark *it* as being the killing block, not the
323 MachineBasicBlock::iterator KillInst;
324 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
325 if (Term != opBlock.end() && Term->readsRegister(SrcReg)) {
328 // Check that no other terminators use values.
330 for (MachineBasicBlock::iterator TI = llvm::next(Term);
331 TI != opBlock.end(); ++TI) {
332 assert(!TI->readsRegister(SrcReg) &&
333 "Terminator instructions cannot use virtual registers unless"
334 "they are the first terminator in a block!");
337 } else if (reusedIncoming || !IncomingReg) {
338 // We may have to rewind a bit if we didn't insert a copy this time.
340 while (KillInst != opBlock.begin())
341 if ((--KillInst)->readsRegister(SrcReg))
344 // We just inserted this copy.
345 KillInst = prior(InsertPos);
347 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
349 // Finally, mark it killed.
350 LV->addVirtualRegisterKilled(SrcReg, KillInst);
352 // This vreg no longer lives all of the way through opBlock.
353 unsigned opBlockNum = opBlock.getNumber();
354 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
358 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
359 if (reusedIncoming || !IncomingReg)
360 MF.DeleteMachineInstr(MPhi);
363 /// analyzePHINodes - Gather information about the PHI nodes in here. In
364 /// particular, we want to map the number of uses of a virtual register which is
365 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
366 /// used later to determine when the vreg is killed in the BB.
368 void llvm::PHIElimination::analyzePHINodes(const MachineFunction& MF) {
369 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
371 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
372 BBI != BBE && BBI->isPHI(); ++BBI)
373 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
374 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(),
375 BBI->getOperand(i).getReg())];
378 bool llvm::PHIElimination::SplitPHIEdges(MachineFunction &MF,
379 MachineBasicBlock &MBB,
381 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
382 return false; // Quick exit for basic blocks without PHIs.
384 for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end();
385 BBI != BBE && BBI->isPHI(); ++BBI) {
386 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
387 unsigned Reg = BBI->getOperand(i).getReg();
388 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
389 // We break edges when registers are live out from the predecessor block
390 // (not considering PHI nodes). If the register is live in to this block
391 // anyway, we would gain nothing from splitting.
392 if (!LV.isLiveIn(Reg, MBB) && LV.isLiveOut(Reg, *PreMBB))
393 SplitCriticalEdge(PreMBB, &MBB);
399 MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
400 MachineBasicBlock *B) {
401 assert(A && B && "Missing MBB end point");
403 MachineFunction *MF = A->getParent();
405 // We may need to update A's terminator, but we can't do that if AnalyzeBranch
406 // fails. If A uses a jump table, we won't touch it.
407 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
408 MachineBasicBlock *TBB = 0, *FBB = 0;
409 SmallVector<MachineOperand, 4> Cond;
410 if (TII->AnalyzeBranch(*A, TBB, FBB, Cond))
415 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
416 MF->insert(llvm::next(MachineFunction::iterator(A)), NMBB);
417 DEBUG(dbgs() << "PHIElimination splitting critical edge:"
418 " BB#" << A->getNumber()
419 << " -- BB#" << NMBB->getNumber()
420 << " -- BB#" << B->getNumber() << '\n');
422 A->ReplaceUsesOfBlockWith(B, NMBB);
423 A->updateTerminator();
425 // Insert unconditional "jump B" instruction in NMBB if necessary.
426 NMBB->addSuccessor(B);
427 if (!NMBB->isLayoutSuccessor(B)) {
429 MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond);
432 // Fix PHI nodes in B so they refer to NMBB instead of A
433 for (MachineBasicBlock::iterator i = B->begin(), e = B->end();
434 i != e && i->isPHI(); ++i)
435 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
436 if (i->getOperand(ni+1).getMBB() == A)
437 i->getOperand(ni+1).setMBB(NMBB);
439 if (LiveVariables *LV=getAnalysisIfAvailable<LiveVariables>())
440 LV->addNewBlock(NMBB, A, B);
442 if (MachineDominatorTree *MDT=getAnalysisIfAvailable<MachineDominatorTree>())
443 MDT->addNewBlock(NMBB, A);