1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/Instructions.h"
27 #include "llvm/Function.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/LiveStackAnalysis.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineMemOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/ADT/DenseSet.h"
42 #include "llvm/ADT/SetOperations.h"
43 #include "llvm/ADT/SmallVector.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/raw_ostream.h"
50 struct MachineVerifier {
52 MachineVerifier(Pass *pass, const char *b) :
55 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
58 bool runOnMachineFunction(MachineFunction &MF);
62 const char *const OutFileName;
64 const MachineFunction *MF;
65 const TargetMachine *TM;
66 const TargetInstrInfo *TII;
67 const TargetRegisterInfo *TRI;
68 const MachineRegisterInfo *MRI;
72 typedef SmallVector<unsigned, 16> RegVector;
73 typedef SmallVector<const uint32_t*, 4> RegMaskVector;
74 typedef DenseSet<unsigned> RegSet;
75 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
77 const MachineInstr *FirstTerminator;
79 BitVector regsReserved;
80 BitVector regsAllocatable;
82 RegVector regsDefined, regsDead, regsKilled;
83 RegMaskVector regMasks;
84 RegSet regsLiveInButUnused;
88 // Add Reg and any sub-registers to RV
89 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
91 if (TargetRegisterInfo::isPhysicalRegister(Reg))
92 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
93 RV.push_back(*SubRegs);
97 // Is this MBB reachable from the MF entry point?
100 // Vregs that must be live in because they are used without being
101 // defined. Map value is the user.
104 // Regs killed in MBB. They may be defined again, and will then be in both
105 // regsKilled and regsLiveOut.
108 // Regs defined in MBB and live out. Note that vregs passing through may
109 // be live out without being mentioned here.
112 // Vregs that pass through MBB untouched. This set is disjoint from
113 // regsKilled and regsLiveOut.
116 // Vregs that must pass through MBB because they are needed by a successor
117 // block. This set is disjoint from regsLiveOut.
118 RegSet vregsRequired;
120 BBInfo() : reachable(false) {}
122 // Add register to vregsPassed if it belongs there. Return true if
124 bool addPassed(unsigned Reg) {
125 if (!TargetRegisterInfo::isVirtualRegister(Reg))
127 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
129 return vregsPassed.insert(Reg).second;
132 // Same for a full set.
133 bool addPassed(const RegSet &RS) {
134 bool changed = false;
135 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
141 // Add register to vregsRequired if it belongs there. Return true if
143 bool addRequired(unsigned Reg) {
144 if (!TargetRegisterInfo::isVirtualRegister(Reg))
146 if (regsLiveOut.count(Reg))
148 return vregsRequired.insert(Reg).second;
151 // Same for a full set.
152 bool addRequired(const RegSet &RS) {
153 bool changed = false;
154 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
160 // Same for a full map.
161 bool addRequired(const RegMap &RM) {
162 bool changed = false;
163 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
164 if (addRequired(I->first))
169 // Live-out registers are either in regsLiveOut or vregsPassed.
170 bool isLiveOut(unsigned Reg) const {
171 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
175 // Extra register info per MBB.
176 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
178 bool isReserved(unsigned Reg) {
179 return Reg < regsReserved.size() && regsReserved.test(Reg);
182 bool isAllocatable(unsigned Reg) {
183 return Reg < regsAllocatable.size() && regsAllocatable.test(Reg);
186 // Analysis information if available
187 LiveVariables *LiveVars;
188 LiveIntervals *LiveInts;
189 LiveStacks *LiveStks;
190 SlotIndexes *Indexes;
192 void visitMachineFunctionBefore();
193 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
194 void visitMachineBundleBefore(const MachineInstr *MI);
195 void visitMachineInstrBefore(const MachineInstr *MI);
196 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
197 void visitMachineInstrAfter(const MachineInstr *MI);
198 void visitMachineBundleAfter(const MachineInstr *MI);
199 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
200 void visitMachineFunctionAfter();
202 void report(const char *msg, const MachineFunction *MF);
203 void report(const char *msg, const MachineBasicBlock *MBB);
204 void report(const char *msg, const MachineInstr *MI);
205 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
207 void checkLiveness(const MachineOperand *MO, unsigned MONum);
208 void markReachable(const MachineBasicBlock *MBB);
209 void calcRegsPassed();
210 void checkPHIOps(const MachineBasicBlock *MBB);
212 void calcRegsRequired();
213 void verifyLiveVariables();
214 void verifyLiveIntervals();
217 struct MachineVerifierPass : public MachineFunctionPass {
218 static char ID; // Pass ID, replacement for typeid
219 const char *const Banner;
221 MachineVerifierPass(const char *b = 0)
222 : MachineFunctionPass(ID), Banner(b) {
223 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
226 void getAnalysisUsage(AnalysisUsage &AU) const {
227 AU.setPreservesAll();
228 MachineFunctionPass::getAnalysisUsage(AU);
231 bool runOnMachineFunction(MachineFunction &MF) {
232 MF.verify(this, Banner);
239 char MachineVerifierPass::ID = 0;
240 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
241 "Verify generated machine code", false, false)
243 FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
244 return new MachineVerifierPass(Banner);
247 void MachineFunction::verify(Pass *p, const char *Banner) const {
248 MachineVerifier(p, Banner)
249 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
252 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
253 raw_ostream *OutFile = 0;
255 std::string ErrorInfo;
256 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
257 raw_fd_ostream::F_Append);
258 if (!ErrorInfo.empty()) {
259 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
271 TM = &MF.getTarget();
272 TII = TM->getInstrInfo();
273 TRI = TM->getRegisterInfo();
274 MRI = &MF.getRegInfo();
281 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
282 // We don't want to verify LiveVariables if LiveIntervals is available.
284 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
285 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
286 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
289 visitMachineFunctionBefore();
290 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
292 visitMachineBasicBlockBefore(MFI);
293 // Keep track of the current bundle header.
294 const MachineInstr *CurBundle = 0;
295 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
296 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
297 if (MBBI->getParent() != MFI) {
298 report("Bad instruction parent pointer", MFI);
299 *OS << "Instruction: " << *MBBI;
302 // Is this a bundle header?
303 if (!MBBI->isInsideBundle()) {
305 visitMachineBundleAfter(CurBundle);
307 visitMachineBundleBefore(CurBundle);
308 } else if (!CurBundle)
309 report("No bundle header", MBBI);
310 visitMachineInstrBefore(MBBI);
311 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
312 visitMachineOperand(&MBBI->getOperand(I), I);
313 visitMachineInstrAfter(MBBI);
316 visitMachineBundleAfter(CurBundle);
317 visitMachineBasicBlockAfter(MFI);
319 visitMachineFunctionAfter();
323 else if (foundErrors)
324 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
332 regsLiveInButUnused.clear();
335 return false; // no changes
338 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
341 if (!foundErrors++) {
343 *OS << "# " << Banner << '\n';
344 MF->print(*OS, Indexes);
346 *OS << "*** Bad machine code: " << msg << " ***\n"
347 << "- function: " << MF->getFunction()->getName() << "\n";
350 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
352 report(msg, MBB->getParent());
353 *OS << "- basic block: " << MBB->getName()
355 << " (BB#" << MBB->getNumber() << ")";
357 *OS << " [" << Indexes->getMBBStartIdx(MBB)
358 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
362 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
364 report(msg, MI->getParent());
365 *OS << "- instruction: ";
366 if (Indexes && Indexes->hasIndex(MI))
367 *OS << Indexes->getInstructionIndex(MI) << '\t';
371 void MachineVerifier::report(const char *msg,
372 const MachineOperand *MO, unsigned MONum) {
374 report(msg, MO->getParent());
375 *OS << "- operand " << MONum << ": ";
380 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
381 BBInfo &MInfo = MBBInfoMap[MBB];
382 if (!MInfo.reachable) {
383 MInfo.reachable = true;
384 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
385 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
390 void MachineVerifier::visitMachineFunctionBefore() {
391 lastIndex = SlotIndex();
392 regsReserved = TRI->getReservedRegs(*MF);
394 // A sub-register of a reserved register is also reserved
395 for (int Reg = regsReserved.find_first(); Reg>=0;
396 Reg = regsReserved.find_next(Reg)) {
397 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
398 // FIXME: This should probably be:
399 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
400 regsReserved.set(*SubRegs);
404 regsAllocatable = TRI->getAllocatableSet(*MF);
406 markReachable(&MF->front());
409 // Does iterator point to a and b as the first two elements?
410 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
411 const MachineBasicBlock *a, const MachineBasicBlock *b) {
420 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
424 // If this block has allocatable physical registers live-in, check that
425 // it is an entry block or landing pad.
426 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
427 LE = MBB->livein_end();
430 if (isAllocatable(reg) && !MBB->isLandingPad() &&
431 MBB != MBB->getParent()->begin()) {
432 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
437 // Count the number of landing pad successors.
438 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
439 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
440 E = MBB->succ_end(); I != E; ++I) {
441 if ((*I)->isLandingPad())
442 LandingPadSuccs.insert(*I);
445 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
446 const BasicBlock *BB = MBB->getBasicBlock();
447 if (LandingPadSuccs.size() > 1 &&
449 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
450 BB && isa<SwitchInst>(BB->getTerminator())))
451 report("MBB has more than one landing pad successor", MBB);
453 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
454 MachineBasicBlock *TBB = 0, *FBB = 0;
455 SmallVector<MachineOperand, 4> Cond;
456 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
458 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
459 // check whether its answers match up with reality.
461 // Block falls through to its successor.
462 MachineFunction::const_iterator MBBI = MBB;
464 if (MBBI == MF->end()) {
465 // It's possible that the block legitimately ends with a noreturn
466 // call or an unreachable, in which case it won't actually fall
467 // out the bottom of the function.
468 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
469 // It's possible that the block legitimately ends with a noreturn
470 // call or an unreachable, in which case it won't actuall fall
472 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
473 report("MBB exits via unconditional fall-through but doesn't have "
474 "exactly one CFG successor!", MBB);
475 } else if (!MBB->isSuccessor(MBBI)) {
476 report("MBB exits via unconditional fall-through but its successor "
477 "differs from its CFG successor!", MBB);
479 if (!MBB->empty() && getBundleStart(&MBB->back())->isBarrier() &&
480 !TII->isPredicated(getBundleStart(&MBB->back()))) {
481 report("MBB exits via unconditional fall-through but ends with a "
482 "barrier instruction!", MBB);
485 report("MBB exits via unconditional fall-through but has a condition!",
488 } else if (TBB && !FBB && Cond.empty()) {
489 // Block unconditionally branches somewhere.
490 if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
491 report("MBB exits via unconditional branch but doesn't have "
492 "exactly one CFG successor!", MBB);
493 } else if (!MBB->isSuccessor(TBB)) {
494 report("MBB exits via unconditional branch but the CFG "
495 "successor doesn't match the actual successor!", MBB);
498 report("MBB exits via unconditional branch but doesn't contain "
499 "any instructions!", MBB);
500 } else if (!getBundleStart(&MBB->back())->isBarrier()) {
501 report("MBB exits via unconditional branch but doesn't end with a "
502 "barrier instruction!", MBB);
503 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
504 report("MBB exits via unconditional branch but the branch isn't a "
505 "terminator instruction!", MBB);
507 } else if (TBB && !FBB && !Cond.empty()) {
508 // Block conditionally branches somewhere, otherwise falls through.
509 MachineFunction::const_iterator MBBI = MBB;
511 if (MBBI == MF->end()) {
512 report("MBB conditionally falls through out of function!", MBB);
513 } if (MBB->succ_size() != 2) {
514 report("MBB exits via conditional branch/fall-through but doesn't have "
515 "exactly two CFG successors!", MBB);
516 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
517 report("MBB exits via conditional branch/fall-through but the CFG "
518 "successors don't match the actual successors!", MBB);
521 report("MBB exits via conditional branch/fall-through but doesn't "
522 "contain any instructions!", MBB);
523 } else if (getBundleStart(&MBB->back())->isBarrier()) {
524 report("MBB exits via conditional branch/fall-through but ends with a "
525 "barrier instruction!", MBB);
526 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
527 report("MBB exits via conditional branch/fall-through but the branch "
528 "isn't a terminator instruction!", MBB);
530 } else if (TBB && FBB) {
531 // Block conditionally branches somewhere, otherwise branches
533 if (MBB->succ_size() != 2) {
534 report("MBB exits via conditional branch/branch but doesn't have "
535 "exactly two CFG successors!", MBB);
536 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
537 report("MBB exits via conditional branch/branch but the CFG "
538 "successors don't match the actual successors!", MBB);
541 report("MBB exits via conditional branch/branch but doesn't "
542 "contain any instructions!", MBB);
543 } else if (!getBundleStart(&MBB->back())->isBarrier()) {
544 report("MBB exits via conditional branch/branch but doesn't end with a "
545 "barrier instruction!", MBB);
546 } else if (!getBundleStart(&MBB->back())->isTerminator()) {
547 report("MBB exits via conditional branch/branch but the branch "
548 "isn't a terminator instruction!", MBB);
551 report("MBB exits via conditinal branch/branch but there's no "
555 report("AnalyzeBranch returned invalid data!", MBB);
560 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
561 E = MBB->livein_end(); I != E; ++I) {
562 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
563 report("MBB live-in list contains non-physical register", MBB);
567 for (MCSubRegIterator SubRegs(*I, TRI); SubRegs.isValid(); ++SubRegs)
568 regsLive.insert(*SubRegs);
570 regsLiveInButUnused = regsLive;
572 const MachineFrameInfo *MFI = MF->getFrameInfo();
573 assert(MFI && "Function has no frame info");
574 BitVector PR = MFI->getPristineRegs(MBB);
575 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
577 for (MCSubRegIterator SubRegs(I, TRI); SubRegs.isValid(); ++SubRegs)
578 regsLive.insert(*SubRegs);
585 lastIndex = Indexes->getMBBStartIdx(MBB);
588 // This function gets called for all bundle headers, including normal
589 // stand-alone unbundled instructions.
590 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
591 if (Indexes && Indexes->hasIndex(MI)) {
592 SlotIndex idx = Indexes->getInstructionIndex(MI);
593 if (!(idx > lastIndex)) {
594 report("Instruction index out of order", MI);
595 *OS << "Last instruction was at " << lastIndex << '\n';
600 // Ensure non-terminators don't follow terminators.
601 // Ignore predicated terminators formed by if conversion.
602 // FIXME: If conversion shouldn't need to violate this rule.
603 if (MI->isTerminator() && !TII->isPredicated(MI)) {
604 if (!FirstTerminator)
605 FirstTerminator = MI;
606 } else if (FirstTerminator) {
607 report("Non-terminator instruction after the first terminator", MI);
608 *OS << "First terminator was:\t" << *FirstTerminator;
612 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
613 const MCInstrDesc &MCID = MI->getDesc();
614 if (MI->getNumOperands() < MCID.getNumOperands()) {
615 report("Too few operands", MI);
616 *OS << MCID.getNumOperands() << " operands expected, but "
617 << MI->getNumExplicitOperands() << " given.\n";
620 // Check the MachineMemOperands for basic consistency.
621 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
622 E = MI->memoperands_end(); I != E; ++I) {
623 if ((*I)->isLoad() && !MI->mayLoad())
624 report("Missing mayLoad flag", MI);
625 if ((*I)->isStore() && !MI->mayStore())
626 report("Missing mayStore flag", MI);
629 // Debug values must not have a slot index.
630 // Other instructions must have one, unless they are inside a bundle.
632 bool mapped = !LiveInts->isNotInMIMap(MI);
633 if (MI->isDebugValue()) {
635 report("Debug instruction has a slot index", MI);
636 } else if (MI->isInsideBundle()) {
638 report("Instruction inside bundle has a slot index", MI);
641 report("Missing slot index", MI);
646 if (!TII->verifyInstruction(MI, ErrorInfo))
647 report(ErrorInfo.data(), MI);
651 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
652 const MachineInstr *MI = MO->getParent();
653 const MCInstrDesc &MCID = MI->getDesc();
654 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
656 // The first MCID.NumDefs operands must be explicit register defines
657 if (MONum < MCID.getNumDefs()) {
659 report("Explicit definition must be a register", MO, MONum);
660 else if (!MO->isDef() && !MCOI.isOptionalDef())
661 report("Explicit definition marked as use", MO, MONum);
662 else if (MO->isImplicit())
663 report("Explicit definition marked as implicit", MO, MONum);
664 } else if (MONum < MCID.getNumOperands()) {
665 // Don't check if it's the last operand in a variadic instruction. See,
666 // e.g., LDM_RET in the arm back end.
668 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
669 if (MO->isDef() && !MCOI.isOptionalDef())
670 report("Explicit operand marked as def", MO, MONum);
671 if (MO->isImplicit())
672 report("Explicit operand marked as implicit", MO, MONum);
675 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
676 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
677 report("Extra explicit operand on non-variadic instruction", MO, MONum);
680 switch (MO->getType()) {
681 case MachineOperand::MO_Register: {
682 const unsigned Reg = MO->getReg();
685 if (MRI->tracksLiveness() && !MI->isDebugValue())
686 checkLiveness(MO, MONum);
688 // Verify two-address constraints after leaving SSA form.
690 if (!MRI->isSSA() && MO->isUse() &&
691 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
692 Reg != MI->getOperand(DefIdx).getReg())
693 report("Two-address instruction operands must be identical", MO, MONum);
695 // Check register classes.
696 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
697 unsigned SubIdx = MO->getSubReg();
699 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
701 report("Illegal subregister index for physical register", MO, MONum);
704 if (const TargetRegisterClass *DRC =
705 TII->getRegClass(MCID, MONum, TRI, *MF)) {
706 if (!DRC->contains(Reg)) {
707 report("Illegal physical register for instruction", MO, MONum);
708 *OS << TRI->getName(Reg) << " is not a "
709 << DRC->getName() << " register.\n";
714 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
716 const TargetRegisterClass *SRC =
717 TRI->getSubClassWithSubReg(RC, SubIdx);
719 report("Invalid subregister index for virtual register", MO, MONum);
720 *OS << "Register class " << RC->getName()
721 << " does not support subreg index " << SubIdx << "\n";
725 report("Invalid register class for subregister index", MO, MONum);
726 *OS << "Register class " << RC->getName()
727 << " does not fully support subreg index " << SubIdx << "\n";
731 if (const TargetRegisterClass *DRC =
732 TII->getRegClass(MCID, MONum, TRI, *MF)) {
734 const TargetRegisterClass *SuperRC =
735 TRI->getLargestLegalSuperClass(RC);
737 report("No largest legal super class exists.", MO, MONum);
740 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
742 report("No matching super-reg register class.", MO, MONum);
746 if (!RC->hasSuperClassEq(DRC)) {
747 report("Illegal virtual register for instruction", MO, MONum);
748 *OS << "Expected a " << DRC->getName() << " register, but got a "
749 << RC->getName() << " register\n";
757 case MachineOperand::MO_RegisterMask:
758 regMasks.push_back(MO->getRegMask());
761 case MachineOperand::MO_MachineBasicBlock:
762 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
763 report("PHI operand is not in the CFG", MO, MONum);
766 case MachineOperand::MO_FrameIndex:
767 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
768 LiveInts && !LiveInts->isNotInMIMap(MI)) {
769 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
770 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
771 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
772 report("Instruction loads from dead spill slot", MO, MONum);
773 *OS << "Live stack: " << LI << '\n';
775 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
776 report("Instruction stores to dead spill slot", MO, MONum);
777 *OS << "Live stack: " << LI << '\n';
787 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
788 const MachineInstr *MI = MO->getParent();
789 const unsigned Reg = MO->getReg();
791 // Both use and def operands can read a register.
792 if (MO->readsReg()) {
793 regsLiveInButUnused.erase(Reg);
796 addRegWithSubRegs(regsKilled, Reg);
798 // Check that LiveVars knows this kill.
799 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
801 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
802 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
803 report("Kill missing from LiveVariables", MO, MONum);
806 // Check LiveInts liveness and kill.
807 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
808 LiveInts && !LiveInts->isNotInMIMap(MI)) {
809 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getRegSlot(true);
810 if (LiveInts->hasInterval(Reg)) {
811 const LiveInterval &LI = LiveInts->getInterval(Reg);
812 if (!LI.liveAt(UseIdx)) {
813 report("No live range at use", MO, MONum);
814 *OS << UseIdx << " is not live in " << LI << '\n';
816 // Check for extra kill flags.
817 // Note that we allow missing kill flags for now.
818 if (MO->isKill() && !LI.killedAt(UseIdx.getRegSlot())) {
819 report("Live range continues after kill flag", MO, MONum);
820 *OS << "Live range: " << LI << '\n';
823 report("Virtual register has no Live interval", MO, MONum);
827 // Use of a dead register.
828 if (!regsLive.count(Reg)) {
829 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
830 // Reserved registers may be used even when 'dead'.
831 if (!isReserved(Reg))
832 report("Using an undefined physical register", MO, MONum);
833 } else if (MRI->def_empty(Reg)) {
834 report("Reading virtual register without a def", MO, MONum);
836 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
837 // We don't know which virtual registers are live in, so only complain
838 // if vreg was killed in this MBB. Otherwise keep track of vregs that
839 // must be live in. PHI instructions are handled separately.
840 if (MInfo.regsKilled.count(Reg))
841 report("Using a killed virtual register", MO, MONum);
842 else if (!MI->isPHI())
843 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
850 // TODO: verify that earlyclobber ops are not used.
852 addRegWithSubRegs(regsDead, Reg);
854 addRegWithSubRegs(regsDefined, Reg);
857 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
858 llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
859 report("Multiple virtual register defs in SSA form", MO, MONum);
861 // Check LiveInts for a live range, but only for virtual registers.
862 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
863 !LiveInts->isNotInMIMap(MI)) {
864 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
865 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
866 if (LiveInts->hasInterval(Reg)) {
867 const LiveInterval &LI = LiveInts->getInterval(Reg);
868 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
869 assert(VNI && "NULL valno is not allowed");
870 if (VNI->def != DefIdx) {
871 report("Inconsistent valno->def", MO, MONum);
872 *OS << "Valno " << VNI->id << " is not defined at "
873 << DefIdx << " in " << LI << '\n';
876 report("No live range at def", MO, MONum);
877 *OS << DefIdx << " is not live in " << LI << '\n';
880 report("Virtual register has no Live interval", MO, MONum);
886 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
889 // This function gets called after visiting all instructions in a bundle. The
890 // argument points to the bundle header.
891 // Normal stand-alone instructions are also considered 'bundles', and this
892 // function is called for all of them.
893 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
894 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
895 set_union(MInfo.regsKilled, regsKilled);
896 set_subtract(regsLive, regsKilled); regsKilled.clear();
897 // Kill any masked registers.
898 while (!regMasks.empty()) {
899 const uint32_t *Mask = regMasks.pop_back_val();
900 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
901 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
902 MachineOperand::clobbersPhysReg(Mask, *I))
903 regsDead.push_back(*I);
905 set_subtract(regsLive, regsDead); regsDead.clear();
906 set_union(regsLive, regsDefined); regsDefined.clear();
910 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
911 MBBInfoMap[MBB].regsLiveOut = regsLive;
915 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
916 if (!(stop > lastIndex)) {
917 report("Block ends before last instruction index", MBB);
918 *OS << "Block ends at " << stop
919 << " last instruction was at " << lastIndex << '\n';
925 // Calculate the largest possible vregsPassed sets. These are the registers that
926 // can pass through an MBB live, but may not be live every time. It is assumed
927 // that all vregsPassed sets are empty before the call.
928 void MachineVerifier::calcRegsPassed() {
929 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
930 // have any vregsPassed.
931 SmallPtrSet<const MachineBasicBlock*, 8> todo;
932 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
934 const MachineBasicBlock &MBB(*MFI);
935 BBInfo &MInfo = MBBInfoMap[&MBB];
936 if (!MInfo.reachable)
938 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
939 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
940 BBInfo &SInfo = MBBInfoMap[*SuI];
941 if (SInfo.addPassed(MInfo.regsLiveOut))
946 // Iteratively push vregsPassed to successors. This will converge to the same
947 // final state regardless of DenseSet iteration order.
948 while (!todo.empty()) {
949 const MachineBasicBlock *MBB = *todo.begin();
951 BBInfo &MInfo = MBBInfoMap[MBB];
952 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
953 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
956 BBInfo &SInfo = MBBInfoMap[*SuI];
957 if (SInfo.addPassed(MInfo.vregsPassed))
963 // Calculate the set of virtual registers that must be passed through each basic
964 // block in order to satisfy the requirements of successor blocks. This is very
965 // similar to calcRegsPassed, only backwards.
966 void MachineVerifier::calcRegsRequired() {
967 // First push live-in regs to predecessors' vregsRequired.
968 SmallPtrSet<const MachineBasicBlock*, 8> todo;
969 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
971 const MachineBasicBlock &MBB(*MFI);
972 BBInfo &MInfo = MBBInfoMap[&MBB];
973 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
974 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
975 BBInfo &PInfo = MBBInfoMap[*PrI];
976 if (PInfo.addRequired(MInfo.vregsLiveIn))
981 // Iteratively push vregsRequired to predecessors. This will converge to the
982 // same final state regardless of DenseSet iteration order.
983 while (!todo.empty()) {
984 const MachineBasicBlock *MBB = *todo.begin();
986 BBInfo &MInfo = MBBInfoMap[MBB];
987 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
988 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
991 BBInfo &SInfo = MBBInfoMap[*PrI];
992 if (SInfo.addRequired(MInfo.vregsRequired))
998 // Check PHI instructions at the beginning of MBB. It is assumed that
999 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1000 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1001 SmallPtrSet<const MachineBasicBlock*, 8> seen;
1002 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
1003 BBI != BBE && BBI->isPHI(); ++BBI) {
1006 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
1007 unsigned Reg = BBI->getOperand(i).getReg();
1008 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
1009 if (!Pre->isSuccessor(MBB))
1012 BBInfo &PrInfo = MBBInfoMap[Pre];
1013 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1014 report("PHI operand is not live-out from predecessor",
1015 &BBI->getOperand(i), i);
1018 // Did we see all predecessors?
1019 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1020 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1021 if (!seen.count(*PrI)) {
1022 report("Missing PHI operand", BBI);
1023 *OS << "BB#" << (*PrI)->getNumber()
1024 << " is a predecessor according to the CFG.\n";
1030 void MachineVerifier::visitMachineFunctionAfter() {
1033 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1034 MFI != MFE; ++MFI) {
1035 BBInfo &MInfo = MBBInfoMap[MFI];
1037 // Skip unreachable MBBs.
1038 if (!MInfo.reachable)
1044 // Now check liveness info if available
1047 // Check for killed virtual registers that should be live out.
1048 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1049 MFI != MFE; ++MFI) {
1050 BBInfo &MInfo = MBBInfoMap[MFI];
1051 for (RegSet::iterator
1052 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1054 if (MInfo.regsKilled.count(*I)) {
1055 report("Virtual register killed in block, but needed live out.", MFI);
1056 *OS << "Virtual register " << PrintReg(*I)
1057 << " is used after the block.\n";
1062 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1063 for (RegSet::iterator
1064 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1066 report("Virtual register def doesn't dominate all uses.",
1067 MRI->getVRegDef(*I));
1071 verifyLiveVariables();
1073 verifyLiveIntervals();
1076 void MachineVerifier::verifyLiveVariables() {
1077 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1078 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1079 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1080 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1081 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1082 MFI != MFE; ++MFI) {
1083 BBInfo &MInfo = MBBInfoMap[MFI];
1085 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1086 if (MInfo.vregsRequired.count(Reg)) {
1087 if (!VI.AliveBlocks.test(MFI->getNumber())) {
1088 report("LiveVariables: Block missing from AliveBlocks", MFI);
1089 *OS << "Virtual register " << PrintReg(Reg)
1090 << " must be live through the block.\n";
1093 if (VI.AliveBlocks.test(MFI->getNumber())) {
1094 report("LiveVariables: Block should not be in AliveBlocks", MFI);
1095 *OS << "Virtual register " << PrintReg(Reg)
1096 << " is not needed live through the block.\n";
1103 void MachineVerifier::verifyLiveIntervals() {
1104 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1105 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1106 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1108 // Spilling and splitting may leave unused registers around. Skip them.
1109 if (MRI->reg_nodbg_empty(Reg))
1112 if (!LiveInts->hasInterval(Reg)) {
1113 report("Missing live interval for virtual register", MF);
1114 *OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
1118 const LiveInterval &LI = LiveInts->getInterval(Reg);
1119 assert(Reg == LI.reg && "Invalid reg to interval mapping");
1121 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
1124 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
1127 if (!VNI->isUnused()) {
1128 report("Valno not live at def and not marked unused", MF);
1129 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1134 if (VNI->isUnused())
1137 if (DefVNI != VNI) {
1138 report("Live range at def has different valno", MF);
1139 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1140 << " where valno #" << DefVNI->id << " is live in " << LI << '\n';
1144 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1146 report("Invalid definition index", MF);
1147 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1148 << " in " << LI << '\n';
1152 if (VNI->isPHIDef()) {
1153 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1154 report("PHIDef value is not defined at MBB start", MF);
1155 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1156 << ", not at the beginning of BB#" << MBB->getNumber()
1157 << " in " << LI << '\n';
1161 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1163 report("No instruction at def index", MF);
1164 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1165 << " in " << LI << '\n';
1169 bool hasDef = false;
1170 bool isEarlyClobber = false;
1171 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1172 if (!MOI->isReg() || !MOI->isDef())
1174 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1175 if (MOI->getReg() != LI.reg)
1178 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1179 !TRI->regsOverlap(LI.reg, MOI->getReg()))
1183 if (MOI->isEarlyClobber())
1184 isEarlyClobber = true;
1188 report("Defining instruction does not modify register", MI);
1189 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1192 // Early clobber defs begin at USE slots, but other defs must begin at
1194 if (isEarlyClobber) {
1195 if (!VNI->def.isEarlyClobber()) {
1196 report("Early clobber def must be at an early-clobber slot", MF);
1197 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1198 << " in " << LI << '\n';
1200 } else if (!VNI->def.isRegister()) {
1201 report("Non-PHI, non-early clobber def must be at a register slot",
1203 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1204 << " in " << LI << '\n';
1209 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
1210 const VNInfo *VNI = I->valno;
1211 assert(VNI && "Live range has no valno");
1213 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1214 report("Foreign valno in live range", MF);
1216 *OS << " has a valno not in " << LI << '\n';
1219 if (VNI->isUnused()) {
1220 report("Live range valno is marked unused", MF);
1222 *OS << " in " << LI << '\n';
1225 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1227 report("Bad start of live segment, no basic block", MF);
1229 *OS << " in " << LI << '\n';
1232 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1233 if (I->start != MBBStartIdx && I->start != VNI->def) {
1234 report("Live segment must begin at MBB entry or valno def", MBB);
1236 *OS << " in " << LI << '\n' << "Basic block starts at "
1237 << MBBStartIdx << '\n';
1240 const MachineBasicBlock *EndMBB =
1241 LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1243 report("Bad end of live segment, no basic block", MF);
1245 *OS << " in " << LI << '\n';
1249 // No more checks for live-out segments.
1250 if (I->end == LiveInts->getMBBEndIdx(EndMBB))
1253 // The live segment is ending inside EndMBB
1254 const MachineInstr *MI =
1255 LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1257 report("Live segment doesn't end at a valid instruction", EndMBB);
1259 *OS << " in " << LI << '\n' << "Basic block starts at "
1260 << MBBStartIdx << '\n';
1264 // The block slot must refer to a basic block boundary.
1265 if (I->end.isBlock()) {
1266 report("Live segment ends at B slot of an instruction", MI);
1268 *OS << " in " << LI << '\n';
1271 if (I->end.isDead()) {
1272 // Segment ends on the dead slot.
1273 // That means there must be a dead def.
1274 if (!SlotIndex::isSameInstr(I->start, I->end)) {
1275 report("Live segment ending at dead slot spans instructions", MI);
1277 *OS << " in " << LI << '\n';
1281 // A live segment can only end at an early-clobber slot if it is being
1282 // redefined by an early-clobber def.
1283 if (I->end.isEarlyClobber()) {
1284 if (I+1 == E || (I+1)->start != I->end) {
1285 report("Live segment ending at early clobber slot must be "
1286 "redefined by an EC def in the same instruction", MI);
1288 *OS << " in " << LI << '\n';
1292 // The following checks only apply to virtual registers. Physreg liveness
1293 // is too weird to check.
1294 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1295 // A live range can end with either a redefinition, a kill flag on a
1296 // use, or a dead flag on a def.
1297 bool hasRead = false;
1298 bool hasDeadDef = false;
1299 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1300 if (!MOI->isReg() || MOI->getReg() != LI.reg)
1302 if (MOI->readsReg())
1304 if (MOI->isDef() && MOI->isDead())
1308 if (I->end.isDead()) {
1310 report("Instruction doesn't have a dead def operand", MI);
1312 *OS << " in " << LI << '\n';
1316 report("Instruction ending live range doesn't read the register",
1319 *OS << " in " << LI << '\n';
1324 // Now check all the basic blocks in this live segment.
1325 MachineFunction::const_iterator MFI = MBB;
1326 // Is this live range the beginning of a non-PHIDef VN?
1327 if (I->start == VNI->def && !VNI->isPHIDef()) {
1328 // Not live-in to any blocks.
1335 assert(LiveInts->isLiveInToMBB(LI, MFI));
1336 // We don't know how to track physregs into a landing pad.
1337 if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
1338 MFI->isLandingPad()) {
1339 if (&*MFI == EndMBB)
1345 // Is VNI a PHI-def in the current block?
1346 bool IsPHI = VNI->isPHIDef() &&
1347 VNI->def == LiveInts->getMBBStartIdx(MFI);
1349 // Check that VNI is live-out of all predecessors.
1350 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1351 PE = MFI->pred_end(); PI != PE; ++PI) {
1352 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1353 const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
1355 // All predecessors must have a live-out value.
1357 report("Register not marked live out of predecessor", *PI);
1358 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1359 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1360 << PEnd << " in " << LI << '\n';
1364 // Only PHI-defs can take different predecessor values.
1365 if (!IsPHI && PVNI != VNI) {
1366 report("Different value live out of predecessor", *PI);
1367 *OS << "Valno #" << PVNI->id << " live out of BB#"
1368 << (*PI)->getNumber() << '@' << PEnd
1369 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1370 << '@' << LiveInts->getMBBStartIdx(MFI) << " in "
1371 << PrintReg(Reg) << ": " << LI << '\n';
1374 if (&*MFI == EndMBB)
1380 // Check the LI only has one connected component.
1381 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1382 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1383 unsigned NumComp = ConEQ.Classify(&LI);
1385 report("Multiple connected components in live interval", MF);
1386 *OS << NumComp << " components in " << LI << '\n';
1387 for (unsigned comp = 0; comp != NumComp; ++comp) {
1388 *OS << comp << ": valnos";
1389 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1390 E = LI.vni_end(); I!=E; ++I)
1391 if (comp == ConEQ.getEqClass(*I))
1392 *OS << ' ' << (*I)->id;