1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/ADT/DenseSet.h"
27 #include "llvm/ADT/SetOperations.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Function.h"
30 #include "llvm/CodeGen/LiveVariables.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
46 struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
47 static char ID; // Pass ID, replacement for typeid
49 MachineVerifier(bool allowDoubleDefs = false) :
50 MachineFunctionPass(&ID),
51 allowVirtDoubleDefs(allowDoubleDefs),
52 allowPhysDoubleDefs(allowDoubleDefs),
53 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
56 void getAnalysisUsage(AnalysisUsage &AU) const {
60 bool runOnMachineFunction(MachineFunction &MF);
62 const bool allowVirtDoubleDefs;
63 const bool allowPhysDoubleDefs;
65 const char *const OutFileName;
67 const MachineFunction *MF;
68 const TargetMachine *TM;
69 const TargetRegisterInfo *TRI;
70 const MachineRegisterInfo *MRI;
74 typedef SmallVector<unsigned, 16> RegVector;
75 typedef DenseSet<unsigned> RegSet;
76 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
78 BitVector regsReserved;
80 RegVector regsDefined, regsImpDefined, regsDead, regsKilled;
82 // Add Reg and any sub-registers to RV
83 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
85 if (TargetRegisterInfo::isPhysicalRegister(Reg))
86 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
90 // Does RS contain any super-registers of Reg?
91 bool anySuperRegisters(const RegSet &RS, unsigned Reg) {
92 for (const unsigned *R = TRI->getSuperRegisters(Reg); *R; R++)
99 // Is this MBB reachable from the MF entry point?
102 // Vregs that must be live in because they are used without being
103 // defined. Map value is the user.
106 // Vregs that must be dead in because they are defined without being
107 // killed first. Map value is the defining instruction.
110 // Regs killed in MBB. They may be defined again, and will then be in both
111 // regsKilled and regsLiveOut.
114 // Regs defined in MBB and live out. Note that vregs passing through may
115 // be live out without being mentioned here.
118 // Vregs that pass through MBB untouched. This set is disjoint from
119 // regsKilled and regsLiveOut.
122 BBInfo() : reachable(false) {}
124 // Add register to vregsPassed if it belongs there. Return true if
126 bool addPassed(unsigned Reg) {
127 if (!TargetRegisterInfo::isVirtualRegister(Reg))
129 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
131 return vregsPassed.insert(Reg).second;
134 // Same for a full set.
135 bool addPassed(const RegSet &RS) {
136 bool changed = false;
137 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
143 // Live-out registers are either in regsLiveOut or vregsPassed.
144 bool isLiveOut(unsigned Reg) const {
145 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
149 // Extra register info per MBB.
150 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
152 bool isReserved(unsigned Reg) {
153 return Reg < regsReserved.size() && regsReserved[Reg];
156 void visitMachineFunctionBefore();
157 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
158 void visitMachineInstrBefore(const MachineInstr *MI);
159 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
160 void visitMachineInstrAfter(const MachineInstr *MI);
161 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
162 void visitMachineFunctionAfter();
164 void report(const char *msg, const MachineFunction *MF);
165 void report(const char *msg, const MachineBasicBlock *MBB);
166 void report(const char *msg, const MachineInstr *MI);
167 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
169 void markReachable(const MachineBasicBlock *MBB);
170 void calcMaxRegsPassed();
171 void calcMinRegsPassed();
172 void checkPHIOps(const MachineBasicBlock *MBB);
176 char MachineVerifier::ID = 0;
177 static RegisterPass<MachineVerifier>
178 MachineVer("machineverifier", "Verify generated machine code");
179 static const PassInfo *const MachineVerifyID = &MachineVer;
182 llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
184 return new MachineVerifier(allowPhysDoubleDefs);
188 MachineVerifier::runOnMachineFunction(MachineFunction &MF)
190 std::ofstream OutFile;
192 OutFile.open(OutFileName, std::ios::out | std::ios::app);
201 TM = &MF.getTarget();
202 TRI = TM->getRegisterInfo();
203 MRI = &MF.getRegInfo();
205 visitMachineFunctionBefore();
206 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
208 visitMachineBasicBlockBefore(MFI);
209 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
210 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
211 visitMachineInstrBefore(MBBI);
212 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
213 visitMachineOperand(&MBBI->getOperand(I), I);
214 visitMachineInstrAfter(MBBI);
216 visitMachineBasicBlockAfter(MFI);
218 visitMachineFunctionAfter();
225 raw_string_ostream Msg(msg);
226 Msg << "\nStopping with " << foundErrors << " machine code errors.";
227 llvm_report_error(Msg.str());
230 return false; // no changes
234 MachineVerifier::report(const char *msg, const MachineFunction *MF)
240 *OS << "*** Bad machine code: " << msg << " ***\n"
241 << "- function: " << MF->getFunction()->getName() << "\n";
245 MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
248 report(msg, MBB->getParent());
249 *OS << "- basic block: " << MBB->getBasicBlock()->getName()
251 << " (#" << MBB->getNumber() << ")\n";
255 MachineVerifier::report(const char *msg, const MachineInstr *MI)
258 report(msg, MI->getParent());
259 *OS << "- instruction: ";
264 MachineVerifier::report(const char *msg,
265 const MachineOperand *MO, unsigned MONum)
268 report(msg, MO->getParent());
269 *OS << "- operand " << MONum << ": ";
275 MachineVerifier::markReachable(const MachineBasicBlock *MBB)
277 BBInfo &MInfo = MBBInfoMap[MBB];
278 if (!MInfo.reachable) {
279 MInfo.reachable = true;
280 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
281 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
287 MachineVerifier::visitMachineFunctionBefore()
289 regsReserved = TRI->getReservedRegs(*MF);
290 markReachable(&MF->front());
294 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
297 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
298 E = MBB->livein_end(); I != E; ++I) {
299 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
300 report("MBB live-in list contains non-physical register", MBB);
304 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
309 regsImpDefined.clear();
313 MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
315 const TargetInstrDesc &TI = MI->getDesc();
316 if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
317 report("Too few operands", MI);
318 *OS << TI.getNumOperands() << " operands expected, but "
319 << MI->getNumExplicitOperands() << " given.\n";
321 if (!TI.isVariadic()) {
322 if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
323 report("Too many operands", MI);
324 *OS << TI.getNumOperands() << " operands expected, but "
325 << MI->getNumExplicitOperands() << " given.\n";
331 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
333 const MachineInstr *MI = MO->getParent();
334 const TargetInstrDesc &TI = MI->getDesc();
336 // The first TI.NumDefs operands must be explicit register defines
337 if (MONum < TI.getNumDefs()) {
339 report("Explicit definition must be a register", MO, MONum);
340 else if (!MO->isDef())
341 report("Explicit definition marked as use", MO, MONum);
342 else if (MO->isImplicit())
343 report("Explicit definition marked as implicit", MO, MONum);
346 switch (MO->getType()) {
347 case MachineOperand::MO_Register: {
348 const unsigned Reg = MO->getReg();
352 // Check Live Variables.
355 addRegWithSubRegs(regsKilled, Reg);
357 // TwoAddress instr modyfying a reg is treated as kill+def.
359 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
360 MI->getOperand(defIdx).getReg() == Reg)
361 addRegWithSubRegs(regsKilled, Reg);
363 // Explicit use of a dead register.
364 if (!MO->isImplicit() && !regsLive.count(Reg)) {
365 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
366 // Reserved registers may be used even when 'dead'.
367 if (!isReserved(Reg))
368 report("Using an undefined physical register", MO, MONum);
370 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
371 // We don't know which virtual registers are live in, so only complain
372 // if vreg was killed in this MBB. Otherwise keep track of vregs that
373 // must be live in. PHI instructions are handled separately.
374 if (MInfo.regsKilled.count(Reg))
375 report("Using a killed virtual register", MO, MONum);
376 else if (MI->getOpcode() != TargetInstrInfo::PHI)
377 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
382 // TODO: verify that earlyclobber ops are not used.
383 if (MO->isImplicit())
384 addRegWithSubRegs(regsImpDefined, Reg);
386 addRegWithSubRegs(regsDefined, Reg);
389 addRegWithSubRegs(regsDead, Reg);
392 // Check register classes.
393 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
394 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
395 unsigned SubIdx = MO->getSubReg();
397 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
400 unsigned s = TRI->getSubReg(Reg, SubIdx);
402 report("Invalid subregister index for physical register",
409 const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass);
410 if (!DRC->contains(sr)) {
411 report("Illegal physical register for instruction", MO, MONum);
412 *OS << TRI->getName(sr) << " is not a "
413 << DRC->getName() << " register.\n";
418 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
420 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
421 report("Invalid subregister index for virtual register", MO, MONum);
424 RC = *(RC->subregclasses_begin()+SubIdx);
427 const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass);
428 if (RC != DRC && !RC->hasSuperClass(DRC)) {
429 report("Illegal virtual register for instruction", MO, MONum);
430 *OS << "Expected a " << DRC->getName() << " register, but got a "
431 << RC->getName() << " register\n";
438 // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
439 // case MachineOperand::MO_MachineBasicBlock:
440 // if (MI->getOpcode() == TargetInstrInfo::PHI) {
441 // if (!MO->getMBB()->isSuccessor(MI->getParent()))
442 // report("PHI operand is not in the CFG", MO, MONum);
451 MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
453 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
454 set_union(MInfo.regsKilled, regsKilled);
455 set_subtract(regsLive, regsKilled);
458 for (RegVector::const_iterator I = regsDefined.begin(),
459 E = regsDefined.end(); I != E; ++I) {
460 if (regsLive.count(*I)) {
461 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
462 // We allow double defines to physical registers with live
464 if (!allowPhysDoubleDefs && !isReserved(*I) &&
465 !anySuperRegisters(regsLive, *I)) {
466 report("Redefining a live physical register", MI);
467 *OS << "Register " << TRI->getName(*I)
468 << " was defined but already live.\n";
471 if (!allowVirtDoubleDefs) {
472 report("Redefining a live virtual register", MI);
473 *OS << "Virtual register %reg" << *I
474 << " was defined but already live.\n";
477 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
478 !MInfo.regsKilled.count(*I)) {
479 // Virtual register defined without being killed first must be dead on
481 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
485 set_union(regsLive, regsDefined); regsDefined.clear();
486 set_union(regsLive, regsImpDefined); regsImpDefined.clear();
487 set_subtract(regsLive, regsDead); regsDead.clear();
491 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
493 MBBInfoMap[MBB].regsLiveOut = regsLive;
497 // Calculate the largest possible vregsPassed sets. These are the registers that
498 // can pass through an MBB live, but may not be live every time. It is assumed
499 // that all vregsPassed sets are empty before the call.
501 MachineVerifier::calcMaxRegsPassed()
503 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
504 // have any vregsPassed.
505 DenseSet<const MachineBasicBlock*> todo;
506 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
508 const MachineBasicBlock &MBB(*MFI);
509 BBInfo &MInfo = MBBInfoMap[&MBB];
510 if (!MInfo.reachable)
512 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
513 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
514 BBInfo &SInfo = MBBInfoMap[*SuI];
515 if (SInfo.addPassed(MInfo.regsLiveOut))
520 // Iteratively push vregsPassed to successors. This will converge to the same
521 // final state regardless of DenseSet iteration order.
522 while (!todo.empty()) {
523 const MachineBasicBlock *MBB = *todo.begin();
525 BBInfo &MInfo = MBBInfoMap[MBB];
526 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
527 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
530 BBInfo &SInfo = MBBInfoMap[*SuI];
531 if (SInfo.addPassed(MInfo.vregsPassed))
537 // Calculate the minimum vregsPassed set. These are the registers that always
538 // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
539 // been called earlier.
541 MachineVerifier::calcMinRegsPassed()
543 DenseSet<const MachineBasicBlock*> todo;
544 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
548 while (!todo.empty()) {
549 const MachineBasicBlock *MBB = *todo.begin();
551 BBInfo &MInfo = MBBInfoMap[MBB];
553 // Remove entries from vRegsPassed that are not live out from all
554 // reachable predecessors.
556 for (RegSet::iterator I = MInfo.vregsPassed.begin(),
557 E = MInfo.vregsPassed.end(); I != E; ++I) {
558 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
559 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
560 BBInfo &PrInfo = MBBInfoMap[*PrI];
561 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
567 // If any regs removed, we need to recheck successors.
569 set_subtract(MInfo.vregsPassed, dead);
570 todo.insert(MBB->succ_begin(), MBB->succ_end());
575 // Check PHI instructions at the beginning of MBB. It is assumed that
576 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
578 MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
580 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
581 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
582 DenseSet<const MachineBasicBlock*> seen;
584 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
585 unsigned Reg = BBI->getOperand(i).getReg();
586 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
587 if (!Pre->isSuccessor(MBB))
590 BBInfo &PrInfo = MBBInfoMap[Pre];
591 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
592 report("PHI operand is not live-out from predecessor",
593 &BBI->getOperand(i), i);
596 // Did we see all predecessors?
597 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
598 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
599 if (!seen.count(*PrI)) {
600 report("Missing PHI operand", BBI);
601 *OS << "MBB #" << (*PrI)->getNumber()
602 << " is a predecessor according to the CFG.\n";
609 MachineVerifier::visitMachineFunctionAfter()
613 // With the maximal set of vregsPassed we can verify dead-in registers.
614 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
616 BBInfo &MInfo = MBBInfoMap[MFI];
618 // Skip unreachable MBBs.
619 if (!MInfo.reachable)
622 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
623 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
624 BBInfo &PrInfo = MBBInfoMap[*PrI];
625 if (!PrInfo.reachable)
628 // Verify physical live-ins. EH landing pads have magic live-ins so we
630 if (!MFI->isLandingPad()) {
631 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
632 E = MFI->livein_end(); I != E; ++I) {
633 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
634 !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
635 report("Live-in physical register is not live-out from predecessor",
637 *OS << "Register " << TRI->getName(*I)
638 << " is not live-out from MBB #" << (*PrI)->getNumber()
645 // Verify dead-in virtual registers.
646 if (!allowVirtDoubleDefs) {
647 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
648 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
649 // DeadIn register must be in neither regsLiveOut or vregsPassed of
651 if (PrInfo.isLiveOut(I->first)) {
652 report("Live-in virtual register redefined", I->second);
653 *OS << "Register %reg" << I->first
654 << " was live-out from predecessor MBB #"
655 << (*PrI)->getNumber() << ".\n";
664 // With the minimal set of vregsPassed we can verify live-in virtual
665 // registers, including PHI instructions.
666 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
668 BBInfo &MInfo = MBBInfoMap[MFI];
670 // Skip unreachable MBBs.
671 if (!MInfo.reachable)
676 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
677 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
678 BBInfo &PrInfo = MBBInfoMap[*PrI];
679 if (!PrInfo.reachable)
682 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
683 E = MInfo.vregsLiveIn.end(); I != E; ++I) {
684 if (!PrInfo.isLiveOut(I->first)) {
685 report("Used virtual register is not live-in", I->second);
686 *OS << "Register %reg" << I->first
687 << " is not live-out from predecessor MBB #"
688 << (*PrI)->getNumber()