1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/PriorityQueue.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterClassInfo.h"
27 #include "llvm/CodeGen/ScheduleDFS.h"
28 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/GraphWriter.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetInstrInfo.h"
40 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
41 cl::desc("Force top-down list scheduling"));
42 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
43 cl::desc("Force bottom-up list scheduling"));
47 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
48 cl::desc("Pop up a window to show MISched dags after they are processed"));
50 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
51 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
53 static bool ViewMISchedDAGs = false;
56 static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
57 cl::desc("Enable register pressure scheduling."), cl::init(true));
59 static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
60 cl::desc("Enable cyclic critical path analysis."), cl::init(false));
62 static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
63 cl::desc("Enable load clustering."), cl::init(true));
65 // Experimental heuristics
66 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
67 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
69 static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
70 cl::desc("Verify machine instrs before and after machine scheduling"));
72 // DAG subtrees must have at least this many nodes.
73 static const unsigned MinSubtreeSize = 8;
75 //===----------------------------------------------------------------------===//
76 // Machine Instruction Scheduling Pass and Registry
77 //===----------------------------------------------------------------------===//
79 MachineSchedContext::MachineSchedContext():
80 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
81 RegClassInfo = new RegisterClassInfo();
84 MachineSchedContext::~MachineSchedContext() {
89 /// MachineScheduler runs after coalescing and before register allocation.
90 class MachineScheduler : public MachineSchedContext,
91 public MachineFunctionPass {
95 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
97 virtual void releaseMemory() {}
99 virtual bool runOnMachineFunction(MachineFunction&);
101 virtual void print(raw_ostream &O, const Module* = 0) const;
103 static char ID; // Class identification, replacement for typeinfo
107 char MachineScheduler::ID = 0;
109 char &llvm::MachineSchedulerID = MachineScheduler::ID;
111 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
112 "Machine Instruction Scheduler", false, false)
113 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
114 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
115 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
116 INITIALIZE_PASS_END(MachineScheduler, "misched",
117 "Machine Instruction Scheduler", false, false)
119 MachineScheduler::MachineScheduler()
120 : MachineFunctionPass(ID) {
121 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
124 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
125 AU.setPreservesCFG();
126 AU.addRequiredID(MachineDominatorsID);
127 AU.addRequired<MachineLoopInfo>();
128 AU.addRequired<AliasAnalysis>();
129 AU.addRequired<TargetPassConfig>();
130 AU.addRequired<SlotIndexes>();
131 AU.addPreserved<SlotIndexes>();
132 AU.addRequired<LiveIntervals>();
133 AU.addPreserved<LiveIntervals>();
134 MachineFunctionPass::getAnalysisUsage(AU);
137 MachinePassRegistry MachineSchedRegistry::Registry;
139 /// A dummy default scheduler factory indicates whether the scheduler
140 /// is overridden on the command line.
141 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
145 /// MachineSchedOpt allows command line selection of the scheduler.
146 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
147 RegisterPassParser<MachineSchedRegistry> >
148 MachineSchedOpt("misched",
149 cl::init(&useDefaultMachineSched), cl::Hidden,
150 cl::desc("Machine instruction scheduler to use"));
152 static MachineSchedRegistry
153 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
154 useDefaultMachineSched);
156 /// Forward declare the standard machine scheduler. This will be used as the
157 /// default scheduler if the target does not set a default.
158 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C);
161 /// Decrement this iterator until reaching the top or a non-debug instr.
162 static MachineBasicBlock::const_iterator
163 priorNonDebug(MachineBasicBlock::const_iterator I,
164 MachineBasicBlock::const_iterator Beg) {
165 assert(I != Beg && "reached the top of the region, cannot decrement");
167 if (!I->isDebugValue())
173 /// Non-const version.
174 static MachineBasicBlock::iterator
175 priorNonDebug(MachineBasicBlock::iterator I,
176 MachineBasicBlock::const_iterator Beg) {
177 return const_cast<MachineInstr*>(
178 &*priorNonDebug(MachineBasicBlock::const_iterator(I), Beg));
181 /// If this iterator is a debug value, increment until reaching the End or a
182 /// non-debug instruction.
183 static MachineBasicBlock::const_iterator
184 nextIfDebug(MachineBasicBlock::const_iterator I,
185 MachineBasicBlock::const_iterator End) {
186 for(; I != End; ++I) {
187 if (!I->isDebugValue())
193 /// Non-const version.
194 static MachineBasicBlock::iterator
195 nextIfDebug(MachineBasicBlock::iterator I,
196 MachineBasicBlock::const_iterator End) {
197 // Cast the return value to nonconst MachineInstr, then cast to an
198 // instr_iterator, which does not check for null, finally return a
200 return MachineBasicBlock::instr_iterator(
201 const_cast<MachineInstr*>(
202 &*nextIfDebug(MachineBasicBlock::const_iterator(I), End)));
205 /// Top-level MachineScheduler pass driver.
207 /// Visit blocks in function order. Divide each block into scheduling regions
208 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
209 /// consistent with the DAG builder, which traverses the interior of the
210 /// scheduling regions bottom-up.
212 /// This design avoids exposing scheduling boundaries to the DAG builder,
213 /// simplifying the DAG builder's support for "special" target instructions.
214 /// At the same time the design allows target schedulers to operate across
215 /// scheduling boundaries, for example to bundle the boudary instructions
216 /// without reordering them. This creates complexity, because the target
217 /// scheduler must update the RegionBegin and RegionEnd positions cached by
218 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
219 /// design would be to split blocks at scheduling boundaries, but LLVM has a
220 /// general bias against block splitting purely for implementation simplicity.
221 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
222 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
224 // Initialize the context of the pass.
226 MLI = &getAnalysis<MachineLoopInfo>();
227 MDT = &getAnalysis<MachineDominatorTree>();
228 PassConfig = &getAnalysis<TargetPassConfig>();
229 AA = &getAnalysis<AliasAnalysis>();
231 LIS = &getAnalysis<LiveIntervals>();
232 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
234 if (VerifyScheduling) {
236 MF->verify(this, "Before machine scheduling.");
238 RegClassInfo->runOnMachineFunction(*MF);
240 // Select the scheduler, or set the default.
241 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
242 if (Ctor == useDefaultMachineSched) {
243 // Get the default scheduler set by the target.
244 Ctor = MachineSchedRegistry::getDefault();
246 Ctor = createConvergingSched;
247 MachineSchedRegistry::setDefault(Ctor);
250 // Instantiate the selected scheduler.
251 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
253 // Visit all machine basic blocks.
255 // TODO: Visit blocks in global postorder or postorder within the bottom-up
256 // loop tree. Then we can optionally compute global RegPressure.
257 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
258 MBB != MBBEnd; ++MBB) {
260 Scheduler->startBlock(MBB);
262 // Break the block into scheduling regions [I, RegionEnd), and schedule each
263 // region as soon as it is discovered. RegionEnd points the scheduling
264 // boundary at the bottom of the region. The DAG does not include RegionEnd,
265 // but the region does (i.e. the next RegionEnd is above the previous
266 // RegionBegin). If the current block has no terminator then RegionEnd ==
267 // MBB->end() for the bottom region.
269 // The Scheduler may insert instructions during either schedule() or
270 // exitRegion(), even for empty regions. So the local iterators 'I' and
271 // 'RegionEnd' are invalid across these calls.
272 unsigned RemainingInstrs = MBB->size();
273 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
274 RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
276 // Avoid decrementing RegionEnd for blocks with no terminator.
277 if (RegionEnd != MBB->end()
278 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
280 // Count the boundary instruction.
284 // The next region starts above the previous region. Look backward in the
285 // instruction stream until we find the nearest boundary.
286 unsigned NumRegionInstrs = 0;
287 MachineBasicBlock::iterator I = RegionEnd;
288 for(;I != MBB->begin(); --I, --RemainingInstrs, ++NumRegionInstrs) {
289 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
292 // Notify the scheduler of the region, even if we may skip scheduling
293 // it. Perhaps it still needs to be bundled.
294 Scheduler->enterRegion(MBB, I, RegionEnd, NumRegionInstrs);
296 // Skip empty scheduling regions (0 or 1 schedulable instructions).
297 if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
298 // Close the current region. Bundle the terminator if needed.
299 // This invalidates 'RegionEnd' and 'I'.
300 Scheduler->exitRegion();
303 DEBUG(dbgs() << "********** MI Scheduling **********\n");
304 DEBUG(dbgs() << MF->getName()
305 << ":BB#" << MBB->getNumber() << " " << MBB->getName()
306 << "\n From: " << *I << " To: ";
307 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
308 else dbgs() << "End";
309 dbgs() << " RegionInstrs: " << NumRegionInstrs
310 << " Remaining: " << RemainingInstrs << "\n");
312 // Schedule a region: possibly reorder instructions.
313 // This invalidates 'RegionEnd' and 'I'.
314 Scheduler->schedule();
316 // Close the current region.
317 Scheduler->exitRegion();
319 // Scheduling has invalidated the current iterator 'I'. Ask the
320 // scheduler for the top of it's scheduled region.
321 RegionEnd = Scheduler->begin();
323 assert(RemainingInstrs == 0 && "Instruction count mismatch!");
324 Scheduler->finishBlock();
326 Scheduler->finalizeSchedule();
328 if (VerifyScheduling)
329 MF->verify(this, "After machine scheduling.");
333 void MachineScheduler::print(raw_ostream &O, const Module* m) const {
337 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
338 void ReadyQueue::dump() {
339 dbgs() << Name << ": ";
340 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
341 dbgs() << Queue[i]->NodeNum << " ";
346 //===----------------------------------------------------------------------===//
347 // ScheduleDAGMI - Base class for MachineInstr scheduling with LiveIntervals
349 //===----------------------------------------------------------------------===//
351 ScheduleDAGMI::~ScheduleDAGMI() {
353 DeleteContainerPointers(Mutations);
357 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
358 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
361 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
362 if (SuccSU != &ExitSU) {
363 // Do not use WillCreateCycle, it assumes SD scheduling.
364 // If Pred is reachable from Succ, then the edge creates a cycle.
365 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
367 Topo.AddPred(SuccSU, PredDep.getSUnit());
369 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
370 // Return true regardless of whether a new edge needed to be inserted.
374 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
375 /// NumPredsLeft reaches zero, release the successor node.
377 /// FIXME: Adjust SuccSU height based on MinLatency.
378 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
379 SUnit *SuccSU = SuccEdge->getSUnit();
381 if (SuccEdge->isWeak()) {
382 --SuccSU->WeakPredsLeft;
383 if (SuccEdge->isCluster())
384 NextClusterSucc = SuccSU;
388 if (SuccSU->NumPredsLeft == 0) {
389 dbgs() << "*** Scheduling failed! ***\n";
391 dbgs() << " has been released too many times!\n";
395 --SuccSU->NumPredsLeft;
396 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
397 SchedImpl->releaseTopNode(SuccSU);
400 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
401 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
402 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
404 releaseSucc(SU, &*I);
408 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
409 /// NumSuccsLeft reaches zero, release the predecessor node.
411 /// FIXME: Adjust PredSU height based on MinLatency.
412 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
413 SUnit *PredSU = PredEdge->getSUnit();
415 if (PredEdge->isWeak()) {
416 --PredSU->WeakSuccsLeft;
417 if (PredEdge->isCluster())
418 NextClusterPred = PredSU;
422 if (PredSU->NumSuccsLeft == 0) {
423 dbgs() << "*** Scheduling failed! ***\n";
425 dbgs() << " has been released too many times!\n";
429 --PredSU->NumSuccsLeft;
430 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
431 SchedImpl->releaseBottomNode(PredSU);
434 /// releasePredecessors - Call releasePred on each of SU's predecessors.
435 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
436 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
438 releasePred(SU, &*I);
442 /// This is normally called from the main scheduler loop but may also be invoked
443 /// by the scheduling strategy to perform additional code motion.
444 void ScheduleDAGMI::moveInstruction(MachineInstr *MI,
445 MachineBasicBlock::iterator InsertPos) {
446 // Advance RegionBegin if the first instruction moves down.
447 if (&*RegionBegin == MI)
450 // Update the instruction stream.
451 BB->splice(InsertPos, BB, MI);
453 // Update LiveIntervals
454 LIS->handleMove(MI, /*UpdateFlags=*/true);
456 // Recede RegionBegin if an instruction moves above the first.
457 if (RegionBegin == InsertPos)
461 bool ScheduleDAGMI::checkSchedLimit() {
463 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
464 CurrentTop = CurrentBottom;
467 ++NumInstrsScheduled;
472 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
473 /// crossing a scheduling boundary. [begin, end) includes all instructions in
474 /// the region, including the boundary itself and single-instruction regions
475 /// that don't get scheduled.
476 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
477 MachineBasicBlock::iterator begin,
478 MachineBasicBlock::iterator end,
479 unsigned regioninstrs)
481 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
483 // For convenience remember the end of the liveness region.
485 (RegionEnd == bb->end()) ? RegionEnd : llvm::next(RegionEnd);
487 SchedImpl->initPolicy(begin, end, regioninstrs);
489 ShouldTrackPressure = SchedImpl->shouldTrackPressure();
492 // Setup the register pressure trackers for the top scheduled top and bottom
493 // scheduled regions.
494 void ScheduleDAGMI::initRegPressure() {
495 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
496 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
498 // Close the RPTracker to finalize live ins.
499 RPTracker.closeRegion();
501 DEBUG(RPTracker.dump());
503 // Initialize the live ins and live outs.
504 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
505 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
507 // Close one end of the tracker so we can call
508 // getMaxUpward/DownwardPressureDelta before advancing across any
509 // instructions. This converts currently live regs into live ins/outs.
510 TopRPTracker.closeTop();
511 BotRPTracker.closeBottom();
513 BotRPTracker.initLiveThru(RPTracker);
514 if (!BotRPTracker.getLiveThru().empty()) {
515 TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
516 DEBUG(dbgs() << "Live Thru: ";
517 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
520 // For each live out vreg reduce the pressure change associated with other
521 // uses of the same vreg below the live-out reaching def.
522 updatePressureDiffs(RPTracker.getPressure().LiveOutRegs);
524 // Account for liveness generated by the region boundary.
525 if (LiveRegionEnd != RegionEnd) {
526 SmallVector<unsigned, 8> LiveUses;
527 BotRPTracker.recede(&LiveUses);
528 updatePressureDiffs(LiveUses);
531 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
533 // Cache the list of excess pressure sets in this region. This will also track
534 // the max pressure in the scheduled code for these sets.
535 RegionCriticalPSets.clear();
536 const std::vector<unsigned> &RegionPressure =
537 RPTracker.getPressure().MaxSetPressure;
538 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
539 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
540 if (RegionPressure[i] > Limit) {
541 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
542 << " Limit " << Limit
543 << " Actual " << RegionPressure[i] << "\n");
544 RegionCriticalPSets.push_back(PressureChange(i));
547 DEBUG(dbgs() << "Excess PSets: ";
548 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
549 dbgs() << TRI->getRegPressureSetName(
550 RegionCriticalPSets[i].getPSet()) << " ";
554 // FIXME: When the pressure tracker deals in pressure differences then we won't
555 // iterate over all RegionCriticalPSets[i].
557 updateScheduledPressure(const std::vector<unsigned> &NewMaxPressure) {
558 for (unsigned i = 0, e = RegionCriticalPSets.size(); i < e; ++i) {
559 unsigned ID = RegionCriticalPSets[i].getPSet();
560 if ((int)NewMaxPressure[ID] > RegionCriticalPSets[i].getUnitInc()
561 && NewMaxPressure[ID] <= INT16_MAX)
562 RegionCriticalPSets[i].setUnitInc(NewMaxPressure[ID]);
565 for (unsigned i = 0, e = NewMaxPressure.size(); i < e; ++i) {
566 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
567 if (NewMaxPressure[i] > Limit ) {
568 dbgs() << " " << TRI->getRegPressureSetName(i) << ": "
569 << NewMaxPressure[i] << " > " << Limit << "(+ "
570 << BotRPTracker.getLiveThru()[i] << " livethru)\n";
575 /// Update the PressureDiff array for liveness after scheduling this
577 void ScheduleDAGMI::updatePressureDiffs(ArrayRef<unsigned> LiveUses) {
578 for (unsigned LUIdx = 0, LUEnd = LiveUses.size(); LUIdx != LUEnd; ++LUIdx) {
579 /// FIXME: Currently assuming single-use physregs.
580 unsigned Reg = LiveUses[LUIdx];
581 DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
582 if (!TRI->isVirtualRegister(Reg))
585 // This may be called before CurrentBottom has been initialized. However,
586 // BotRPTracker must have a valid position. We want the value live into the
587 // instruction or live out of the block, so ask for the previous
588 // instruction's live-out.
589 const LiveInterval &LI = LIS->getInterval(Reg);
591 MachineBasicBlock::const_iterator I =
592 nextIfDebug(BotRPTracker.getPos(), BB->end());
594 VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
596 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(I));
599 // RegisterPressureTracker guarantees that readsReg is true for LiveUses.
600 assert(VNI && "No live value at use.");
601 for (VReg2UseMap::iterator
602 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
604 DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
606 // If this use comes before the reaching def, it cannot be a last use, so
607 // descrease its pressure change.
608 if (!SU->isScheduled && SU != &ExitSU) {
609 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(SU->getInstr()));
610 if (LRQ.valueIn() == VNI)
611 getPressureDiff(SU).addPressureChange(Reg, true, &MRI);
617 /// schedule - Called back from MachineScheduler::runOnMachineFunction
618 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
619 /// only includes instructions that have DAG nodes, not scheduling boundaries.
621 /// This is a skeletal driver, with all the functionality pushed into helpers,
622 /// so that it can be easilly extended by experimental schedulers. Generally,
623 /// implementing MachineSchedStrategy should be sufficient to implement a new
624 /// scheduling algorithm. However, if a scheduler further subclasses
625 /// ScheduleDAGMI then it will want to override this virtual method in order to
626 /// update any specialized state.
627 void ScheduleDAGMI::schedule() {
628 buildDAGWithRegPressure();
630 Topo.InitDAGTopologicalSorting();
634 SmallVector<SUnit*, 8> TopRoots, BotRoots;
635 findRootsAndBiasEdges(TopRoots, BotRoots);
637 // Initialize the strategy before modifying the DAG.
638 // This may initialize a DFSResult to be used for queue priority.
639 SchedImpl->initialize(this);
641 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
642 SUnits[su].dumpAll(this));
643 if (ViewMISchedDAGs) viewGraph();
645 // Initialize ready queues now that the DAG and priority data are finalized.
646 initQueues(TopRoots, BotRoots);
648 bool IsTopNode = false;
649 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
650 assert(!SU->isScheduled && "Node already scheduled");
651 if (!checkSchedLimit())
654 scheduleMI(SU, IsTopNode);
656 updateQueues(SU, IsTopNode);
658 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
663 unsigned BBNum = begin()->getParent()->getNumber();
664 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
670 /// Build the DAG and setup three register pressure trackers.
671 void ScheduleDAGMI::buildDAGWithRegPressure() {
672 if (!ShouldTrackPressure) {
674 RegionCriticalPSets.clear();
679 // Initialize the register pressure tracker used by buildSchedGraph.
680 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
681 /*TrackUntiedDefs=*/true);
683 // Account for liveness generate by the region boundary.
684 if (LiveRegionEnd != RegionEnd)
687 // Build the DAG, and compute current register pressure.
688 buildSchedGraph(AA, &RPTracker, &SUPressureDiffs);
690 // Initialize top/bottom trackers after computing region pressure.
694 /// Apply each ScheduleDAGMutation step in order.
695 void ScheduleDAGMI::postprocessDAG() {
696 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
697 Mutations[i]->apply(this);
701 void ScheduleDAGMI::computeDFSResult() {
703 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
705 ScheduledTrees.clear();
706 DFSResult->resize(SUnits.size());
707 DFSResult->compute(SUnits);
708 ScheduledTrees.resize(DFSResult->getNumSubtrees());
711 void ScheduleDAGMI::findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
712 SmallVectorImpl<SUnit*> &BotRoots) {
713 for (std::vector<SUnit>::iterator
714 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
716 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
718 // Order predecessors so DFSResult follows the critical path.
719 SU->biasCriticalPath();
721 // A SUnit is ready to top schedule if it has no predecessors.
722 if (!I->NumPredsLeft)
723 TopRoots.push_back(SU);
724 // A SUnit is ready to bottom schedule if it has no successors.
725 if (!I->NumSuccsLeft)
726 BotRoots.push_back(SU);
728 ExitSU.biasCriticalPath();
731 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
732 /// only provides the critical path for single block loops. To handle loops that
733 /// span blocks, we could use the vreg path latencies provided by
734 /// MachineTraceMetrics instead. However, MachineTraceMetrics is not currently
735 /// available for use in the scheduler.
737 /// The cyclic path estimation identifies a def-use pair that crosses the back
738 /// edge and considers the depth and height of the nodes. For example, consider
739 /// the following instruction sequence where each instruction has unit latency
740 /// and defines an epomymous virtual register:
742 /// a->b(a,c)->c(b)->d(c)->exit
744 /// The cyclic critical path is a two cycles: b->c->b
745 /// The acyclic critical path is four cycles: a->b->c->d->exit
746 /// LiveOutHeight = height(c) = len(c->d->exit) = 2
747 /// LiveOutDepth = depth(c) + 1 = len(a->b->c) + 1 = 3
748 /// LiveInHeight = height(b) + 1 = len(b->c->d->exit) + 1 = 4
749 /// LiveInDepth = depth(b) = len(a->b) = 1
751 /// LiveOutDepth - LiveInDepth = 3 - 1 = 2
752 /// LiveInHeight - LiveOutHeight = 4 - 2 = 2
753 /// CyclicCriticalPath = min(2, 2) = 2
754 unsigned ScheduleDAGMI::computeCyclicCriticalPath() {
755 // This only applies to single block loop.
756 if (!BB->isSuccessor(BB))
759 unsigned MaxCyclicLatency = 0;
760 // Visit each live out vreg def to find def/use pairs that cross iterations.
761 ArrayRef<unsigned> LiveOuts = RPTracker.getPressure().LiveOutRegs;
762 for (ArrayRef<unsigned>::iterator RI = LiveOuts.begin(), RE = LiveOuts.end();
765 if (!TRI->isVirtualRegister(Reg))
767 const LiveInterval &LI = LIS->getInterval(Reg);
768 const VNInfo *DefVNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
772 MachineInstr *DefMI = LIS->getInstructionFromIndex(DefVNI->def);
773 const SUnit *DefSU = getSUnit(DefMI);
777 unsigned LiveOutHeight = DefSU->getHeight();
778 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency;
779 // Visit all local users of the vreg def.
780 for (VReg2UseMap::iterator
781 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
782 if (UI->SU == &ExitSU)
785 // Only consider uses of the phi.
786 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(UI->SU->getInstr()));
787 if (!LRQ.valueIn()->isPHIDef())
790 // Assume that a path spanning two iterations is a cycle, which could
791 // overestimate in strange cases. This allows cyclic latency to be
792 // estimated as the minimum slack of the vreg's depth or height.
793 unsigned CyclicLatency = 0;
794 if (LiveOutDepth > UI->SU->getDepth())
795 CyclicLatency = LiveOutDepth - UI->SU->getDepth();
797 unsigned LiveInHeight = UI->SU->getHeight() + DefSU->Latency;
798 if (LiveInHeight > LiveOutHeight) {
799 if (LiveInHeight - LiveOutHeight < CyclicLatency)
800 CyclicLatency = LiveInHeight - LiveOutHeight;
805 DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
806 << UI->SU->NodeNum << ") = " << CyclicLatency << "c\n");
807 if (CyclicLatency > MaxCyclicLatency)
808 MaxCyclicLatency = CyclicLatency;
811 DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
812 return MaxCyclicLatency;
815 /// Identify DAG roots and setup scheduler queues.
816 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
817 ArrayRef<SUnit*> BotRoots) {
818 NextClusterSucc = NULL;
819 NextClusterPred = NULL;
821 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
823 // Nodes with unreleased weak edges can still be roots.
824 // Release top roots in forward order.
825 for (SmallVectorImpl<SUnit*>::const_iterator
826 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) {
827 SchedImpl->releaseTopNode(*I);
829 // Release bottom roots in reverse order so the higher priority nodes appear
830 // first. This is more natural and slightly more efficient.
831 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
832 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
833 SchedImpl->releaseBottomNode(*I);
836 releaseSuccessors(&EntrySU);
837 releasePredecessors(&ExitSU);
839 SchedImpl->registerRoots();
841 // Advance past initial DebugValues.
842 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
843 CurrentBottom = RegionEnd;
845 if (ShouldTrackPressure) {
846 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
847 TopRPTracker.setPos(CurrentTop);
851 /// Move an instruction and update register pressure.
852 void ScheduleDAGMI::scheduleMI(SUnit *SU, bool IsTopNode) {
853 // Move the instruction to its new location in the instruction stream.
854 MachineInstr *MI = SU->getInstr();
857 assert(SU->isTopReady() && "node still has unscheduled dependencies");
858 if (&*CurrentTop == MI)
859 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
861 moveInstruction(MI, CurrentTop);
862 TopRPTracker.setPos(MI);
865 if (ShouldTrackPressure) {
866 // Update top scheduled pressure.
867 TopRPTracker.advance();
868 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
869 updateScheduledPressure(TopRPTracker.getPressure().MaxSetPressure);
873 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
874 MachineBasicBlock::iterator priorII =
875 priorNonDebug(CurrentBottom, CurrentTop);
877 CurrentBottom = priorII;
879 if (&*CurrentTop == MI) {
880 CurrentTop = nextIfDebug(++CurrentTop, priorII);
881 TopRPTracker.setPos(CurrentTop);
883 moveInstruction(MI, CurrentBottom);
886 if (ShouldTrackPressure) {
887 // Update bottom scheduled pressure.
888 SmallVector<unsigned, 8> LiveUses;
889 BotRPTracker.recede(&LiveUses);
890 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
891 updatePressureDiffs(LiveUses);
892 updateScheduledPressure(BotRPTracker.getPressure().MaxSetPressure);
897 /// Update scheduler queues after scheduling an instruction.
898 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
899 // Release dependent instructions for scheduling.
901 releaseSuccessors(SU);
903 releasePredecessors(SU);
905 SU->isScheduled = true;
908 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
909 if (!ScheduledTrees.test(SubtreeID)) {
910 ScheduledTrees.set(SubtreeID);
911 DFSResult->scheduleTree(SubtreeID);
912 SchedImpl->scheduleTree(SubtreeID);
916 // Notify the scheduling strategy after updating the DAG.
917 SchedImpl->schedNode(SU, IsTopNode);
920 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
921 void ScheduleDAGMI::placeDebugValues() {
922 // If first instruction was a DBG_VALUE then put it back.
924 BB->splice(RegionBegin, BB, FirstDbgValue);
925 RegionBegin = FirstDbgValue;
928 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
929 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
930 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
931 MachineInstr *DbgValue = P.first;
932 MachineBasicBlock::iterator OrigPrevMI = P.second;
933 if (&*RegionBegin == DbgValue)
935 BB->splice(++OrigPrevMI, BB, DbgValue);
936 if (OrigPrevMI == llvm::prior(RegionEnd))
937 RegionEnd = DbgValue;
940 FirstDbgValue = NULL;
943 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
944 void ScheduleDAGMI::dumpSchedule() const {
945 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
946 if (SUnit *SU = getSUnit(&(*MI)))
949 dbgs() << "Missing SUnit\n";
954 //===----------------------------------------------------------------------===//
955 // LoadClusterMutation - DAG post-processing to cluster loads.
956 //===----------------------------------------------------------------------===//
959 /// \brief Post-process the DAG to create cluster edges between neighboring
961 class LoadClusterMutation : public ScheduleDAGMutation {
966 LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
967 : SU(su), BaseReg(reg), Offset(ofs) {}
969 static bool LoadInfoLess(const LoadClusterMutation::LoadInfo &LHS,
970 const LoadClusterMutation::LoadInfo &RHS);
972 const TargetInstrInfo *TII;
973 const TargetRegisterInfo *TRI;
975 LoadClusterMutation(const TargetInstrInfo *tii,
976 const TargetRegisterInfo *tri)
977 : TII(tii), TRI(tri) {}
979 virtual void apply(ScheduleDAGMI *DAG);
981 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
985 bool LoadClusterMutation::LoadInfoLess(
986 const LoadClusterMutation::LoadInfo &LHS,
987 const LoadClusterMutation::LoadInfo &RHS) {
988 if (LHS.BaseReg != RHS.BaseReg)
989 return LHS.BaseReg < RHS.BaseReg;
990 return LHS.Offset < RHS.Offset;
993 void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
994 ScheduleDAGMI *DAG) {
995 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
996 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
997 SUnit *SU = Loads[Idx];
1000 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
1001 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
1003 if (LoadRecords.size() < 2)
1005 std::sort(LoadRecords.begin(), LoadRecords.end(), LoadInfoLess);
1006 unsigned ClusterLength = 1;
1007 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
1008 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
1013 SUnit *SUa = LoadRecords[Idx].SU;
1014 SUnit *SUb = LoadRecords[Idx+1].SU;
1015 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
1016 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
1018 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
1019 << SUb->NodeNum << ")\n");
1020 // Copy successor edges from SUa to SUb. Interleaving computation
1021 // dependent on SUa can prevent load combining due to register reuse.
1022 // Predecessor edges do not need to be copied from SUb to SUa since nearby
1023 // loads should have effectively the same inputs.
1024 for (SUnit::const_succ_iterator
1025 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
1026 if (SI->getSUnit() == SUb)
1028 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
1029 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
1038 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
1039 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
1040 // Map DAG NodeNum to store chain ID.
1041 DenseMap<unsigned, unsigned> StoreChainIDs;
1042 // Map each store chain to a set of dependent loads.
1043 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
1044 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1045 SUnit *SU = &DAG->SUnits[Idx];
1046 if (!SU->getInstr()->mayLoad())
1048 unsigned ChainPredID = DAG->SUnits.size();
1049 for (SUnit::const_pred_iterator
1050 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1052 ChainPredID = PI->getSUnit()->NodeNum;
1056 // Check if this chain-like pred has been seen
1057 // before. ChainPredID==MaxNodeID for loads at the top of the schedule.
1058 unsigned NumChains = StoreChainDependents.size();
1059 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
1060 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
1062 StoreChainDependents.resize(NumChains + 1);
1063 StoreChainDependents[Result.first->second].push_back(SU);
1065 // Iterate over the store chains.
1066 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
1067 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
1070 //===----------------------------------------------------------------------===//
1071 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
1072 //===----------------------------------------------------------------------===//
1075 /// \brief Post-process the DAG to create cluster edges between instructions
1076 /// that may be fused by the processor into a single operation.
1077 class MacroFusion : public ScheduleDAGMutation {
1078 const TargetInstrInfo *TII;
1080 MacroFusion(const TargetInstrInfo *tii): TII(tii) {}
1082 virtual void apply(ScheduleDAGMI *DAG);
1086 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
1087 /// fused operations.
1088 void MacroFusion::apply(ScheduleDAGMI *DAG) {
1089 // For now, assume targets can only fuse with the branch.
1090 MachineInstr *Branch = DAG->ExitSU.getInstr();
1094 for (unsigned Idx = DAG->SUnits.size(); Idx > 0;) {
1095 SUnit *SU = &DAG->SUnits[--Idx];
1096 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch))
1099 // Create a single weak edge from SU to ExitSU. The only effect is to cause
1100 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
1101 // need to copy predecessor edges from ExitSU to SU, since top-down
1102 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
1103 // of SU, we could create an artificial edge from the deepest root, but it
1104 // hasn't been needed yet.
1105 bool Success = DAG->addEdge(&DAG->ExitSU, SDep(SU, SDep::Cluster));
1107 assert(Success && "No DAG nodes should be reachable from ExitSU");
1109 DEBUG(dbgs() << "Macro Fuse SU(" << SU->NodeNum << ")\n");
1114 //===----------------------------------------------------------------------===//
1115 // CopyConstrain - DAG post-processing to encourage copy elimination.
1116 //===----------------------------------------------------------------------===//
1119 /// \brief Post-process the DAG to create weak edges from all uses of a copy to
1120 /// the one use that defines the copy's source vreg, most likely an induction
1121 /// variable increment.
1122 class CopyConstrain : public ScheduleDAGMutation {
1124 SlotIndex RegionBeginIdx;
1125 // RegionEndIdx is the slot index of the last non-debug instruction in the
1126 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
1127 SlotIndex RegionEndIdx;
1129 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
1131 virtual void apply(ScheduleDAGMI *DAG);
1134 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG);
1138 /// constrainLocalCopy handles two possibilities:
1143 /// I3: dst = src (copy)
1144 /// (create pred->succ edges I0->I1, I2->I1)
1147 /// I0: dst = src (copy)
1151 /// (create pred->succ edges I1->I2, I3->I2)
1153 /// Although the MachineScheduler is currently constrained to single blocks,
1154 /// this algorithm should handle extended blocks. An EBB is a set of
1155 /// contiguously numbered blocks such that the previous block in the EBB is
1156 /// always the single predecessor.
1157 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG) {
1158 LiveIntervals *LIS = DAG->getLIS();
1159 MachineInstr *Copy = CopySU->getInstr();
1161 // Check for pure vreg copies.
1162 unsigned SrcReg = Copy->getOperand(1).getReg();
1163 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1166 unsigned DstReg = Copy->getOperand(0).getReg();
1167 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1170 // Check if either the dest or source is local. If it's live across a back
1171 // edge, it's not local. Note that if both vregs are live across the back
1172 // edge, we cannot successfully contrain the copy without cyclic scheduling.
1173 unsigned LocalReg = DstReg;
1174 unsigned GlobalReg = SrcReg;
1175 LiveInterval *LocalLI = &LIS->getInterval(LocalReg);
1176 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) {
1179 LocalLI = &LIS->getInterval(LocalReg);
1180 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx))
1183 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg);
1185 // Find the global segment after the start of the local LI.
1186 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex());
1187 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a
1188 // local live range. We could create edges from other global uses to the local
1189 // start, but the coalescer should have already eliminated these cases, so
1190 // don't bother dealing with it.
1191 if (GlobalSegment == GlobalLI->end())
1194 // If GlobalSegment is killed at the LocalLI->start, the call to find()
1195 // returned the next global segment. But if GlobalSegment overlaps with
1196 // LocalLI->start, then advance to the next segement. If a hole in GlobalLI
1197 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole.
1198 if (GlobalSegment->contains(LocalLI->beginIndex()))
1201 if (GlobalSegment == GlobalLI->end())
1204 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
1205 if (GlobalSegment != GlobalLI->begin()) {
1206 // Two address defs have no hole.
1207 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->end,
1208 GlobalSegment->start)) {
1211 // If the prior global segment may be defined by the same two-address
1212 // instruction that also defines LocalLI, then can't make a hole here.
1213 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->start,
1214 LocalLI->beginIndex())) {
1217 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
1218 // it would be a disconnected component in the live range.
1219 assert(llvm::prior(GlobalSegment)->start < LocalLI->beginIndex() &&
1220 "Disconnected LRG within the scheduling region.");
1222 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
1226 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1230 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by
1231 // constraining the uses of the last local def to precede GlobalDef.
1232 SmallVector<SUnit*,8> LocalUses;
1233 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex());
1234 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
1235 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1236 for (SUnit::const_succ_iterator
1237 I = LastLocalSU->Succs.begin(), E = LastLocalSU->Succs.end();
1239 if (I->getKind() != SDep::Data || I->getReg() != LocalReg)
1241 if (I->getSUnit() == GlobalSU)
1243 if (!DAG->canAddEdge(GlobalSU, I->getSUnit()))
1245 LocalUses.push_back(I->getSUnit());
1247 // Open the top of the GlobalLI hole by constraining any earlier global uses
1248 // to precede the start of LocalLI.
1249 SmallVector<SUnit*,8> GlobalUses;
1250 MachineInstr *FirstLocalDef =
1251 LIS->getInstructionFromIndex(LocalLI->beginIndex());
1252 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1253 for (SUnit::const_pred_iterator
1254 I = GlobalSU->Preds.begin(), E = GlobalSU->Preds.end(); I != E; ++I) {
1255 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg)
1257 if (I->getSUnit() == FirstLocalSU)
1259 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit()))
1261 GlobalUses.push_back(I->getSUnit());
1263 DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
1264 // Add the weak edges.
1265 for (SmallVectorImpl<SUnit*>::const_iterator
1266 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
1267 DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
1268 << GlobalSU->NodeNum << ")\n");
1269 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1271 for (SmallVectorImpl<SUnit*>::const_iterator
1272 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
1273 DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
1274 << FirstLocalSU->NodeNum << ")\n");
1275 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1279 /// \brief Callback from DAG postProcessing to create weak edges to encourage
1280 /// copy elimination.
1281 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1282 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1283 if (FirstPos == DAG->end())
1285 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
1286 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1287 &*priorNonDebug(DAG->end(), DAG->begin()));
1289 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1290 SUnit *SU = &DAG->SUnits[Idx];
1291 if (!SU->getInstr()->isCopy())
1294 constrainLocalCopy(SU, DAG);
1298 //===----------------------------------------------------------------------===//
1299 // ConvergingScheduler - Implementation of the generic MachineSchedStrategy.
1300 //===----------------------------------------------------------------------===//
1303 /// ConvergingScheduler shrinks the unscheduled zone using heuristics to balance
1305 class ConvergingScheduler : public MachineSchedStrategy {
1307 /// Represent the type of SchedCandidate found within a single queue.
1308 /// pickNodeBidirectional depends on these listed by decreasing priority.
1310 NoCand, PhysRegCopy, RegExcess, RegCritical, Cluster, Weak, RegMax,
1311 ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
1312 TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
1315 static const char *getReasonStr(ConvergingScheduler::CandReason Reason);
1318 /// Policy for scheduling the next instruction in the candidate's zone.
1321 unsigned ReduceResIdx;
1322 unsigned DemandResIdx;
1324 CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
1327 /// Status of an instruction's critical resource consumption.
1328 struct SchedResourceDelta {
1329 // Count critical resources in the scheduled region required by SU.
1330 unsigned CritResources;
1332 // Count critical resources from another region consumed by SU.
1333 unsigned DemandedResources;
1335 SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
1337 bool operator==(const SchedResourceDelta &RHS) const {
1338 return CritResources == RHS.CritResources
1339 && DemandedResources == RHS.DemandedResources;
1341 bool operator!=(const SchedResourceDelta &RHS) const {
1342 return !operator==(RHS);
1346 /// Store the state used by ConvergingScheduler heuristics, required for the
1347 /// lifetime of one invocation of pickNode().
1348 struct SchedCandidate {
1351 // The best SUnit candidate.
1354 // The reason for this candidate.
1357 // Set of reasons that apply to multiple candidates.
1358 uint32_t RepeatReasonSet;
1360 // Register pressure values for the best candidate.
1361 RegPressureDelta RPDelta;
1363 // Critical resource consumption of the best candidate.
1364 SchedResourceDelta ResDelta;
1366 SchedCandidate(const CandPolicy &policy)
1367 : Policy(policy), SU(NULL), Reason(NoCand), RepeatReasonSet(0) {}
1369 bool isValid() const { return SU; }
1371 // Copy the status of another candidate without changing policy.
1372 void setBest(SchedCandidate &Best) {
1373 assert(Best.Reason != NoCand && "uninitialized Sched candidate");
1375 Reason = Best.Reason;
1376 RPDelta = Best.RPDelta;
1377 ResDelta = Best.ResDelta;
1380 bool isRepeat(CandReason R) { return RepeatReasonSet & (1 << R); }
1381 void setRepeat(CandReason R) { RepeatReasonSet |= (1 << R); }
1383 void initResourceDelta(const ScheduleDAGMI *DAG,
1384 const TargetSchedModel *SchedModel);
1387 /// Summarize the unscheduled region.
1388 struct SchedRemainder {
1389 // Critical path through the DAG in expected latency.
1390 unsigned CriticalPath;
1391 unsigned CyclicCritPath;
1393 // Scaled count of micro-ops left to schedule.
1394 unsigned RemIssueCount;
1396 bool IsAcyclicLatencyLimited;
1398 // Unscheduled resources
1399 SmallVector<unsigned, 16> RemainingCounts;
1405 IsAcyclicLatencyLimited = false;
1406 RemainingCounts.clear();
1409 SchedRemainder() { reset(); }
1411 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
1414 /// Each Scheduling boundary is associated with ready queues. It tracks the
1415 /// current cycle in the direction of movement, and maintains the state
1416 /// of "hazards" and other interlocks at the current cycle.
1417 struct SchedBoundary {
1419 const TargetSchedModel *SchedModel;
1420 SchedRemainder *Rem;
1422 ReadyQueue Available;
1426 // For heuristics, keep a list of the nodes that immediately depend on the
1427 // most recently scheduled node.
1428 SmallPtrSet<const SUnit*, 8> NextSUs;
1430 ScheduleHazardRecognizer *HazardRec;
1432 /// Number of cycles it takes to issue the instructions scheduled in this
1433 /// zone. It is defined as: scheduled-micro-ops / issue-width + stalls.
1434 /// See getStalls().
1437 /// Micro-ops issued in the current cycle
1440 /// MinReadyCycle - Cycle of the soonest available instruction.
1441 unsigned MinReadyCycle;
1443 // The expected latency of the critical path in this scheduled zone.
1444 unsigned ExpectedLatency;
1446 // The latency of dependence chains leading into this zone.
1447 // For each node scheduled bottom-up: DLat = max DLat, N.Depth.
1448 // For each cycle scheduled: DLat -= 1.
1449 unsigned DependentLatency;
1451 /// Count the scheduled (issued) micro-ops that can be retired by
1452 /// time=CurrCycle assuming the first scheduled instr is retired at time=0.
1453 unsigned RetiredMOps;
1455 // Count scheduled resources that have been executed. Resources are
1456 // considered executed if they become ready in the time that it takes to
1457 // saturate any resource including the one in question. Counts are scaled
1458 // for direct comparison with other resources. Counts can be compared with
1459 // MOps * getMicroOpFactor and Latency * getLatencyFactor.
1460 SmallVector<unsigned, 16> ExecutedResCounts;
1462 /// Cache the max count for a single resource.
1463 unsigned MaxExecutedResCount;
1465 // Cache the critical resources ID in this scheduled zone.
1466 unsigned ZoneCritResIdx;
1468 // Is the scheduled region resource limited vs. latency limited.
1469 bool IsResourceLimited;
1472 // Remember the greatest operand latency as an upper bound on the number of
1473 // times we should retry the pending queue because of a hazard.
1474 unsigned MaxObservedLatency;
1478 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1479 // Destroying and reconstructing it is very expensive though. So keep
1480 // invalid, placeholder HazardRecs.
1481 if (HazardRec && HazardRec->isEnabled()) {
1487 CheckPending = false;
1491 MinReadyCycle = UINT_MAX;
1492 ExpectedLatency = 0;
1493 DependentLatency = 0;
1495 MaxExecutedResCount = 0;
1497 IsResourceLimited = false;
1499 MaxObservedLatency = 0;
1501 // Reserve a zero-count for invalid CritResIdx.
1502 ExecutedResCounts.resize(1);
1503 assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
1506 /// Pending queues extend the ready queues with the same ID and the
1507 /// PendingFlag set.
1508 SchedBoundary(unsigned ID, const Twine &Name):
1509 DAG(0), SchedModel(0), Rem(0), Available(ID, Name+".A"),
1510 Pending(ID << ConvergingScheduler::LogMaxQID, Name+".P"),
1515 ~SchedBoundary() { delete HazardRec; }
1517 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
1518 SchedRemainder *rem);
1520 bool isTop() const {
1521 return Available.getID() == ConvergingScheduler::TopQID;
1525 const char *getResourceName(unsigned PIdx) {
1528 return SchedModel->getProcResource(PIdx)->Name;
1532 /// Get the number of latency cycles "covered" by the scheduled
1533 /// instructions. This is the larger of the critical path within the zone
1534 /// and the number of cycles required to issue the instructions.
1535 unsigned getScheduledLatency() const {
1536 return std::max(ExpectedLatency, CurrCycle);
1539 unsigned getUnscheduledLatency(SUnit *SU) const {
1540 return isTop() ? SU->getHeight() : SU->getDepth();
1543 unsigned getResourceCount(unsigned ResIdx) const {
1544 return ExecutedResCounts[ResIdx];
1547 /// Get the scaled count of scheduled micro-ops and resources, including
1548 /// executed resources.
1549 unsigned getCriticalCount() const {
1550 if (!ZoneCritResIdx)
1551 return RetiredMOps * SchedModel->getMicroOpFactor();
1552 return getResourceCount(ZoneCritResIdx);
1555 /// Get a scaled count for the minimum execution time of the scheduled
1556 /// micro-ops that are ready to execute by getExecutedCount. Notice the
1558 unsigned getExecutedCount() const {
1559 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
1560 MaxExecutedResCount);
1563 bool checkHazard(SUnit *SU);
1565 unsigned findMaxLatency(ArrayRef<SUnit*> ReadySUs);
1567 unsigned getOtherResourceCount(unsigned &OtherCritIdx);
1569 void setPolicy(CandPolicy &Policy, SchedBoundary &OtherZone);
1571 void releaseNode(SUnit *SU, unsigned ReadyCycle);
1573 void bumpCycle(unsigned NextCycle);
1575 void incExecutedResources(unsigned PIdx, unsigned Count);
1577 unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle);
1579 void bumpNode(SUnit *SU);
1581 void releasePending();
1583 void removeReady(SUnit *SU);
1585 SUnit *pickOnlyChoice();
1588 void dumpScheduledState();
1593 const MachineSchedContext *Context;
1595 const TargetSchedModel *SchedModel;
1596 const TargetRegisterInfo *TRI;
1598 // State of the top and bottom scheduled instruction boundaries.
1603 MachineSchedPolicy RegionPolicy;
1605 /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
1612 ConvergingScheduler(const MachineSchedContext *C):
1613 Context(C), DAG(0), SchedModel(0), TRI(0),
1614 Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
1616 virtual void initPolicy(MachineBasicBlock::iterator Begin,
1617 MachineBasicBlock::iterator End,
1618 unsigned NumRegionInstrs);
1620 bool shouldTrackPressure() const { return RegionPolicy.ShouldTrackPressure; }
1622 virtual void initialize(ScheduleDAGMI *dag);
1624 virtual SUnit *pickNode(bool &IsTopNode);
1626 virtual void schedNode(SUnit *SU, bool IsTopNode);
1628 virtual void releaseTopNode(SUnit *SU);
1630 virtual void releaseBottomNode(SUnit *SU);
1632 virtual void registerRoots();
1635 void checkAcyclicLatency();
1637 void tryCandidate(SchedCandidate &Cand,
1638 SchedCandidate &TryCand,
1639 SchedBoundary &Zone,
1640 const RegPressureTracker &RPTracker,
1641 RegPressureTracker &TempTracker);
1643 SUnit *pickNodeBidirectional(bool &IsTopNode);
1645 void pickNodeFromQueue(SchedBoundary &Zone,
1646 const RegPressureTracker &RPTracker,
1647 SchedCandidate &Candidate);
1649 void reschedulePhysRegCopies(SUnit *SU, bool isTop);
1652 void traceCandidate(const SchedCandidate &Cand);
1657 void ConvergingScheduler::SchedRemainder::
1658 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1660 if (!SchedModel->hasInstrSchedModel())
1662 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1663 for (std::vector<SUnit>::iterator
1664 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1665 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1666 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1667 * SchedModel->getMicroOpFactor();
1668 for (TargetSchedModel::ProcResIter
1669 PI = SchedModel->getWriteProcResBegin(SC),
1670 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1671 unsigned PIdx = PI->ProcResourceIdx;
1672 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1673 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1678 void ConvergingScheduler::SchedBoundary::
1679 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1682 SchedModel = smodel;
1684 if (SchedModel->hasInstrSchedModel())
1685 ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds());
1688 /// Initialize the per-region scheduling policy.
1689 void ConvergingScheduler::initPolicy(MachineBasicBlock::iterator Begin,
1690 MachineBasicBlock::iterator End,
1691 unsigned NumRegionInstrs) {
1692 const TargetMachine &TM = Context->MF->getTarget();
1694 // Avoid setting up the register pressure tracker for small regions to save
1695 // compile time. As a rough heuristic, only track pressure when the number of
1696 // schedulable instructions exceeds half the integer register file.
1697 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
1698 TM.getTargetLowering()->getRegClassFor(MVT::i32));
1700 RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
1702 // For generic targets, we default to bottom-up, because it's simpler and more
1703 // compile-time optimizations have been implemented in that direction.
1704 RegionPolicy.OnlyBottomUp = true;
1706 // Allow the subtarget to override default policy.
1707 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
1708 ST.overrideSchedPolicy(RegionPolicy, Begin, End, NumRegionInstrs);
1710 // After subtarget overrides, apply command line options.
1711 if (!EnableRegPressure)
1712 RegionPolicy.ShouldTrackPressure = false;
1714 // Check -misched-topdown/bottomup can force or unforce scheduling direction.
1715 // e.g. -misched-bottomup=false allows scheduling in both directions.
1716 assert((!ForceTopDown || !ForceBottomUp) &&
1717 "-misched-topdown incompatible with -misched-bottomup");
1718 if (ForceBottomUp.getNumOccurrences() > 0) {
1719 RegionPolicy.OnlyBottomUp = ForceBottomUp;
1720 if (RegionPolicy.OnlyBottomUp)
1721 RegionPolicy.OnlyTopDown = false;
1723 if (ForceTopDown.getNumOccurrences() > 0) {
1724 RegionPolicy.OnlyTopDown = ForceTopDown;
1725 if (RegionPolicy.OnlyTopDown)
1726 RegionPolicy.OnlyBottomUp = false;
1730 void ConvergingScheduler::initialize(ScheduleDAGMI *dag) {
1732 SchedModel = DAG->getSchedModel();
1735 Rem.init(DAG, SchedModel);
1736 Top.init(DAG, SchedModel, &Rem);
1737 Bot.init(DAG, SchedModel, &Rem);
1739 // Initialize resource counts.
1741 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
1742 // are disabled, then these HazardRecs will be disabled.
1743 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
1744 const TargetMachine &TM = DAG->MF.getTarget();
1745 if (!Top.HazardRec) {
1747 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1749 if (!Bot.HazardRec) {
1751 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1755 void ConvergingScheduler::releaseTopNode(SUnit *SU) {
1756 if (SU->isScheduled)
1759 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1763 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
1764 unsigned Latency = I->getLatency();
1766 Top.MaxObservedLatency = std::max(Latency, Top.MaxObservedLatency);
1768 if (SU->TopReadyCycle < PredReadyCycle + Latency)
1769 SU->TopReadyCycle = PredReadyCycle + Latency;
1771 Top.releaseNode(SU, SU->TopReadyCycle);
1774 void ConvergingScheduler::releaseBottomNode(SUnit *SU) {
1775 if (SU->isScheduled)
1778 assert(SU->getInstr() && "Scheduled SUnit must have instr");
1780 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1784 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
1785 unsigned Latency = I->getLatency();
1787 Bot.MaxObservedLatency = std::max(Latency, Bot.MaxObservedLatency);
1789 if (SU->BotReadyCycle < SuccReadyCycle + Latency)
1790 SU->BotReadyCycle = SuccReadyCycle + Latency;
1792 Bot.releaseNode(SU, SU->BotReadyCycle);
1795 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
1796 /// critical path by more cycles than it takes to drain the instruction buffer.
1797 /// We estimate an upper bounds on in-flight instructions as:
1799 /// CyclesPerIteration = max( CyclicPath, Loop-Resource-Height )
1800 /// InFlightIterations = AcyclicPath / CyclesPerIteration
1801 /// InFlightResources = InFlightIterations * LoopResources
1803 /// TODO: Check execution resources in addition to IssueCount.
1804 void ConvergingScheduler::checkAcyclicLatency() {
1805 if (Rem.CyclicCritPath == 0 || Rem.CyclicCritPath >= Rem.CriticalPath)
1808 // Scaled number of cycles per loop iteration.
1809 unsigned IterCount =
1810 std::max(Rem.CyclicCritPath * SchedModel->getLatencyFactor(),
1812 // Scaled acyclic critical path.
1813 unsigned AcyclicCount = Rem.CriticalPath * SchedModel->getLatencyFactor();
1814 // InFlightCount = (AcyclicPath / IterCycles) * InstrPerLoop
1815 unsigned InFlightCount =
1816 (AcyclicCount * Rem.RemIssueCount + IterCount-1) / IterCount;
1817 unsigned BufferLimit =
1818 SchedModel->getMicroOpBufferSize() * SchedModel->getMicroOpFactor();
1820 Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;
1822 DEBUG(dbgs() << "IssueCycles="
1823 << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
1824 << "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
1825 << "c NumIters=" << (AcyclicCount + IterCount-1) / IterCount
1826 << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
1827 << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
1828 if (Rem.IsAcyclicLatencyLimited)
1829 dbgs() << " ACYCLIC LATENCY LIMIT\n");
1832 void ConvergingScheduler::registerRoots() {
1833 Rem.CriticalPath = DAG->ExitSU.getDepth();
1835 // Some roots may not feed into ExitSU. Check all of them in case.
1836 for (std::vector<SUnit*>::const_iterator
1837 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) {
1838 if ((*I)->getDepth() > Rem.CriticalPath)
1839 Rem.CriticalPath = (*I)->getDepth();
1841 DEBUG(dbgs() << "Critical Path: " << Rem.CriticalPath << '\n');
1843 if (EnableCyclicPath) {
1844 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
1845 checkAcyclicLatency();
1849 /// Does this SU have a hazard within the current instruction group.
1851 /// The scheduler supports two modes of hazard recognition. The first is the
1852 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
1853 /// supports highly complicated in-order reservation tables
1854 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
1856 /// The second is a streamlined mechanism that checks for hazards based on
1857 /// simple counters that the scheduler itself maintains. It explicitly checks
1858 /// for instruction dispatch limitations, including the number of micro-ops that
1859 /// can dispatch per cycle.
1861 /// TODO: Also check whether the SU must start a new group.
1862 bool ConvergingScheduler::SchedBoundary::checkHazard(SUnit *SU) {
1863 if (HazardRec->isEnabled())
1864 return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
1866 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1867 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
1868 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
1869 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1875 // Find the unscheduled node in ReadySUs with the highest latency.
1876 unsigned ConvergingScheduler::SchedBoundary::
1877 findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
1879 unsigned RemLatency = 0;
1880 for (ArrayRef<SUnit*>::iterator I = ReadySUs.begin(), E = ReadySUs.end();
1882 unsigned L = getUnscheduledLatency(*I);
1883 if (L > RemLatency) {
1889 DEBUG(dbgs() << Available.getName() << " RemLatency SU("
1890 << LateSU->NodeNum << ") " << RemLatency << "c\n");
1895 // Count resources in this zone and the remaining unscheduled
1896 // instruction. Return the max count, scaled. Set OtherCritIdx to the critical
1897 // resource index, or zero if the zone is issue limited.
1898 unsigned ConvergingScheduler::SchedBoundary::
1899 getOtherResourceCount(unsigned &OtherCritIdx) {
1901 if (!SchedModel->hasInstrSchedModel())
1904 unsigned OtherCritCount = Rem->RemIssueCount
1905 + (RetiredMOps * SchedModel->getMicroOpFactor());
1906 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
1907 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
1908 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
1909 PIdx != PEnd; ++PIdx) {
1910 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
1911 if (OtherCount > OtherCritCount) {
1912 OtherCritCount = OtherCount;
1913 OtherCritIdx = PIdx;
1917 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
1918 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
1919 << " " << getResourceName(OtherCritIdx) << "\n");
1921 return OtherCritCount;
1924 /// Set the CandPolicy for this zone given the current resources and latencies
1925 /// inside and outside the zone.
1926 void ConvergingScheduler::SchedBoundary::setPolicy(CandPolicy &Policy,
1927 SchedBoundary &OtherZone) {
1928 // Now that potential stalls have been considered, apply preemptive heuristics
1929 // based on the the total latency and resources inside and outside this
1932 // Compute remaining latency. We need this both to determine whether the
1933 // overall schedule has become latency-limited and whether the instructions
1934 // outside this zone are resource or latency limited.
1936 // The "dependent" latency is updated incrementally during scheduling as the
1937 // max height/depth of scheduled nodes minus the cycles since it was
1939 // DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
1941 // The "independent" latency is the max ready queue depth:
1942 // ILat = max N.depth for N in Available|Pending
1944 // RemainingLatency is the greater of independent and dependent latency.
1945 unsigned RemLatency = DependentLatency;
1946 RemLatency = std::max(RemLatency, findMaxLatency(Available.elements()));
1947 RemLatency = std::max(RemLatency, findMaxLatency(Pending.elements()));
1949 // Compute the critical resource outside the zone.
1950 unsigned OtherCritIdx;
1951 unsigned OtherCount = OtherZone.getOtherResourceCount(OtherCritIdx);
1953 bool OtherResLimited = false;
1954 if (SchedModel->hasInstrSchedModel()) {
1955 unsigned LFactor = SchedModel->getLatencyFactor();
1956 OtherResLimited = (int)(OtherCount - (RemLatency * LFactor)) > (int)LFactor;
1958 if (!OtherResLimited && (RemLatency + CurrCycle > Rem->CriticalPath)) {
1959 Policy.ReduceLatency |= true;
1960 DEBUG(dbgs() << " " << Available.getName() << " RemainingLatency "
1961 << RemLatency << " + " << CurrCycle << "c > CritPath "
1962 << Rem->CriticalPath << "\n");
1964 // If the same resource is limiting inside and outside the zone, do nothing.
1965 if (ZoneCritResIdx == OtherCritIdx)
1969 if (IsResourceLimited) {
1970 dbgs() << " " << Available.getName() << " ResourceLimited: "
1971 << getResourceName(ZoneCritResIdx) << "\n";
1973 if (OtherResLimited)
1974 dbgs() << " RemainingLimit: " << getResourceName(OtherCritIdx) << "\n";
1975 if (!IsResourceLimited && !OtherResLimited)
1976 dbgs() << " Latency limited both directions.\n");
1978 if (IsResourceLimited && !Policy.ReduceResIdx)
1979 Policy.ReduceResIdx = ZoneCritResIdx;
1981 if (OtherResLimited)
1982 Policy.DemandResIdx = OtherCritIdx;
1985 void ConvergingScheduler::SchedBoundary::releaseNode(SUnit *SU,
1986 unsigned ReadyCycle) {
1987 if (ReadyCycle < MinReadyCycle)
1988 MinReadyCycle = ReadyCycle;
1990 // Check for interlocks first. For the purpose of other heuristics, an
1991 // instruction that cannot issue appears as if it's not in the ReadyQueue.
1992 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
1993 if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
1998 // Record this node as an immediate dependent of the scheduled node.
2002 /// Move the boundary of scheduled code by one cycle.
2003 void ConvergingScheduler::SchedBoundary::bumpCycle(unsigned NextCycle) {
2004 if (SchedModel->getMicroOpBufferSize() == 0) {
2005 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
2006 if (MinReadyCycle > NextCycle)
2007 NextCycle = MinReadyCycle;
2009 // Update the current micro-ops, which will issue in the next cycle.
2010 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle);
2011 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps;
2013 // Decrement DependentLatency based on the next cycle.
2014 if ((NextCycle - CurrCycle) > DependentLatency)
2015 DependentLatency = 0;
2017 DependentLatency -= (NextCycle - CurrCycle);
2019 if (!HazardRec->isEnabled()) {
2020 // Bypass HazardRec virtual calls.
2021 CurrCycle = NextCycle;
2024 // Bypass getHazardType calls in case of long latency.
2025 for (; CurrCycle != NextCycle; ++CurrCycle) {
2027 HazardRec->AdvanceCycle();
2029 HazardRec->RecedeCycle();
2032 CheckPending = true;
2033 unsigned LFactor = SchedModel->getLatencyFactor();
2035 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
2038 DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n');
2041 void ConvergingScheduler::SchedBoundary::incExecutedResources(unsigned PIdx,
2043 ExecutedResCounts[PIdx] += Count;
2044 if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
2045 MaxExecutedResCount = ExecutedResCounts[PIdx];
2048 /// Add the given processor resource to this scheduled zone.
2050 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
2051 /// during which this resource is consumed.
2053 /// \return the next cycle at which the instruction may execute without
2054 /// oversubscribing resources.
2055 unsigned ConvergingScheduler::SchedBoundary::
2056 countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle) {
2057 unsigned Factor = SchedModel->getResourceFactor(PIdx);
2058 unsigned Count = Factor * Cycles;
2059 DEBUG(dbgs() << " " << getResourceName(PIdx)
2060 << " +" << Cycles << "x" << Factor << "u\n");
2062 // Update Executed resources counts.
2063 incExecutedResources(PIdx, Count);
2064 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
2065 Rem->RemainingCounts[PIdx] -= Count;
2067 // Check if this resource exceeds the current critical resource. If so, it
2068 // becomes the critical resource.
2069 if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
2070 ZoneCritResIdx = PIdx;
2071 DEBUG(dbgs() << " *** Critical resource "
2072 << getResourceName(PIdx) << ": "
2073 << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n");
2075 // TODO: We don't yet model reserved resources. It's not hard though.
2079 /// Move the boundary of scheduled code by one SUnit.
2080 void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU) {
2081 // Update the reservation table.
2082 if (HazardRec->isEnabled()) {
2083 if (!isTop() && SU->isCall) {
2084 // Calls are scheduled with their preceding instructions. For bottom-up
2085 // scheduling, clear the pipeline state before emitting.
2088 HazardRec->EmitInstruction(SU);
2090 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2091 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
2092 CurrMOps += IncMOps;
2093 // checkHazard prevents scheduling multiple instructions per cycle that exceed
2094 // issue width. However, we commonly reach the maximum. In this case
2095 // opportunistically bump the cycle to avoid uselessly checking everything in
2096 // the readyQ. Furthermore, a single instruction may produce more than one
2097 // cycle's worth of micro-ops.
2099 // TODO: Also check if this SU must end a dispatch group.
2100 unsigned NextCycle = CurrCycle;
2101 if (CurrMOps >= SchedModel->getIssueWidth()) {
2103 DEBUG(dbgs() << " *** Max MOps " << CurrMOps
2104 << " at cycle " << CurrCycle << '\n');
2106 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
2107 DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
2109 switch (SchedModel->getMicroOpBufferSize()) {
2111 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue");
2114 if (ReadyCycle > NextCycle) {
2115 NextCycle = ReadyCycle;
2116 DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
2120 // We don't currently model the OOO reorder buffer, so consider all
2121 // scheduled MOps to be "retired".
2124 RetiredMOps += IncMOps;
2126 // Update resource counts and critical resource.
2127 if (SchedModel->hasInstrSchedModel()) {
2128 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor();
2129 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted");
2130 Rem->RemIssueCount -= DecRemIssue;
2131 if (ZoneCritResIdx) {
2132 // Scale scheduled micro-ops for comparing with the critical resource.
2133 unsigned ScaledMOps =
2134 RetiredMOps * SchedModel->getMicroOpFactor();
2136 // If scaled micro-ops are now more than the previous critical resource by
2137 // a full cycle, then micro-ops issue becomes critical.
2138 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
2139 >= (int)SchedModel->getLatencyFactor()) {
2141 DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
2142 << ScaledMOps / SchedModel->getLatencyFactor() << "c\n");
2145 for (TargetSchedModel::ProcResIter
2146 PI = SchedModel->getWriteProcResBegin(SC),
2147 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2149 countResource(PI->ProcResourceIdx, PI->Cycles, ReadyCycle);
2150 if (RCycle > NextCycle)
2154 // Update ExpectedLatency and DependentLatency.
2155 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency;
2156 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
2157 if (SU->getDepth() > TopLatency) {
2158 TopLatency = SU->getDepth();
2159 DEBUG(dbgs() << " " << Available.getName()
2160 << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n");
2162 if (SU->getHeight() > BotLatency) {
2163 BotLatency = SU->getHeight();
2164 DEBUG(dbgs() << " " << Available.getName()
2165 << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n");
2167 // If we stall for any reason, bump the cycle.
2168 if (NextCycle > CurrCycle) {
2169 bumpCycle(NextCycle);
2172 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
2173 // resource limited. If a stall occured, bumpCycle does this.
2174 unsigned LFactor = SchedModel->getLatencyFactor();
2176 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
2179 DEBUG(dumpScheduledState());
2182 /// Release pending ready nodes in to the available queue. This makes them
2183 /// visible to heuristics.
2184 void ConvergingScheduler::SchedBoundary::releasePending() {
2185 // If the available queue is empty, it is safe to reset MinReadyCycle.
2186 if (Available.empty())
2187 MinReadyCycle = UINT_MAX;
2189 // Check to see if any of the pending instructions are ready to issue. If
2190 // so, add them to the available queue.
2191 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
2192 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
2193 SUnit *SU = *(Pending.begin()+i);
2194 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
2196 if (ReadyCycle < MinReadyCycle)
2197 MinReadyCycle = ReadyCycle;
2199 if (!IsBuffered && ReadyCycle > CurrCycle)
2202 if (checkHazard(SU))
2206 Pending.remove(Pending.begin()+i);
2209 DEBUG(if (!Pending.empty()) Pending.dump());
2210 CheckPending = false;
2213 /// Remove SU from the ready set for this boundary.
2214 void ConvergingScheduler::SchedBoundary::removeReady(SUnit *SU) {
2215 if (Available.isInQueue(SU))
2216 Available.remove(Available.find(SU));
2218 assert(Pending.isInQueue(SU) && "bad ready count");
2219 Pending.remove(Pending.find(SU));
2223 /// If this queue only has one ready candidate, return it. As a side effect,
2224 /// defer any nodes that now hit a hazard, and advance the cycle until at least
2225 /// one node is ready. If multiple instructions are ready, return NULL.
2226 SUnit *ConvergingScheduler::SchedBoundary::pickOnlyChoice() {
2231 // Defer any ready instrs that now have a hazard.
2232 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
2233 if (checkHazard(*I)) {
2235 I = Available.remove(I);
2241 for (unsigned i = 0; Available.empty(); ++i) {
2242 assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedLatency) &&
2243 "permanent hazard"); (void)i;
2244 bumpCycle(CurrCycle + 1);
2247 if (Available.size() == 1)
2248 return *Available.begin();
2253 // This is useful information to dump after bumpNode.
2254 // Note that the Queue contents are more useful before pickNodeFromQueue.
2255 void ConvergingScheduler::SchedBoundary::dumpScheduledState() {
2258 if (ZoneCritResIdx) {
2259 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
2260 ResCount = getResourceCount(ZoneCritResIdx);
2263 ResFactor = SchedModel->getMicroOpFactor();
2264 ResCount = RetiredMOps * SchedModel->getMicroOpFactor();
2266 unsigned LFactor = SchedModel->getLatencyFactor();
2267 dbgs() << Available.getName() << " @" << CurrCycle << "c\n"
2268 << " Retired: " << RetiredMOps;
2269 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c";
2270 dbgs() << "\n Critical: " << ResCount / LFactor << "c, "
2271 << ResCount / ResFactor << " " << getResourceName(ZoneCritResIdx)
2272 << "\n ExpectedLatency: " << ExpectedLatency << "c\n"
2273 << (IsResourceLimited ? " - Resource" : " - Latency")
2278 void ConvergingScheduler::SchedCandidate::
2279 initResourceDelta(const ScheduleDAGMI *DAG,
2280 const TargetSchedModel *SchedModel) {
2281 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
2284 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2285 for (TargetSchedModel::ProcResIter
2286 PI = SchedModel->getWriteProcResBegin(SC),
2287 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2288 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
2289 ResDelta.CritResources += PI->Cycles;
2290 if (PI->ProcResourceIdx == Policy.DemandResIdx)
2291 ResDelta.DemandedResources += PI->Cycles;
2296 /// Return true if this heuristic determines order.
2297 static bool tryLess(int TryVal, int CandVal,
2298 ConvergingScheduler::SchedCandidate &TryCand,
2299 ConvergingScheduler::SchedCandidate &Cand,
2300 ConvergingScheduler::CandReason Reason) {
2301 if (TryVal < CandVal) {
2302 TryCand.Reason = Reason;
2305 if (TryVal > CandVal) {
2306 if (Cand.Reason > Reason)
2307 Cand.Reason = Reason;
2310 Cand.setRepeat(Reason);
2314 static bool tryGreater(int TryVal, int CandVal,
2315 ConvergingScheduler::SchedCandidate &TryCand,
2316 ConvergingScheduler::SchedCandidate &Cand,
2317 ConvergingScheduler::CandReason Reason) {
2318 if (TryVal > CandVal) {
2319 TryCand.Reason = Reason;
2322 if (TryVal < CandVal) {
2323 if (Cand.Reason > Reason)
2324 Cand.Reason = Reason;
2327 Cand.setRepeat(Reason);
2331 static bool tryPressure(const PressureChange &TryP,
2332 const PressureChange &CandP,
2333 ConvergingScheduler::SchedCandidate &TryCand,
2334 ConvergingScheduler::SchedCandidate &Cand,
2335 ConvergingScheduler::CandReason Reason) {
2336 int TryRank = TryP.getPSetOrMax();
2337 int CandRank = CandP.getPSetOrMax();
2338 // If both candidates affect the same set, go with the smallest increase.
2339 if (TryRank == CandRank) {
2340 return tryLess(TryP.getUnitInc(), CandP.getUnitInc(), TryCand, Cand,
2343 // If one candidate decreases and the other increases, go with it.
2344 // Invalid candidates have UnitInc==0.
2345 if (tryLess(TryP.getUnitInc() < 0, CandP.getUnitInc() < 0, TryCand, Cand,
2349 // If the candidates are decreasing pressure, reverse priority.
2350 if (TryP.getUnitInc() < 0)
2351 std::swap(TryRank, CandRank);
2352 return tryGreater(TryRank, CandRank, TryCand, Cand, Reason);
2355 static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
2356 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
2359 /// Minimize physical register live ranges. Regalloc wants them adjacent to
2360 /// their physreg def/use.
2362 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
2363 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
2364 /// with the operation that produces or consumes the physreg. We'll do this when
2365 /// regalloc has support for parallel copies.
2366 static int biasPhysRegCopy(const SUnit *SU, bool isTop) {
2367 const MachineInstr *MI = SU->getInstr();
2371 unsigned ScheduledOper = isTop ? 1 : 0;
2372 unsigned UnscheduledOper = isTop ? 0 : 1;
2373 // If we have already scheduled the physreg produce/consumer, immediately
2374 // schedule the copy.
2375 if (TargetRegisterInfo::isPhysicalRegister(
2376 MI->getOperand(ScheduledOper).getReg()))
2378 // If the physreg is at the boundary, defer it. Otherwise schedule it
2379 // immediately to free the dependent. We can hoist the copy later.
2380 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
2381 if (TargetRegisterInfo::isPhysicalRegister(
2382 MI->getOperand(UnscheduledOper).getReg()))
2383 return AtBoundary ? -1 : 1;
2387 static bool tryLatency(ConvergingScheduler::SchedCandidate &TryCand,
2388 ConvergingScheduler::SchedCandidate &Cand,
2389 ConvergingScheduler::SchedBoundary &Zone) {
2391 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) {
2392 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2393 TryCand, Cand, ConvergingScheduler::TopDepthReduce))
2396 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2397 TryCand, Cand, ConvergingScheduler::TopPathReduce))
2401 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) {
2402 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2403 TryCand, Cand, ConvergingScheduler::BotHeightReduce))
2406 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2407 TryCand, Cand, ConvergingScheduler::BotPathReduce))
2413 /// Apply a set of heursitics to a new candidate. Heuristics are currently
2414 /// hierarchical. This may be more efficient than a graduated cost model because
2415 /// we don't need to evaluate all aspects of the model for each node in the
2416 /// queue. But it's really done to make the heuristics easier to debug and
2417 /// statistically analyze.
2419 /// \param Cand provides the policy and current best candidate.
2420 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2421 /// \param Zone describes the scheduled zone that we are extending.
2422 /// \param RPTracker describes reg pressure within the scheduled zone.
2423 /// \param TempTracker is a scratch pressure tracker to reuse in queries.
2424 void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
2425 SchedCandidate &TryCand,
2426 SchedBoundary &Zone,
2427 const RegPressureTracker &RPTracker,
2428 RegPressureTracker &TempTracker) {
2430 if (DAG->isTrackingPressure()) {
2431 // Always initialize TryCand's RPDelta.
2433 TempTracker.getMaxDownwardPressureDelta(
2434 TryCand.SU->getInstr(),
2436 DAG->getRegionCriticalPSets(),
2437 DAG->getRegPressure().MaxSetPressure);
2440 if (VerifyScheduling) {
2441 TempTracker.getMaxUpwardPressureDelta(
2442 TryCand.SU->getInstr(),
2443 &DAG->getPressureDiff(TryCand.SU),
2445 DAG->getRegionCriticalPSets(),
2446 DAG->getRegPressure().MaxSetPressure);
2449 RPTracker.getUpwardPressureDelta(
2450 TryCand.SU->getInstr(),
2451 DAG->getPressureDiff(TryCand.SU),
2453 DAG->getRegionCriticalPSets(),
2454 DAG->getRegPressure().MaxSetPressure);
2458 DEBUG(if (TryCand.RPDelta.Excess.isValid())
2459 dbgs() << " SU(" << TryCand.SU->NodeNum << ") "
2460 << TRI->getRegPressureSetName(TryCand.RPDelta.Excess.getPSet())
2461 << ":" << TryCand.RPDelta.Excess.getUnitInc() << "\n");
2463 // Initialize the candidate if needed.
2464 if (!Cand.isValid()) {
2465 TryCand.Reason = NodeOrder;
2469 if (tryGreater(biasPhysRegCopy(TryCand.SU, Zone.isTop()),
2470 biasPhysRegCopy(Cand.SU, Zone.isTop()),
2471 TryCand, Cand, PhysRegCopy))
2474 // Avoid exceeding the target's limit. If signed PSetID is negative, it is
2475 // invalid; convert it to INT_MAX to give it lowest priority.
2476 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.Excess,
2477 Cand.RPDelta.Excess,
2478 TryCand, Cand, RegExcess))
2481 // Avoid increasing the max critical pressure in the scheduled region.
2482 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
2483 Cand.RPDelta.CriticalMax,
2484 TryCand, Cand, RegCritical))
2487 // For loops that are acyclic path limited, aggressively schedule for latency.
2488 if (Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, Zone))
2491 // Keep clustered nodes together to encourage downstream peephole
2492 // optimizations which may reduce resource requirements.
2494 // This is a best effort to set things up for a post-RA pass. Optimizations
2495 // like generating loads of multiple registers should ideally be done within
2496 // the scheduler pass by combining the loads during DAG postprocessing.
2497 const SUnit *NextClusterSU =
2498 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
2499 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
2500 TryCand, Cand, Cluster))
2503 // Weak edges are for clustering and other constraints.
2504 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
2505 getWeakLeft(Cand.SU, Zone.isTop()),
2506 TryCand, Cand, Weak)) {
2509 // Avoid increasing the max pressure of the entire region.
2510 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
2511 Cand.RPDelta.CurrentMax,
2512 TryCand, Cand, RegMax))
2515 // Avoid critical resource consumption and balance the schedule.
2516 TryCand.initResourceDelta(DAG, SchedModel);
2517 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2518 TryCand, Cand, ResourceReduce))
2520 if (tryGreater(TryCand.ResDelta.DemandedResources,
2521 Cand.ResDelta.DemandedResources,
2522 TryCand, Cand, ResourceDemand))
2525 // Avoid serializing long latency dependence chains.
2526 // For acyclic path limited loops, latency was already checked above.
2527 if (Cand.Policy.ReduceLatency && !Rem.IsAcyclicLatencyLimited
2528 && tryLatency(TryCand, Cand, Zone)) {
2532 // Prefer immediate defs/users of the last scheduled instruction. This is a
2533 // local pressure avoidance strategy that also makes the machine code
2535 if (tryGreater(Zone.NextSUs.count(TryCand.SU), Zone.NextSUs.count(Cand.SU),
2536 TryCand, Cand, NextDefUse))
2539 // Fall through to original instruction order.
2540 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
2541 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
2542 TryCand.Reason = NodeOrder;
2547 const char *ConvergingScheduler::getReasonStr(
2548 ConvergingScheduler::CandReason Reason) {
2550 case NoCand: return "NOCAND ";
2551 case PhysRegCopy: return "PREG-COPY";
2552 case RegExcess: return "REG-EXCESS";
2553 case RegCritical: return "REG-CRIT ";
2554 case Cluster: return "CLUSTER ";
2555 case Weak: return "WEAK ";
2556 case RegMax: return "REG-MAX ";
2557 case ResourceReduce: return "RES-REDUCE";
2558 case ResourceDemand: return "RES-DEMAND";
2559 case TopDepthReduce: return "TOP-DEPTH ";
2560 case TopPathReduce: return "TOP-PATH ";
2561 case BotHeightReduce:return "BOT-HEIGHT";
2562 case BotPathReduce: return "BOT-PATH ";
2563 case NextDefUse: return "DEF-USE ";
2564 case NodeOrder: return "ORDER ";
2566 llvm_unreachable("Unknown reason!");
2569 void ConvergingScheduler::traceCandidate(const SchedCandidate &Cand) {
2571 unsigned ResIdx = 0;
2572 unsigned Latency = 0;
2573 switch (Cand.Reason) {
2577 P = Cand.RPDelta.Excess;
2580 P = Cand.RPDelta.CriticalMax;
2583 P = Cand.RPDelta.CurrentMax;
2585 case ResourceReduce:
2586 ResIdx = Cand.Policy.ReduceResIdx;
2588 case ResourceDemand:
2589 ResIdx = Cand.Policy.DemandResIdx;
2591 case TopDepthReduce:
2592 Latency = Cand.SU->getDepth();
2595 Latency = Cand.SU->getHeight();
2597 case BotHeightReduce:
2598 Latency = Cand.SU->getHeight();
2601 Latency = Cand.SU->getDepth();
2604 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
2606 dbgs() << " " << TRI->getRegPressureSetName(P.getPSet())
2607 << ":" << P.getUnitInc() << " ";
2611 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
2615 dbgs() << " " << Latency << " cycles ";
2622 /// Pick the best candidate from the queue.
2624 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
2625 /// DAG building. To adjust for the current scheduling location we need to
2626 /// maintain the number of vreg uses remaining to be top-scheduled.
2627 void ConvergingScheduler::pickNodeFromQueue(SchedBoundary &Zone,
2628 const RegPressureTracker &RPTracker,
2629 SchedCandidate &Cand) {
2630 ReadyQueue &Q = Zone.Available;
2634 // getMaxPressureDelta temporarily modifies the tracker.
2635 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
2637 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2639 SchedCandidate TryCand(Cand.Policy);
2641 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker);
2642 if (TryCand.Reason != NoCand) {
2643 // Initialize resource delta if needed in case future heuristics query it.
2644 if (TryCand.ResDelta == SchedResourceDelta())
2645 TryCand.initResourceDelta(DAG, SchedModel);
2646 Cand.setBest(TryCand);
2647 DEBUG(traceCandidate(Cand));
2652 static void tracePick(const ConvergingScheduler::SchedCandidate &Cand,
2654 DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
2655 << ConvergingScheduler::getReasonStr(Cand.Reason) << '\n');
2658 /// Pick the best candidate node from either the top or bottom queue.
2659 SUnit *ConvergingScheduler::pickNodeBidirectional(bool &IsTopNode) {
2660 // Schedule as far as possible in the direction of no choice. This is most
2661 // efficient, but also provides the best heuristics for CriticalPSets.
2662 if (SUnit *SU = Bot.pickOnlyChoice()) {
2664 DEBUG(dbgs() << "Pick Bot NOCAND\n");
2667 if (SUnit *SU = Top.pickOnlyChoice()) {
2669 DEBUG(dbgs() << "Pick Top NOCAND\n");
2672 CandPolicy NoPolicy;
2673 SchedCandidate BotCand(NoPolicy);
2674 SchedCandidate TopCand(NoPolicy);
2675 Bot.setPolicy(BotCand.Policy, Top);
2676 Top.setPolicy(TopCand.Policy, Bot);
2678 // Prefer bottom scheduling when heuristics are silent.
2679 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2680 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2682 // If either Q has a single candidate that provides the least increase in
2683 // Excess pressure, we can immediately schedule from that Q.
2685 // RegionCriticalPSets summarizes the pressure within the scheduled region and
2686 // affects picking from either Q. If scheduling in one direction must
2687 // increase pressure for one of the excess PSets, then schedule in that
2688 // direction first to provide more freedom in the other direction.
2689 if ((BotCand.Reason == RegExcess && !BotCand.isRepeat(RegExcess))
2690 || (BotCand.Reason == RegCritical
2691 && !BotCand.isRepeat(RegCritical)))
2694 tracePick(BotCand, IsTopNode);
2697 // Check if the top Q has a better candidate.
2698 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2699 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2701 // Choose the queue with the most important (lowest enum) reason.
2702 if (TopCand.Reason < BotCand.Reason) {
2704 tracePick(TopCand, IsTopNode);
2707 // Otherwise prefer the bottom candidate, in node order if all else failed.
2709 tracePick(BotCand, IsTopNode);
2713 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
2714 SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
2715 if (DAG->top() == DAG->bottom()) {
2716 assert(Top.Available.empty() && Top.Pending.empty() &&
2717 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
2722 if (RegionPolicy.OnlyTopDown) {
2723 SU = Top.pickOnlyChoice();
2725 CandPolicy NoPolicy;
2726 SchedCandidate TopCand(NoPolicy);
2727 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2728 assert(TopCand.Reason != NoCand && "failed to find a candidate");
2729 tracePick(TopCand, true);
2734 else if (RegionPolicy.OnlyBottomUp) {
2735 SU = Bot.pickOnlyChoice();
2737 CandPolicy NoPolicy;
2738 SchedCandidate BotCand(NoPolicy);
2739 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2740 assert(BotCand.Reason != NoCand && "failed to find a candidate");
2741 tracePick(BotCand, false);
2747 SU = pickNodeBidirectional(IsTopNode);
2749 } while (SU->isScheduled);
2751 if (SU->isTopReady())
2752 Top.removeReady(SU);
2753 if (SU->isBottomReady())
2754 Bot.removeReady(SU);
2756 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
2760 void ConvergingScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
2762 MachineBasicBlock::iterator InsertPos = SU->getInstr();
2765 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
2767 // Find already scheduled copies with a single physreg dependence and move
2768 // them just above the scheduled instruction.
2769 for (SmallVectorImpl<SDep>::iterator I = Deps.begin(), E = Deps.end();
2771 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg()))
2773 SUnit *DepSU = I->getSUnit();
2774 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
2776 MachineInstr *Copy = DepSU->getInstr();
2777 if (!Copy->isCopy())
2779 DEBUG(dbgs() << " Rescheduling physreg copy ";
2780 I->getSUnit()->dump(DAG));
2781 DAG->moveInstruction(Copy, InsertPos);
2785 /// Update the scheduler's state after scheduling a node. This is the same node
2786 /// that was just returned by pickNode(). However, ScheduleDAGMI needs to update
2787 /// it's state based on the current cycle before MachineSchedStrategy does.
2789 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
2790 /// them here. See comments in biasPhysRegCopy.
2791 void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2793 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.CurrCycle);
2795 if (SU->hasPhysRegUses)
2796 reschedulePhysRegCopies(SU, true);
2799 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.CurrCycle);
2801 if (SU->hasPhysRegDefs)
2802 reschedulePhysRegCopies(SU, false);
2806 /// Create the standard converging machine scheduler. This will be used as the
2807 /// default scheduler if the target does not set a default.
2808 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
2809 ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new ConvergingScheduler(C));
2810 // Register DAG post-processors.
2812 // FIXME: extend the mutation API to allow earlier mutations to instantiate
2813 // data and pass it to later mutations. Have a single mutation that gathers
2814 // the interesting nodes in one pass.
2815 DAG->addMutation(new CopyConstrain(DAG->TII, DAG->TRI));
2816 if (EnableLoadCluster && DAG->TII->enableClusterLoads())
2817 DAG->addMutation(new LoadClusterMutation(DAG->TII, DAG->TRI));
2818 if (EnableMacroFusion)
2819 DAG->addMutation(new MacroFusion(DAG->TII));
2822 static MachineSchedRegistry
2823 ConvergingSchedRegistry("converge", "Standard converging scheduler.",
2824 createConvergingSched);
2826 //===----------------------------------------------------------------------===//
2827 // ILP Scheduler. Currently for experimental analysis of heuristics.
2828 //===----------------------------------------------------------------------===//
2831 /// \brief Order nodes by the ILP metric.
2833 const SchedDFSResult *DFSResult;
2834 const BitVector *ScheduledTrees;
2837 ILPOrder(bool MaxILP): DFSResult(0), ScheduledTrees(0), MaximizeILP(MaxILP) {}
2839 /// \brief Apply a less-than relation on node priority.
2841 /// (Return true if A comes after B in the Q.)
2842 bool operator()(const SUnit *A, const SUnit *B) const {
2843 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
2844 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
2845 if (SchedTreeA != SchedTreeB) {
2846 // Unscheduled trees have lower priority.
2847 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
2848 return ScheduledTrees->test(SchedTreeB);
2850 // Trees with shallower connections have have lower priority.
2851 if (DFSResult->getSubtreeLevel(SchedTreeA)
2852 != DFSResult->getSubtreeLevel(SchedTreeB)) {
2853 return DFSResult->getSubtreeLevel(SchedTreeA)
2854 < DFSResult->getSubtreeLevel(SchedTreeB);
2858 return DFSResult->getILP(A) < DFSResult->getILP(B);
2860 return DFSResult->getILP(A) > DFSResult->getILP(B);
2864 /// \brief Schedule based on the ILP metric.
2865 class ILPScheduler : public MachineSchedStrategy {
2869 std::vector<SUnit*> ReadyQ;
2871 ILPScheduler(bool MaximizeILP): DAG(0), Cmp(MaximizeILP) {}
2873 virtual void initialize(ScheduleDAGMI *dag) {
2875 DAG->computeDFSResult();
2876 Cmp.DFSResult = DAG->getDFSResult();
2877 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
2881 virtual void registerRoots() {
2882 // Restore the heap in ReadyQ with the updated DFS results.
2883 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2886 /// Implement MachineSchedStrategy interface.
2887 /// -----------------------------------------
2889 /// Callback to select the highest priority node from the ready Q.
2890 virtual SUnit *pickNode(bool &IsTopNode) {
2891 if (ReadyQ.empty()) return NULL;
2892 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2893 SUnit *SU = ReadyQ.back();
2896 DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") "
2897 << " ILP: " << DAG->getDFSResult()->getILP(SU)
2898 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
2899 << DAG->getDFSResult()->getSubtreeLevel(
2900 DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
2901 << "Scheduling " << *SU->getInstr());
2905 /// \brief Scheduler callback to notify that a new subtree is scheduled.
2906 virtual void scheduleTree(unsigned SubtreeID) {
2907 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2910 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
2911 /// DFSResults, and resort the priority Q.
2912 virtual void schedNode(SUnit *SU, bool IsTopNode) {
2913 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
2916 virtual void releaseTopNode(SUnit *) { /*only called for top roots*/ }
2918 virtual void releaseBottomNode(SUnit *SU) {
2919 ReadyQ.push_back(SU);
2920 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2925 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
2926 return new ScheduleDAGMI(C, new ILPScheduler(true));
2928 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
2929 return new ScheduleDAGMI(C, new ILPScheduler(false));
2931 static MachineSchedRegistry ILPMaxRegistry(
2932 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
2933 static MachineSchedRegistry ILPMinRegistry(
2934 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
2936 //===----------------------------------------------------------------------===//
2937 // Machine Instruction Shuffler for Correctness Testing
2938 //===----------------------------------------------------------------------===//
2942 /// Apply a less-than relation on the node order, which corresponds to the
2943 /// instruction order prior to scheduling. IsReverse implements greater-than.
2944 template<bool IsReverse>
2946 bool operator()(SUnit *A, SUnit *B) const {
2948 return A->NodeNum > B->NodeNum;
2950 return A->NodeNum < B->NodeNum;
2954 /// Reorder instructions as much as possible.
2955 class InstructionShuffler : public MachineSchedStrategy {
2959 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
2960 // gives nodes with a higher number higher priority causing the latest
2961 // instructions to be scheduled first.
2962 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
2964 // When scheduling bottom-up, use greater-than as the queue priority.
2965 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
2968 InstructionShuffler(bool alternate, bool topdown)
2969 : IsAlternating(alternate), IsTopDown(topdown) {}
2971 virtual void initialize(ScheduleDAGMI *) {
2976 /// Implement MachineSchedStrategy interface.
2977 /// -----------------------------------------
2979 virtual SUnit *pickNode(bool &IsTopNode) {
2983 if (TopQ.empty()) return NULL;
2986 } while (SU->isScheduled);
2991 if (BottomQ.empty()) return NULL;
2994 } while (SU->isScheduled);
2998 IsTopDown = !IsTopDown;
3002 virtual void schedNode(SUnit *SU, bool IsTopNode) {}
3004 virtual void releaseTopNode(SUnit *SU) {
3007 virtual void releaseBottomNode(SUnit *SU) {
3013 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
3014 bool Alternate = !ForceTopDown && !ForceBottomUp;
3015 bool TopDown = !ForceBottomUp;
3016 assert((TopDown || !ForceTopDown) &&
3017 "-misched-topdown incompatible with -misched-bottomup");
3018 return new ScheduleDAGMI(C, new InstructionShuffler(Alternate, TopDown));
3020 static MachineSchedRegistry ShufflerRegistry(
3021 "shuffle", "Shuffle machine instructions alternating directions",
3022 createInstructionShuffler);
3025 //===----------------------------------------------------------------------===//
3026 // GraphWriter support for ScheduleDAGMI.
3027 //===----------------------------------------------------------------------===//
3032 template<> struct GraphTraits<
3033 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
3036 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
3038 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
3040 static std::string getGraphName(const ScheduleDAG *G) {
3041 return G->MF.getName();
3044 static bool renderGraphFromBottomUp() {
3048 static bool isNodeHidden(const SUnit *Node) {
3049 return (Node->Preds.size() > 10 || Node->Succs.size() > 10);
3052 static bool hasNodeAddressLabel(const SUnit *Node,
3053 const ScheduleDAG *Graph) {
3057 /// If you want to override the dot attributes printed for a particular
3058 /// edge, override this method.
3059 static std::string getEdgeAttributes(const SUnit *Node,
3061 const ScheduleDAG *Graph) {
3062 if (EI.isArtificialDep())
3063 return "color=cyan,style=dashed";
3065 return "color=blue,style=dashed";
3069 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
3071 raw_string_ostream SS(Str);
3072 const SchedDFSResult *DFS =
3073 static_cast<const ScheduleDAGMI*>(G)->getDFSResult();
3074 SS << "SU:" << SU->NodeNum;
3076 SS << " I:" << DFS->getNumInstrs(SU);
3079 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
3080 return G->getGraphNodeLabel(SU);
3083 static std::string getNodeAttributes(const SUnit *N,
3084 const ScheduleDAG *Graph) {
3085 std::string Str("shape=Mrecord");
3086 const SchedDFSResult *DFS =
3087 static_cast<const ScheduleDAGMI*>(Graph)->getDFSResult();
3089 Str += ",style=filled,fillcolor=\"#";
3090 Str += DOT::getColorString(DFS->getSubtreeID(N));
3099 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
3100 /// rendered using 'dot'.
3102 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
3104 ViewGraph(this, Name, false, Title);
3106 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
3107 << "systems with Graphviz or gv!\n";
3111 /// Out-of-line implementation with no arguments is handy for gdb.
3112 void ScheduleDAGMI::viewGraph() {
3113 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());