1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetMachine.h"
20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
21 : TRI(&TRI), IsSSA(true), TracksLiveness(true) {
22 VRegInfo.reserve(256);
23 RegAllocHints.reserve(256);
24 UsedPhysRegs.resize(TRI.getNumRegs());
25 UsedPhysRegMask.resize(TRI.getNumRegs());
27 // Create the physreg use/def lists.
28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
32 MachineRegisterInfo::~MachineRegisterInfo() {
35 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
36 assert(!PhysRegUseDefLists[i] &&
37 "PhysRegUseDefLists has entries after all instructions are deleted");
39 delete [] PhysRegUseDefLists;
42 /// setRegClass - Set the register class of the specified virtual register.
45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
46 VRegInfo[Reg].first = RC;
49 const TargetRegisterClass *
50 MachineRegisterInfo::constrainRegClass(unsigned Reg,
51 const TargetRegisterClass *RC,
52 unsigned MinNumRegs) {
53 const TargetRegisterClass *OldRC = getRegClass(Reg);
56 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
57 if (!NewRC || NewRC == OldRC)
59 if (NewRC->getNumRegs() < MinNumRegs)
61 setRegClass(Reg, NewRC);
66 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
67 const TargetInstrInfo *TII = TM.getInstrInfo();
68 const TargetRegisterClass *OldRC = getRegClass(Reg);
69 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
71 // Stop early if there is no room to grow.
75 // Accumulate constraints from all uses.
76 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
78 const TargetRegisterClass *OpRC =
79 I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
80 if (unsigned SubIdx = I.getOperand().getSubReg()) {
82 NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
84 NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
86 NewRC = TRI->getCommonSubClass(NewRC, OpRC);
87 if (!NewRC || NewRC == OldRC)
90 setRegClass(Reg, NewRC);
94 /// createVirtualRegister - Create and return a new virtual register in the
95 /// function with the specified register class.
98 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
99 assert(RegClass && "Cannot create register without RegClass!");
100 assert(RegClass->isAllocatable() &&
101 "Virtual register RegClass must be allocatable.");
103 // New virtual register number.
104 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
106 // Add a reg, but keep track of whether the vector reallocated or not.
107 const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
108 void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
110 VRegInfo[Reg].first = RegClass;
111 RegAllocHints.grow(Reg);
113 if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
114 // The vector reallocated, handle this now.
115 HandleVRegListReallocation();
119 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
120 void MachineRegisterInfo::clearVirtRegs() {
122 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
123 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
124 "Vreg use list non-empty still?");
129 /// Add MO to the linked list of operands for its register.
130 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
131 assert(!MO->isOnRegUseList() && "Already on list");
132 MachineOperand **Head = &getRegUseDefListHead(MO->getReg());
134 // For SSA values, we prefer to keep the definition at the start of the list.
135 // we do this by skipping over the definition if it is at the head of the
137 if (*Head && (*Head)->isDef())
138 Head = &(*Head)->Contents.Reg.Next;
140 MO->Contents.Reg.Next = *Head;
141 if (MO->Contents.Reg.Next) {
142 assert(MO->getReg() == MO->Contents.Reg.Next->getReg() &&
143 "Different regs on the same list!");
144 MO->Contents.Reg.Next->Contents.Reg.Prev = &MO->Contents.Reg.Next;
147 MO->Contents.Reg.Prev = Head;
151 /// Remove MO from its use-def list.
152 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
153 assert(MO->isOnRegUseList() && "Operand not on use list");
155 // Unlink this from the doubly linked list of operands.
156 MachineOperand *NextOp = MO->Contents.Reg.Next;
157 *MO->Contents.Reg.Prev = NextOp;
159 assert(NextOp->getReg() == MO->getReg() && "Corrupt reg use/def chain!");
160 NextOp->Contents.Reg.Prev = MO->Contents.Reg.Prev;
162 MO->Contents.Reg.Prev = 0;
163 MO->Contents.Reg.Next = 0;
166 /// HandleVRegListReallocation - We just added a virtual register to the
167 /// VRegInfo info list and it reallocated. Update the use/def lists info
169 void MachineRegisterInfo::HandleVRegListReallocation() {
170 // The back pointers for the vreg lists point into the previous vector.
171 // Update them to point to their correct slots.
172 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
173 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
174 MachineOperand *List = VRegInfo[Reg].second;
176 // Update the back-pointer to be accurate once more.
177 List->Contents.Reg.Prev = &VRegInfo[Reg].second;
181 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
182 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
183 /// except that it also changes any definitions of the register as well.
184 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
185 assert(FromReg != ToReg && "Cannot replace a reg with itself");
187 // TODO: This could be more efficient by bulk changing the operands.
188 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
189 MachineOperand &O = I.getOperand();
196 /// getVRegDef - Return the machine instr that defines the specified virtual
197 /// register or null if none is found. This assumes that the code is in SSA
198 /// form, so there should only be one definition.
199 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
200 // Since we are in SSA form, we can use the first definition.
201 def_iterator I = def_begin(Reg);
202 assert((I.atEnd() || llvm::next(I) == def_end()) &&
203 "getVRegDef assumes a single definition or no definition");
204 return !I.atEnd() ? &*I : 0;
207 /// getUniqueVRegDef - Return the unique machine instr that defines the
208 /// specified virtual register or null if none is found. If there are
209 /// multiple definitions or no definition, return null.
210 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
211 if (def_empty(Reg)) return 0;
212 def_iterator I = def_begin(Reg);
213 if (llvm::next(I) != def_end())
218 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
219 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
220 if (UI == use_nodbg_end())
222 return ++UI == use_nodbg_end();
225 /// clearKillFlags - Iterate over all the uses of the given register and
226 /// clear the kill flag from the MachineOperand. This function is used by
227 /// optimization passes which extend register lifetimes and need only
228 /// preserve conservative kill flag information.
229 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
230 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
231 UI.getOperand().setIsKill(false);
234 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
235 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
236 if (I->first == Reg || I->second == Reg)
241 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
242 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
248 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
249 /// corresponding live-in physical register.
250 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
251 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
252 if (I->second == VReg)
257 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
258 /// corresponding live-in physical register.
259 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
260 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
261 if (I->first == PReg)
266 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
267 /// into the given entry block.
269 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
270 const TargetRegisterInfo &TRI,
271 const TargetInstrInfo &TII) {
272 // Emit the copies into the top of the block.
273 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
274 if (LiveIns[i].second) {
275 if (use_empty(LiveIns[i].second)) {
276 // The livein has no uses. Drop it.
278 // It would be preferable to have isel avoid creating live-in
279 // records for unused arguments in the first place, but it's
280 // complicated by the debug info code for arguments.
281 LiveIns.erase(LiveIns.begin() + i);
285 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
286 TII.get(TargetOpcode::COPY), LiveIns[i].second)
287 .addReg(LiveIns[i].first);
289 // Add the register to the entry block live-in set.
290 EntryMBB->addLiveIn(LiveIns[i].first);
293 // Add the register to the entry block live-in set.
294 EntryMBB->addLiveIn(LiveIns[i].first);
299 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
300 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
301 I.getOperand().getParent()->dump();
305 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
306 ReservedRegs = TRI->getReservedRegs(MF);
309 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
310 const MachineFunction &MF) const {
311 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
313 // Check if any overlapping register is modified.
314 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
318 // Check if any overlapping register is allocatable so it may be used later.
319 if (AllocatableRegs.empty())
320 AllocatableRegs = TRI->getAllocatableSet(MF);
321 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
322 if (AllocatableRegs.test(*AI))