1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Analysis/AliasAnalysis.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/SmallSet.h"
37 #include "llvm/ADT/Statistic.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
44 STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
45 STATISTIC(NumPostRAHoisted,
46 "Number of machine instructions hoisted out of loops post regalloc");
49 class MachineLICM : public MachineFunctionPass {
52 const TargetMachine *TM;
53 const TargetInstrInfo *TII;
54 const TargetRegisterInfo *TRI;
55 const MachineFrameInfo *MFI;
56 MachineRegisterInfo *RegInfo;
58 // Various analyses that we use...
59 AliasAnalysis *AA; // Alias analysis info.
60 MachineLoopInfo *MLI; // Current MachineLoopInfo
61 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
63 // State that is updated as we process loops
64 bool Changed; // True if a loop is changed.
65 bool FirstInLoop; // True if it's the first LICM in the loop.
66 MachineLoop *CurLoop; // The current loop we are working on.
67 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
69 BitVector AllocatableSet;
71 // For each opcode, keep a list of potential CSE instructions.
72 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
75 static char ID; // Pass identification, replacement for typeid
77 MachineFunctionPass(ID), PreRegAlloc(true) {}
79 explicit MachineLICM(bool PreRA) :
80 MachineFunctionPass(ID), PreRegAlloc(PreRA) {}
82 virtual bool runOnMachineFunction(MachineFunction &MF);
84 const char *getPassName() const { return "Machine Instruction LICM"; }
86 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
88 AU.addRequired<MachineLoopInfo>();
89 AU.addRequired<MachineDominatorTree>();
90 AU.addRequired<AliasAnalysis>();
91 AU.addPreserved<MachineLoopInfo>();
92 AU.addPreserved<MachineDominatorTree>();
93 MachineFunctionPass::getAnalysisUsage(AU);
96 virtual void releaseMemory() {
101 /// CandidateInfo - Keep track of information about hoisting candidates.
102 struct CandidateInfo {
106 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
107 : MI(mi), Def(def), FI(fi) {}
110 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
111 /// invariants out to the preheader.
112 void HoistRegionPostRA();
114 /// HoistPostRA - When an instruction is found to only use loop invariant
115 /// operands that is safe to hoist, this instruction is called to do the
117 void HoistPostRA(MachineInstr *MI, unsigned Def);
119 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
120 /// gather register def and frame object update information.
121 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
122 SmallSet<int, 32> &StoredFIs,
123 SmallVector<CandidateInfo, 32> &Candidates);
125 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
127 void AddToLiveIns(unsigned Reg);
129 /// IsLICMCandidate - Returns true if the instruction may be a suitable
130 /// candidate for LICM. e.g. If the instruction is a call, then it's
131 /// obviously not safe to hoist it.
132 bool IsLICMCandidate(MachineInstr &I);
134 /// IsLoopInvariantInst - Returns true if the instruction is loop
135 /// invariant. I.e., all virtual register operands are defined outside of
136 /// the loop, physical registers aren't accessed (explicitly or implicitly),
137 /// and the instruction is hoistable.
139 bool IsLoopInvariantInst(MachineInstr &I);
141 /// IsProfitableToHoist - Return true if it is potentially profitable to
142 /// hoist the given loop invariant.
143 bool IsProfitableToHoist(MachineInstr &MI);
145 /// HoistRegion - Walk the specified region of the CFG (defined by all
146 /// blocks dominated by the specified block, and that are in the current
147 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
148 /// visit definitions before uses, allowing us to hoist a loop body in one
149 /// pass without iteration.
151 void HoistRegion(MachineDomTreeNode *N);
153 /// isLoadFromConstantMemory - Return true if the given instruction is a
154 /// load from constant memory.
155 bool isLoadFromConstantMemory(MachineInstr *MI);
157 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if
158 /// the load itself could be hoisted. Return the unfolded and hoistable
159 /// load, or null if the load couldn't be unfolded or if it wouldn't
161 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
163 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
164 /// duplicate of MI. Return this instruction if it's found.
165 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
166 std::vector<const MachineInstr*> &PrevMIs);
168 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
169 /// the preheader that compute the same value. If it's found, do a RAU on
170 /// with the definition of the existing instruction rather than hoisting
171 /// the instruction to the preheader.
172 bool EliminateCSE(MachineInstr *MI,
173 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
175 /// Hoist - When an instruction is found to only use loop invariant operands
176 /// that is safe to hoist, this instruction is called to do the dirty work.
178 void Hoist(MachineInstr *MI);
180 /// InitCSEMap - Initialize the CSE map with instructions that are in the
181 /// current loop preheader that may become duplicates of instructions that
182 /// are hoisted out of the loop.
183 void InitCSEMap(MachineBasicBlock *BB);
185 /// getCurPreheader - Get the preheader for the current loop, splitting
186 /// a critical edge if needed.
187 MachineBasicBlock *getCurPreheader();
189 } // end anonymous namespace
191 char MachineLICM::ID = 0;
192 INITIALIZE_PASS_BEGIN(MachineLICM, "machinelicm",
193 "Machine Loop Invariant Code Motion", false, false)
194 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
195 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
196 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
197 INITIALIZE_PASS_END(MachineLICM, "machinelicm",
198 "Machine Loop Invariant Code Motion", false, false)
200 FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
201 return new MachineLICM(PreRegAlloc);
204 /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most
205 /// loop that has a unique predecessor.
206 static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
207 // Check whether this loop even has a unique predecessor.
208 if (!CurLoop->getLoopPredecessor())
210 // Ok, now check to see if any of its outer loops do.
211 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
212 if (L->getLoopPredecessor())
214 // None of them did, so this is the outermost with a unique predecessor.
218 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
220 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM ********\n");
222 DEBUG(dbgs() << "******** Post-regalloc Machine LICM ********\n");
224 Changed = FirstInLoop = false;
225 TM = &MF.getTarget();
226 TII = TM->getInstrInfo();
227 TRI = TM->getRegisterInfo();
228 MFI = MF.getFrameInfo();
229 RegInfo = &MF.getRegInfo();
230 AllocatableSet = TRI->getAllocatableSet(MF);
232 // Get our Loop information...
233 MLI = &getAnalysis<MachineLoopInfo>();
234 DT = &getAnalysis<MachineDominatorTree>();
235 AA = &getAnalysis<AliasAnalysis>();
237 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
238 while (!Worklist.empty()) {
239 CurLoop = Worklist.pop_back_val();
242 // If this is done before regalloc, only visit outer-most preheader-sporting
244 if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
245 Worklist.append(CurLoop->begin(), CurLoop->end());
252 // CSEMap is initialized for loop header when the first instruction is
254 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
264 /// InstructionStoresToFI - Return true if instruction stores to the
266 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
267 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
268 oe = MI->memoperands_end(); o != oe; ++o) {
269 if (!(*o)->isStore() || !(*o)->getValue())
271 if (const FixedStackPseudoSourceValue *Value =
272 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
273 if (Value->getFrameIndex() == FI)
280 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
281 /// gather register def and frame object update information.
282 void MachineLICM::ProcessMI(MachineInstr *MI,
283 unsigned *PhysRegDefs,
284 SmallSet<int, 32> &StoredFIs,
285 SmallVector<CandidateInfo, 32> &Candidates) {
286 bool RuledOut = false;
287 bool HasNonInvariantUse = false;
289 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
290 const MachineOperand &MO = MI->getOperand(i);
292 // Remember if the instruction stores to the frame index.
293 int FI = MO.getIndex();
294 if (!StoredFIs.count(FI) &&
295 MFI->isSpillSlotObjectIndex(FI) &&
296 InstructionStoresToFI(MI, FI))
297 StoredFIs.insert(FI);
298 HasNonInvariantUse = true;
304 unsigned Reg = MO.getReg();
307 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
308 "Not expecting virtual register!");
311 if (Reg && PhysRegDefs[Reg])
312 // If it's using a non-loop-invariant register, then it's obviously not
314 HasNonInvariantUse = true;
318 if (MO.isImplicit()) {
320 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
323 // Non-dead implicit def? This cannot be hoisted.
325 // No need to check if a dead implicit def is also defined by
326 // another instruction.
330 // FIXME: For now, avoid instructions with multiple defs, unless
331 // it's a dead implicit def.
337 // If we have already seen another instruction that defines the same
338 // register, then this is not safe.
339 if (++PhysRegDefs[Reg] > 1)
340 // MI defined register is seen defined by another instruction in
341 // the loop, it cannot be a LICM candidate.
343 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
344 if (++PhysRegDefs[*AS] > 1)
348 // Only consider reloads for now and remats which do not have register
349 // operands. FIXME: Consider unfold load folding instructions.
350 if (Def && !RuledOut) {
352 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
353 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
354 Candidates.push_back(CandidateInfo(MI, Def, FI));
358 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
359 /// invariants out to the preheader.
360 void MachineLICM::HoistRegionPostRA() {
361 unsigned NumRegs = TRI->getNumRegs();
362 unsigned *PhysRegDefs = new unsigned[NumRegs];
363 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
365 SmallVector<CandidateInfo, 32> Candidates;
366 SmallSet<int, 32> StoredFIs;
368 // Walk the entire region, count number of defs for each register, and
369 // collect potential LICM candidates.
370 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
371 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
372 MachineBasicBlock *BB = Blocks[i];
373 // Conservatively treat live-in's as an external def.
374 // FIXME: That means a reload that're reused in successor block(s) will not
376 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
377 E = BB->livein_end(); I != E; ++I) {
380 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
384 for (MachineBasicBlock::iterator
385 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
386 MachineInstr *MI = &*MII;
387 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
391 // Now evaluate whether the potential candidates qualify.
392 // 1. Check if the candidate defined register is defined by another
393 // instruction in the loop.
394 // 2. If the candidate is a load from stack slot (always true for now),
395 // check if the slot is stored anywhere in the loop.
396 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
397 if (Candidates[i].FI != INT_MIN &&
398 StoredFIs.count(Candidates[i].FI))
401 if (PhysRegDefs[Candidates[i].Def] == 1) {
403 MachineInstr *MI = Candidates[i].MI;
404 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
405 const MachineOperand &MO = MI->getOperand(j);
406 if (!MO.isReg() || MO.isDef() || !MO.getReg())
408 if (PhysRegDefs[MO.getReg()]) {
409 // If it's using a non-loop-invariant register, then it's obviously
410 // not safe to hoist.
416 HoistPostRA(MI, Candidates[i].Def);
420 delete[] PhysRegDefs;
423 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
424 /// loop, and make sure it is not killed by any instructions in the loop.
425 void MachineLICM::AddToLiveIns(unsigned Reg) {
426 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
427 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
428 MachineBasicBlock *BB = Blocks[i];
429 if (!BB->isLiveIn(Reg))
431 for (MachineBasicBlock::iterator
432 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
433 MachineInstr *MI = &*MII;
434 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
435 MachineOperand &MO = MI->getOperand(i);
436 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
437 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
444 /// HoistPostRA - When an instruction is found to only use loop invariant
445 /// operands that is safe to hoist, this instruction is called to do the
447 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
448 MachineBasicBlock *Preheader = getCurPreheader();
449 if (!Preheader) return;
451 // Now move the instructions to the predecessor, inserting it before any
452 // terminator instructions.
454 dbgs() << "Hoisting " << *MI;
455 if (Preheader->getBasicBlock())
456 dbgs() << " to MachineBasicBlock "
457 << Preheader->getName();
458 if (MI->getParent()->getBasicBlock())
459 dbgs() << " from MachineBasicBlock "
460 << MI->getParent()->getName();
464 // Splice the instruction to the preheader.
465 MachineBasicBlock *MBB = MI->getParent();
466 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
468 // Add register to livein list to all the BBs in the current loop since a
469 // loop invariant must be kept live throughout the whole loop. This is
470 // important to ensure later passes do not scavenge the def register.
477 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
478 /// dominated by the specified block, and that are in the current loop) in depth
479 /// first order w.r.t the DominatorTree. This allows us to visit definitions
480 /// before uses, allowing us to hoist a loop body in one pass without iteration.
482 void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
483 assert(N != 0 && "Null dominator tree node?");
484 MachineBasicBlock *BB = N->getBlock();
486 // If this subregion is not in the top level loop at all, exit.
487 if (!CurLoop->contains(BB)) return;
489 for (MachineBasicBlock::iterator
490 MII = BB->begin(), E = BB->end(); MII != E; ) {
491 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
496 // Don't hoist things out of a large switch statement. This often causes
497 // code to be hoisted that wasn't going to be executed, and increases
498 // register pressure in a situation where it's likely to matter.
499 if (BB->succ_size() < 25) {
500 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
501 for (unsigned I = 0, E = Children.size(); I != E; ++I)
502 HoistRegion(Children[I]);
506 /// IsLICMCandidate - Returns true if the instruction may be a suitable
507 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously
508 /// not safe to hoist it.
509 bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
510 // Check if it's safe to move the instruction.
511 bool DontMoveAcrossStore = true;
512 if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore))
518 /// IsLoopInvariantInst - Returns true if the instruction is loop
519 /// invariant. I.e., all virtual register operands are defined outside of the
520 /// loop, physical registers aren't accessed explicitly, and there are no side
521 /// effects that aren't captured by the operands or other flags.
523 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
524 if (!IsLICMCandidate(I))
527 // The instruction is loop invariant if all of its operands are.
528 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
529 const MachineOperand &MO = I.getOperand(i);
534 unsigned Reg = MO.getReg();
535 if (Reg == 0) continue;
537 // Don't hoist an instruction that uses or defines a physical register.
538 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
540 // If the physreg has no defs anywhere, it's just an ambient register
541 // and we can freely move its uses. Alternatively, if it's allocatable,
542 // it could get allocated to something with a def during allocation.
543 if (!RegInfo->def_empty(Reg))
545 if (AllocatableSet.test(Reg))
547 // Check for a def among the register's aliases too.
548 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
549 unsigned AliasReg = *Alias;
550 if (!RegInfo->def_empty(AliasReg))
552 if (AllocatableSet.test(AliasReg))
555 // Otherwise it's safe to move.
557 } else if (!MO.isDead()) {
558 // A def that isn't dead. We can't move it.
560 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
561 // If the reg is live into the loop, we can't hoist an instruction
562 // which would clobber it.
570 assert(RegInfo->getVRegDef(Reg) &&
571 "Machine instr not mapped for this vreg?!");
573 // If the loop contains the definition of an operand, then the instruction
574 // isn't loop invariant.
575 if (CurLoop->contains(RegInfo->getVRegDef(Reg)))
579 // If we got this far, the instruction is loop invariant!
584 /// HasPHIUses - Return true if the specified register has any PHI use.
585 static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) {
586 for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg),
587 UE = RegInfo->use_end(); UI != UE; ++UI) {
588 MachineInstr *UseMI = &*UI;
595 /// isLoadFromConstantMemory - Return true if the given instruction is a
596 /// load from constant memory. Machine LICM will hoist these even if they are
597 /// not re-materializable.
598 bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) {
599 if (!MI->getDesc().mayLoad()) return false;
600 if (!MI->hasOneMemOperand()) return false;
601 MachineMemOperand *MMO = *MI->memoperands_begin();
602 if (MMO->isVolatile()) return false;
603 if (!MMO->getValue()) return false;
604 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(MMO->getValue());
606 MachineFunction &MF = *MI->getParent()->getParent();
607 return PSV->isConstant(MF.getFrameInfo());
609 return AA->pointsToConstantMemory(MMO->getValue());
613 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
614 /// the given loop invariant.
615 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
616 // FIXME: For now, only hoist re-materilizable instructions. LICM will
617 // increase register pressure. We want to make sure it doesn't increase
619 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
620 // these tend to help performance in low register pressure situation. The
621 // trade off is it may cause spill in high pressure situation. It will end up
622 // adding a store in the loop preheader. But the reload is no more expensive.
623 // The side benefit is these loads are frequently CSE'ed.
624 if (!TII->isTriviallyReMaterializable(&MI, AA)) {
625 if (!isLoadFromConstantMemory(&MI))
629 // If result(s) of this instruction is used by PHIs, then don't hoist it.
630 // The presence of joins makes it difficult for current register allocator
631 // implementation to perform remat.
632 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
633 const MachineOperand &MO = MI.getOperand(i);
634 if (!MO.isReg() || !MO.isDef())
636 if (HasPHIUses(MO.getReg(), RegInfo))
643 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
644 // Don't unfold simple loads.
645 if (MI->getDesc().canFoldAsLoad())
648 // If not, we may be able to unfold a load and hoist that.
649 // First test whether the instruction is loading from an amenable
651 if (!isLoadFromConstantMemory(MI))
654 // Next determine the register class for a temporary register.
655 unsigned LoadRegIndex;
657 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
659 /*UnfoldStore=*/false,
661 if (NewOpc == 0) return 0;
662 const TargetInstrDesc &TID = TII->get(NewOpc);
663 if (TID.getNumDefs() != 1) return 0;
664 const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI);
665 // Ok, we're unfolding. Create a temporary register and do the unfold.
666 unsigned Reg = RegInfo->createVirtualRegister(RC);
668 MachineFunction &MF = *MI->getParent()->getParent();
669 SmallVector<MachineInstr *, 2> NewMIs;
671 TII->unfoldMemoryOperand(MF, MI, Reg,
672 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
676 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
678 assert(NewMIs.size() == 2 &&
679 "Unfolded a load into multiple instructions!");
680 MachineBasicBlock *MBB = MI->getParent();
681 MBB->insert(MI, NewMIs[0]);
682 MBB->insert(MI, NewMIs[1]);
683 // If unfolding produced a load that wasn't loop-invariant or profitable to
684 // hoist, discard the new instructions and bail.
685 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
686 NewMIs[0]->eraseFromParent();
687 NewMIs[1]->eraseFromParent();
690 // Otherwise we successfully unfolded a load that we can hoist.
691 MI->eraseFromParent();
695 void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
696 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
697 const MachineInstr *MI = &*I;
698 // FIXME: For now, only hoist re-materilizable instructions. LICM will
699 // increase register pressure. We want to make sure it doesn't increase
701 if (TII->isTriviallyReMaterializable(MI, AA)) {
702 unsigned Opcode = MI->getOpcode();
703 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
704 CI = CSEMap.find(Opcode);
705 if (CI != CSEMap.end())
706 CI->second.push_back(MI);
708 std::vector<const MachineInstr*> CSEMIs;
709 CSEMIs.push_back(MI);
710 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
717 MachineLICM::LookForDuplicate(const MachineInstr *MI,
718 std::vector<const MachineInstr*> &PrevMIs) {
719 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
720 const MachineInstr *PrevMI = PrevMIs[i];
721 if (TII->produceSameValue(MI, PrevMI))
727 bool MachineLICM::EliminateCSE(MachineInstr *MI,
728 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
729 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
730 // the undef property onto uses.
731 if (CI == CSEMap.end() || MI->isImplicitDef())
734 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
735 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
737 // Replace virtual registers defined by MI by their counterparts defined
739 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
740 const MachineOperand &MO = MI->getOperand(i);
742 // Physical registers may not differ here.
743 assert((!MO.isReg() || MO.getReg() == 0 ||
744 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
745 MO.getReg() == Dup->getOperand(i).getReg()) &&
746 "Instructions with different phys regs are not identical!");
748 if (MO.isReg() && MO.isDef() &&
749 !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
750 RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
751 RegInfo->clearKillFlags(Dup->getOperand(i).getReg());
754 MI->eraseFromParent();
761 /// Hoist - When an instruction is found to use only loop invariant operands
762 /// that are safe to hoist, this instruction is called to do the dirty work.
764 void MachineLICM::Hoist(MachineInstr *MI) {
765 MachineBasicBlock *Preheader = getCurPreheader();
766 if (!Preheader) return;
768 // First check whether we should hoist this instruction.
769 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
770 // If not, try unfolding a hoistable load.
771 MI = ExtractHoistableLoad(MI);
775 // Now move the instructions to the predecessor, inserting it before any
776 // terminator instructions.
778 dbgs() << "Hoisting " << *MI;
779 if (Preheader->getBasicBlock())
780 dbgs() << " to MachineBasicBlock "
781 << Preheader->getName();
782 if (MI->getParent()->getBasicBlock())
783 dbgs() << " from MachineBasicBlock "
784 << MI->getParent()->getName();
788 // If this is the first instruction being hoisted to the preheader,
789 // initialize the CSE map with potential common expressions.
791 InitCSEMap(Preheader);
795 // Look for opportunity to CSE the hoisted instruction.
796 unsigned Opcode = MI->getOpcode();
797 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
798 CI = CSEMap.find(Opcode);
799 if (!EliminateCSE(MI, CI)) {
800 // Otherwise, splice the instruction to the preheader.
801 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
803 // Clear the kill flags of any register this instruction defines,
804 // since they may need to be live throughout the entire loop
805 // rather than just live for part of it.
806 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
807 MachineOperand &MO = MI->getOperand(i);
808 if (MO.isReg() && MO.isDef() && !MO.isDead())
809 RegInfo->clearKillFlags(MO.getReg());
812 // Add to the CSE map.
813 if (CI != CSEMap.end())
814 CI->second.push_back(MI);
816 std::vector<const MachineInstr*> CSEMIs;
817 CSEMIs.push_back(MI);
818 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
826 MachineBasicBlock *MachineLICM::getCurPreheader() {
827 // Determine the block to which to hoist instructions. If we can't find a
828 // suitable loop predecessor, we can't do any hoisting.
830 // If we've tried to get a preheader and failed, don't try again.
831 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
835 CurPreheader = CurLoop->getLoopPreheader();
837 MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
839 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
843 CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), this);
845 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);