1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/Target/TargetLowering.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetInstrItineraries.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/raw_ostream.h"
46 "Number of machine instructions hoisted out of loops");
48 "Number of instructions hoisted in low reg pressure situation");
49 STATISTIC(NumHighLatency,
50 "Number of high latency instructions hoisted");
52 "Number of hoisted machine instructions CSEed");
53 STATISTIC(NumPostRAHoisted,
54 "Number of machine instructions hoisted out of loops post regalloc");
57 class MachineLICM : public MachineFunctionPass {
60 const TargetMachine *TM;
61 const TargetInstrInfo *TII;
62 const TargetLowering *TLI;
63 const TargetRegisterInfo *TRI;
64 const MachineFrameInfo *MFI;
65 MachineRegisterInfo *MRI;
66 const InstrItineraryData *InstrItins;
68 // Various analyses that we use...
69 AliasAnalysis *AA; // Alias analysis info.
70 MachineLoopInfo *MLI; // Current MachineLoopInfo
71 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
73 // State that is updated as we process loops
74 bool Changed; // True if a loop is changed.
75 bool FirstInLoop; // True if it's the first LICM in the loop.
76 MachineLoop *CurLoop; // The current loop we are working on.
77 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
79 BitVector AllocatableSet;
81 // Track 'estimated' register pressure.
82 SmallSet<unsigned, 32> RegSeen;
83 SmallVector<unsigned, 8> RegPressure;
85 // Register pressure "limit" per register class. If the pressure
86 // is higher than the limit, then it's considered high.
87 SmallVector<unsigned, 8> RegLimit;
89 // Register pressure on path leading from loop preheader to current BB.
90 SmallVector<SmallVector<unsigned, 8>, 16> BackTrace;
92 // For each opcode, keep a list of potential CSE instructions.
93 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
96 static char ID; // Pass identification, replacement for typeid
98 MachineFunctionPass(ID), PreRegAlloc(true) {
99 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
102 explicit MachineLICM(bool PreRA) :
103 MachineFunctionPass(ID), PreRegAlloc(PreRA) {
104 initializeMachineLICMPass(*PassRegistry::getPassRegistry());
107 virtual bool runOnMachineFunction(MachineFunction &MF);
109 const char *getPassName() const { return "Machine Instruction LICM"; }
111 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
112 AU.setPreservesCFG();
113 AU.addRequired<MachineLoopInfo>();
114 AU.addRequired<MachineDominatorTree>();
115 AU.addRequired<AliasAnalysis>();
116 AU.addPreserved<MachineLoopInfo>();
117 AU.addPreserved<MachineDominatorTree>();
118 MachineFunctionPass::getAnalysisUsage(AU);
121 virtual void releaseMemory() {
126 for (DenseMap<unsigned,std::vector<const MachineInstr*> >::iterator
127 CI = CSEMap.begin(), CE = CSEMap.end(); CI != CE; ++CI)
133 /// CandidateInfo - Keep track of information about hoisting candidates.
134 struct CandidateInfo {
138 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
139 : MI(mi), Def(def), FI(fi) {}
142 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
143 /// invariants out to the preheader.
144 void HoistRegionPostRA();
146 /// HoistPostRA - When an instruction is found to only use loop invariant
147 /// operands that is safe to hoist, this instruction is called to do the
149 void HoistPostRA(MachineInstr *MI, unsigned Def);
151 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
152 /// gather register def and frame object update information.
153 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
154 SmallSet<int, 32> &StoredFIs,
155 SmallVector<CandidateInfo, 32> &Candidates);
157 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
159 void AddToLiveIns(unsigned Reg);
161 /// IsLICMCandidate - Returns true if the instruction may be a suitable
162 /// candidate for LICM. e.g. If the instruction is a call, then it's
163 /// obviously not safe to hoist it.
164 bool IsLICMCandidate(MachineInstr &I);
166 /// IsLoopInvariantInst - Returns true if the instruction is loop
167 /// invariant. I.e., all virtual register operands are defined outside of
168 /// the loop, physical registers aren't accessed (explicitly or implicitly),
169 /// and the instruction is hoistable.
171 bool IsLoopInvariantInst(MachineInstr &I);
173 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
174 /// and an use in the current loop, return true if the target considered
176 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg);
178 /// CanCauseHighRegPressure - Visit BBs from header to current BB,
179 /// check if hoisting an instruction of the given cost matrix can cause high
180 /// register pressure.
181 bool CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost);
183 /// UpdateBackTraceRegPressure - Traverse the back trace from header to
184 /// the current block and update their register pressures to reflect the
185 /// effect of hoisting MI from the current block to the preheader.
186 void UpdateBackTraceRegPressure(const MachineInstr *MI);
188 /// IsProfitableToHoist - Return true if it is potentially profitable to
189 /// hoist the given loop invariant.
190 bool IsProfitableToHoist(MachineInstr &MI);
192 /// HoistRegion - Walk the specified region of the CFG (defined by all
193 /// blocks dominated by the specified block, and that are in the current
194 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
195 /// visit definitions before uses, allowing us to hoist a loop body in one
196 /// pass without iteration.
198 void HoistRegion(MachineDomTreeNode *N, bool IsHeader = false);
200 /// InitRegPressure - Find all virtual register references that are liveout
201 /// of the preheader to initialize the starting "register pressure". Note
202 /// this does not count live through (livein but not used) registers.
203 void InitRegPressure(MachineBasicBlock *BB);
205 /// UpdateRegPressure - Update estimate of register pressure after the
206 /// specified instruction.
207 void UpdateRegPressure(const MachineInstr *MI);
209 /// isLoadFromConstantMemory - Return true if the given instruction is a
210 /// load from constant memory.
211 bool isLoadFromConstantMemory(MachineInstr *MI);
213 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if
214 /// the load itself could be hoisted. Return the unfolded and hoistable
215 /// load, or null if the load couldn't be unfolded or if it wouldn't
217 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
219 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
220 /// duplicate of MI. Return this instruction if it's found.
221 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
222 std::vector<const MachineInstr*> &PrevMIs);
224 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
225 /// the preheader that compute the same value. If it's found, do a RAU on
226 /// with the definition of the existing instruction rather than hoisting
227 /// the instruction to the preheader.
228 bool EliminateCSE(MachineInstr *MI,
229 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI);
231 /// Hoist - When an instruction is found to only use loop invariant operands
232 /// that is safe to hoist, this instruction is called to do the dirty work.
233 /// It returns true if the instruction is hoisted.
234 bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
236 /// InitCSEMap - Initialize the CSE map with instructions that are in the
237 /// current loop preheader that may become duplicates of instructions that
238 /// are hoisted out of the loop.
239 void InitCSEMap(MachineBasicBlock *BB);
241 /// getCurPreheader - Get the preheader for the current loop, splitting
242 /// a critical edge if needed.
243 MachineBasicBlock *getCurPreheader();
245 } // end anonymous namespace
247 char MachineLICM::ID = 0;
248 INITIALIZE_PASS_BEGIN(MachineLICM, "machinelicm",
249 "Machine Loop Invariant Code Motion", false, false)
250 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
251 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
252 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
253 INITIALIZE_PASS_END(MachineLICM, "machinelicm",
254 "Machine Loop Invariant Code Motion", false, false)
256 FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
257 return new MachineLICM(PreRegAlloc);
260 /// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most
261 /// loop that has a unique predecessor.
262 static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
263 // Check whether this loop even has a unique predecessor.
264 if (!CurLoop->getLoopPredecessor())
266 // Ok, now check to see if any of its outer loops do.
267 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
268 if (L->getLoopPredecessor())
270 // None of them did, so this is the outermost with a unique predecessor.
274 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
276 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
278 DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
279 DEBUG(dbgs() << MF.getFunction()->getName() << " ********\n");
281 Changed = FirstInLoop = false;
282 TM = &MF.getTarget();
283 TII = TM->getInstrInfo();
284 TLI = TM->getTargetLowering();
285 TRI = TM->getRegisterInfo();
286 MFI = MF.getFrameInfo();
287 MRI = &MF.getRegInfo();
288 InstrItins = TM->getInstrItineraryData();
289 AllocatableSet = TRI->getAllocatableSet(MF);
292 // Estimate register pressure during pre-regalloc pass.
293 unsigned NumRC = TRI->getNumRegClasses();
294 RegPressure.resize(NumRC);
295 std::fill(RegPressure.begin(), RegPressure.end(), 0);
296 RegLimit.resize(NumRC);
297 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
298 E = TRI->regclass_end(); I != E; ++I)
299 RegLimit[(*I)->getID()] = TLI->getRegPressureLimit(*I, MF);
302 // Get our Loop information...
303 MLI = &getAnalysis<MachineLoopInfo>();
304 DT = &getAnalysis<MachineDominatorTree>();
305 AA = &getAnalysis<AliasAnalysis>();
307 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end());
308 while (!Worklist.empty()) {
309 CurLoop = Worklist.pop_back_val();
312 // If this is done before regalloc, only visit outer-most preheader-sporting
314 if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) {
315 Worklist.append(CurLoop->begin(), CurLoop->end());
322 // CSEMap is initialized for loop header when the first instruction is
324 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
326 HoistRegion(N, true);
334 /// InstructionStoresToFI - Return true if instruction stores to the
336 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
337 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
338 oe = MI->memoperands_end(); o != oe; ++o) {
339 if (!(*o)->isStore() || !(*o)->getValue())
341 if (const FixedStackPseudoSourceValue *Value =
342 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
343 if (Value->getFrameIndex() == FI)
350 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
351 /// gather register def and frame object update information.
352 void MachineLICM::ProcessMI(MachineInstr *MI,
353 unsigned *PhysRegDefs,
354 SmallSet<int, 32> &StoredFIs,
355 SmallVector<CandidateInfo, 32> &Candidates) {
356 bool RuledOut = false;
357 bool HasNonInvariantUse = false;
359 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
360 const MachineOperand &MO = MI->getOperand(i);
362 // Remember if the instruction stores to the frame index.
363 int FI = MO.getIndex();
364 if (!StoredFIs.count(FI) &&
365 MFI->isSpillSlotObjectIndex(FI) &&
366 InstructionStoresToFI(MI, FI))
367 StoredFIs.insert(FI);
368 HasNonInvariantUse = true;
374 unsigned Reg = MO.getReg();
377 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
378 "Not expecting virtual register!");
381 if (Reg && PhysRegDefs[Reg])
382 // If it's using a non-loop-invariant register, then it's obviously not
384 HasNonInvariantUse = true;
388 if (MO.isImplicit()) {
390 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
393 // Non-dead implicit def? This cannot be hoisted.
395 // No need to check if a dead implicit def is also defined by
396 // another instruction.
400 // FIXME: For now, avoid instructions with multiple defs, unless
401 // it's a dead implicit def.
407 // If we have already seen another instruction that defines the same
408 // register, then this is not safe.
409 if (++PhysRegDefs[Reg] > 1)
410 // MI defined register is seen defined by another instruction in
411 // the loop, it cannot be a LICM candidate.
413 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
414 if (++PhysRegDefs[*AS] > 1)
418 // Only consider reloads for now and remats which do not have register
419 // operands. FIXME: Consider unfold load folding instructions.
420 if (Def && !RuledOut) {
422 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
423 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
424 Candidates.push_back(CandidateInfo(MI, Def, FI));
428 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
429 /// invariants out to the preheader.
430 void MachineLICM::HoistRegionPostRA() {
431 unsigned NumRegs = TRI->getNumRegs();
432 unsigned *PhysRegDefs = new unsigned[NumRegs];
433 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
435 SmallVector<CandidateInfo, 32> Candidates;
436 SmallSet<int, 32> StoredFIs;
438 // Walk the entire region, count number of defs for each register, and
439 // collect potential LICM candidates.
440 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
441 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
442 MachineBasicBlock *BB = Blocks[i];
443 // Conservatively treat live-in's as an external def.
444 // FIXME: That means a reload that're reused in successor block(s) will not
446 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
447 E = BB->livein_end(); I != E; ++I) {
450 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
454 for (MachineBasicBlock::iterator
455 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
456 MachineInstr *MI = &*MII;
457 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
461 // Now evaluate whether the potential candidates qualify.
462 // 1. Check if the candidate defined register is defined by another
463 // instruction in the loop.
464 // 2. If the candidate is a load from stack slot (always true for now),
465 // check if the slot is stored anywhere in the loop.
466 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
467 if (Candidates[i].FI != INT_MIN &&
468 StoredFIs.count(Candidates[i].FI))
471 if (PhysRegDefs[Candidates[i].Def] == 1) {
473 MachineInstr *MI = Candidates[i].MI;
474 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
475 const MachineOperand &MO = MI->getOperand(j);
476 if (!MO.isReg() || MO.isDef() || !MO.getReg())
478 if (PhysRegDefs[MO.getReg()]) {
479 // If it's using a non-loop-invariant register, then it's obviously
480 // not safe to hoist.
486 HoistPostRA(MI, Candidates[i].Def);
490 delete[] PhysRegDefs;
493 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
494 /// loop, and make sure it is not killed by any instructions in the loop.
495 void MachineLICM::AddToLiveIns(unsigned Reg) {
496 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks();
497 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
498 MachineBasicBlock *BB = Blocks[i];
499 if (!BB->isLiveIn(Reg))
501 for (MachineBasicBlock::iterator
502 MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
503 MachineInstr *MI = &*MII;
504 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
505 MachineOperand &MO = MI->getOperand(i);
506 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
507 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
514 /// HoistPostRA - When an instruction is found to only use loop invariant
515 /// operands that is safe to hoist, this instruction is called to do the
517 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
518 MachineBasicBlock *Preheader = getCurPreheader();
519 if (!Preheader) return;
521 // Now move the instructions to the predecessor, inserting it before any
522 // terminator instructions.
524 dbgs() << "Hoisting " << *MI;
525 if (Preheader->getBasicBlock())
526 dbgs() << " to MachineBasicBlock "
527 << Preheader->getName();
528 if (MI->getParent()->getBasicBlock())
529 dbgs() << " from MachineBasicBlock "
530 << MI->getParent()->getName();
534 // Splice the instruction to the preheader.
535 MachineBasicBlock *MBB = MI->getParent();
536 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
538 // Add register to livein list to all the BBs in the current loop since a
539 // loop invariant must be kept live throughout the whole loop. This is
540 // important to ensure later passes do not scavenge the def register.
547 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
548 /// dominated by the specified block, and that are in the current loop) in depth
549 /// first order w.r.t the DominatorTree. This allows us to visit definitions
550 /// before uses, allowing us to hoist a loop body in one pass without iteration.
552 void MachineLICM::HoistRegion(MachineDomTreeNode *N, bool IsHeader) {
553 assert(N != 0 && "Null dominator tree node?");
554 MachineBasicBlock *BB = N->getBlock();
556 // If this subregion is not in the top level loop at all, exit.
557 if (!CurLoop->contains(BB)) return;
559 MachineBasicBlock *Preheader = getCurPreheader();
564 // Compute registers which are livein into the loop headers.
567 InitRegPressure(Preheader);
570 // Remember livein register pressure.
571 BackTrace.push_back(RegPressure);
573 for (MachineBasicBlock::iterator
574 MII = BB->begin(), E = BB->end(); MII != E; ) {
575 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
576 MachineInstr *MI = &*MII;
577 if (!Hoist(MI, Preheader))
578 UpdateRegPressure(MI);
582 // Don't hoist things out of a large switch statement. This often causes
583 // code to be hoisted that wasn't going to be executed, and increases
584 // register pressure in a situation where it's likely to matter.
585 if (BB->succ_size() < 25) {
586 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
587 for (unsigned I = 0, E = Children.size(); I != E; ++I)
588 HoistRegion(Children[I]);
591 BackTrace.pop_back();
594 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
595 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
598 /// InitRegPressure - Find all virtual register references that are liveout of
599 /// the preheader to initialize the starting "register pressure". Note this
600 /// does not count live through (livein but not used) registers.
601 void MachineLICM::InitRegPressure(MachineBasicBlock *BB) {
602 std::fill(RegPressure.begin(), RegPressure.end(), 0);
604 // If the preheader has only a single predecessor and it ends with a
605 // fallthrough or an unconditional branch, then scan its predecessor for live
606 // defs as well. This happens whenever the preheader is created by splitting
607 // the critical edge from the loop predecessor to the loop header.
608 if (BB->pred_size() == 1) {
609 MachineBasicBlock *TBB = 0, *FBB = 0;
610 SmallVector<MachineOperand, 4> Cond;
611 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
612 InitRegPressure(*BB->pred_begin());
615 for (MachineBasicBlock::iterator MII = BB->begin(), E = BB->end();
617 MachineInstr *MI = &*MII;
618 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
619 const MachineOperand &MO = MI->getOperand(i);
620 if (!MO.isReg() || MO.isImplicit())
622 unsigned Reg = MO.getReg();
623 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
626 bool isNew = RegSeen.insert(Reg);
627 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
628 EVT VT = *RC->vt_begin();
629 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
631 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
633 bool isKill = isOperandKill(MO, MRI);
634 if (isNew && !isKill)
635 // Haven't seen this, it must be a livein.
636 RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
637 else if (!isNew && isKill)
638 RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
644 /// UpdateRegPressure - Update estimate of register pressure after the
645 /// specified instruction.
646 void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
647 if (MI->isImplicitDef())
650 SmallVector<unsigned, 4> Defs;
651 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
652 const MachineOperand &MO = MI->getOperand(i);
653 if (!MO.isReg() || MO.isImplicit())
655 unsigned Reg = MO.getReg();
656 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
659 bool isNew = RegSeen.insert(Reg);
662 else if (!isNew && isOperandKill(MO, MRI)) {
663 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
664 EVT VT = *RC->vt_begin();
665 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
666 unsigned RCCost = TLI->getRepRegClassCostFor(VT);
668 if (RCCost > RegPressure[RCId])
669 RegPressure[RCId] = 0;
671 RegPressure[RCId] -= RCCost;
675 while (!Defs.empty()) {
676 unsigned Reg = Defs.pop_back_val();
677 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
678 EVT VT = *RC->vt_begin();
679 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
680 unsigned RCCost = TLI->getRepRegClassCostFor(VT);
681 RegPressure[RCId] += RCCost;
685 /// IsLICMCandidate - Returns true if the instruction may be a suitable
686 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously
687 /// not safe to hoist it.
688 bool MachineLICM::IsLICMCandidate(MachineInstr &I) {
689 // Check if it's safe to move the instruction.
690 bool DontMoveAcrossStore = true;
691 if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore))
697 /// IsLoopInvariantInst - Returns true if the instruction is loop
698 /// invariant. I.e., all virtual register operands are defined outside of the
699 /// loop, physical registers aren't accessed explicitly, and there are no side
700 /// effects that aren't captured by the operands or other flags.
702 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
703 if (!IsLICMCandidate(I))
706 // The instruction is loop invariant if all of its operands are.
707 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
708 const MachineOperand &MO = I.getOperand(i);
713 unsigned Reg = MO.getReg();
714 if (Reg == 0) continue;
716 // Don't hoist an instruction that uses or defines a physical register.
717 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
719 // If the physreg has no defs anywhere, it's just an ambient register
720 // and we can freely move its uses. Alternatively, if it's allocatable,
721 // it could get allocated to something with a def during allocation.
722 if (!MRI->def_empty(Reg))
724 if (AllocatableSet.test(Reg))
726 // Check for a def among the register's aliases too.
727 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
728 unsigned AliasReg = *Alias;
729 if (!MRI->def_empty(AliasReg))
731 if (AllocatableSet.test(AliasReg))
734 // Otherwise it's safe to move.
736 } else if (!MO.isDead()) {
737 // A def that isn't dead. We can't move it.
739 } else if (CurLoop->getHeader()->isLiveIn(Reg)) {
740 // If the reg is live into the loop, we can't hoist an instruction
741 // which would clobber it.
749 assert(MRI->getVRegDef(Reg) &&
750 "Machine instr not mapped for this vreg?!");
752 // If the loop contains the definition of an operand, then the instruction
753 // isn't loop invariant.
754 if (CurLoop->contains(MRI->getVRegDef(Reg)))
758 // If we got this far, the instruction is loop invariant!
763 /// HasPHIUses - Return true if the specified register has any PHI use.
764 static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *MRI) {
765 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
766 UE = MRI->use_end(); UI != UE; ++UI) {
767 MachineInstr *UseMI = &*UI;
774 /// isLoadFromConstantMemory - Return true if the given instruction is a
775 /// load from constant memory. Machine LICM will hoist these even if they are
776 /// not re-materializable.
777 bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) {
778 if (!MI->getDesc().mayLoad()) return false;
779 if (!MI->hasOneMemOperand()) return false;
780 MachineMemOperand *MMO = *MI->memoperands_begin();
781 if (MMO->isVolatile()) return false;
782 if (!MMO->getValue()) return false;
783 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(MMO->getValue());
785 MachineFunction &MF = *MI->getParent()->getParent();
786 return PSV->isConstant(MF.getFrameInfo());
788 return AA->pointsToConstantMemory(AliasAnalysis::Location(MMO->getValue(),
790 MMO->getTBAAInfo()));
794 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg'
795 /// and an use in the current loop, return true if the target considered
797 bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
798 unsigned DefIdx, unsigned Reg) {
799 if (MRI->use_nodbg_empty(Reg))
802 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
803 E = MRI->use_nodbg_end(); I != E; ++I) {
804 MachineInstr *UseMI = &*I;
805 if (!CurLoop->contains(UseMI->getParent()))
807 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
808 const MachineOperand &MO = UseMI->getOperand(i);
809 if (!MO.isReg() || !MO.isUse())
811 unsigned MOReg = MO.getReg();
815 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
819 // Only look at the first in loop use.
826 /// CanCauseHighRegPressure - Visit BBs from header to current BB, check
827 /// if hoisting an instruction of the given cost matrix can cause high
828 /// register pressure.
829 bool MachineLICM::CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost) {
830 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
835 unsigned RCId = CI->first;
836 for (unsigned i = BackTrace.size(); i != 0; --i) {
837 SmallVector<unsigned, 8> &RP = BackTrace[i-1];
838 if (RP[RCId] + CI->second >= RegLimit[RCId])
846 /// UpdateBackTraceRegPressure - Traverse the back trace from header to the
847 /// current block and update their register pressures to reflect the effect
848 /// of hoisting MI from the current block to the preheader.
849 void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
850 if (MI->isImplicitDef())
853 // First compute the 'cost' of the instruction, i.e. its contribution
854 // to register pressure.
855 DenseMap<unsigned, int> Cost;
856 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
857 const MachineOperand &MO = MI->getOperand(i);
858 if (!MO.isReg() || MO.isImplicit())
860 unsigned Reg = MO.getReg();
861 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
864 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
865 EVT VT = *RC->vt_begin();
866 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
867 unsigned RCCost = TLI->getRepRegClassCostFor(VT);
869 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
870 if (CI != Cost.end())
871 CI->second += RCCost;
873 Cost.insert(std::make_pair(RCId, RCCost));
874 } else if (isOperandKill(MO, MRI)) {
875 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
876 if (CI != Cost.end())
877 CI->second -= RCCost;
879 Cost.insert(std::make_pair(RCId, -RCCost));
883 // Update register pressure of blocks from loop header to current block.
884 for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) {
885 SmallVector<unsigned, 8> &RP = BackTrace[i];
886 for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
888 unsigned RCId = CI->first;
889 RP[RCId] += CI->second;
894 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
895 /// the given loop invariant.
896 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
897 if (MI.isImplicitDef())
900 // If the instruction is cheap, only hoist if it is re-materilizable. LICM
901 // will increase register pressure. It's probably not worth it if the
902 // instruction is cheap.
903 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting
904 // these tend to help performance in low register pressure situation. The
905 // trade off is it may cause spill in high pressure situation. It will end up
906 // adding a store in the loop preheader. But the reload is no more expensive.
907 // The side benefit is these loads are frequently CSE'ed.
908 if (MI.getDesc().isAsCheapAsAMove()) {
909 if (!TII->isTriviallyReMaterializable(&MI, AA))
912 // Estimate register pressure to determine whether to LICM the instruction.
913 // In low register pressure situation, we can be more aggressive about
914 // hoisting. Also, favors hoisting long latency instructions even in
915 // moderately high pressure situation.
916 DenseMap<unsigned, int> Cost;
917 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
918 const MachineOperand &MO = MI.getOperand(i);
919 if (!MO.isReg() || MO.isImplicit())
921 unsigned Reg = MO.getReg();
922 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
925 if (HasHighOperandLatency(MI, i, Reg)) {
930 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
931 EVT VT = *RC->vt_begin();
932 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
933 unsigned RCCost = TLI->getRepRegClassCostFor(VT);
934 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
935 if (CI != Cost.end())
936 CI->second += RCCost;
938 Cost.insert(std::make_pair(RCId, RCCost));
939 } else if (isOperandKill(MO, MRI)) {
940 // Is a virtual register use is a kill, hoisting it out of the loop
941 // may actually reduce register pressure or be register pressure
943 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
944 EVT VT = *RC->vt_begin();
945 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
946 unsigned RCCost = TLI->getRepRegClassCostFor(VT);
947 DenseMap<unsigned, int>::iterator CI = Cost.find(RCId);
948 if (CI != Cost.end())
949 CI->second -= RCCost;
951 Cost.insert(std::make_pair(RCId, -RCCost));
955 // Visit BBs from header to current BB, if hoisting this doesn't cause
956 // high register pressure, then it's safe to proceed.
957 if (!CanCauseHighRegPressure(Cost)) {
962 // High register pressure situation, only hoist if the instruction is going to
964 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
965 !isLoadFromConstantMemory(&MI))
969 // If result(s) of this instruction is used by PHIs, then don't hoist it.
970 // The presence of joins makes it difficult for current register allocator
971 // implementation to perform remat.
972 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
973 const MachineOperand &MO = MI.getOperand(i);
974 if (!MO.isReg() || !MO.isDef())
976 if (HasPHIUses(MO.getReg(), MRI))
983 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
984 // Don't unfold simple loads.
985 if (MI->getDesc().canFoldAsLoad())
988 // If not, we may be able to unfold a load and hoist that.
989 // First test whether the instruction is loading from an amenable
991 if (!isLoadFromConstantMemory(MI))
994 // Next determine the register class for a temporary register.
995 unsigned LoadRegIndex;
997 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
999 /*UnfoldStore=*/false,
1001 if (NewOpc == 0) return 0;
1002 const TargetInstrDesc &TID = TII->get(NewOpc);
1003 if (TID.getNumDefs() != 1) return 0;
1004 const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI);
1005 // Ok, we're unfolding. Create a temporary register and do the unfold.
1006 unsigned Reg = MRI->createVirtualRegister(RC);
1008 MachineFunction &MF = *MI->getParent()->getParent();
1009 SmallVector<MachineInstr *, 2> NewMIs;
1011 TII->unfoldMemoryOperand(MF, MI, Reg,
1012 /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
1016 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1018 assert(NewMIs.size() == 2 &&
1019 "Unfolded a load into multiple instructions!");
1020 MachineBasicBlock *MBB = MI->getParent();
1021 MBB->insert(MI, NewMIs[0]);
1022 MBB->insert(MI, NewMIs[1]);
1023 // If unfolding produced a load that wasn't loop-invariant or profitable to
1024 // hoist, discard the new instructions and bail.
1025 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1026 NewMIs[0]->eraseFromParent();
1027 NewMIs[1]->eraseFromParent();
1031 // Update register pressure for the unfolded instruction.
1032 UpdateRegPressure(NewMIs[1]);
1034 // Otherwise we successfully unfolded a load that we can hoist.
1035 MI->eraseFromParent();
1039 void MachineLICM::InitCSEMap(MachineBasicBlock *BB) {
1040 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) {
1041 const MachineInstr *MI = &*I;
1042 // FIXME: For now, only hoist re-materilizable instructions. LICM will
1043 // increase register pressure. We want to make sure it doesn't increase
1045 if (TII->isTriviallyReMaterializable(MI, AA)) {
1046 unsigned Opcode = MI->getOpcode();
1047 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1048 CI = CSEMap.find(Opcode);
1049 if (CI != CSEMap.end())
1050 CI->second.push_back(MI);
1052 std::vector<const MachineInstr*> CSEMIs;
1053 CSEMIs.push_back(MI);
1054 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1061 MachineLICM::LookForDuplicate(const MachineInstr *MI,
1062 std::vector<const MachineInstr*> &PrevMIs) {
1063 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
1064 const MachineInstr *PrevMI = PrevMIs[i];
1065 if (TII->produceSameValue(MI, PrevMI))
1071 bool MachineLICM::EliminateCSE(MachineInstr *MI,
1072 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
1073 // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate
1074 // the undef property onto uses.
1075 if (CI == CSEMap.end() || MI->isImplicitDef())
1078 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1079 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1081 // Replace virtual registers defined by MI by their counterparts defined
1083 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1084 const MachineOperand &MO = MI->getOperand(i);
1086 // Physical registers may not differ here.
1087 assert((!MO.isReg() || MO.getReg() == 0 ||
1088 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
1089 MO.getReg() == Dup->getOperand(i).getReg()) &&
1090 "Instructions with different phys regs are not identical!");
1092 if (MO.isReg() && MO.isDef() &&
1093 !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
1094 MRI->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
1095 MRI->clearKillFlags(Dup->getOperand(i).getReg());
1098 MI->eraseFromParent();
1105 /// Hoist - When an instruction is found to use only loop invariant operands
1106 /// that are safe to hoist, this instruction is called to do the dirty work.
1108 bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
1109 // First check whether we should hoist this instruction.
1110 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1111 // If not, try unfolding a hoistable load.
1112 MI = ExtractHoistableLoad(MI);
1113 if (!MI) return false;
1116 // Now move the instructions to the predecessor, inserting it before any
1117 // terminator instructions.
1119 dbgs() << "Hoisting " << *MI;
1120 if (Preheader->getBasicBlock())
1121 dbgs() << " to MachineBasicBlock "
1122 << Preheader->getName();
1123 if (MI->getParent()->getBasicBlock())
1124 dbgs() << " from MachineBasicBlock "
1125 << MI->getParent()->getName();
1129 // If this is the first instruction being hoisted to the preheader,
1130 // initialize the CSE map with potential common expressions.
1132 InitCSEMap(Preheader);
1133 FirstInLoop = false;
1136 // Look for opportunity to CSE the hoisted instruction.
1137 unsigned Opcode = MI->getOpcode();
1138 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator
1139 CI = CSEMap.find(Opcode);
1140 if (!EliminateCSE(MI, CI)) {
1141 // Otherwise, splice the instruction to the preheader.
1142 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
1144 // Update register pressure for BBs from header to this block.
1145 UpdateBackTraceRegPressure(MI);
1147 // Clear the kill flags of any register this instruction defines,
1148 // since they may need to be live throughout the entire loop
1149 // rather than just live for part of it.
1150 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1151 MachineOperand &MO = MI->getOperand(i);
1152 if (MO.isReg() && MO.isDef() && !MO.isDead())
1153 MRI->clearKillFlags(MO.getReg());
1156 // Add to the CSE map.
1157 if (CI != CSEMap.end())
1158 CI->second.push_back(MI);
1160 std::vector<const MachineInstr*> CSEMIs;
1161 CSEMIs.push_back(MI);
1162 CSEMap.insert(std::make_pair(Opcode, CSEMIs));
1172 MachineBasicBlock *MachineLICM::getCurPreheader() {
1173 // Determine the block to which to hoist instructions. If we can't find a
1174 // suitable loop predecessor, we can't do any hoisting.
1176 // If we've tried to get a preheader and failed, don't try again.
1177 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1))
1180 if (!CurPreheader) {
1181 CurPreheader = CurLoop->getLoopPreheader();
1182 if (!CurPreheader) {
1183 MachineBasicBlock *Pred = CurLoop->getLoopPredecessor();
1185 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1189 CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), this);
1190 if (!CurPreheader) {
1191 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1);
1196 return CurPreheader;