1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/Metadata.h"
20 #include "llvm/Module.h"
21 #include "llvm/Type.h"
22 #include "llvm/Value.h"
23 #include "llvm/Assembly/Writer.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/Analysis/DebugInfo.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
43 #include "llvm/ADT/Hashing.h"
46 //===----------------------------------------------------------------------===//
47 // MachineOperand Implementation
48 //===----------------------------------------------------------------------===//
50 /// AddRegOperandToRegInfo - Add this register operand to the specified
51 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
52 /// explicitly nulled out.
53 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
54 assert(isReg() && "Can only add reg operand to use lists");
56 // If the reginfo pointer is null, just explicitly null out or next/prev
57 // pointers, to ensure they are not garbage.
59 Contents.Reg.Prev = 0;
60 Contents.Reg.Next = 0;
64 // Otherwise, add this operand to the head of the registers use/def list.
65 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
67 // For SSA values, we prefer to keep the definition at the start of the list.
68 // we do this by skipping over the definition if it is at the head of the
70 if (*Head && (*Head)->isDef())
71 Head = &(*Head)->Contents.Reg.Next;
73 Contents.Reg.Next = *Head;
74 if (Contents.Reg.Next) {
75 assert(getReg() == Contents.Reg.Next->getReg() &&
76 "Different regs on the same list!");
77 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
80 Contents.Reg.Prev = Head;
84 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
85 /// MachineRegisterInfo it is linked with.
86 void MachineOperand::RemoveRegOperandFromRegInfo() {
87 assert(isOnRegUseList() && "Reg operand is not on a use list");
88 // Unlink this from the doubly linked list of operands.
89 MachineOperand *NextOp = Contents.Reg.Next;
90 *Contents.Reg.Prev = NextOp;
92 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
93 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
95 Contents.Reg.Prev = 0;
96 Contents.Reg.Next = 0;
99 void MachineOperand::setReg(unsigned Reg) {
100 if (getReg() == Reg) return; // No change.
102 // Otherwise, we have to change the register. If this operand is embedded
103 // into a machine function, we need to update the old and new register's
105 if (MachineInstr *MI = getParent())
106 if (MachineBasicBlock *MBB = MI->getParent())
107 if (MachineFunction *MF = MBB->getParent()) {
108 RemoveRegOperandFromRegInfo();
109 SmallContents.RegNo = Reg;
110 AddRegOperandToRegInfo(&MF->getRegInfo());
114 // Otherwise, just change the register, no problem. :)
115 SmallContents.RegNo = Reg;
118 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
119 const TargetRegisterInfo &TRI) {
120 assert(TargetRegisterInfo::isVirtualRegister(Reg));
121 if (SubIdx && getSubReg())
122 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
128 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
129 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
131 Reg = TRI.getSubReg(Reg, getSubReg());
132 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
133 // That won't happen in legal code.
139 /// ChangeToImmediate - Replace this operand with a new immediate operand of
140 /// the specified value. If an operand is known to be an immediate already,
141 /// the setImm method should be used.
142 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
143 // If this operand is currently a register operand, and if this is in a
144 // function, deregister the operand from the register's use/def list.
145 if (isReg() && getParent() && getParent()->getParent() &&
146 getParent()->getParent()->getParent())
147 RemoveRegOperandFromRegInfo();
149 OpKind = MO_Immediate;
150 Contents.ImmVal = ImmVal;
153 /// ChangeToRegister - Replace this operand with a new register operand of
154 /// the specified value. If an operand is known to be an register already,
155 /// the setReg method should be used.
156 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
157 bool isKill, bool isDead, bool isUndef,
159 // If this operand is already a register operand, use setReg to update the
160 // register's use/def lists.
162 assert(!isEarlyClobber());
165 // Otherwise, change this to a register and set the reg#.
166 OpKind = MO_Register;
167 SmallContents.RegNo = Reg;
169 // If this operand is embedded in a function, add the operand to the
170 // register's use/def list.
171 if (MachineInstr *MI = getParent())
172 if (MachineBasicBlock *MBB = MI->getParent())
173 if (MachineFunction *MF = MBB->getParent())
174 AddRegOperandToRegInfo(&MF->getRegInfo());
182 IsInternalRead = false;
183 IsEarlyClobber = false;
188 /// isIdenticalTo - Return true if this operand is identical to the specified
190 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
191 if (getType() != Other.getType() ||
192 getTargetFlags() != Other.getTargetFlags())
196 case MachineOperand::MO_Register:
197 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
198 getSubReg() == Other.getSubReg();
199 case MachineOperand::MO_Immediate:
200 return getImm() == Other.getImm();
201 case MachineOperand::MO_CImmediate:
202 return getCImm() == Other.getCImm();
203 case MachineOperand::MO_FPImmediate:
204 return getFPImm() == Other.getFPImm();
205 case MachineOperand::MO_MachineBasicBlock:
206 return getMBB() == Other.getMBB();
207 case MachineOperand::MO_FrameIndex:
208 return getIndex() == Other.getIndex();
209 case MachineOperand::MO_ConstantPoolIndex:
210 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
211 case MachineOperand::MO_JumpTableIndex:
212 return getIndex() == Other.getIndex();
213 case MachineOperand::MO_GlobalAddress:
214 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
215 case MachineOperand::MO_ExternalSymbol:
216 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
217 getOffset() == Other.getOffset();
218 case MachineOperand::MO_BlockAddress:
219 return getBlockAddress() == Other.getBlockAddress();
220 case MO_RegisterMask:
221 return getRegMask() == Other.getRegMask();
222 case MachineOperand::MO_MCSymbol:
223 return getMCSymbol() == Other.getMCSymbol();
224 case MachineOperand::MO_Metadata:
225 return getMetadata() == Other.getMetadata();
227 llvm_unreachable("Invalid machine operand type");
230 /// print - Print the specified machine operand.
232 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
233 // If the instruction is embedded into a basic block, we can find the
234 // target info for the instruction.
236 if (const MachineInstr *MI = getParent())
237 if (const MachineBasicBlock *MBB = MI->getParent())
238 if (const MachineFunction *MF = MBB->getParent())
239 TM = &MF->getTarget();
240 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
243 case MachineOperand::MO_Register:
244 OS << PrintReg(getReg(), TRI, getSubReg());
246 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
247 isInternalRead() || isEarlyClobber()) {
249 bool NeedComma = false;
251 if (NeedComma) OS << ',';
252 if (isEarlyClobber())
253 OS << "earlyclobber,";
258 } else if (isImplicit()) {
263 if (isKill() || isDead() || isUndef() || isInternalRead()) {
264 if (NeedComma) OS << ',';
275 if (NeedComma) OS << ',';
279 if (isInternalRead()) {
280 if (NeedComma) OS << ',';
288 case MachineOperand::MO_Immediate:
291 case MachineOperand::MO_CImmediate:
292 getCImm()->getValue().print(OS, false);
294 case MachineOperand::MO_FPImmediate:
295 if (getFPImm()->getType()->isFloatTy())
296 OS << getFPImm()->getValueAPF().convertToFloat();
298 OS << getFPImm()->getValueAPF().convertToDouble();
300 case MachineOperand::MO_MachineBasicBlock:
301 OS << "<BB#" << getMBB()->getNumber() << ">";
303 case MachineOperand::MO_FrameIndex:
304 OS << "<fi#" << getIndex() << '>';
306 case MachineOperand::MO_ConstantPoolIndex:
307 OS << "<cp#" << getIndex();
308 if (getOffset()) OS << "+" << getOffset();
311 case MachineOperand::MO_JumpTableIndex:
312 OS << "<jt#" << getIndex() << '>';
314 case MachineOperand::MO_GlobalAddress:
316 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
317 if (getOffset()) OS << "+" << getOffset();
320 case MachineOperand::MO_ExternalSymbol:
321 OS << "<es:" << getSymbolName();
322 if (getOffset()) OS << "+" << getOffset();
325 case MachineOperand::MO_BlockAddress:
327 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
330 case MachineOperand::MO_RegisterMask:
333 case MachineOperand::MO_Metadata:
335 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
338 case MachineOperand::MO_MCSymbol:
339 OS << "<MCSym=" << *getMCSymbol() << '>';
343 if (unsigned TF = getTargetFlags())
344 OS << "[TF=" << TF << ']';
347 //===----------------------------------------------------------------------===//
348 // MachineMemOperand Implementation
349 //===----------------------------------------------------------------------===//
351 /// getAddrSpace - Return the LLVM IR address space number that this pointer
353 unsigned MachinePointerInfo::getAddrSpace() const {
354 if (V == 0) return 0;
355 return cast<PointerType>(V->getType())->getAddressSpace();
358 /// getConstantPool - Return a MachinePointerInfo record that refers to the
360 MachinePointerInfo MachinePointerInfo::getConstantPool() {
361 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
364 /// getFixedStack - Return a MachinePointerInfo record that refers to the
365 /// the specified FrameIndex.
366 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
367 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
370 MachinePointerInfo MachinePointerInfo::getJumpTable() {
371 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
374 MachinePointerInfo MachinePointerInfo::getGOT() {
375 return MachinePointerInfo(PseudoSourceValue::getGOT());
378 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
379 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
382 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
383 uint64_t s, unsigned int a,
384 const MDNode *TBAAInfo)
385 : PtrInfo(ptrinfo), Size(s),
386 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
388 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
389 "invalid pointer value");
390 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
391 assert((isLoad() || isStore()) && "Not a load/store!");
394 /// Profile - Gather unique data for the object.
396 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
397 ID.AddInteger(getOffset());
399 ID.AddPointer(getValue());
400 ID.AddInteger(Flags);
403 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
404 // The Value and Offset may differ due to CSE. But the flags and size
405 // should be the same.
406 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
407 assert(MMO->getSize() == getSize() && "Size mismatch!");
409 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
410 // Update the alignment value.
411 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
412 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
413 // Also update the base and offset, because the new alignment may
414 // not be applicable with the old ones.
415 PtrInfo = MMO->PtrInfo;
419 /// getAlignment - Return the minimum known alignment in bytes of the
420 /// actual memory reference.
421 uint64_t MachineMemOperand::getAlignment() const {
422 return MinAlign(getBaseAlignment(), getOffset());
425 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
426 assert((MMO.isLoad() || MMO.isStore()) &&
427 "SV has to be a load, store or both.");
429 if (MMO.isVolatile())
438 // Print the address information.
443 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
445 // If the alignment of the memory reference itself differs from the alignment
446 // of the base pointer, print the base alignment explicitly, next to the base
448 if (MMO.getBaseAlignment() != MMO.getAlignment())
449 OS << "(align=" << MMO.getBaseAlignment() << ")";
451 if (MMO.getOffset() != 0)
452 OS << "+" << MMO.getOffset();
455 // Print the alignment of the reference.
456 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
457 MMO.getBaseAlignment() != MMO.getSize())
458 OS << "(align=" << MMO.getAlignment() << ")";
461 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
463 if (TBAAInfo->getNumOperands() > 0)
464 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
470 // Print nontemporal info.
471 if (MMO.isNonTemporal())
472 OS << "(nontemporal)";
477 //===----------------------------------------------------------------------===//
478 // MachineInstr Implementation
479 //===----------------------------------------------------------------------===//
481 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
482 /// MCID NULL and no operands.
483 MachineInstr::MachineInstr()
484 : MCID(0), Flags(0), AsmPrinterFlags(0),
485 NumMemRefs(0), MemRefs(0),
487 // Make sure that we get added to a machine basicblock
488 LeakDetector::addGarbageObject(this);
491 void MachineInstr::addImplicitDefUseOperands() {
492 if (MCID->ImplicitDefs)
493 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
494 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
495 if (MCID->ImplicitUses)
496 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
497 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
500 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
501 /// implicit operands. It reserves space for the number of operands specified by
503 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
504 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
505 NumMemRefs(0), MemRefs(0), Parent(0) {
506 unsigned NumImplicitOps = 0;
508 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
509 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
511 addImplicitDefUseOperands();
512 // Make sure that we get added to a machine basicblock
513 LeakDetector::addGarbageObject(this);
516 /// MachineInstr ctor - As above, but with a DebugLoc.
517 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
519 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
520 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
521 unsigned NumImplicitOps = 0;
523 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
524 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
526 addImplicitDefUseOperands();
527 // Make sure that we get added to a machine basicblock
528 LeakDetector::addGarbageObject(this);
531 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
532 /// that the MachineInstr is created and added to the end of the specified
534 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
535 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
536 NumMemRefs(0), MemRefs(0), Parent(0) {
537 assert(MBB && "Cannot use inserting ctor with null basic block!");
538 unsigned NumImplicitOps =
539 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
540 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
541 addImplicitDefUseOperands();
542 // Make sure that we get added to a machine basicblock
543 LeakDetector::addGarbageObject(this);
544 MBB->push_back(this); // Add instruction to end of basic block!
547 /// MachineInstr ctor - As above, but with a DebugLoc.
549 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
550 const MCInstrDesc &tid)
551 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
552 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
553 assert(MBB && "Cannot use inserting ctor with null basic block!");
554 unsigned NumImplicitOps =
555 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
556 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
557 addImplicitDefUseOperands();
558 // Make sure that we get added to a machine basicblock
559 LeakDetector::addGarbageObject(this);
560 MBB->push_back(this); // Add instruction to end of basic block!
563 /// MachineInstr ctor - Copies MachineInstr arg exactly
565 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
566 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
567 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
568 Parent(0), debugLoc(MI.getDebugLoc()) {
569 Operands.reserve(MI.getNumOperands());
572 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
573 addOperand(MI.getOperand(i));
575 // Copy all the flags.
578 // Set parent to null.
581 LeakDetector::addGarbageObject(this);
584 MachineInstr::~MachineInstr() {
585 LeakDetector::removeGarbageObject(this);
587 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
588 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
589 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
590 "Reg operand def/use list corrupted");
595 /// getRegInfo - If this instruction is embedded into a MachineFunction,
596 /// return the MachineRegisterInfo object for the current function, otherwise
598 MachineRegisterInfo *MachineInstr::getRegInfo() {
599 if (MachineBasicBlock *MBB = getParent())
600 return &MBB->getParent()->getRegInfo();
604 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
605 /// this instruction from their respective use lists. This requires that the
606 /// operands already be on their use lists.
607 void MachineInstr::RemoveRegOperandsFromUseLists() {
608 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
609 if (Operands[i].isReg())
610 Operands[i].RemoveRegOperandFromRegInfo();
614 /// AddRegOperandsToUseLists - Add all of the register operands in
615 /// this instruction from their respective use lists. This requires that the
616 /// operands not be on their use lists yet.
617 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
618 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
619 if (Operands[i].isReg())
620 Operands[i].AddRegOperandToRegInfo(&RegInfo);
625 /// addOperand - Add the specified operand to the instruction. If it is an
626 /// implicit operand, it is added to the end of the operand list. If it is
627 /// an explicit operand it is added at the end of the explicit operand list
628 /// (before the first implicit operand).
629 void MachineInstr::addOperand(const MachineOperand &Op) {
630 assert(MCID && "Cannot add operands before providing an instr descriptor");
631 bool isImpReg = Op.isReg() && Op.isImplicit();
632 MachineRegisterInfo *RegInfo = getRegInfo();
634 // If the Operands backing store is reallocated, all register operands must
635 // be removed and re-added to RegInfo. It is storing pointers to operands.
636 bool Reallocate = RegInfo &&
637 !Operands.empty() && Operands.size() == Operands.capacity();
639 // Find the insert location for the new operand. Implicit registers go at
640 // the end, everything goes before the implicit regs.
641 unsigned OpNo = Operands.size();
643 // Remove all the implicit operands from RegInfo if they need to be shifted.
644 // FIXME: Allow mixed explicit and implicit operands on inline asm.
645 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
646 // implicit-defs, but they must not be moved around. See the FIXME in
648 if (!isImpReg && !isInlineAsm()) {
649 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
652 Operands[OpNo].RemoveRegOperandFromRegInfo();
656 // OpNo now points as the desired insertion point. Unless this is a variadic
657 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
658 assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
659 "Trying to add an operand to a machine instr that is already done!");
661 // All operands from OpNo have been removed from RegInfo. If the Operands
662 // backing store needs to be reallocated, we also need to remove any other
663 // register operands.
665 for (unsigned i = 0; i != OpNo; ++i)
666 if (Operands[i].isReg())
667 Operands[i].RemoveRegOperandFromRegInfo();
669 // Insert the new operand at OpNo.
670 Operands.insert(Operands.begin() + OpNo, Op);
671 Operands[OpNo].ParentMI = this;
673 // The Operands backing store has now been reallocated, so we can re-add the
674 // operands before OpNo.
676 for (unsigned i = 0; i != OpNo; ++i)
677 if (Operands[i].isReg())
678 Operands[i].AddRegOperandToRegInfo(RegInfo);
680 // When adding a register operand, tell RegInfo about it.
681 if (Operands[OpNo].isReg()) {
682 // Add the new operand to RegInfo, even when RegInfo is NULL.
683 // This will initialize the linked list pointers.
684 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
685 // If the register operand is flagged as early, mark the operand as such.
686 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
687 Operands[OpNo].setIsEarlyClobber(true);
690 // Re-add all the implicit ops.
692 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
693 assert(Operands[i].isReg() && "Should only be an implicit reg!");
694 Operands[i].AddRegOperandToRegInfo(RegInfo);
699 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
700 /// fewer operand than it started with.
702 void MachineInstr::RemoveOperand(unsigned OpNo) {
703 assert(OpNo < Operands.size() && "Invalid operand number");
705 // Special case removing the last one.
706 if (OpNo == Operands.size()-1) {
707 // If needed, remove from the reg def/use list.
708 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
709 Operands.back().RemoveRegOperandFromRegInfo();
715 // Otherwise, we are removing an interior operand. If we have reginfo to
716 // update, remove all operands that will be shifted down from their reg lists,
717 // move everything down, then re-add them.
718 MachineRegisterInfo *RegInfo = getRegInfo();
720 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
721 if (Operands[i].isReg())
722 Operands[i].RemoveRegOperandFromRegInfo();
726 Operands.erase(Operands.begin()+OpNo);
729 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
730 if (Operands[i].isReg())
731 Operands[i].AddRegOperandToRegInfo(RegInfo);
736 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
737 /// This function should be used only occasionally. The setMemRefs function
738 /// is the primary method for setting up a MachineInstr's MemRefs list.
739 void MachineInstr::addMemOperand(MachineFunction &MF,
740 MachineMemOperand *MO) {
741 mmo_iterator OldMemRefs = MemRefs;
742 uint16_t OldNumMemRefs = NumMemRefs;
744 uint16_t NewNum = NumMemRefs + 1;
745 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
747 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
748 NewMemRefs[NewNum - 1] = MO;
750 MemRefs = NewMemRefs;
755 MachineInstr::hasProperty(unsigned MCFlag, QueryType Type) const {
756 if (Type == IgnoreBundle || !isBundle())
757 return getDesc().getFlags() & (1 << MCFlag);
759 const MachineBasicBlock *MBB = getParent();
760 MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
761 while (MII != MBB->end() && MII->isInsideBundle()) {
762 if (MII->getDesc().getFlags() & (1 << MCFlag)) {
763 if (Type == AnyInBundle)
766 if (Type == AllInBundle)
772 return Type == AllInBundle;
775 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
776 MICheckType Check) const {
777 // If opcodes or number of operands are not the same then the two
778 // instructions are obviously not identical.
779 if (Other->getOpcode() != getOpcode() ||
780 Other->getNumOperands() != getNumOperands())
784 // Both instructions are bundles, compare MIs inside the bundle.
785 MachineBasicBlock::const_instr_iterator I1 = *this;
786 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
787 MachineBasicBlock::const_instr_iterator I2 = *Other;
788 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
789 while (++I1 != E1 && I1->isInsideBundle()) {
791 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
796 // Check operands to make sure they match.
797 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
798 const MachineOperand &MO = getOperand(i);
799 const MachineOperand &OMO = Other->getOperand(i);
801 if (!MO.isIdenticalTo(OMO))
806 // Clients may or may not want to ignore defs when testing for equality.
807 // For example, machine CSE pass only cares about finding common
808 // subexpressions, so it's safe to ignore virtual register defs.
810 if (Check == IgnoreDefs)
812 else if (Check == IgnoreVRegDefs) {
813 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
814 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
815 if (MO.getReg() != OMO.getReg())
818 if (!MO.isIdenticalTo(OMO))
820 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
824 if (!MO.isIdenticalTo(OMO))
826 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
830 // If DebugLoc does not match then two dbg.values are not identical.
832 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
833 && getDebugLoc() != Other->getDebugLoc())
838 /// removeFromParent - This method unlinks 'this' from the containing basic
839 /// block, and returns it, but does not delete it.
840 MachineInstr *MachineInstr::removeFromParent() {
841 assert(getParent() && "Not embedded in a basic block!");
843 // If it's a bundle then remove the MIs inside the bundle as well.
845 MachineBasicBlock *MBB = getParent();
846 MachineBasicBlock::instr_iterator MII = *this; ++MII;
847 MachineBasicBlock::instr_iterator E = MBB->instr_end();
848 while (MII != E && MII->isInsideBundle()) {
849 MachineInstr *MI = &*MII;
854 getParent()->remove(this);
859 /// eraseFromParent - This method unlinks 'this' from the containing basic
860 /// block, and deletes it.
861 void MachineInstr::eraseFromParent() {
862 assert(getParent() && "Not embedded in a basic block!");
863 // If it's a bundle then remove the MIs inside the bundle as well.
865 MachineBasicBlock *MBB = getParent();
866 MachineBasicBlock::instr_iterator MII = *this; ++MII;
867 MachineBasicBlock::instr_iterator E = MBB->instr_end();
868 while (MII != E && MII->isInsideBundle()) {
869 MachineInstr *MI = &*MII;
874 getParent()->erase(this);
878 /// getNumExplicitOperands - Returns the number of non-implicit operands.
880 unsigned MachineInstr::getNumExplicitOperands() const {
881 unsigned NumOperands = MCID->getNumOperands();
882 if (!MCID->isVariadic())
885 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
886 const MachineOperand &MO = getOperand(i);
887 if (!MO.isReg() || !MO.isImplicit())
893 /// isBundled - Return true if this instruction part of a bundle. This is true
894 /// if either itself or its following instruction is marked "InsideBundle".
895 bool MachineInstr::isBundled() const {
896 if (isInsideBundle())
898 MachineBasicBlock::const_instr_iterator nextMI = this;
900 return nextMI != Parent->instr_end() && nextMI->isInsideBundle();
903 bool MachineInstr::isStackAligningInlineAsm() const {
905 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
906 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
912 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
913 unsigned *GroupNo) const {
914 assert(isInlineAsm() && "Expected an inline asm instruction");
915 assert(OpIdx < getNumOperands() && "OpIdx out of range");
917 // Ignore queries about the initial operands.
918 if (OpIdx < InlineAsm::MIOp_FirstOperand)
923 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
925 const MachineOperand &FlagMO = getOperand(i);
926 // If we reach the implicit register operands, stop looking.
929 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
930 if (i + NumOps > OpIdx) {
940 const TargetRegisterClass*
941 MachineInstr::getRegClassConstraint(unsigned OpIdx,
942 const TargetInstrInfo *TII,
943 const TargetRegisterInfo *TRI) const {
944 // Most opcodes have fixed constraints in their MCInstrDesc.
946 return TII->getRegClass(getDesc(), OpIdx, TRI);
948 if (!getOperand(OpIdx).isReg())
951 // For tied uses on inline asm, get the constraint from the def.
953 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
956 // Inline asm stores register class constraints in the flag word.
957 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
961 unsigned Flag = getOperand(FlagIdx).getImm();
963 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
964 return TRI->getRegClass(RCID);
966 // Assume that all registers in a memory operand are pointers.
967 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
968 return TRI->getPointerRegClass();
973 /// getBundleSize - Return the number of instructions inside the MI bundle.
974 unsigned MachineInstr::getBundleSize() const {
975 assert(isBundle() && "Expecting a bundle");
977 MachineBasicBlock::const_instr_iterator I = *this;
979 while ((++I)->isInsideBundle()) {
982 assert(Size > 1 && "Malformed bundle");
987 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
988 /// the specific register or -1 if it is not found. It further tightens
989 /// the search criteria to a use that kills the register if isKill is true.
990 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
991 const TargetRegisterInfo *TRI) const {
992 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
993 const MachineOperand &MO = getOperand(i);
994 if (!MO.isReg() || !MO.isUse())
996 unsigned MOReg = MO.getReg();
1001 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1002 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1003 TRI->isSubRegister(MOReg, Reg)))
1004 if (!isKill || MO.isKill())
1010 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1011 /// indicating if this instruction reads or writes Reg. This also considers
1012 /// partial defines.
1013 std::pair<bool,bool>
1014 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1015 SmallVectorImpl<unsigned> *Ops) const {
1016 bool PartDef = false; // Partial redefine.
1017 bool FullDef = false; // Full define.
1020 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1021 const MachineOperand &MO = getOperand(i);
1022 if (!MO.isReg() || MO.getReg() != Reg)
1027 Use |= !MO.isUndef();
1028 else if (MO.getSubReg() && !MO.isUndef())
1029 // A partial <def,undef> doesn't count as reading the register.
1034 // A partial redefine uses Reg unless there is also a full define.
1035 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1038 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1039 /// the specified register or -1 if it is not found. If isDead is true, defs
1040 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1041 /// also checks if there is a def of a super-register.
1043 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1044 const TargetRegisterInfo *TRI) const {
1045 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1046 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1047 const MachineOperand &MO = getOperand(i);
1048 // Accept regmask operands when Overlap is set.
1049 // Ignore them when looking for a specific def operand (Overlap == false).
1050 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1052 if (!MO.isReg() || !MO.isDef())
1054 unsigned MOReg = MO.getReg();
1055 bool Found = (MOReg == Reg);
1056 if (!Found && TRI && isPhys &&
1057 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1059 Found = TRI->regsOverlap(MOReg, Reg);
1061 Found = TRI->isSubRegister(MOReg, Reg);
1063 if (Found && (!isDead || MO.isDead()))
1069 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1070 /// operand list that is used to represent the predicate. It returns -1 if
1072 int MachineInstr::findFirstPredOperandIdx() const {
1073 // Don't call MCID.findFirstPredOperandIdx() because this variant
1074 // is sometimes called on an instruction that's not yet complete, and
1075 // so the number of operands is less than the MCID indicates. In
1076 // particular, the PTX target does this.
1077 const MCInstrDesc &MCID = getDesc();
1078 if (MCID.isPredicable()) {
1079 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1080 if (MCID.OpInfo[i].isPredicate())
1087 /// isRegTiedToUseOperand - Given the index of a register def operand,
1088 /// check if the register def is tied to a source operand, due to either
1089 /// two-address elimination or inline assembly constraints. Returns the
1090 /// first tied use operand index by reference is UseOpIdx is not null.
1092 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1093 if (isInlineAsm()) {
1094 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1095 const MachineOperand &MO = getOperand(DefOpIdx);
1096 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1098 // Determine the actual operand index that corresponds to this index.
1100 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1104 // Which part of the group is DefOpIdx?
1105 unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1107 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1109 const MachineOperand &FMO = getOperand(i);
1112 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1115 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1118 *UseOpIdx = (unsigned)i + 1 + DefPart;
1125 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1126 const MCInstrDesc &MCID = getDesc();
1127 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1128 const MachineOperand &MO = getOperand(i);
1129 if (MO.isReg() && MO.isUse() &&
1130 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1132 *UseOpIdx = (unsigned)i;
1139 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1140 /// is a register use and it is tied to an def operand. It also returns the def
1141 /// operand index by reference.
1143 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1144 if (isInlineAsm()) {
1145 const MachineOperand &MO = getOperand(UseOpIdx);
1146 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1149 // Find the flag operand corresponding to UseOpIdx
1150 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1154 const MachineOperand &UFMO = getOperand(FlagIdx);
1156 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1160 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1161 // Remember to adjust the index. First operand is asm string, second is
1162 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1164 const MachineOperand &FMO = getOperand(DefIdx);
1165 assert(FMO.isImm());
1166 // Skip over this def.
1167 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1170 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1176 const MCInstrDesc &MCID = getDesc();
1177 if (UseOpIdx >= MCID.getNumOperands())
1179 const MachineOperand &MO = getOperand(UseOpIdx);
1180 if (!MO.isReg() || !MO.isUse())
1182 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1186 *DefOpIdx = (unsigned)DefIdx;
1190 /// clearKillInfo - Clears kill flags on all operands.
1192 void MachineInstr::clearKillInfo() {
1193 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1194 MachineOperand &MO = getOperand(i);
1195 if (MO.isReg() && MO.isUse())
1196 MO.setIsKill(false);
1200 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1202 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1203 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1204 const MachineOperand &MO = MI->getOperand(i);
1205 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1207 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1208 MachineOperand &MOp = getOperand(j);
1209 if (!MOp.isIdenticalTo(MO))
1220 /// copyPredicates - Copies predicate operand(s) from MI.
1221 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1222 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1224 const MCInstrDesc &MCID = MI->getDesc();
1225 if (!MCID.isPredicable())
1227 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1228 if (MCID.OpInfo[i].isPredicate()) {
1229 // Predicated operands must be last operands.
1230 addOperand(MI->getOperand(i));
1235 void MachineInstr::substituteRegister(unsigned FromReg,
1238 const TargetRegisterInfo &RegInfo) {
1239 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1241 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1242 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1243 MachineOperand &MO = getOperand(i);
1244 if (!MO.isReg() || MO.getReg() != FromReg)
1246 MO.substPhysReg(ToReg, RegInfo);
1249 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1250 MachineOperand &MO = getOperand(i);
1251 if (!MO.isReg() || MO.getReg() != FromReg)
1253 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1258 /// isSafeToMove - Return true if it is safe to move this instruction. If
1259 /// SawStore is set to true, it means that there is a store (or call) between
1260 /// the instruction's location and its intended destination.
1261 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1263 bool &SawStore) const {
1264 // Ignore stuff that we obviously can't move.
1265 if (mayStore() || isCall()) {
1270 if (isLabel() || isDebugValue() ||
1271 isTerminator() || hasUnmodeledSideEffects())
1274 // See if this instruction does a load. If so, we have to guarantee that the
1275 // loaded value doesn't change between the load and the its intended
1276 // destination. The check for isInvariantLoad gives the targe the chance to
1277 // classify the load as always returning a constant, e.g. a constant pool
1279 if (mayLoad() && !isInvariantLoad(AA))
1280 // Otherwise, this is a real load. If there is a store between the load and
1281 // end of block, or if the load is volatile, we can't move it.
1282 return !SawStore && !hasVolatileMemoryRef();
1287 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1288 /// instruction which defined the specified register instead of copying it.
1289 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1291 unsigned DstReg) const {
1292 bool SawStore = false;
1293 if (!TII->isTriviallyReMaterializable(this, AA) ||
1294 !isSafeToMove(TII, AA, SawStore))
1296 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1297 const MachineOperand &MO = getOperand(i);
1300 // FIXME: For now, do not remat any instruction with register operands.
1301 // Later on, we can loosen the restriction is the register operands have
1302 // not been modified between the def and use. Note, this is different from
1303 // MachineSink because the code is no longer in two-address form (at least
1307 else if (!MO.isDead() && MO.getReg() != DstReg)
1313 /// hasVolatileMemoryRef - Return true if this instruction may have a
1314 /// volatile memory reference, or if the information describing the
1315 /// memory reference is not available. Return false if it is known to
1316 /// have no volatile memory references.
1317 bool MachineInstr::hasVolatileMemoryRef() const {
1318 // An instruction known never to access memory won't have a volatile access.
1322 !hasUnmodeledSideEffects())
1325 // Otherwise, if the instruction has no memory reference information,
1326 // conservatively assume it wasn't preserved.
1327 if (memoperands_empty())
1330 // Check the memory reference information for volatile references.
1331 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1332 if ((*I)->isVolatile())
1338 /// isInvariantLoad - Return true if this instruction is loading from a
1339 /// location whose value is invariant across the function. For example,
1340 /// loading a value from the constant pool or from the argument area
1341 /// of a function if it does not change. This should only return true of
1342 /// *all* loads the instruction does are invariant (if it does multiple loads).
1343 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1344 // If the instruction doesn't load at all, it isn't an invariant load.
1348 // If the instruction has lost its memoperands, conservatively assume that
1349 // it may not be an invariant load.
1350 if (memoperands_empty())
1353 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1355 for (mmo_iterator I = memoperands_begin(),
1356 E = memoperands_end(); I != E; ++I) {
1357 if ((*I)->isVolatile()) return false;
1358 if ((*I)->isStore()) return false;
1359 if ((*I)->isInvariant()) return true;
1361 if (const Value *V = (*I)->getValue()) {
1362 // A load from a constant PseudoSourceValue is invariant.
1363 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1364 if (PSV->isConstant(MFI))
1366 // If we have an AliasAnalysis, ask it whether the memory is constant.
1367 if (AA && AA->pointsToConstantMemory(
1368 AliasAnalysis::Location(V, (*I)->getSize(),
1369 (*I)->getTBAAInfo())))
1373 // Otherwise assume conservatively.
1377 // Everything checks out.
1381 /// isConstantValuePHI - If the specified instruction is a PHI that always
1382 /// merges together the same virtual register, return the register, otherwise
1384 unsigned MachineInstr::isConstantValuePHI() const {
1387 assert(getNumOperands() >= 3 &&
1388 "It's illegal to have a PHI without source operands");
1390 unsigned Reg = getOperand(1).getReg();
1391 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1392 if (getOperand(i).getReg() != Reg)
1397 bool MachineInstr::hasUnmodeledSideEffects() const {
1398 if (hasProperty(MCID::UnmodeledSideEffects))
1400 if (isInlineAsm()) {
1401 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1402 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1409 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1411 bool MachineInstr::allDefsAreDead() const {
1412 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1413 const MachineOperand &MO = getOperand(i);
1414 if (!MO.isReg() || MO.isUse())
1422 /// copyImplicitOps - Copy implicit register operands from specified
1423 /// instruction to this instruction.
1424 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1425 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1427 const MachineOperand &MO = MI->getOperand(i);
1428 if (MO.isReg() && MO.isImplicit())
1433 void MachineInstr::dump() const {
1434 dbgs() << " " << *this;
1437 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1438 raw_ostream &CommentOS) {
1439 const LLVMContext &Ctx = MF->getFunction()->getContext();
1440 if (!DL.isUnknown()) { // Print source line info.
1441 DIScope Scope(DL.getScope(Ctx));
1442 // Omit the directory, because it's likely to be long and uninteresting.
1444 CommentOS << Scope.getFilename();
1446 CommentOS << "<unknown>";
1447 CommentOS << ':' << DL.getLine();
1448 if (DL.getCol() != 0)
1449 CommentOS << ':' << DL.getCol();
1450 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1451 if (!InlinedAtDL.isUnknown()) {
1452 CommentOS << " @[ ";
1453 printDebugLoc(InlinedAtDL, MF, CommentOS);
1459 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1460 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1461 const MachineFunction *MF = 0;
1462 const MachineRegisterInfo *MRI = 0;
1463 if (const MachineBasicBlock *MBB = getParent()) {
1464 MF = MBB->getParent();
1466 TM = &MF->getTarget();
1468 MRI = &MF->getRegInfo();
1471 // Save a list of virtual registers.
1472 SmallVector<unsigned, 8> VirtRegs;
1474 // Print explicitly defined operands on the left of an assignment syntax.
1475 unsigned StartOp = 0, e = getNumOperands();
1476 for (; StartOp < e && getOperand(StartOp).isReg() &&
1477 getOperand(StartOp).isDef() &&
1478 !getOperand(StartOp).isImplicit();
1480 if (StartOp != 0) OS << ", ";
1481 getOperand(StartOp).print(OS, TM);
1482 unsigned Reg = getOperand(StartOp).getReg();
1483 if (TargetRegisterInfo::isVirtualRegister(Reg))
1484 VirtRegs.push_back(Reg);
1490 // Print the opcode name.
1491 if (TM && TM->getInstrInfo())
1492 OS << TM->getInstrInfo()->getName(getOpcode());
1496 // Print the rest of the operands.
1497 bool OmittedAnyCallClobbers = false;
1498 bool FirstOp = true;
1499 unsigned AsmDescOp = ~0u;
1500 unsigned AsmOpCount = 0;
1502 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1503 // Print asm string.
1505 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1507 // Print HasSideEffects, IsAlignStack
1508 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1509 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1510 OS << " [sideeffect]";
1511 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1512 OS << " [alignstack]";
1514 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1519 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1520 const MachineOperand &MO = getOperand(i);
1522 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1523 VirtRegs.push_back(MO.getReg());
1525 // Omit call-clobbered registers which aren't used anywhere. This makes
1526 // call instructions much less noisy on targets where calls clobber lots
1527 // of registers. Don't rely on MO.isDead() because we may be called before
1528 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1529 if (MF && isCall() &&
1530 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1531 unsigned Reg = MO.getReg();
1532 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1533 const MachineRegisterInfo &MRI = MF->getRegInfo();
1534 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1535 bool HasAliasLive = false;
1536 for (const uint16_t *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1537 unsigned AliasReg = *Alias; ++Alias)
1538 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1539 HasAliasLive = true;
1542 if (!HasAliasLive) {
1543 OmittedAnyCallClobbers = true;
1550 if (FirstOp) FirstOp = false; else OS << ",";
1552 if (i < getDesc().NumOperands) {
1553 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1554 if (MCOI.isPredicate())
1556 if (MCOI.isOptionalDef())
1559 if (isDebugValue() && MO.isMetadata()) {
1560 // Pretty print DBG_VALUE instructions.
1561 const MDNode *MD = MO.getMetadata();
1562 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1563 OS << "!\"" << MDS->getString() << '\"';
1566 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1567 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1568 } else if (i == AsmDescOp && MO.isImm()) {
1569 // Pretty print the inline asm operand descriptor.
1570 OS << '$' << AsmOpCount++;
1571 unsigned Flag = MO.getImm();
1572 switch (InlineAsm::getKind(Flag)) {
1573 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1574 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1575 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1576 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1577 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1578 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1579 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1583 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1585 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1587 OS << ":RC" << RCID;
1590 unsigned TiedTo = 0;
1591 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1592 OS << " tiedto:$" << TiedTo;
1596 // Compute the index of the next operand descriptor.
1597 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1602 // Briefly indicate whether any call clobbers were omitted.
1603 if (OmittedAnyCallClobbers) {
1604 if (!FirstOp) OS << ",";
1608 bool HaveSemi = false;
1610 if (!HaveSemi) OS << ";"; HaveSemi = true;
1613 if (Flags & FrameSetup)
1617 if (!memoperands_empty()) {
1618 if (!HaveSemi) OS << ";"; HaveSemi = true;
1621 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1624 if (llvm::next(i) != e)
1629 // Print the regclass of any virtual registers encountered.
1630 if (MRI && !VirtRegs.empty()) {
1631 if (!HaveSemi) OS << ";"; HaveSemi = true;
1632 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1633 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1634 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1635 for (unsigned j = i+1; j != VirtRegs.size();) {
1636 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1640 if (VirtRegs[i] != VirtRegs[j])
1641 OS << "," << PrintReg(VirtRegs[j]);
1642 VirtRegs.erase(VirtRegs.begin()+j);
1647 // Print debug location information.
1648 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1649 if (!HaveSemi) OS << ";"; HaveSemi = true;
1650 DIVariable DV(getOperand(e - 1).getMetadata());
1651 OS << " line no:" << DV.getLineNumber();
1652 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1653 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1654 if (!InlinedAtDL.isUnknown()) {
1655 OS << " inlined @[ ";
1656 printDebugLoc(InlinedAtDL, MF, OS);
1660 } else if (!debugLoc.isUnknown() && MF) {
1661 if (!HaveSemi) OS << ";"; HaveSemi = true;
1663 printDebugLoc(debugLoc, MF, OS);
1669 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1670 const TargetRegisterInfo *RegInfo,
1671 bool AddIfNotFound) {
1672 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1673 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1675 SmallVector<unsigned,4> DeadOps;
1676 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1677 MachineOperand &MO = getOperand(i);
1678 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1680 unsigned Reg = MO.getReg();
1684 if (Reg == IncomingReg) {
1687 // The register is already marked kill.
1689 if (isPhysReg && isRegTiedToDefOperand(i))
1690 // Two-address uses of physregs must not be marked kill.
1695 } else if (hasAliases && MO.isKill() &&
1696 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1697 // A super-register kill already exists.
1698 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1700 if (RegInfo->isSubRegister(IncomingReg, Reg))
1701 DeadOps.push_back(i);
1705 // Trim unneeded kill operands.
1706 while (!DeadOps.empty()) {
1707 unsigned OpIdx = DeadOps.back();
1708 if (getOperand(OpIdx).isImplicit())
1709 RemoveOperand(OpIdx);
1711 getOperand(OpIdx).setIsKill(false);
1715 // If not found, this means an alias of one of the operands is killed. Add a
1716 // new implicit operand if required.
1717 if (!Found && AddIfNotFound) {
1718 addOperand(MachineOperand::CreateReg(IncomingReg,
1727 void MachineInstr::clearRegisterKills(unsigned Reg,
1728 const TargetRegisterInfo *RegInfo) {
1729 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1731 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1732 MachineOperand &MO = getOperand(i);
1733 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1735 unsigned OpReg = MO.getReg();
1736 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1737 MO.setIsKill(false);
1741 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1742 const TargetRegisterInfo *RegInfo,
1743 bool AddIfNotFound) {
1744 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1745 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1747 SmallVector<unsigned,4> DeadOps;
1748 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1749 MachineOperand &MO = getOperand(i);
1750 if (!MO.isReg() || !MO.isDef())
1752 unsigned Reg = MO.getReg();
1756 if (Reg == IncomingReg) {
1759 } else if (hasAliases && MO.isDead() &&
1760 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1761 // There exists a super-register that's marked dead.
1762 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1764 if (RegInfo->getSubRegisters(IncomingReg) &&
1765 RegInfo->getSuperRegisters(Reg) &&
1766 RegInfo->isSubRegister(IncomingReg, Reg))
1767 DeadOps.push_back(i);
1771 // Trim unneeded dead operands.
1772 while (!DeadOps.empty()) {
1773 unsigned OpIdx = DeadOps.back();
1774 if (getOperand(OpIdx).isImplicit())
1775 RemoveOperand(OpIdx);
1777 getOperand(OpIdx).setIsDead(false);
1781 // If not found, this means an alias of one of the operands is dead. Add a
1782 // new implicit operand if required.
1783 if (Found || !AddIfNotFound)
1786 addOperand(MachineOperand::CreateReg(IncomingReg,
1794 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1795 const TargetRegisterInfo *RegInfo) {
1796 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1797 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1801 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1802 const MachineOperand &MO = getOperand(i);
1803 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1804 MO.getSubReg() == 0)
1808 addOperand(MachineOperand::CreateReg(IncomingReg,
1813 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1814 const TargetRegisterInfo &TRI) {
1815 bool HasRegMask = false;
1816 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1817 MachineOperand &MO = getOperand(i);
1818 if (MO.isRegMask()) {
1822 if (!MO.isReg() || !MO.isDef()) continue;
1823 unsigned Reg = MO.getReg();
1824 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1826 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1828 if (TRI.regsOverlap(*I, Reg)) {
1832 // If there are no uses, including partial uses, the def is dead.
1833 if (Dead) MO.setIsDead();
1836 // This is a call with a register mask operand.
1837 // Mask clobbers are always dead, so add defs for the non-dead defines.
1839 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1841 addRegisterDefined(*I, &TRI);
1845 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1846 // Build up a buffer of hash code components.
1848 // FIXME: This is a total hack. We should have a hash_value overload for
1849 // MachineOperand, but currently that doesn't work because there are many
1850 // different ideas of "equality" and thus different sets of information that
1851 // contribute to the hash code. This one happens to want to take a specific
1852 // subset. And it's still not clear that this routine uses the *correct*
1853 // subset of information when computing the hash code. The goal is to use the
1854 // same inputs for the hash code here that MachineInstr::isIdenticalTo uses to
1855 // test for equality when passed the 'IgnoreVRegDefs' filter flag. It would
1856 // be very useful to factor the selection of relevant inputs out of the two
1857 // functions and into a common routine, but it's not clear how that can be
1859 SmallVector<size_t, 8> HashComponents;
1860 HashComponents.reserve(MI->getNumOperands() + 1);
1861 HashComponents.push_back(MI->getOpcode());
1862 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1863 const MachineOperand &MO = MI->getOperand(i);
1864 switch (MO.getType()) {
1866 case MachineOperand::MO_Register:
1867 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1868 continue; // Skip virtual register defs.
1869 HashComponents.push_back(hash_combine(MO.getType(), MO.getReg()));
1871 case MachineOperand::MO_Immediate:
1872 HashComponents.push_back(hash_combine(MO.getType(), MO.getImm()));
1874 case MachineOperand::MO_FrameIndex:
1875 case MachineOperand::MO_ConstantPoolIndex:
1876 case MachineOperand::MO_JumpTableIndex:
1877 HashComponents.push_back(hash_combine(MO.getType(), MO.getIndex()));
1879 case MachineOperand::MO_MachineBasicBlock:
1880 HashComponents.push_back(hash_combine(MO.getType(), MO.getMBB()));
1882 case MachineOperand::MO_GlobalAddress:
1883 HashComponents.push_back(hash_combine(MO.getType(), MO.getGlobal()));
1885 case MachineOperand::MO_BlockAddress:
1886 HashComponents.push_back(hash_combine(MO.getType(),
1887 MO.getBlockAddress()));
1889 case MachineOperand::MO_MCSymbol:
1890 HashComponents.push_back(hash_combine(MO.getType(), MO.getMCSymbol()));
1894 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1897 void MachineInstr::emitError(StringRef Msg) const {
1898 // Find the source location cookie.
1899 unsigned LocCookie = 0;
1900 const MDNode *LocMD = 0;
1901 for (unsigned i = getNumOperands(); i != 0; --i) {
1902 if (getOperand(i-1).isMetadata() &&
1903 (LocMD = getOperand(i-1).getMetadata()) &&
1904 LocMD->getNumOperands() != 0) {
1905 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1906 LocCookie = CI->getZExtValue();
1912 if (const MachineBasicBlock *MBB = getParent())
1913 if (const MachineFunction *MF = MBB->getParent())
1914 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1915 report_fatal_error(Msg);