1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/DebugInfo.h"
17 #include "llvm/Function.h"
18 #include "llvm/InlineAsm.h"
19 #include "llvm/LLVMContext.h"
20 #include "llvm/Metadata.h"
21 #include "llvm/Module.h"
22 #include "llvm/Type.h"
23 #include "llvm/Value.h"
24 #include "llvm/Assembly/Writer.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
43 #include "llvm/ADT/Hashing.h"
46 //===----------------------------------------------------------------------===//
47 // MachineOperand Implementation
48 //===----------------------------------------------------------------------===//
50 void MachineOperand::setReg(unsigned Reg) {
51 if (getReg() == Reg) return; // No change.
53 // Otherwise, we have to change the register. If this operand is embedded
54 // into a machine function, we need to update the old and new register's
56 if (MachineInstr *MI = getParent())
57 if (MachineBasicBlock *MBB = MI->getParent())
58 if (MachineFunction *MF = MBB->getParent()) {
59 MachineRegisterInfo &MRI = MF->getRegInfo();
60 MRI.removeRegOperandFromUseList(this);
61 SmallContents.RegNo = Reg;
62 MRI.addRegOperandToUseList(this);
66 // Otherwise, just change the register, no problem. :)
67 SmallContents.RegNo = Reg;
70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71 const TargetRegisterInfo &TRI) {
72 assert(TargetRegisterInfo::isVirtualRegister(Reg));
73 if (SubIdx && getSubReg())
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
80 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
83 Reg = TRI.getSubReg(Reg, getSubReg());
84 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85 // That won't happen in legal code.
91 /// Change a def to a use, or a use to a def.
92 void MachineOperand::setIsDef(bool Val) {
93 assert(isReg() && "Wrong MachineOperand accessor");
94 assert((!Val || !isDebug()) && "Marking a debug operation as def");
97 // MRI may keep uses and defs in different list positions.
98 if (MachineInstr *MI = getParent())
99 if (MachineBasicBlock *MBB = MI->getParent())
100 if (MachineFunction *MF = MBB->getParent()) {
101 MachineRegisterInfo &MRI = MF->getRegInfo();
102 MRI.removeRegOperandFromUseList(this);
104 MRI.addRegOperandToUseList(this);
110 /// ChangeToImmediate - Replace this operand with a new immediate operand of
111 /// the specified value. If an operand is known to be an immediate already,
112 /// the setImm method should be used.
113 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
114 // If this operand is currently a register operand, and if this is in a
115 // function, deregister the operand from the register's use/def list.
116 if (isReg() && isOnRegUseList())
117 if (MachineInstr *MI = getParent())
118 if (MachineBasicBlock *MBB = MI->getParent())
119 if (MachineFunction *MF = MBB->getParent())
120 MF->getRegInfo().removeRegOperandFromUseList(this);
122 OpKind = MO_Immediate;
123 Contents.ImmVal = ImmVal;
126 /// ChangeToRegister - Replace this operand with a new register operand of
127 /// the specified value. If an operand is known to be an register already,
128 /// the setReg method should be used.
129 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
130 bool isKill, bool isDead, bool isUndef,
132 MachineRegisterInfo *RegInfo = 0;
133 if (MachineInstr *MI = getParent())
134 if (MachineBasicBlock *MBB = MI->getParent())
135 if (MachineFunction *MF = MBB->getParent())
136 RegInfo = &MF->getRegInfo();
137 // If this operand is already a register operand, remove it from the
138 // register's use/def lists.
139 if (RegInfo && isReg())
140 RegInfo->removeRegOperandFromUseList(this);
142 // Change this to a register and set the reg#.
143 OpKind = MO_Register;
144 SmallContents.RegNo = Reg;
151 IsInternalRead = false;
152 IsEarlyClobber = false;
154 // Ensure isOnRegUseList() returns false.
155 Contents.Reg.Prev = 0;
157 // If this operand is embedded in a function, add the operand to the
158 // register's use/def list.
160 RegInfo->addRegOperandToUseList(this);
163 /// isIdenticalTo - Return true if this operand is identical to the specified
164 /// operand. Note that this should stay in sync with the hash_value overload
166 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
167 if (getType() != Other.getType() ||
168 getTargetFlags() != Other.getTargetFlags())
172 case MachineOperand::MO_Register:
173 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
174 getSubReg() == Other.getSubReg();
175 case MachineOperand::MO_Immediate:
176 return getImm() == Other.getImm();
177 case MachineOperand::MO_CImmediate:
178 return getCImm() == Other.getCImm();
179 case MachineOperand::MO_FPImmediate:
180 return getFPImm() == Other.getFPImm();
181 case MachineOperand::MO_MachineBasicBlock:
182 return getMBB() == Other.getMBB();
183 case MachineOperand::MO_FrameIndex:
184 return getIndex() == Other.getIndex();
185 case MachineOperand::MO_ConstantPoolIndex:
186 case MachineOperand::MO_TargetIndex:
187 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
188 case MachineOperand::MO_JumpTableIndex:
189 return getIndex() == Other.getIndex();
190 case MachineOperand::MO_GlobalAddress:
191 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
192 case MachineOperand::MO_ExternalSymbol:
193 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
194 getOffset() == Other.getOffset();
195 case MachineOperand::MO_BlockAddress:
196 return getBlockAddress() == Other.getBlockAddress();
197 case MO_RegisterMask:
198 return getRegMask() == Other.getRegMask();
199 case MachineOperand::MO_MCSymbol:
200 return getMCSymbol() == Other.getMCSymbol();
201 case MachineOperand::MO_Metadata:
202 return getMetadata() == Other.getMetadata();
204 llvm_unreachable("Invalid machine operand type");
207 // Note: this must stay exactly in sync with isIdenticalTo above.
208 hash_code llvm::hash_value(const MachineOperand &MO) {
209 switch (MO.getType()) {
210 case MachineOperand::MO_Register:
211 // Register operands don't have target flags.
212 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
213 case MachineOperand::MO_Immediate:
214 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
215 case MachineOperand::MO_CImmediate:
216 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
217 case MachineOperand::MO_FPImmediate:
218 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
219 case MachineOperand::MO_MachineBasicBlock:
220 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
221 case MachineOperand::MO_FrameIndex:
222 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
223 case MachineOperand::MO_ConstantPoolIndex:
224 case MachineOperand::MO_TargetIndex:
225 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
227 case MachineOperand::MO_JumpTableIndex:
228 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
229 case MachineOperand::MO_ExternalSymbol:
230 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
232 case MachineOperand::MO_GlobalAddress:
233 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
235 case MachineOperand::MO_BlockAddress:
236 return hash_combine(MO.getType(), MO.getTargetFlags(),
237 MO.getBlockAddress());
238 case MachineOperand::MO_RegisterMask:
239 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
240 case MachineOperand::MO_Metadata:
241 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
242 case MachineOperand::MO_MCSymbol:
243 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
245 llvm_unreachable("Invalid machine operand type");
248 /// print - Print the specified machine operand.
250 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
251 // If the instruction is embedded into a basic block, we can find the
252 // target info for the instruction.
254 if (const MachineInstr *MI = getParent())
255 if (const MachineBasicBlock *MBB = MI->getParent())
256 if (const MachineFunction *MF = MBB->getParent())
257 TM = &MF->getTarget();
258 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
261 case MachineOperand::MO_Register:
262 OS << PrintReg(getReg(), TRI, getSubReg());
264 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
265 isInternalRead() || isEarlyClobber() || isTied()) {
267 bool NeedComma = false;
269 if (NeedComma) OS << ',';
270 if (isEarlyClobber())
271 OS << "earlyclobber,";
276 // <def,read-undef> only makes sense when getSubReg() is set.
277 // Don't clutter the output otherwise.
278 if (isUndef() && getSubReg())
280 } else if (isImplicit()) {
286 if (NeedComma) OS << ',';
291 if (NeedComma) OS << ',';
295 if (isUndef() && isUse()) {
296 if (NeedComma) OS << ',';
300 if (isInternalRead()) {
301 if (NeedComma) OS << ',';
306 if (NeedComma) OS << ',';
313 case MachineOperand::MO_Immediate:
316 case MachineOperand::MO_CImmediate:
317 getCImm()->getValue().print(OS, false);
319 case MachineOperand::MO_FPImmediate:
320 if (getFPImm()->getType()->isFloatTy())
321 OS << getFPImm()->getValueAPF().convertToFloat();
323 OS << getFPImm()->getValueAPF().convertToDouble();
325 case MachineOperand::MO_MachineBasicBlock:
326 OS << "<BB#" << getMBB()->getNumber() << ">";
328 case MachineOperand::MO_FrameIndex:
329 OS << "<fi#" << getIndex() << '>';
331 case MachineOperand::MO_ConstantPoolIndex:
332 OS << "<cp#" << getIndex();
333 if (getOffset()) OS << "+" << getOffset();
336 case MachineOperand::MO_TargetIndex:
337 OS << "<ti#" << getIndex();
338 if (getOffset()) OS << "+" << getOffset();
341 case MachineOperand::MO_JumpTableIndex:
342 OS << "<jt#" << getIndex() << '>';
344 case MachineOperand::MO_GlobalAddress:
346 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
347 if (getOffset()) OS << "+" << getOffset();
350 case MachineOperand::MO_ExternalSymbol:
351 OS << "<es:" << getSymbolName();
352 if (getOffset()) OS << "+" << getOffset();
355 case MachineOperand::MO_BlockAddress:
357 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
360 case MachineOperand::MO_RegisterMask:
363 case MachineOperand::MO_Metadata:
365 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
368 case MachineOperand::MO_MCSymbol:
369 OS << "<MCSym=" << *getMCSymbol() << '>';
373 if (unsigned TF = getTargetFlags())
374 OS << "[TF=" << TF << ']';
377 //===----------------------------------------------------------------------===//
378 // MachineMemOperand Implementation
379 //===----------------------------------------------------------------------===//
381 /// getAddrSpace - Return the LLVM IR address space number that this pointer
383 unsigned MachinePointerInfo::getAddrSpace() const {
384 if (V == 0) return 0;
385 return cast<PointerType>(V->getType())->getAddressSpace();
388 /// getConstantPool - Return a MachinePointerInfo record that refers to the
390 MachinePointerInfo MachinePointerInfo::getConstantPool() {
391 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
394 /// getFixedStack - Return a MachinePointerInfo record that refers to the
395 /// the specified FrameIndex.
396 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
397 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
400 MachinePointerInfo MachinePointerInfo::getJumpTable() {
401 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
404 MachinePointerInfo MachinePointerInfo::getGOT() {
405 return MachinePointerInfo(PseudoSourceValue::getGOT());
408 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
409 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
412 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
413 uint64_t s, unsigned int a,
414 const MDNode *TBAAInfo,
415 const MDNode *Ranges)
416 : PtrInfo(ptrinfo), Size(s),
417 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
418 TBAAInfo(TBAAInfo), Ranges(Ranges) {
419 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
420 "invalid pointer value");
421 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
422 assert((isLoad() || isStore()) && "Not a load/store!");
425 /// Profile - Gather unique data for the object.
427 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
428 ID.AddInteger(getOffset());
430 ID.AddPointer(getValue());
431 ID.AddInteger(Flags);
434 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
435 // The Value and Offset may differ due to CSE. But the flags and size
436 // should be the same.
437 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
438 assert(MMO->getSize() == getSize() && "Size mismatch!");
440 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
441 // Update the alignment value.
442 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
443 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
444 // Also update the base and offset, because the new alignment may
445 // not be applicable with the old ones.
446 PtrInfo = MMO->PtrInfo;
450 /// getAlignment - Return the minimum known alignment in bytes of the
451 /// actual memory reference.
452 uint64_t MachineMemOperand::getAlignment() const {
453 return MinAlign(getBaseAlignment(), getOffset());
456 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
457 assert((MMO.isLoad() || MMO.isStore()) &&
458 "SV has to be a load, store or both.");
460 if (MMO.isVolatile())
469 // Print the address information.
474 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
476 // If the alignment of the memory reference itself differs from the alignment
477 // of the base pointer, print the base alignment explicitly, next to the base
479 if (MMO.getBaseAlignment() != MMO.getAlignment())
480 OS << "(align=" << MMO.getBaseAlignment() << ")";
482 if (MMO.getOffset() != 0)
483 OS << "+" << MMO.getOffset();
486 // Print the alignment of the reference.
487 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
488 MMO.getBaseAlignment() != MMO.getSize())
489 OS << "(align=" << MMO.getAlignment() << ")";
492 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
494 if (TBAAInfo->getNumOperands() > 0)
495 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
501 // Print nontemporal info.
502 if (MMO.isNonTemporal())
503 OS << "(nontemporal)";
508 //===----------------------------------------------------------------------===//
509 // MachineInstr Implementation
510 //===----------------------------------------------------------------------===//
512 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
513 /// MCID NULL and no operands.
514 MachineInstr::MachineInstr()
515 : MCID(0), Flags(0), AsmPrinterFlags(0),
516 NumMemRefs(0), MemRefs(0),
518 // Make sure that we get added to a machine basicblock
519 LeakDetector::addGarbageObject(this);
522 void MachineInstr::addImplicitDefUseOperands() {
523 if (MCID->ImplicitDefs)
524 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
525 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
526 if (MCID->ImplicitUses)
527 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
528 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
531 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
532 /// implicit operands. It reserves space for the number of operands specified by
534 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
535 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
536 NumMemRefs(0), MemRefs(0), Parent(0) {
537 unsigned NumImplicitOps = 0;
539 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
540 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
542 addImplicitDefUseOperands();
543 // Make sure that we get added to a machine basicblock
544 LeakDetector::addGarbageObject(this);
547 /// MachineInstr ctor - As above, but with a DebugLoc.
548 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
550 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
551 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
552 unsigned NumImplicitOps = 0;
554 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
555 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
557 addImplicitDefUseOperands();
558 // Make sure that we get added to a machine basicblock
559 LeakDetector::addGarbageObject(this);
562 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
563 /// that the MachineInstr is created and added to the end of the specified
565 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
566 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
567 NumMemRefs(0), MemRefs(0), Parent(0) {
568 assert(MBB && "Cannot use inserting ctor with null basic block!");
569 unsigned NumImplicitOps =
570 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
571 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
572 addImplicitDefUseOperands();
573 // Make sure that we get added to a machine basicblock
574 LeakDetector::addGarbageObject(this);
575 MBB->push_back(this); // Add instruction to end of basic block!
578 /// MachineInstr ctor - As above, but with a DebugLoc.
580 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
581 const MCInstrDesc &tid)
582 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
583 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
584 assert(MBB && "Cannot use inserting ctor with null basic block!");
585 unsigned NumImplicitOps =
586 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
587 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
588 addImplicitDefUseOperands();
589 // Make sure that we get added to a machine basicblock
590 LeakDetector::addGarbageObject(this);
591 MBB->push_back(this); // Add instruction to end of basic block!
594 /// MachineInstr ctor - Copies MachineInstr arg exactly
596 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
597 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
598 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
599 Parent(0), debugLoc(MI.getDebugLoc()) {
600 Operands.reserve(MI.getNumOperands());
603 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
604 addOperand(MI.getOperand(i));
606 // Copy all the flags.
609 // Set parent to null.
612 LeakDetector::addGarbageObject(this);
615 MachineInstr::~MachineInstr() {
616 LeakDetector::removeGarbageObject(this);
618 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
619 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
620 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
621 "Reg operand def/use list corrupted");
626 /// getRegInfo - If this instruction is embedded into a MachineFunction,
627 /// return the MachineRegisterInfo object for the current function, otherwise
629 MachineRegisterInfo *MachineInstr::getRegInfo() {
630 if (MachineBasicBlock *MBB = getParent())
631 return &MBB->getParent()->getRegInfo();
635 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
636 /// this instruction from their respective use lists. This requires that the
637 /// operands already be on their use lists.
638 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
639 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
640 if (Operands[i].isReg())
641 MRI.removeRegOperandFromUseList(&Operands[i]);
644 /// AddRegOperandsToUseLists - Add all of the register operands in
645 /// this instruction from their respective use lists. This requires that the
646 /// operands not be on their use lists yet.
647 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
648 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
649 if (Operands[i].isReg())
650 MRI.addRegOperandToUseList(&Operands[i]);
653 /// addOperand - Add the specified operand to the instruction. If it is an
654 /// implicit operand, it is added to the end of the operand list. If it is
655 /// an explicit operand it is added at the end of the explicit operand list
656 /// (before the first implicit operand).
657 void MachineInstr::addOperand(const MachineOperand &Op) {
658 assert(MCID && "Cannot add operands before providing an instr descriptor");
659 bool isImpReg = Op.isReg() && Op.isImplicit();
660 MachineRegisterInfo *RegInfo = getRegInfo();
662 // If the Operands backing store is reallocated, all register operands must
663 // be removed and re-added to RegInfo. It is storing pointers to operands.
664 bool Reallocate = RegInfo &&
665 !Operands.empty() && Operands.size() == Operands.capacity();
667 // Find the insert location for the new operand. Implicit registers go at
668 // the end, everything goes before the implicit regs.
669 unsigned OpNo = Operands.size();
671 // Remove all the implicit operands from RegInfo if they need to be shifted.
672 // FIXME: Allow mixed explicit and implicit operands on inline asm.
673 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
674 // implicit-defs, but they must not be moved around. See the FIXME in
676 if (!isImpReg && !isInlineAsm()) {
677 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
680 RegInfo->removeRegOperandFromUseList(&Operands[OpNo]);
684 // OpNo now points as the desired insertion point. Unless this is a variadic
685 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
686 // RegMask operands go between the explicit and implicit operands.
687 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
688 OpNo < MCID->getNumOperands()) &&
689 "Trying to add an operand to a machine instr that is already done!");
691 // All operands from OpNo have been removed from RegInfo. If the Operands
692 // backing store needs to be reallocated, we also need to remove any other
693 // register operands.
695 for (unsigned i = 0; i != OpNo; ++i)
696 if (Operands[i].isReg())
697 RegInfo->removeRegOperandFromUseList(&Operands[i]);
699 // Insert the new operand at OpNo.
700 Operands.insert(Operands.begin() + OpNo, Op);
701 Operands[OpNo].ParentMI = this;
703 // The Operands backing store has now been reallocated, so we can re-add the
704 // operands before OpNo.
706 for (unsigned i = 0; i != OpNo; ++i)
707 if (Operands[i].isReg())
708 RegInfo->addRegOperandToUseList(&Operands[i]);
710 // When adding a register operand, tell RegInfo about it.
711 if (Operands[OpNo].isReg()) {
712 // Ensure isOnRegUseList() returns false, regardless of Op's status.
713 Operands[OpNo].Contents.Reg.Prev = 0;
714 // Add the new operand to RegInfo.
716 RegInfo->addRegOperandToUseList(&Operands[OpNo]);
717 // Set the IsTied bit if MC indicates this use is tied to a def.
718 if (Operands[OpNo].isUse()) {
719 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
721 MachineOperand &DefMO = getOperand(DefIdx);
722 assert(DefMO.isDef() && "Use tied to operand that isn't a def");
724 Operands[OpNo].IsTied = true;
727 // If the register operand is flagged as early, mark the operand as such.
728 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
729 Operands[OpNo].setIsEarlyClobber(true);
732 // Re-add all the implicit ops.
734 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
735 assert(Operands[i].isReg() && "Should only be an implicit reg!");
736 RegInfo->addRegOperandToUseList(&Operands[i]);
741 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
742 /// fewer operand than it started with.
744 void MachineInstr::RemoveOperand(unsigned OpNo) {
745 assert(OpNo < Operands.size() && "Invalid operand number");
746 MachineRegisterInfo *RegInfo = getRegInfo();
748 // Special case removing the last one.
749 if (OpNo == Operands.size()-1) {
750 // If needed, remove from the reg def/use list.
751 if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList())
752 RegInfo->removeRegOperandFromUseList(&Operands.back());
758 // Otherwise, we are removing an interior operand. If we have reginfo to
759 // update, remove all operands that will be shifted down from their reg lists,
760 // move everything down, then re-add them.
762 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
763 if (Operands[i].isReg())
764 RegInfo->removeRegOperandFromUseList(&Operands[i]);
768 Operands.erase(Operands.begin()+OpNo);
771 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
772 if (Operands[i].isReg())
773 RegInfo->addRegOperandToUseList(&Operands[i]);
778 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
779 /// This function should be used only occasionally. The setMemRefs function
780 /// is the primary method for setting up a MachineInstr's MemRefs list.
781 void MachineInstr::addMemOperand(MachineFunction &MF,
782 MachineMemOperand *MO) {
783 mmo_iterator OldMemRefs = MemRefs;
784 uint16_t OldNumMemRefs = NumMemRefs;
786 uint16_t NewNum = NumMemRefs + 1;
787 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
789 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
790 NewMemRefs[NewNum - 1] = MO;
792 MemRefs = NewMemRefs;
796 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
797 const MachineBasicBlock *MBB = getParent();
798 MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
799 while (MII != MBB->end() && MII->isInsideBundle()) {
800 if (MII->getDesc().getFlags() & Mask) {
801 if (Type == AnyInBundle)
804 if (Type == AllInBundle)
810 return Type == AllInBundle;
813 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
814 MICheckType Check) const {
815 // If opcodes or number of operands are not the same then the two
816 // instructions are obviously not identical.
817 if (Other->getOpcode() != getOpcode() ||
818 Other->getNumOperands() != getNumOperands())
822 // Both instructions are bundles, compare MIs inside the bundle.
823 MachineBasicBlock::const_instr_iterator I1 = *this;
824 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
825 MachineBasicBlock::const_instr_iterator I2 = *Other;
826 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
827 while (++I1 != E1 && I1->isInsideBundle()) {
829 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
834 // Check operands to make sure they match.
835 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
836 const MachineOperand &MO = getOperand(i);
837 const MachineOperand &OMO = Other->getOperand(i);
839 if (!MO.isIdenticalTo(OMO))
844 // Clients may or may not want to ignore defs when testing for equality.
845 // For example, machine CSE pass only cares about finding common
846 // subexpressions, so it's safe to ignore virtual register defs.
848 if (Check == IgnoreDefs)
850 else if (Check == IgnoreVRegDefs) {
851 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
852 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
853 if (MO.getReg() != OMO.getReg())
856 if (!MO.isIdenticalTo(OMO))
858 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
862 if (!MO.isIdenticalTo(OMO))
864 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
868 // If DebugLoc does not match then two dbg.values are not identical.
870 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
871 && getDebugLoc() != Other->getDebugLoc())
876 /// removeFromParent - This method unlinks 'this' from the containing basic
877 /// block, and returns it, but does not delete it.
878 MachineInstr *MachineInstr::removeFromParent() {
879 assert(getParent() && "Not embedded in a basic block!");
881 // If it's a bundle then remove the MIs inside the bundle as well.
883 MachineBasicBlock *MBB = getParent();
884 MachineBasicBlock::instr_iterator MII = *this; ++MII;
885 MachineBasicBlock::instr_iterator E = MBB->instr_end();
886 while (MII != E && MII->isInsideBundle()) {
887 MachineInstr *MI = &*MII;
892 getParent()->remove(this);
897 /// eraseFromParent - This method unlinks 'this' from the containing basic
898 /// block, and deletes it.
899 void MachineInstr::eraseFromParent() {
900 assert(getParent() && "Not embedded in a basic block!");
901 // If it's a bundle then remove the MIs inside the bundle as well.
903 MachineBasicBlock *MBB = getParent();
904 MachineBasicBlock::instr_iterator MII = *this; ++MII;
905 MachineBasicBlock::instr_iterator E = MBB->instr_end();
906 while (MII != E && MII->isInsideBundle()) {
907 MachineInstr *MI = &*MII;
912 // Erase the individual instruction, which may itself be inside a bundle.
913 getParent()->erase_instr(this);
917 /// getNumExplicitOperands - Returns the number of non-implicit operands.
919 unsigned MachineInstr::getNumExplicitOperands() const {
920 unsigned NumOperands = MCID->getNumOperands();
921 if (!MCID->isVariadic())
924 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
925 const MachineOperand &MO = getOperand(i);
926 if (!MO.isReg() || !MO.isImplicit())
932 /// isBundled - Return true if this instruction part of a bundle. This is true
933 /// if either itself or its following instruction is marked "InsideBundle".
934 bool MachineInstr::isBundled() const {
935 if (isInsideBundle())
937 MachineBasicBlock::const_instr_iterator nextMI = this;
939 return nextMI != Parent->instr_end() && nextMI->isInsideBundle();
942 bool MachineInstr::isStackAligningInlineAsm() const {
944 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
945 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
951 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
952 unsigned *GroupNo) const {
953 assert(isInlineAsm() && "Expected an inline asm instruction");
954 assert(OpIdx < getNumOperands() && "OpIdx out of range");
956 // Ignore queries about the initial operands.
957 if (OpIdx < InlineAsm::MIOp_FirstOperand)
962 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
964 const MachineOperand &FlagMO = getOperand(i);
965 // If we reach the implicit register operands, stop looking.
968 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
969 if (i + NumOps > OpIdx) {
979 const TargetRegisterClass*
980 MachineInstr::getRegClassConstraint(unsigned OpIdx,
981 const TargetInstrInfo *TII,
982 const TargetRegisterInfo *TRI) const {
983 assert(getParent() && "Can't have an MBB reference here!");
984 assert(getParent()->getParent() && "Can't have an MF reference here!");
985 const MachineFunction &MF = *getParent()->getParent();
987 // Most opcodes have fixed constraints in their MCInstrDesc.
989 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
991 if (!getOperand(OpIdx).isReg())
994 // For tied uses on inline asm, get the constraint from the def.
996 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
999 // Inline asm stores register class constraints in the flag word.
1000 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1004 unsigned Flag = getOperand(FlagIdx).getImm();
1006 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
1007 return TRI->getRegClass(RCID);
1009 // Assume that all registers in a memory operand are pointers.
1010 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
1011 return TRI->getPointerRegClass(MF);
1016 /// getBundleSize - Return the number of instructions inside the MI bundle.
1017 unsigned MachineInstr::getBundleSize() const {
1018 assert(isBundle() && "Expecting a bundle");
1020 MachineBasicBlock::const_instr_iterator I = *this;
1022 while ((++I)->isInsideBundle()) {
1025 assert(Size > 1 && "Malformed bundle");
1030 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1031 /// the specific register or -1 if it is not found. It further tightens
1032 /// the search criteria to a use that kills the register if isKill is true.
1033 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1034 const TargetRegisterInfo *TRI) const {
1035 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1036 const MachineOperand &MO = getOperand(i);
1037 if (!MO.isReg() || !MO.isUse())
1039 unsigned MOReg = MO.getReg();
1044 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1045 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1046 TRI->isSubRegister(MOReg, Reg)))
1047 if (!isKill || MO.isKill())
1053 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1054 /// indicating if this instruction reads or writes Reg. This also considers
1055 /// partial defines.
1056 std::pair<bool,bool>
1057 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1058 SmallVectorImpl<unsigned> *Ops) const {
1059 bool PartDef = false; // Partial redefine.
1060 bool FullDef = false; // Full define.
1063 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1064 const MachineOperand &MO = getOperand(i);
1065 if (!MO.isReg() || MO.getReg() != Reg)
1070 Use |= !MO.isUndef();
1071 else if (MO.getSubReg() && !MO.isUndef())
1072 // A partial <def,undef> doesn't count as reading the register.
1077 // A partial redefine uses Reg unless there is also a full define.
1078 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1081 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1082 /// the specified register or -1 if it is not found. If isDead is true, defs
1083 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1084 /// also checks if there is a def of a super-register.
1086 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1087 const TargetRegisterInfo *TRI) const {
1088 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1089 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1090 const MachineOperand &MO = getOperand(i);
1091 // Accept regmask operands when Overlap is set.
1092 // Ignore them when looking for a specific def operand (Overlap == false).
1093 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1095 if (!MO.isReg() || !MO.isDef())
1097 unsigned MOReg = MO.getReg();
1098 bool Found = (MOReg == Reg);
1099 if (!Found && TRI && isPhys &&
1100 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1102 Found = TRI->regsOverlap(MOReg, Reg);
1104 Found = TRI->isSubRegister(MOReg, Reg);
1106 if (Found && (!isDead || MO.isDead()))
1112 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1113 /// operand list that is used to represent the predicate. It returns -1 if
1115 int MachineInstr::findFirstPredOperandIdx() const {
1116 // Don't call MCID.findFirstPredOperandIdx() because this variant
1117 // is sometimes called on an instruction that's not yet complete, and
1118 // so the number of operands is less than the MCID indicates. In
1119 // particular, the PTX target does this.
1120 const MCInstrDesc &MCID = getDesc();
1121 if (MCID.isPredicable()) {
1122 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1123 if (MCID.OpInfo[i].isPredicate())
1130 /// isRegTiedToUseOperand - Given the index of a register def operand,
1131 /// check if the register def is tied to a source operand, due to either
1132 /// two-address elimination or inline assembly constraints. Returns the
1133 /// first tied use operand index by reference is UseOpIdx is not null.
1135 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1136 if (isInlineAsm()) {
1137 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1138 const MachineOperand &MO = getOperand(DefOpIdx);
1139 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1141 // Determine the actual operand index that corresponds to this index.
1143 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1147 // Which part of the group is DefOpIdx?
1148 unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1150 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1152 const MachineOperand &FMO = getOperand(i);
1155 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1158 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1161 *UseOpIdx = (unsigned)i + 1 + DefPart;
1168 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1169 const MCInstrDesc &MCID = getDesc();
1170 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1171 const MachineOperand &MO = getOperand(i);
1172 if (MO.isReg() && MO.isUse() &&
1173 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1175 *UseOpIdx = (unsigned)i;
1182 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1183 /// is a register use and it is tied to an def operand. It also returns the def
1184 /// operand index by reference.
1186 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1187 if (isInlineAsm()) {
1188 const MachineOperand &MO = getOperand(UseOpIdx);
1189 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1192 // Find the flag operand corresponding to UseOpIdx
1193 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1197 const MachineOperand &UFMO = getOperand(FlagIdx);
1199 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1203 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1204 // Remember to adjust the index. First operand is asm string, second is
1205 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1207 const MachineOperand &FMO = getOperand(DefIdx);
1208 assert(FMO.isImm());
1209 // Skip over this def.
1210 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1213 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1219 const MCInstrDesc &MCID = getDesc();
1220 if (UseOpIdx >= MCID.getNumOperands())
1222 const MachineOperand &MO = getOperand(UseOpIdx);
1223 if (!MO.isReg() || !MO.isUse())
1225 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1229 *DefOpIdx = (unsigned)DefIdx;
1233 /// clearKillInfo - Clears kill flags on all operands.
1235 void MachineInstr::clearKillInfo() {
1236 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1237 MachineOperand &MO = getOperand(i);
1238 if (MO.isReg() && MO.isUse())
1239 MO.setIsKill(false);
1243 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1245 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1246 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1247 const MachineOperand &MO = MI->getOperand(i);
1248 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1250 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1251 MachineOperand &MOp = getOperand(j);
1252 if (!MOp.isIdenticalTo(MO))
1263 /// copyPredicates - Copies predicate operand(s) from MI.
1264 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1265 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1267 const MCInstrDesc &MCID = MI->getDesc();
1268 if (!MCID.isPredicable())
1270 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1271 if (MCID.OpInfo[i].isPredicate()) {
1272 // Predicated operands must be last operands.
1273 addOperand(MI->getOperand(i));
1278 void MachineInstr::substituteRegister(unsigned FromReg,
1281 const TargetRegisterInfo &RegInfo) {
1282 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1284 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1285 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1286 MachineOperand &MO = getOperand(i);
1287 if (!MO.isReg() || MO.getReg() != FromReg)
1289 MO.substPhysReg(ToReg, RegInfo);
1292 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1293 MachineOperand &MO = getOperand(i);
1294 if (!MO.isReg() || MO.getReg() != FromReg)
1296 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1301 /// isSafeToMove - Return true if it is safe to move this instruction. If
1302 /// SawStore is set to true, it means that there is a store (or call) between
1303 /// the instruction's location and its intended destination.
1304 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1306 bool &SawStore) const {
1307 // Ignore stuff that we obviously can't move.
1308 if (mayStore() || isCall()) {
1313 if (isLabel() || isDebugValue() ||
1314 isTerminator() || hasUnmodeledSideEffects())
1317 // See if this instruction does a load. If so, we have to guarantee that the
1318 // loaded value doesn't change between the load and the its intended
1319 // destination. The check for isInvariantLoad gives the targe the chance to
1320 // classify the load as always returning a constant, e.g. a constant pool
1322 if (mayLoad() && !isInvariantLoad(AA))
1323 // Otherwise, this is a real load. If there is a store between the load and
1324 // end of block, or if the load is volatile, we can't move it.
1325 return !SawStore && !hasVolatileMemoryRef();
1330 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1331 /// instruction which defined the specified register instead of copying it.
1332 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1334 unsigned DstReg) const {
1335 bool SawStore = false;
1336 if (!TII->isTriviallyReMaterializable(this, AA) ||
1337 !isSafeToMove(TII, AA, SawStore))
1339 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1340 const MachineOperand &MO = getOperand(i);
1343 // FIXME: For now, do not remat any instruction with register operands.
1344 // Later on, we can loosen the restriction is the register operands have
1345 // not been modified between the def and use. Note, this is different from
1346 // MachineSink because the code is no longer in two-address form (at least
1350 else if (!MO.isDead() && MO.getReg() != DstReg)
1356 /// hasVolatileMemoryRef - Return true if this instruction may have a
1357 /// volatile memory reference, or if the information describing the
1358 /// memory reference is not available. Return false if it is known to
1359 /// have no volatile memory references.
1360 bool MachineInstr::hasVolatileMemoryRef() const {
1361 // An instruction known never to access memory won't have a volatile access.
1365 !hasUnmodeledSideEffects())
1368 // Otherwise, if the instruction has no memory reference information,
1369 // conservatively assume it wasn't preserved.
1370 if (memoperands_empty())
1373 // Check the memory reference information for volatile references.
1374 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1375 if ((*I)->isVolatile())
1381 /// isInvariantLoad - Return true if this instruction is loading from a
1382 /// location whose value is invariant across the function. For example,
1383 /// loading a value from the constant pool or from the argument area
1384 /// of a function if it does not change. This should only return true of
1385 /// *all* loads the instruction does are invariant (if it does multiple loads).
1386 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1387 // If the instruction doesn't load at all, it isn't an invariant load.
1391 // If the instruction has lost its memoperands, conservatively assume that
1392 // it may not be an invariant load.
1393 if (memoperands_empty())
1396 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1398 for (mmo_iterator I = memoperands_begin(),
1399 E = memoperands_end(); I != E; ++I) {
1400 if ((*I)->isVolatile()) return false;
1401 if ((*I)->isStore()) return false;
1402 if ((*I)->isInvariant()) return true;
1404 if (const Value *V = (*I)->getValue()) {
1405 // A load from a constant PseudoSourceValue is invariant.
1406 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1407 if (PSV->isConstant(MFI))
1409 // If we have an AliasAnalysis, ask it whether the memory is constant.
1410 if (AA && AA->pointsToConstantMemory(
1411 AliasAnalysis::Location(V, (*I)->getSize(),
1412 (*I)->getTBAAInfo())))
1416 // Otherwise assume conservatively.
1420 // Everything checks out.
1424 /// isConstantValuePHI - If the specified instruction is a PHI that always
1425 /// merges together the same virtual register, return the register, otherwise
1427 unsigned MachineInstr::isConstantValuePHI() const {
1430 assert(getNumOperands() >= 3 &&
1431 "It's illegal to have a PHI without source operands");
1433 unsigned Reg = getOperand(1).getReg();
1434 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1435 if (getOperand(i).getReg() != Reg)
1440 bool MachineInstr::hasUnmodeledSideEffects() const {
1441 if (hasProperty(MCID::UnmodeledSideEffects))
1443 if (isInlineAsm()) {
1444 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1445 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1452 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1454 bool MachineInstr::allDefsAreDead() const {
1455 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1456 const MachineOperand &MO = getOperand(i);
1457 if (!MO.isReg() || MO.isUse())
1465 /// copyImplicitOps - Copy implicit register operands from specified
1466 /// instruction to this instruction.
1467 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1468 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1470 const MachineOperand &MO = MI->getOperand(i);
1471 if (MO.isReg() && MO.isImplicit())
1476 void MachineInstr::dump() const {
1477 dbgs() << " " << *this;
1480 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1481 raw_ostream &CommentOS) {
1482 const LLVMContext &Ctx = MF->getFunction()->getContext();
1483 if (!DL.isUnknown()) { // Print source line info.
1484 DIScope Scope(DL.getScope(Ctx));
1485 // Omit the directory, because it's likely to be long and uninteresting.
1487 CommentOS << Scope.getFilename();
1489 CommentOS << "<unknown>";
1490 CommentOS << ':' << DL.getLine();
1491 if (DL.getCol() != 0)
1492 CommentOS << ':' << DL.getCol();
1493 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1494 if (!InlinedAtDL.isUnknown()) {
1495 CommentOS << " @[ ";
1496 printDebugLoc(InlinedAtDL, MF, CommentOS);
1502 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1503 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1504 const MachineFunction *MF = 0;
1505 const MachineRegisterInfo *MRI = 0;
1506 if (const MachineBasicBlock *MBB = getParent()) {
1507 MF = MBB->getParent();
1509 TM = &MF->getTarget();
1511 MRI = &MF->getRegInfo();
1514 // Save a list of virtual registers.
1515 SmallVector<unsigned, 8> VirtRegs;
1517 // Print explicitly defined operands on the left of an assignment syntax.
1518 unsigned StartOp = 0, e = getNumOperands();
1519 for (; StartOp < e && getOperand(StartOp).isReg() &&
1520 getOperand(StartOp).isDef() &&
1521 !getOperand(StartOp).isImplicit();
1523 if (StartOp != 0) OS << ", ";
1524 getOperand(StartOp).print(OS, TM);
1525 unsigned Reg = getOperand(StartOp).getReg();
1526 if (TargetRegisterInfo::isVirtualRegister(Reg))
1527 VirtRegs.push_back(Reg);
1533 // Print the opcode name.
1534 if (TM && TM->getInstrInfo())
1535 OS << TM->getInstrInfo()->getName(getOpcode());
1539 // Print the rest of the operands.
1540 bool OmittedAnyCallClobbers = false;
1541 bool FirstOp = true;
1542 unsigned AsmDescOp = ~0u;
1543 unsigned AsmOpCount = 0;
1545 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1546 // Print asm string.
1548 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1550 // Print HasSideEffects, IsAlignStack
1551 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1552 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1553 OS << " [sideeffect]";
1554 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1555 OS << " [alignstack]";
1557 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1562 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1563 const MachineOperand &MO = getOperand(i);
1565 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1566 VirtRegs.push_back(MO.getReg());
1568 // Omit call-clobbered registers which aren't used anywhere. This makes
1569 // call instructions much less noisy on targets where calls clobber lots
1570 // of registers. Don't rely on MO.isDead() because we may be called before
1571 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1572 if (MF && isCall() &&
1573 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1574 unsigned Reg = MO.getReg();
1575 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1576 const MachineRegisterInfo &MRI = MF->getRegInfo();
1577 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1578 bool HasAliasLive = false;
1579 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1580 AI.isValid(); ++AI) {
1581 unsigned AliasReg = *AI;
1582 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1583 HasAliasLive = true;
1587 if (!HasAliasLive) {
1588 OmittedAnyCallClobbers = true;
1595 if (FirstOp) FirstOp = false; else OS << ",";
1597 if (i < getDesc().NumOperands) {
1598 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1599 if (MCOI.isPredicate())
1601 if (MCOI.isOptionalDef())
1604 if (isDebugValue() && MO.isMetadata()) {
1605 // Pretty print DBG_VALUE instructions.
1606 const MDNode *MD = MO.getMetadata();
1607 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1608 OS << "!\"" << MDS->getString() << '\"';
1611 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1612 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1613 } else if (i == AsmDescOp && MO.isImm()) {
1614 // Pretty print the inline asm operand descriptor.
1615 OS << '$' << AsmOpCount++;
1616 unsigned Flag = MO.getImm();
1617 switch (InlineAsm::getKind(Flag)) {
1618 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1619 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1620 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1621 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1622 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1623 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1624 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1628 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1630 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1632 OS << ":RC" << RCID;
1635 unsigned TiedTo = 0;
1636 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1637 OS << " tiedto:$" << TiedTo;
1641 // Compute the index of the next operand descriptor.
1642 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1647 // Briefly indicate whether any call clobbers were omitted.
1648 if (OmittedAnyCallClobbers) {
1649 if (!FirstOp) OS << ",";
1653 bool HaveSemi = false;
1655 if (!HaveSemi) OS << ";"; HaveSemi = true;
1658 if (Flags & FrameSetup)
1662 if (!memoperands_empty()) {
1663 if (!HaveSemi) OS << ";"; HaveSemi = true;
1666 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1669 if (llvm::next(i) != e)
1674 // Print the regclass of any virtual registers encountered.
1675 if (MRI && !VirtRegs.empty()) {
1676 if (!HaveSemi) OS << ";"; HaveSemi = true;
1677 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1678 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1679 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1680 for (unsigned j = i+1; j != VirtRegs.size();) {
1681 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1685 if (VirtRegs[i] != VirtRegs[j])
1686 OS << "," << PrintReg(VirtRegs[j]);
1687 VirtRegs.erase(VirtRegs.begin()+j);
1692 // Print debug location information.
1693 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1694 if (!HaveSemi) OS << ";"; HaveSemi = true;
1695 DIVariable DV(getOperand(e - 1).getMetadata());
1696 OS << " line no:" << DV.getLineNumber();
1697 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1698 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1699 if (!InlinedAtDL.isUnknown()) {
1700 OS << " inlined @[ ";
1701 printDebugLoc(InlinedAtDL, MF, OS);
1705 } else if (!debugLoc.isUnknown() && MF) {
1706 if (!HaveSemi) OS << ";"; HaveSemi = true;
1708 printDebugLoc(debugLoc, MF, OS);
1714 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1715 const TargetRegisterInfo *RegInfo,
1716 bool AddIfNotFound) {
1717 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1718 bool hasAliases = isPhysReg &&
1719 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1721 SmallVector<unsigned,4> DeadOps;
1722 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1723 MachineOperand &MO = getOperand(i);
1724 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1726 unsigned Reg = MO.getReg();
1730 if (Reg == IncomingReg) {
1733 // The register is already marked kill.
1735 if (isPhysReg && isRegTiedToDefOperand(i))
1736 // Two-address uses of physregs must not be marked kill.
1741 } else if (hasAliases && MO.isKill() &&
1742 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1743 // A super-register kill already exists.
1744 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1746 if (RegInfo->isSubRegister(IncomingReg, Reg))
1747 DeadOps.push_back(i);
1751 // Trim unneeded kill operands.
1752 while (!DeadOps.empty()) {
1753 unsigned OpIdx = DeadOps.back();
1754 if (getOperand(OpIdx).isImplicit())
1755 RemoveOperand(OpIdx);
1757 getOperand(OpIdx).setIsKill(false);
1761 // If not found, this means an alias of one of the operands is killed. Add a
1762 // new implicit operand if required.
1763 if (!Found && AddIfNotFound) {
1764 addOperand(MachineOperand::CreateReg(IncomingReg,
1773 void MachineInstr::clearRegisterKills(unsigned Reg,
1774 const TargetRegisterInfo *RegInfo) {
1775 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1777 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1778 MachineOperand &MO = getOperand(i);
1779 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1781 unsigned OpReg = MO.getReg();
1782 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1783 MO.setIsKill(false);
1787 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1788 const TargetRegisterInfo *RegInfo,
1789 bool AddIfNotFound) {
1790 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1791 bool hasAliases = isPhysReg &&
1792 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1794 SmallVector<unsigned,4> DeadOps;
1795 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1796 MachineOperand &MO = getOperand(i);
1797 if (!MO.isReg() || !MO.isDef())
1799 unsigned Reg = MO.getReg();
1803 if (Reg == IncomingReg) {
1806 } else if (hasAliases && MO.isDead() &&
1807 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1808 // There exists a super-register that's marked dead.
1809 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1811 if (RegInfo->isSubRegister(IncomingReg, Reg))
1812 DeadOps.push_back(i);
1816 // Trim unneeded dead operands.
1817 while (!DeadOps.empty()) {
1818 unsigned OpIdx = DeadOps.back();
1819 if (getOperand(OpIdx).isImplicit())
1820 RemoveOperand(OpIdx);
1822 getOperand(OpIdx).setIsDead(false);
1826 // If not found, this means an alias of one of the operands is dead. Add a
1827 // new implicit operand if required.
1828 if (Found || !AddIfNotFound)
1831 addOperand(MachineOperand::CreateReg(IncomingReg,
1839 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1840 const TargetRegisterInfo *RegInfo) {
1841 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1842 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1846 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1847 const MachineOperand &MO = getOperand(i);
1848 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1849 MO.getSubReg() == 0)
1853 addOperand(MachineOperand::CreateReg(IncomingReg,
1858 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1859 const TargetRegisterInfo &TRI) {
1860 bool HasRegMask = false;
1861 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1862 MachineOperand &MO = getOperand(i);
1863 if (MO.isRegMask()) {
1867 if (!MO.isReg() || !MO.isDef()) continue;
1868 unsigned Reg = MO.getReg();
1869 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1871 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1873 if (TRI.regsOverlap(*I, Reg)) {
1877 // If there are no uses, including partial uses, the def is dead.
1878 if (Dead) MO.setIsDead();
1881 // This is a call with a register mask operand.
1882 // Mask clobbers are always dead, so add defs for the non-dead defines.
1884 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1886 addRegisterDefined(*I, &TRI);
1890 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1891 // Build up a buffer of hash code components.
1892 SmallVector<size_t, 8> HashComponents;
1893 HashComponents.reserve(MI->getNumOperands() + 1);
1894 HashComponents.push_back(MI->getOpcode());
1895 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1896 const MachineOperand &MO = MI->getOperand(i);
1897 if (MO.isReg() && MO.isDef() &&
1898 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1899 continue; // Skip virtual register defs.
1901 HashComponents.push_back(hash_value(MO));
1903 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1906 void MachineInstr::emitError(StringRef Msg) const {
1907 // Find the source location cookie.
1908 unsigned LocCookie = 0;
1909 const MDNode *LocMD = 0;
1910 for (unsigned i = getNumOperands(); i != 0; --i) {
1911 if (getOperand(i-1).isMetadata() &&
1912 (LocMD = getOperand(i-1).getMetadata()) &&
1913 LocMD->getNumOperands() != 0) {
1914 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1915 LocCookie = CI->getZExtValue();
1921 if (const MachineBasicBlock *MBB = getParent())
1922 if (const MachineFunction *MF = MBB->getParent())
1923 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1924 report_fatal_error(Msg);