1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/MIRYamlMapping.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/IR/Module.h"
22 #include "llvm/Support/MemoryBuffer.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Support/YAMLTraits.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetSubtargetInfo.h"
32 /// This class prints out the machine functions using the MIR serialization
38 MIRPrinter(raw_ostream &OS) : OS(OS) {}
40 void print(const MachineFunction &MF);
42 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
43 void convert(const Module &M, yaml::MachineBasicBlock &YamlMBB,
44 const MachineBasicBlock &MBB);
47 /// This class prints out the machine instructions using the MIR serialization
54 MIPrinter(const Module &M, raw_ostream &OS) : M(M), OS(OS) {}
56 void print(const MachineInstr &MI);
57 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
60 } // end anonymous namespace
65 /// This struct serializes the LLVM IR module.
66 template <> struct BlockScalarTraits<Module> {
67 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
68 Mod.print(OS, nullptr);
70 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
71 llvm_unreachable("LLVM Module is supposed to be parsed separately");
76 } // end namespace yaml
77 } // end namespace llvm
79 void MIRPrinter::print(const MachineFunction &MF) {
80 yaml::MachineFunction YamlMF;
81 YamlMF.Name = MF.getName();
82 YamlMF.Alignment = MF.getAlignment();
83 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
84 YamlMF.HasInlineAsm = MF.hasInlineAsm();
85 convert(YamlMF, MF.getRegInfo());
88 const auto &M = *MF.getFunction()->getParent();
89 for (const auto &MBB : MF) {
90 // TODO: Allow printing of non sequentially numbered MBBs.
91 // This is currently needed as the basic block references get their index
92 // from MBB.getNumber(), thus it should be sequential so that the parser can
93 // map back to the correct MBBs when parsing the output.
94 assert(MBB.getNumber() == I++ &&
95 "Can't print MBBs that aren't sequentially numbered");
97 yaml::MachineBasicBlock YamlMBB;
98 convert(M, YamlMBB, MBB);
99 YamlMF.BasicBlocks.push_back(YamlMBB);
101 yaml::Output Out(OS);
105 void MIRPrinter::convert(yaml::MachineFunction &MF,
106 const MachineRegisterInfo &RegInfo) {
107 MF.IsSSA = RegInfo.isSSA();
108 MF.TracksRegLiveness = RegInfo.tracksLiveness();
109 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
112 void MIRPrinter::convert(const Module &M, yaml::MachineBasicBlock &YamlMBB,
113 const MachineBasicBlock &MBB) {
114 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
115 YamlMBB.ID = (unsigned)MBB.getNumber();
116 // TODO: Serialize unnamed BB references.
117 if (const auto *BB = MBB.getBasicBlock())
118 YamlMBB.Name = BB->hasName() ? BB->getName() : "<unnamed bb>";
121 YamlMBB.Alignment = MBB.getAlignment();
122 YamlMBB.AddressTaken = MBB.hasAddressTaken();
123 YamlMBB.IsLandingPad = MBB.isLandingPad();
125 // Print the machine instructions.
126 YamlMBB.Instructions.reserve(MBB.size());
128 for (const auto &MI : MBB) {
129 raw_string_ostream StrOS(Str);
130 MIPrinter(M, StrOS).print(MI);
131 YamlMBB.Instructions.push_back(StrOS.str());
136 void MIPrinter::print(const MachineInstr &MI) {
137 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
138 const auto *TRI = SubTarget.getRegisterInfo();
139 assert(TRI && "Expected target register info");
140 const auto *TII = SubTarget.getInstrInfo();
141 assert(TII && "Expected target instruction info");
143 unsigned I = 0, E = MI.getNumOperands();
144 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
145 !MI.getOperand(I).isImplicit();
149 print(MI.getOperand(I), TRI);
154 OS << TII->getName(MI.getOpcode());
155 // TODO: Print the instruction flags, machine mem operands.
159 bool NeedComma = false;
163 print(MI.getOperand(I), TRI);
168 static void printReg(unsigned Reg, raw_ostream &OS,
169 const TargetRegisterInfo *TRI) {
170 // TODO: Print Stack Slots.
171 // TODO: Print virtual registers.
174 else if (Reg < TRI->getNumRegs())
175 OS << '%' << StringRef(TRI->getName(Reg)).lower();
177 llvm_unreachable("Can't print this kind of register yet");
180 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
181 switch (Op.getType()) {
182 case MachineOperand::MO_Register:
183 // TODO: Print register flags.
184 printReg(Op.getReg(), OS, TRI);
185 // TODO: Print sub register.
187 case MachineOperand::MO_Immediate:
190 case MachineOperand::MO_MachineBasicBlock:
191 OS << "%bb." << Op.getMBB()->getNumber();
192 if (const auto *BB = Op.getMBB()->getBasicBlock()) {
194 OS << '.' << BB->getName();
197 case MachineOperand::MO_GlobalAddress:
198 // FIXME: Make this faster - print as operand will create a slot tracker to
199 // print unnamed values for the whole module every time it's called, which
201 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, &M);
202 // TODO: Print offset and target flags.
205 // TODO: Print the other machine operands.
206 llvm_unreachable("Can't print this machine operand at the moment");
210 void llvm::printMIR(raw_ostream &OS, const Module &M) {
211 yaml::Output Out(OS);
212 Out << const_cast<Module &>(M);
215 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
216 MIRPrinter Printer(OS);