1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/MIRYamlMapping.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/IR/Module.h"
22 #include "llvm/Support/MemoryBuffer.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Support/YAMLTraits.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetSubtargetInfo.h"
32 /// This class prints out the machine functions using the MIR serialization
38 MIRPrinter(raw_ostream &OS) : OS(OS) {}
40 void print(const MachineFunction &MF);
42 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
43 void convert(yaml::MachineBasicBlock &YamlMBB, const MachineBasicBlock &MBB);
46 /// This class prints out the machine instructions using the MIR serialization
52 MIPrinter(raw_ostream &OS) : OS(OS) {}
54 void print(const MachineInstr &MI);
55 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
58 } // end anonymous namespace
63 /// This struct serializes the LLVM IR module.
64 template <> struct BlockScalarTraits<Module> {
65 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
66 Mod.print(OS, nullptr);
68 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
69 llvm_unreachable("LLVM Module is supposed to be parsed separately");
74 } // end namespace yaml
75 } // end namespace llvm
77 void MIRPrinter::print(const MachineFunction &MF) {
78 yaml::MachineFunction YamlMF;
79 YamlMF.Name = MF.getName();
80 YamlMF.Alignment = MF.getAlignment();
81 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
82 YamlMF.HasInlineAsm = MF.hasInlineAsm();
83 convert(YamlMF, MF.getRegInfo());
86 for (const auto &MBB : MF) {
87 // TODO: Allow printing of non sequentially numbered MBBs.
88 // This is currently needed as the basic block references get their index
89 // from MBB.getNumber(), thus it should be sequential so that the parser can
90 // map back to the correct MBBs when parsing the output.
91 assert(MBB.getNumber() == I++ &&
92 "Can't print MBBs that aren't sequentially numbered");
94 yaml::MachineBasicBlock YamlMBB;
95 convert(YamlMBB, MBB);
96 YamlMF.BasicBlocks.push_back(YamlMBB);
102 void MIRPrinter::convert(yaml::MachineFunction &MF,
103 const MachineRegisterInfo &RegInfo) {
104 MF.IsSSA = RegInfo.isSSA();
105 MF.TracksRegLiveness = RegInfo.tracksLiveness();
106 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
109 void MIRPrinter::convert(yaml::MachineBasicBlock &YamlMBB,
110 const MachineBasicBlock &MBB) {
111 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
112 YamlMBB.ID = (unsigned)MBB.getNumber();
113 // TODO: Serialize unnamed BB references.
114 if (const auto *BB = MBB.getBasicBlock())
115 YamlMBB.Name = BB->hasName() ? BB->getName() : "<unnamed bb>";
118 YamlMBB.Alignment = MBB.getAlignment();
119 YamlMBB.AddressTaken = MBB.hasAddressTaken();
120 YamlMBB.IsLandingPad = MBB.isLandingPad();
122 // Print the machine instructions.
123 YamlMBB.Instructions.reserve(MBB.size());
125 for (const auto &MI : MBB) {
126 raw_string_ostream StrOS(Str);
127 MIPrinter(StrOS).print(MI);
128 YamlMBB.Instructions.push_back(StrOS.str());
133 void MIPrinter::print(const MachineInstr &MI) {
134 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
135 const auto *TRI = SubTarget.getRegisterInfo();
136 assert(TRI && "Expected target register info");
137 const auto *TII = SubTarget.getInstrInfo();
138 assert(TII && "Expected target instruction info");
140 unsigned I = 0, E = MI.getNumOperands();
141 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
142 !MI.getOperand(I).isImplicit();
146 print(MI.getOperand(I), TRI);
151 OS << TII->getName(MI.getOpcode());
152 // TODO: Print the instruction flags, machine mem operands.
156 bool NeedComma = false;
160 print(MI.getOperand(I), TRI);
165 static void printReg(unsigned Reg, raw_ostream &OS,
166 const TargetRegisterInfo *TRI) {
167 // TODO: Print Stack Slots.
168 // TODO: Print virtual registers.
171 else if (Reg < TRI->getNumRegs())
172 OS << '%' << StringRef(TRI->getName(Reg)).lower();
174 llvm_unreachable("Can't print this kind of register yet");
177 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
178 switch (Op.getType()) {
179 case MachineOperand::MO_Register:
180 // TODO: Print register flags.
181 printReg(Op.getReg(), OS, TRI);
182 // TODO: Print sub register.
184 case MachineOperand::MO_Immediate:
187 case MachineOperand::MO_MachineBasicBlock:
188 OS << "%bb." << Op.getMBB()->getNumber();
189 if (const auto *BB = Op.getMBB()->getBasicBlock()) {
191 OS << '.' << BB->getName();
195 // TODO: Print the other machine operands.
196 llvm_unreachable("Can't print this machine operand at the moment");
200 void llvm::printMIR(raw_ostream &OS, const Module &M) {
201 yaml::Output Out(OS);
202 Out << const_cast<Module &>(M);
205 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
206 MIRPrinter Printer(OS);