1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MIRYamlMapping.h"
21 #include "llvm/IR/BasicBlock.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/IR/ModuleSlotTracker.h"
24 #include "llvm/Support/MemoryBuffer.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Support/YAMLTraits.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
34 /// This class prints out the machine functions using the MIR serialization
38 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
41 MIRPrinter(raw_ostream &OS) : OS(OS) {}
43 void print(const MachineFunction &MF);
45 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
46 const TargetRegisterInfo *TRI);
47 void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
48 void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
49 const MachineBasicBlock &MBB);
52 void initRegisterMaskIds(const MachineFunction &MF);
55 /// This class prints out the machine instructions using the MIR serialization
59 ModuleSlotTracker &MST;
60 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
63 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
64 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
65 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds) {}
67 void print(const MachineInstr &MI);
68 void printMBBReference(const MachineBasicBlock &MBB);
69 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
72 } // end anonymous namespace
77 /// This struct serializes the LLVM IR module.
78 template <> struct BlockScalarTraits<Module> {
79 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
80 Mod.print(OS, nullptr);
82 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
83 llvm_unreachable("LLVM Module is supposed to be parsed separately");
88 } // end namespace yaml
89 } // end namespace llvm
91 void MIRPrinter::print(const MachineFunction &MF) {
92 initRegisterMaskIds(MF);
94 yaml::MachineFunction YamlMF;
95 YamlMF.Name = MF.getName();
96 YamlMF.Alignment = MF.getAlignment();
97 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
98 YamlMF.HasInlineAsm = MF.hasInlineAsm();
99 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
100 convert(YamlMF.FrameInfo, *MF.getFrameInfo());
103 ModuleSlotTracker MST(MF.getFunction()->getParent());
104 for (const auto &MBB : MF) {
105 // TODO: Allow printing of non sequentially numbered MBBs.
106 // This is currently needed as the basic block references get their index
107 // from MBB.getNumber(), thus it should be sequential so that the parser can
108 // map back to the correct MBBs when parsing the output.
109 assert(MBB.getNumber() == I++ &&
110 "Can't print MBBs that aren't sequentially numbered");
112 yaml::MachineBasicBlock YamlMBB;
113 convert(MST, YamlMBB, MBB);
114 YamlMF.BasicBlocks.push_back(YamlMBB);
116 yaml::Output Out(OS);
120 void MIRPrinter::convert(yaml::MachineFunction &MF,
121 const MachineRegisterInfo &RegInfo,
122 const TargetRegisterInfo *TRI) {
123 MF.IsSSA = RegInfo.isSSA();
124 MF.TracksRegLiveness = RegInfo.tracksLiveness();
125 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
127 // Print the virtual register definitions.
128 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
129 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
130 yaml::VirtualRegisterDefinition VReg;
133 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
134 MF.VirtualRegisters.push_back(VReg);
138 void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
139 const MachineFrameInfo &MFI) {
140 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
141 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
142 YamlMFI.HasStackMap = MFI.hasStackMap();
143 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
144 YamlMFI.StackSize = MFI.getStackSize();
145 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
146 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
147 YamlMFI.AdjustsStack = MFI.adjustsStack();
148 YamlMFI.HasCalls = MFI.hasCalls();
149 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
150 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
151 YamlMFI.HasVAStart = MFI.hasVAStart();
152 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
155 void MIRPrinter::convert(ModuleSlotTracker &MST,
156 yaml::MachineBasicBlock &YamlMBB,
157 const MachineBasicBlock &MBB) {
158 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
159 YamlMBB.ID = (unsigned)MBB.getNumber();
160 // TODO: Serialize unnamed BB references.
161 if (const auto *BB = MBB.getBasicBlock())
162 YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
164 YamlMBB.Name.Value = "";
165 YamlMBB.Alignment = MBB.getAlignment();
166 YamlMBB.AddressTaken = MBB.hasAddressTaken();
167 YamlMBB.IsLandingPad = MBB.isLandingPad();
168 for (const auto *SuccMBB : MBB.successors()) {
170 raw_string_ostream StrOS(Str);
171 MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
172 YamlMBB.Successors.push_back(StrOS.str());
175 // Print the machine instructions.
176 YamlMBB.Instructions.reserve(MBB.size());
178 for (const auto &MI : MBB) {
179 raw_string_ostream StrOS(Str);
180 MIPrinter(StrOS, MST, RegisterMaskIds).print(MI);
181 YamlMBB.Instructions.push_back(StrOS.str());
186 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
187 const auto *TRI = MF.getSubtarget().getRegisterInfo();
189 for (const uint32_t *Mask : TRI->getRegMasks())
190 RegisterMaskIds.insert(std::make_pair(Mask, I++));
193 void MIPrinter::print(const MachineInstr &MI) {
194 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
195 const auto *TRI = SubTarget.getRegisterInfo();
196 assert(TRI && "Expected target register info");
197 const auto *TII = SubTarget.getInstrInfo();
198 assert(TII && "Expected target instruction info");
200 unsigned I = 0, E = MI.getNumOperands();
201 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
202 !MI.getOperand(I).isImplicit();
206 print(MI.getOperand(I), TRI);
211 OS << TII->getName(MI.getOpcode());
212 // TODO: Print the instruction flags, machine mem operands.
216 bool NeedComma = false;
220 print(MI.getOperand(I), TRI);
225 static void printReg(unsigned Reg, raw_ostream &OS,
226 const TargetRegisterInfo *TRI) {
227 // TODO: Print Stack Slots.
228 // TODO: Print virtual registers.
231 else if (Reg < TRI->getNumRegs())
232 OS << '%' << StringRef(TRI->getName(Reg)).lower();
234 llvm_unreachable("Can't print this kind of register yet");
237 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
238 OS << "%bb." << MBB.getNumber();
239 if (const auto *BB = MBB.getBasicBlock()) {
241 OS << '.' << BB->getName();
245 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
246 switch (Op.getType()) {
247 case MachineOperand::MO_Register:
248 // TODO: Print the other register flags.
250 OS << (Op.isDef() ? "implicit-def " : "implicit ");
257 printReg(Op.getReg(), OS, TRI);
258 // TODO: Print sub register.
260 case MachineOperand::MO_Immediate:
263 case MachineOperand::MO_MachineBasicBlock:
264 printMBBReference(*Op.getMBB());
266 case MachineOperand::MO_GlobalAddress:
267 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
268 // TODO: Print offset and target flags.
270 case MachineOperand::MO_RegisterMask: {
271 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
272 if (RegMaskInfo != RegisterMaskIds.end())
273 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
275 llvm_unreachable("Can't print this machine register mask yet.");
279 // TODO: Print the other machine operands.
280 llvm_unreachable("Can't print this machine operand at the moment");
284 void llvm::printMIR(raw_ostream &OS, const Module &M) {
285 yaml::Output Out(OS);
286 Out << const_cast<Module &>(M);
289 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
290 MIRPrinter Printer(OS);