1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MIRYamlMapping.h"
24 #include "llvm/IR/BasicBlock.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Instructions.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/Module.h"
29 #include "llvm/IR/ModuleSlotTracker.h"
30 #include "llvm/Support/MemoryBuffer.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Support/YAMLTraits.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
40 /// This structure describes how to print out stack object references.
41 struct FrameIndexOperand {
46 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
47 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
49 /// Return an ordinary stack object reference.
50 static FrameIndexOperand create(StringRef Name, unsigned ID) {
51 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
54 /// Return a fixed stack object reference.
55 static FrameIndexOperand createFixed(unsigned ID) {
56 return FrameIndexOperand("", ID, /*IsFixed=*/true);
60 } // end anonymous namespace
64 /// This class prints out the machine functions using the MIR serialization
68 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
69 /// Maps from stack object indices to operand indices which will be used when
70 /// printing frame index machine operands.
71 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
74 MIRPrinter(raw_ostream &OS) : OS(OS) {}
76 void print(const MachineFunction &MF);
78 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
79 const TargetRegisterInfo *TRI);
80 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
81 const MachineFrameInfo &MFI);
82 void convert(yaml::MachineFunction &MF,
83 const MachineConstantPool &ConstantPool);
84 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
85 const MachineJumpTableInfo &JTI);
86 void convertStackObjects(yaml::MachineFunction &MF,
87 const MachineFrameInfo &MFI, MachineModuleInfo &MMI,
88 ModuleSlotTracker &MST,
89 const TargetRegisterInfo *TRI);
92 void initRegisterMaskIds(const MachineFunction &MF);
95 /// This class prints out the machine instructions using the MIR serialization
99 ModuleSlotTracker &MST;
100 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
101 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
104 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
105 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
106 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
107 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
108 StackObjectOperandMapping(StackObjectOperandMapping) {}
110 void print(const MachineBasicBlock &MBB);
112 void print(const MachineInstr &MI);
113 void printMBBReference(const MachineBasicBlock &MBB);
114 void printIRBlockReference(const BasicBlock &BB);
115 void printIRValueReference(const Value &V);
116 void printStackObjectReference(int FrameIndex);
117 void printOffset(int64_t Offset);
118 void printTargetFlags(const MachineOperand &Op);
119 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
120 void print(const MachineMemOperand &Op);
122 void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
125 } // end namespace llvm
130 /// This struct serializes the LLVM IR module.
131 template <> struct BlockScalarTraits<Module> {
132 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
133 Mod.print(OS, nullptr);
135 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
136 llvm_unreachable("LLVM Module is supposed to be parsed separately");
141 } // end namespace yaml
142 } // end namespace llvm
144 static void printReg(unsigned Reg, raw_ostream &OS,
145 const TargetRegisterInfo *TRI) {
146 // TODO: Print Stack Slots.
149 else if (TargetRegisterInfo::isVirtualRegister(Reg))
150 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
151 else if (Reg < TRI->getNumRegs())
152 OS << '%' << StringRef(TRI->getName(Reg)).lower();
154 llvm_unreachable("Can't print this kind of register yet");
157 static void printReg(unsigned Reg, yaml::StringValue &Dest,
158 const TargetRegisterInfo *TRI) {
159 raw_string_ostream OS(Dest.Value);
160 printReg(Reg, OS, TRI);
163 void MIRPrinter::print(const MachineFunction &MF) {
164 initRegisterMaskIds(MF);
166 yaml::MachineFunction YamlMF;
167 YamlMF.Name = MF.getName();
168 YamlMF.Alignment = MF.getAlignment();
169 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
170 YamlMF.HasInlineAsm = MF.hasInlineAsm();
171 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
172 ModuleSlotTracker MST(MF.getFunction()->getParent());
173 MST.incorporateFunction(*MF.getFunction());
174 convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
175 convertStackObjects(YamlMF, *MF.getFrameInfo(), MF.getMMI(), MST,
176 MF.getSubtarget().getRegisterInfo());
177 if (const auto *ConstantPool = MF.getConstantPool())
178 convert(YamlMF, *ConstantPool);
179 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
180 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
181 raw_string_ostream StrOS(YamlMF.Body.Value.Value);
182 bool IsNewlineNeeded = false;
183 for (const auto &MBB : MF) {
186 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
188 IsNewlineNeeded = true;
191 yaml::Output Out(OS);
195 void MIRPrinter::convert(yaml::MachineFunction &MF,
196 const MachineRegisterInfo &RegInfo,
197 const TargetRegisterInfo *TRI) {
198 MF.IsSSA = RegInfo.isSSA();
199 MF.TracksRegLiveness = RegInfo.tracksLiveness();
200 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
202 // Print the virtual register definitions.
203 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
204 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
205 yaml::VirtualRegisterDefinition VReg;
208 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
209 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
211 printReg(PreferredReg, VReg.PreferredRegister, TRI);
212 MF.VirtualRegisters.push_back(VReg);
215 // Print the live ins.
216 for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
217 yaml::MachineFunctionLiveIn LiveIn;
218 printReg(I->first, LiveIn.Register, TRI);
220 printReg(I->second, LiveIn.VirtualRegister, TRI);
221 MF.LiveIns.push_back(LiveIn);
223 // The used physical register mask is printed as an inverted callee saved
225 const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
226 if (UsedPhysRegMask.none())
228 std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
229 for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
230 if (!UsedPhysRegMask[I]) {
231 yaml::FlowStringValue Reg;
232 printReg(I, Reg, TRI);
233 CalleeSavedRegisters.push_back(Reg);
236 MF.CalleeSavedRegisters = CalleeSavedRegisters;
239 void MIRPrinter::convert(ModuleSlotTracker &MST,
240 yaml::MachineFrameInfo &YamlMFI,
241 const MachineFrameInfo &MFI) {
242 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
243 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
244 YamlMFI.HasStackMap = MFI.hasStackMap();
245 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
246 YamlMFI.StackSize = MFI.getStackSize();
247 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
248 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
249 YamlMFI.AdjustsStack = MFI.adjustsStack();
250 YamlMFI.HasCalls = MFI.hasCalls();
251 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
252 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
253 YamlMFI.HasVAStart = MFI.hasVAStart();
254 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
255 if (MFI.getSavePoint()) {
256 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
257 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
258 .printMBBReference(*MFI.getSavePoint());
260 if (MFI.getRestorePoint()) {
261 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
262 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
263 .printMBBReference(*MFI.getRestorePoint());
267 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
268 const MachineFrameInfo &MFI,
269 MachineModuleInfo &MMI,
270 ModuleSlotTracker &MST,
271 const TargetRegisterInfo *TRI) {
272 // Process fixed stack objects.
274 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
275 if (MFI.isDeadObjectIndex(I))
278 yaml::FixedMachineStackObject YamlObject;
280 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
281 ? yaml::FixedMachineStackObject::SpillSlot
282 : yaml::FixedMachineStackObject::DefaultType;
283 YamlObject.Offset = MFI.getObjectOffset(I);
284 YamlObject.Size = MFI.getObjectSize(I);
285 YamlObject.Alignment = MFI.getObjectAlignment(I);
286 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
287 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
288 MF.FixedStackObjects.push_back(YamlObject);
289 StackObjectOperandMapping.insert(
290 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
293 // Process ordinary stack objects.
295 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
296 if (MFI.isDeadObjectIndex(I))
299 yaml::MachineStackObject YamlObject;
301 if (const auto *Alloca = MFI.getObjectAllocation(I))
302 YamlObject.Name.Value =
303 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
304 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
305 ? yaml::MachineStackObject::SpillSlot
306 : MFI.isVariableSizedObjectIndex(I)
307 ? yaml::MachineStackObject::VariableSized
308 : yaml::MachineStackObject::DefaultType;
309 YamlObject.Offset = MFI.getObjectOffset(I);
310 YamlObject.Size = MFI.getObjectSize(I);
311 YamlObject.Alignment = MFI.getObjectAlignment(I);
313 MF.StackObjects.push_back(YamlObject);
314 StackObjectOperandMapping.insert(std::make_pair(
315 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
318 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
319 yaml::StringValue Reg;
320 printReg(CSInfo.getReg(), Reg, TRI);
321 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
322 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
323 "Invalid stack object index");
324 const FrameIndexOperand &StackObject = StackObjectInfo->second;
325 if (StackObject.IsFixed)
326 MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
328 MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
330 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
331 auto LocalObject = MFI.getLocalFrameObjectMap(I);
332 auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
333 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
334 "Invalid stack object index");
335 const FrameIndexOperand &StackObject = StackObjectInfo->second;
336 assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
337 MF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
340 // Print the stack object references in the frame information class after
341 // converting the stack objects.
342 if (MFI.hasStackProtectorIndex()) {
343 raw_string_ostream StrOS(MF.FrameInfo.StackProtector.Value);
344 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
345 .printStackObjectReference(MFI.getStackProtectorIndex());
348 // Print the debug variable information.
349 for (MachineModuleInfo::VariableDbgInfo &DebugVar :
350 MMI.getVariableDbgInfo()) {
351 auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
352 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
353 "Invalid stack object index");
354 const FrameIndexOperand &StackObject = StackObjectInfo->second;
355 assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
356 auto &Object = MF.StackObjects[StackObject.ID];
358 raw_string_ostream StrOS(Object.DebugVar.Value);
359 DebugVar.Var->printAsOperand(StrOS, MST);
362 raw_string_ostream StrOS(Object.DebugExpr.Value);
363 DebugVar.Expr->printAsOperand(StrOS, MST);
366 raw_string_ostream StrOS(Object.DebugLoc.Value);
367 DebugVar.Loc->printAsOperand(StrOS, MST);
372 void MIRPrinter::convert(yaml::MachineFunction &MF,
373 const MachineConstantPool &ConstantPool) {
375 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
376 // TODO: Serialize target specific constant pool entries.
377 if (Constant.isMachineConstantPoolEntry())
378 llvm_unreachable("Can't print target specific constant pool entries yet");
380 yaml::MachineConstantPoolValue YamlConstant;
382 raw_string_ostream StrOS(Str);
383 Constant.Val.ConstVal->printAsOperand(StrOS);
384 YamlConstant.ID = ID++;
385 YamlConstant.Value = StrOS.str();
386 YamlConstant.Alignment = Constant.getAlignment();
387 MF.Constants.push_back(YamlConstant);
391 void MIRPrinter::convert(ModuleSlotTracker &MST,
392 yaml::MachineJumpTable &YamlJTI,
393 const MachineJumpTableInfo &JTI) {
394 YamlJTI.Kind = JTI.getEntryKind();
396 for (const auto &Table : JTI.getJumpTables()) {
398 yaml::MachineJumpTable::Entry Entry;
400 for (const auto *MBB : Table.MBBs) {
401 raw_string_ostream StrOS(Str);
402 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
403 .printMBBReference(*MBB);
404 Entry.Blocks.push_back(StrOS.str());
407 YamlJTI.Entries.push_back(Entry);
411 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
412 const auto *TRI = MF.getSubtarget().getRegisterInfo();
414 for (const uint32_t *Mask : TRI->getRegMasks())
415 RegisterMaskIds.insert(std::make_pair(Mask, I++));
418 void MIPrinter::print(const MachineBasicBlock &MBB) {
419 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
420 OS << "bb." << MBB.getNumber();
421 bool HasAttributes = false;
422 if (const auto *BB = MBB.getBasicBlock()) {
424 OS << "." << BB->getName();
426 HasAttributes = true;
428 int Slot = MST.getLocalSlot(BB);
430 OS << "<ir-block badref>";
432 OS << (Twine("%ir-block.") + Twine(Slot)).str();
435 if (MBB.hasAddressTaken()) {
436 OS << (HasAttributes ? ", " : " (");
437 OS << "address-taken";
438 HasAttributes = true;
440 if (MBB.isLandingPad()) {
441 OS << (HasAttributes ? ", " : " (");
443 HasAttributes = true;
445 if (MBB.getAlignment()) {
446 OS << (HasAttributes ? ", " : " (");
447 OS << "align " << MBB.getAlignment();
448 HasAttributes = true;
454 bool HasLineAttributes = false;
455 // Print the successors
456 if (!MBB.succ_empty()) {
457 OS.indent(2) << "successors: ";
458 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
459 if (I != MBB.succ_begin())
461 printMBBReference(**I);
462 if (MBB.hasSuccessorWeights())
463 OS << '(' << MBB.getSuccWeight(I) << ')';
466 HasLineAttributes = true;
469 // Print the live in registers.
470 const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
471 assert(TRI && "Expected target register info");
472 if (!MBB.livein_empty()) {
473 OS.indent(2) << "liveins: ";
474 for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
475 if (I != MBB.livein_begin())
477 printReg(*I, OS, TRI);
480 HasLineAttributes = true;
483 if (HasLineAttributes)
485 bool IsInBundle = false;
486 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
487 const MachineInstr &MI = *I;
488 if (IsInBundle && !MI.isInsideBundle()) {
489 OS.indent(2) << "}\n";
492 OS.indent(IsInBundle ? 4 : 2);
494 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
501 OS.indent(2) << "}\n";
504 void MIPrinter::print(const MachineInstr &MI) {
505 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
506 const auto *TRI = SubTarget.getRegisterInfo();
507 assert(TRI && "Expected target register info");
508 const auto *TII = SubTarget.getInstrInfo();
509 assert(TII && "Expected target instruction info");
510 if (MI.isCFIInstruction())
511 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
513 unsigned I = 0, E = MI.getNumOperands();
514 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
515 !MI.getOperand(I).isImplicit();
519 print(MI.getOperand(I), TRI);
524 if (MI.getFlag(MachineInstr::FrameSetup))
525 OS << "frame-setup ";
526 OS << TII->getName(MI.getOpcode());
530 bool NeedComma = false;
534 print(MI.getOperand(I), TRI);
538 if (MI.getDebugLoc()) {
541 OS << " debug-location ";
542 MI.getDebugLoc()->printAsOperand(OS, MST);
545 if (!MI.memoperands_empty()) {
547 bool NeedComma = false;
548 for (const auto *Op : MI.memoperands()) {
557 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
558 OS << "%bb." << MBB.getNumber();
559 if (const auto *BB = MBB.getBasicBlock()) {
561 OS << '.' << BB->getName();
565 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
568 printLLVMNameWithoutPrefix(OS, BB.getName());
571 const Function *F = BB.getParent();
573 if (F == MST.getCurrentFunction()) {
574 Slot = MST.getLocalSlot(&BB);
576 ModuleSlotTracker CustomMST(F->getParent(),
577 /*ShouldInitializeAllMetadata=*/false);
578 CustomMST.incorporateFunction(*F);
579 Slot = CustomMST.getLocalSlot(&BB);
587 void MIPrinter::printIRValueReference(const Value &V) {
590 printLLVMNameWithoutPrefix(OS, V.getName());
593 // TODO: Serialize the unnamed IR value references.
594 OS << "<unserializable ir value>";
597 void MIPrinter::printStackObjectReference(int FrameIndex) {
598 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
599 assert(ObjectInfo != StackObjectOperandMapping.end() &&
600 "Invalid frame index");
601 const FrameIndexOperand &Operand = ObjectInfo->second;
602 if (Operand.IsFixed) {
603 OS << "%fixed-stack." << Operand.ID;
606 OS << "%stack." << Operand.ID;
607 if (!Operand.Name.empty())
608 OS << '.' << Operand.Name;
611 void MIPrinter::printOffset(int64_t Offset) {
615 OS << " - " << -Offset;
618 OS << " + " << Offset;
621 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
622 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
623 for (const auto &I : Flags) {
631 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
632 if (!Op.getTargetFlags())
635 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
636 assert(TII && "expected instruction info");
637 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
638 OS << "target-flags(";
639 const bool HasDirectFlags = Flags.first;
640 const bool HasBitmaskFlags = Flags.second;
641 if (!HasDirectFlags && !HasBitmaskFlags) {
645 if (HasDirectFlags) {
646 if (const auto *Name = getTargetFlagName(TII, Flags.first))
649 OS << "<unknown target flag>";
651 if (!HasBitmaskFlags) {
655 bool IsCommaNeeded = HasDirectFlags;
656 unsigned BitMask = Flags.second;
657 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
658 for (const auto &Mask : BitMasks) {
659 // Check if the flag's bitmask has the bits of the current mask set.
660 if ((BitMask & Mask.first) == Mask.first) {
663 IsCommaNeeded = true;
665 // Clear the bits which were serialized from the flag's bitmask.
666 BitMask &= ~(Mask.first);
670 // When the resulting flag's bitmask isn't zero, we know that we didn't
671 // serialize all of the bit flags.
674 OS << "<unknown bitmask target flag>";
679 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
680 const auto *TII = MF.getSubtarget().getInstrInfo();
681 assert(TII && "expected instruction info");
682 auto Indices = TII->getSerializableTargetIndices();
683 for (const auto &I : Indices) {
684 if (I.first == Index) {
691 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
692 printTargetFlags(Op);
693 switch (Op.getType()) {
694 case MachineOperand::MO_Register:
695 // FIXME: Serialize the tied register.
697 OS << (Op.isDef() ? "implicit-def " : "implicit ");
698 if (Op.isInternalRead())
706 if (Op.isEarlyClobber())
707 OS << "early-clobber ";
710 printReg(Op.getReg(), OS, TRI);
711 // Print the sub register.
712 if (Op.getSubReg() != 0)
713 OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
715 case MachineOperand::MO_Immediate:
718 case MachineOperand::MO_CImmediate:
719 Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
721 case MachineOperand::MO_FPImmediate:
722 Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
724 case MachineOperand::MO_MachineBasicBlock:
725 printMBBReference(*Op.getMBB());
727 case MachineOperand::MO_FrameIndex:
728 printStackObjectReference(Op.getIndex());
730 case MachineOperand::MO_ConstantPoolIndex:
731 OS << "%const." << Op.getIndex();
732 printOffset(Op.getOffset());
734 case MachineOperand::MO_TargetIndex: {
735 OS << "target-index(";
736 if (const auto *Name = getTargetIndexName(
737 *Op.getParent()->getParent()->getParent(), Op.getIndex()))
742 printOffset(Op.getOffset());
745 case MachineOperand::MO_JumpTableIndex:
746 OS << "%jump-table." << Op.getIndex();
748 case MachineOperand::MO_ExternalSymbol:
750 printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
751 printOffset(Op.getOffset());
753 case MachineOperand::MO_GlobalAddress:
754 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
755 printOffset(Op.getOffset());
757 case MachineOperand::MO_BlockAddress:
758 OS << "blockaddress(";
759 Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
762 printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
764 printOffset(Op.getOffset());
766 case MachineOperand::MO_RegisterMask: {
767 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
768 if (RegMaskInfo != RegisterMaskIds.end())
769 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
771 llvm_unreachable("Can't print this machine register mask yet.");
774 case MachineOperand::MO_RegisterLiveOut: {
775 const uint32_t *RegMask = Op.getRegLiveOut();
777 bool IsCommaNeeded = false;
778 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
779 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
782 printReg(Reg, OS, TRI);
783 IsCommaNeeded = true;
789 case MachineOperand::MO_Metadata:
790 Op.getMetadata()->printAsOperand(OS, MST);
792 case MachineOperand::MO_CFIIndex: {
793 const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
794 print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
798 // TODO: Print the other machine operands.
799 llvm_unreachable("Can't print this machine operand at the moment");
803 void MIPrinter::print(const MachineMemOperand &Op) {
805 // TODO: Print operand's target specific flags.
808 if (Op.isNonTemporal())
809 OS << "non-temporal ";
810 if (Op.isInvariant())
815 assert(Op.isStore() && "Non load machine operand must be a store");
818 OS << Op.getSize() << (Op.isLoad() ? " from " : " into ");
819 if (const Value *Val = Op.getValue()) {
820 printIRValueReference(*Val);
822 const PseudoSourceValue *PVal = Op.getPseudoValue();
823 assert(PVal && "Expected a pseudo source value");
824 switch (PVal->kind()) {
825 case PseudoSourceValue::Stack:
828 case PseudoSourceValue::GOT:
831 case PseudoSourceValue::JumpTable:
834 case PseudoSourceValue::ConstantPool:
835 OS << "constant-pool";
837 case PseudoSourceValue::FixedStack:
838 printStackObjectReference(
839 cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
841 case PseudoSourceValue::GlobalValueCallEntry:
842 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
843 OS, /*PrintType=*/false, MST);
845 case PseudoSourceValue::ExternalSymbolCallEntry:
847 printLLVMNameWithoutPrefix(
848 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
852 printOffset(Op.getOffset());
853 if (Op.getBaseAlignment() != Op.getSize())
854 OS << ", align " << Op.getBaseAlignment();
855 auto AAInfo = Op.getAAInfo();
858 AAInfo.TBAA->printAsOperand(OS, MST);
861 OS << ", !alias.scope ";
862 AAInfo.Scope->printAsOperand(OS, MST);
864 if (AAInfo.NoAlias) {
866 AAInfo.NoAlias->printAsOperand(OS, MST);
868 if (Op.getRanges()) {
870 Op.getRanges()->printAsOperand(OS, MST);
875 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
876 const TargetRegisterInfo *TRI) {
877 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
882 printReg(Reg, OS, TRI);
885 void MIPrinter::print(const MCCFIInstruction &CFI,
886 const TargetRegisterInfo *TRI) {
887 switch (CFI.getOperation()) {
888 case MCCFIInstruction::OpSameValue:
889 OS << ".cfi_same_value ";
892 printCFIRegister(CFI.getRegister(), OS, TRI);
894 case MCCFIInstruction::OpOffset:
895 OS << ".cfi_offset ";
898 printCFIRegister(CFI.getRegister(), OS, TRI);
899 OS << ", " << CFI.getOffset();
901 case MCCFIInstruction::OpDefCfaRegister:
902 OS << ".cfi_def_cfa_register ";
905 printCFIRegister(CFI.getRegister(), OS, TRI);
907 case MCCFIInstruction::OpDefCfaOffset:
908 OS << ".cfi_def_cfa_offset ";
911 OS << CFI.getOffset();
913 case MCCFIInstruction::OpDefCfa:
914 OS << ".cfi_def_cfa ";
917 printCFIRegister(CFI.getRegister(), OS, TRI);
918 OS << ", " << CFI.getOffset();
921 // TODO: Print the other CFI Operations.
922 OS << "<unserializable cfi operation>";
927 void llvm::printMIR(raw_ostream &OS, const Module &M) {
928 yaml::Output Out(OS);
929 Out << const_cast<Module &>(M);
932 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
933 MIRPrinter Printer(OS);