1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/ADT/DepthFirstIterator.h"
36 #include "llvm/ADT/SmallPtrSet.h"
37 #include "llvm/ADT/STLExtras.h"
38 #include "llvm/Config/alloca.h"
42 char LiveVariables::ID = 0;
43 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
45 void LiveVariables::VarInfo::dump() const {
46 cerr << " Alive in blocks: ";
47 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
48 if (AliveBlocks[i]) cerr << i << ", ";
49 cerr << " Used in blocks: ";
50 for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i)
51 if (UsedBlocks[i]) cerr << i << ", ";
52 cerr << "\n Killed by:";
54 cerr << " No instructions.\n";
56 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
57 cerr << "\n #" << i << ": " << *Kills[i];
62 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
63 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
64 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
65 "getVarInfo: not a virtual register!");
66 RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
67 if (RegIdx >= VirtRegInfo.size()) {
68 if (RegIdx >= 2*VirtRegInfo.size())
69 VirtRegInfo.resize(RegIdx*2);
71 VirtRegInfo.resize(2*VirtRegInfo.size());
73 VarInfo &VI = VirtRegInfo[RegIdx];
74 VI.AliveBlocks.resize(MF->getNumBlockIDs());
75 VI.UsedBlocks.resize(MF->getNumBlockIDs());
79 /// KillsRegister - Returns true if the machine instruction kills the specified
81 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
82 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
83 const MachineOperand &MO = MI->getOperand(i);
84 if (MO.isRegister() && MO.isKill()) {
85 unsigned MOReg = MO.getReg();
87 (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
88 TargetRegisterInfo::isPhysicalRegister(Reg) &&
89 RegInfo->isSubRegister(MOReg, Reg)))
96 /// RegisterDefIsDead - Returns true if the register is dead in this machine
98 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
99 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
100 const MachineOperand &MO = MI->getOperand(i);
101 if (MO.isRegister() && MO.isDead()) {
102 unsigned MOReg = MO.getReg();
103 if ((MOReg == Reg) ||
104 (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
105 TargetRegisterInfo::isPhysicalRegister(Reg) &&
106 RegInfo->isSubRegister(MOReg, Reg)))
113 /// ModifiesRegister - Returns true if the machine instruction modifies the
115 bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
116 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
117 const MachineOperand &MO = MI->getOperand(i);
118 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
124 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
125 MachineBasicBlock *DefBlock,
126 MachineBasicBlock *MBB,
127 std::vector<MachineBasicBlock*> &WorkList) {
128 unsigned BBNum = MBB->getNumber();
130 // Check to see if this basic block is one of the killing blocks. If so,
132 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
133 if (VRInfo.Kills[i]->getParent() == MBB) {
134 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
138 if (MBB == DefBlock) return; // Terminate recursion
140 if (VRInfo.AliveBlocks[BBNum])
141 return; // We already know the block is live
143 // Mark the variable known alive in this bb
144 VRInfo.AliveBlocks[BBNum] = true;
146 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
147 E = MBB->pred_rend(); PI != E; ++PI)
148 WorkList.push_back(*PI);
151 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
152 MachineBasicBlock *DefBlock,
153 MachineBasicBlock *MBB) {
154 std::vector<MachineBasicBlock*> WorkList;
155 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
157 while (!WorkList.empty()) {
158 MachineBasicBlock *Pred = WorkList.back();
160 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
164 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
166 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
167 assert(MRI.getVRegDef(reg) && "Register use before def!");
169 unsigned BBNum = MBB->getNumber();
171 VarInfo& VRInfo = getVarInfo(reg);
172 VRInfo.UsedBlocks[BBNum] = true;
175 // Check to see if this basic block is already a kill block.
176 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
177 // Yes, this register is killed in this basic block already. Increase the
178 // live range by updating the kill instruction.
179 VRInfo.Kills.back() = MI;
184 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
185 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
188 assert(MBB != MRI.getVRegDef(reg)->getParent() &&
189 "Should have kill for defblock!");
191 // Add a new kill entry for this basic block. If this virtual register is
192 // already marked as alive in this basic block, that means it is alive in at
193 // least one of the successor blocks, it's not a kill.
194 if (!VRInfo.AliveBlocks[BBNum])
195 VRInfo.Kills.push_back(MI);
197 // Update all dominating blocks to mark them as "known live".
198 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
199 E = MBB->pred_end(); PI != E; ++PI)
200 MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI);
203 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
204 /// implicit defs to a machine instruction if there was an earlier def of its
206 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
207 // Turn previous partial def's into read/mod/write.
208 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
209 MachineInstr *Def = PhysRegPartDef[Reg][i];
211 // First one is just a def. This means the use is reading some undef bits.
213 Def->addOperand(MachineOperand::CreateReg(Reg,
218 Def->addOperand(MachineOperand::CreateReg(Reg,
223 PhysRegPartDef[Reg].clear();
225 // There was an earlier def of a super-register. Add implicit def to that MI.
230 // Add implicit def to A.
231 if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
233 MachineInstr *Def = PhysRegInfo[Reg];
235 if (!Def->findRegisterDefOperand(Reg))
236 Def->addOperand(MachineOperand::CreateReg(Reg,
241 // There is a now a proper use, forget about the last partial use.
242 PhysRegPartUse[Reg] = NULL;
243 PhysRegInfo[Reg] = MI;
244 PhysRegUsed[Reg] = true;
246 // Now reset the use information for the sub-registers.
247 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
248 unsigned SubReg = *SubRegs; ++SubRegs) {
249 // FIXME: Should we do: "PhysRegPartUse[SubReg] = NULL;" here?
250 PhysRegInfo[SubReg] = MI;
251 PhysRegUsed[SubReg] = true;
254 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
255 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
256 // Remember the partial use of this super-register if it was previously
258 bool HasPrevDef = PhysRegInfo[SuperReg] != NULL;
261 // FIXME: This only goes back one level of super-registers. It might miss
263 for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg);
264 unsigned SSReg = *SSRegs; ++SSRegs)
265 if (PhysRegInfo[SSReg] != NULL) {
271 PhysRegInfo[SuperReg] = MI;
272 PhysRegPartUse[SuperReg] = MI;
277 /// addRegisterKills - For all of a register's sub-registers that are killed in
278 /// at this machine instruction, mark them as "killed". (If the machine operand
279 /// isn't found, add it first.)
280 void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
281 SmallSet<unsigned, 4> &SubKills) {
282 if (SubKills.count(Reg) == 0) {
283 MI->addRegisterKilled(Reg, RegInfo, true);
287 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
288 unsigned SubReg = *SubRegs; ++SubRegs)
289 addRegisterKills(SubReg, MI, SubKills);
292 /// HandlePhysRegKill - The recursive version of HandlePhysRegKill. Returns true
295 /// - The register has no sub-registers and the machine instruction is the
296 /// last def/use of the register, or
297 /// - The register has sub-registers and none of them are killed elsewhere.
299 bool LiveVariables::HandlePhysRegKill(unsigned Reg, const MachineInstr *RefMI,
300 SmallSet<unsigned, 4> &SubKills) {
301 const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
303 for (; unsigned SubReg = *SubRegs; ++SubRegs) {
304 const MachineInstr *LastRef = PhysRegInfo[SubReg];
306 if (LastRef != RefMI ||
307 !HandlePhysRegKill(SubReg, RefMI, SubKills))
308 SubKills.insert(SubReg);
312 // No sub-registers, just check if reg is killed by RefMI.
313 if (PhysRegInfo[Reg] == RefMI)
315 } else if (SubKills.empty()) {
316 // None of the sub-registers are killed elsewhere.
323 /// HandlePhysRegKill - Calls the recursive version of HandlePhysRegKill. (See
324 /// above for details.)
325 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
326 SmallSet<unsigned, 4> SubKills;
328 if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
329 // This machine instruction kills this register.
330 RefMI->addRegisterKilled(Reg, RegInfo, true);
334 // Some sub-registers are killed by another machine instruction.
335 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
336 unsigned SubReg = *SubRegs; ++SubRegs)
337 addRegisterKills(SubReg, RefMI, SubKills);
342 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
343 // Does this kill a previous version of this register?
344 if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
345 if (PhysRegUsed[Reg]) {
346 if (!HandlePhysRegKill(Reg, LastRef)) {
347 if (PhysRegPartUse[Reg])
348 PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
350 } else if (PhysRegPartUse[Reg]) {
351 // Add implicit use / kill to last partial use.
352 PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
353 } else if (LastRef != MI) {
354 // Defined, but not used. However, watch out for cases where a super-reg
355 // is also defined on the same MI.
356 LastRef->addRegisterDead(Reg, RegInfo);
360 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
361 unsigned SubReg = *SubRegs; ++SubRegs) {
362 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
363 if (PhysRegUsed[SubReg]) {
364 if (!HandlePhysRegKill(SubReg, LastRef)) {
365 if (PhysRegPartUse[SubReg])
366 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
368 } else if (PhysRegPartUse[SubReg]) {
369 // Add implicit use / kill to last use of a sub-register.
370 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
371 } else if (LastRef != MI) {
372 // This must be a def of the subreg on the same MI.
373 LastRef->addRegisterDead(SubReg, RegInfo);
379 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
380 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
381 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
382 // The larger register is previously defined. Now a smaller part is
383 // being re-defined. Treat it as read/mod/write.
385 // AX = EAX<imp-use,kill>, EAX<imp-def>
386 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
387 true/*IsImp*/,true/*IsKill*/));
388 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
390 PhysRegInfo[SuperReg] = MI;
391 PhysRegUsed[SuperReg] = false;
392 PhysRegPartUse[SuperReg] = NULL;
394 // Remember this partial def.
395 PhysRegPartDef[SuperReg].push_back(MI);
399 PhysRegInfo[Reg] = MI;
400 PhysRegUsed[Reg] = false;
401 PhysRegPartDef[Reg].clear();
402 PhysRegPartUse[Reg] = NULL;
404 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
405 unsigned SubReg = *SubRegs; ++SubRegs) {
406 PhysRegInfo[SubReg] = MI;
407 PhysRegUsed[SubReg] = false;
408 PhysRegPartDef[SubReg].clear();
409 PhysRegPartUse[SubReg] = NULL;
414 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
416 RegInfo = MF->getTarget().getRegisterInfo();
417 MachineRegisterInfo& MRI = mf.getRegInfo();
418 assert(RegInfo && "Target doesn't have register information?");
420 ReservedRegisters = RegInfo->getReservedRegs(mf);
422 unsigned NumRegs = RegInfo->getNumRegs();
423 PhysRegInfo = new MachineInstr*[NumRegs];
424 PhysRegUsed = new bool[NumRegs];
425 PhysRegPartUse = new MachineInstr*[NumRegs];
426 PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs];
427 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
428 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
429 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
430 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
432 /// Get some space for a respectable number of registers.
433 VirtRegInfo.resize(64);
437 // Calculate live variable information in depth first order on the CFG of the
438 // function. This guarantees that we will see the definition of a virtual
439 // register before its uses due to dominance properties of SSA (except for PHI
440 // nodes, which are treated as a special case).
441 MachineBasicBlock *Entry = MF->begin();
442 SmallPtrSet<MachineBasicBlock*,16> Visited;
444 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
445 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
447 MachineBasicBlock *MBB = *DFI;
449 // Mark live-in registers as live-in.
450 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
451 EE = MBB->livein_end(); II != EE; ++II) {
452 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
453 "Cannot have a live-in virtual register!");
454 HandlePhysRegDef(*II, 0);
457 // Loop over all of the instructions, processing them.
458 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
460 MachineInstr *MI = I;
462 // Process all of the operands of the instruction...
463 unsigned NumOperandsToProcess = MI->getNumOperands();
465 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
466 // of the uses. They will be handled in other basic blocks.
467 if (MI->getOpcode() == TargetInstrInfo::PHI)
468 NumOperandsToProcess = 1;
471 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
472 const MachineOperand &MO = MI->getOperand(i);
474 if (MO.isRegister() && MO.isUse() && MO.getReg()) {
475 unsigned MOReg = MO.getReg();
477 if (TargetRegisterInfo::isVirtualRegister(MOReg))
478 HandleVirtRegUse(MOReg, MBB, MI);
479 else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
480 !ReservedRegisters[MOReg])
481 HandlePhysRegUse(MOReg, MI);
486 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
487 const MachineOperand &MO = MI->getOperand(i);
489 if (MO.isRegister() && MO.isDef() && MO.getReg()) {
490 unsigned MOReg = MO.getReg();
492 if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
493 VarInfo &VRInfo = getVarInfo(MOReg);
495 if (VRInfo.AliveBlocks.none())
496 // If vr is not alive in any block, then defaults to dead.
497 VRInfo.Kills.push_back(MI);
498 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
499 !ReservedRegisters[MOReg]) {
500 HandlePhysRegDef(MOReg, MI);
506 // Handle any virtual assignments from PHI nodes which might be at the
507 // bottom of this basic block. We check all of our successor blocks to see
508 // if they have PHI nodes, and if so, we simulate an assignment at the end
509 // of the current block.
510 if (!PHIVarInfo[MBB->getNumber()].empty()) {
511 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
513 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
514 E = VarInfoVec.end(); I != E; ++I)
515 // Mark it alive only in the block we are representing.
516 MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(),
520 // Finally, if the last instruction in the block is a return, make sure to
521 // mark it as using all of the live-out values in the function.
522 if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
523 MachineInstr *Ret = &MBB->back();
525 for (MachineRegisterInfo::liveout_iterator
526 I = MF->getRegInfo().liveout_begin(),
527 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
528 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
529 "Cannot have a live-in virtual register!");
530 HandlePhysRegUse(*I, Ret);
532 // Add live-out registers as implicit uses.
533 if (Ret->findRegisterUseOperandIdx(*I) == -1)
534 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
538 // Loop over PhysRegInfo, killing any registers that are available at the
539 // end of the basic block. This also resets the PhysRegInfo map.
540 for (unsigned i = 0; i != NumRegs; ++i)
542 HandlePhysRegDef(i, 0);
544 // Clear some states between BB's. These are purely local information.
545 for (unsigned i = 0; i != NumRegs; ++i)
546 PhysRegPartDef[i].clear();
548 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
549 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
550 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
553 // Convert and transfer the dead / killed information we have gathered into
554 // VirtRegInfo onto MI's.
555 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
556 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
557 if (VirtRegInfo[i].Kills[j] ==
558 MRI.getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
560 .Kills[j]->addRegisterDead(i +
561 TargetRegisterInfo::FirstVirtualRegister,
565 .Kills[j]->addRegisterKilled(i +
566 TargetRegisterInfo::FirstVirtualRegister,
569 // Check to make sure there are no unreachable blocks in the MC CFG for the
570 // function. If so, it is due to a bug in the instruction selector or some
571 // other part of the code generator if this happens.
573 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
574 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
577 delete[] PhysRegInfo;
578 delete[] PhysRegUsed;
579 delete[] PhysRegPartUse;
580 delete[] PhysRegPartDef;
586 /// instructionChanged - When the address of an instruction changes, this method
587 /// should be called so that live variables can update its internal data
588 /// structures. This removes the records for OldMI, transfering them to the
589 /// records for NewMI.
590 void LiveVariables::instructionChanged(MachineInstr *OldMI,
591 MachineInstr *NewMI) {
592 // If the instruction defines any virtual registers, update the VarInfo,
593 // kill and dead information for the instruction.
594 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
595 MachineOperand &MO = OldMI->getOperand(i);
596 if (MO.isRegister() && MO.getReg() &&
597 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
598 unsigned Reg = MO.getReg();
599 VarInfo &VI = getVarInfo(Reg);
603 addVirtualRegisterDead(Reg, NewMI);
608 addVirtualRegisterKilled(Reg, NewMI);
610 // If this is a kill of the value, update the VI kills list.
611 if (VI.removeKill(OldMI))
612 VI.Kills.push_back(NewMI); // Yes, there was a kill of it
617 /// removeVirtualRegistersKilled - Remove all killed info for the specified
619 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
620 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
621 MachineOperand &MO = MI->getOperand(i);
622 if (MO.isRegister() && MO.isKill()) {
624 unsigned Reg = MO.getReg();
625 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
626 bool removed = getVarInfo(Reg).removeKill(MI);
627 assert(removed && "kill not in register's VarInfo?");
633 /// removeVirtualRegistersDead - Remove all of the dead registers for the
634 /// specified instruction from the live variable information.
635 void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
636 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
637 MachineOperand &MO = MI->getOperand(i);
638 if (MO.isRegister() && MO.isDead()) {
640 unsigned Reg = MO.getReg();
641 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
642 bool removed = getVarInfo(Reg).removeKill(MI);
643 assert(removed && "kill not in register's VarInfo?");
649 /// analyzePHINodes - Gather information about the PHI nodes in here. In
650 /// particular, we want to map the variable information of a virtual register
651 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
653 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
654 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
656 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
657 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
658 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
659 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
660 .push_back(BBI->getOperand(i).getReg());