1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/CFG.h"
34 #include "Support/DepthFirstIterator.h"
37 static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
39 const std::pair<MachineBasicBlock*, unsigned> &
40 LiveVariables::getMachineBasicBlockInfo(MachineBasicBlock *MBB) const{
41 return BBMap.find(MBB->getBasicBlock())->second;
44 /// getIndexMachineBasicBlock() - Given a block index, return the
45 /// MachineBasicBlock corresponding to it.
46 MachineBasicBlock *LiveVariables::getIndexMachineBasicBlock(unsigned Idx) {
47 if (BBIdxMap.empty()) {
48 BBIdxMap.resize(BBMap.size());
49 for (std::map<const BasicBlock*, std::pair<MachineBasicBlock*, unsigned> >
50 ::iterator I = BBMap.begin(), E = BBMap.end(); I != E; ++I) {
51 assert(BBIdxMap.size() > I->second.second &&"Indices are not sequential");
52 assert(BBIdxMap[I->second.second] == 0 && "Multiple idx collision!");
53 BBIdxMap[I->second.second] = I->second.first;
56 assert(Idx < BBIdxMap.size() && "BB Index out of range!");
60 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
61 assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
62 "getVarInfo: not a virtual register!");
63 RegIdx -= MRegisterInfo::FirstVirtualRegister;
64 if (RegIdx >= VirtRegInfo.size()) {
65 if (RegIdx >= 2*VirtRegInfo.size())
66 VirtRegInfo.resize(RegIdx*2);
68 VirtRegInfo.resize(2*VirtRegInfo.size());
70 return VirtRegInfo[RegIdx];
75 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
76 const BasicBlock *BB) {
77 const std::pair<MachineBasicBlock*,unsigned> &Info = BBMap.find(BB)->second;
78 MachineBasicBlock *MBB = Info.first;
79 unsigned BBNum = Info.second;
81 // Check to see if this basic block is one of the killing blocks. If so,
83 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
84 if (VRInfo.Kills[i].first == MBB) {
85 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
89 if (MBB == VRInfo.DefBlock) return; // Terminate recursion
91 if (VRInfo.AliveBlocks.size() <= BBNum)
92 VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
94 if (VRInfo.AliveBlocks[BBNum])
95 return; // We already know the block is live
97 // Mark the variable known alive in this bb
98 VRInfo.AliveBlocks[BBNum] = true;
100 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
101 MarkVirtRegAliveInBlock(VRInfo, *PI);
104 void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
106 // Check to see if this basic block is already a kill block...
107 if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) {
108 // Yes, this register is killed in this basic block already. Increase the
109 // live range by updating the kill instruction.
110 VRInfo.Kills.back().second = MI;
115 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
116 assert(VRInfo.Kills[i].first != MBB && "entry should be at end!");
119 assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!");
121 // Add a new kill entry for this basic block.
122 VRInfo.Kills.push_back(std::make_pair(MBB, MI));
124 // Update all dominating blocks to mark them known live.
125 const BasicBlock *BB = MBB->getBasicBlock();
126 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB);
128 MarkVirtRegAliveInBlock(VRInfo, *PI);
131 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
132 PhysRegInfo[Reg] = MI;
133 PhysRegUsed[Reg] = true;
136 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
137 // Does this kill a previous version of this register?
138 if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
139 if (PhysRegUsed[Reg])
140 RegistersKilled.insert(std::make_pair(LastUse, Reg));
142 RegistersDead.insert(std::make_pair(LastUse, Reg));
144 PhysRegInfo[Reg] = MI;
145 PhysRegUsed[Reg] = false;
147 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
148 *AliasSet; ++AliasSet) {
149 if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) {
150 if (PhysRegUsed[*AliasSet])
151 RegistersKilled.insert(std::make_pair(LastUse, *AliasSet));
153 RegistersDead.insert(std::make_pair(LastUse, *AliasSet));
155 PhysRegInfo[*AliasSet] = MI;
156 PhysRegUsed[*AliasSet] = false;
160 bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
161 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
162 RegInfo = MF.getTarget().getRegisterInfo();
163 assert(RegInfo && "Target doesn't have register information?");
165 // First time though, initialize AllocatablePhysicalRegisters for the target
166 if (AllocatablePhysicalRegisters.empty()) {
167 // Make space, initializing to false...
168 AllocatablePhysicalRegisters.resize(RegInfo->getNumRegs());
170 // Loop over all of the register classes...
171 for (MRegisterInfo::regclass_iterator RCI = RegInfo->regclass_begin(),
172 E = RegInfo->regclass_end(); RCI != E; ++RCI)
173 // Loop over all of the allocatable registers in the function...
174 for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF),
175 E = (*RCI)->allocation_order_end(MF); I != E; ++I)
176 AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable!
181 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
182 BBMap[I->getBasicBlock()] = std::make_pair(I, BBNum++);
184 // PhysRegInfo - Keep track of which instruction was the last use of a
185 // physical register. This is a purely local property, because all physical
186 // register references as presumed dead across basic blocks.
188 MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister];
189 bool PhysRegUsedA[MRegisterInfo::FirstVirtualRegister];
190 std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister,
192 PhysRegInfo = PhysRegInfoA;
193 PhysRegUsed = PhysRegUsedA;
195 /// Get some space for a respectable number of registers...
196 VirtRegInfo.resize(64);
198 // Calculate live variable information in depth first order on the CFG of the
199 // function. This guarantees that we will see the definition of a virtual
200 // register before its uses due to dominance properties of SSA (except for PHI
201 // nodes, which are treated as a special case).
203 const BasicBlock *Entry = MF.getFunction()->begin();
204 for (df_iterator<const BasicBlock*> DFI = df_begin(Entry), E = df_end(Entry);
206 const BasicBlock *BB = *DFI;
207 std::pair<MachineBasicBlock*, unsigned> &BBRec = BBMap.find(BB)->second;
208 MachineBasicBlock *MBB = BBRec.first;
209 unsigned BBNum = BBRec.second;
211 // Loop over all of the instructions, processing them.
212 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
214 MachineInstr *MI = *I;
215 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
217 // Process all of the operands of the instruction...
218 unsigned NumOperandsToProcess = MI->getNumOperands();
220 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
221 // of the uses. They will be handled in other basic blocks.
222 if (MI->getOpcode() == TargetInstrInfo::PHI)
223 NumOperandsToProcess = 1;
225 // Loop over implicit uses, using them.
226 for (const unsigned *ImplicitUses = MID.ImplicitUses;
227 *ImplicitUses; ++ImplicitUses)
228 HandlePhysRegUse(*ImplicitUses, MI);
230 // Process all explicit uses...
231 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
232 MachineOperand &MO = MI->getOperand(i);
234 if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) {
235 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
236 } else if (MO.isPhysicalRegister() &&
237 AllocatablePhysicalRegisters[MO.getReg()]) {
238 HandlePhysRegUse(MO.getReg(), MI);
243 // Loop over implicit defs, defining them.
244 for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
245 *ImplicitDefs; ++ImplicitDefs)
246 HandlePhysRegDef(*ImplicitDefs, MI);
248 // Process all explicit defs...
249 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
250 MachineOperand &MO = MI->getOperand(i);
252 if (MO.isVirtualRegister()) {
253 VarInfo &VRInfo = getVarInfo(MO.getReg());
255 assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
256 VRInfo.DefBlock = MBB; // Created here...
258 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
259 } else if (MO.isPhysicalRegister() &&
260 AllocatablePhysicalRegisters[MO.getReg()]) {
261 HandlePhysRegDef(MO.getReg(), MI);
267 // Handle any virtual assignments from PHI nodes which might be at the
268 // bottom of this basic block. We check all of our successor blocks to see
269 // if they have PHI nodes, and if so, we simulate an assignment at the end
270 // of the current block.
271 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB);
273 MachineBasicBlock *Succ = BBMap.find(*SI)->second.first;
275 // PHI nodes are guaranteed to be at the top of the block...
276 for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end();
277 I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) {
278 MachineInstr *MI = *I;
279 for (unsigned i = 1; ; i += 2)
280 if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
281 MachineOperand &MO = MI->getOperand(i);
282 if (!MO.getVRegValueOrNull()) {
283 VarInfo &VRInfo = getVarInfo(MO.getReg());
285 // Only mark it alive only in the block we are representing...
286 MarkVirtRegAliveInBlock(VRInfo, BB);
287 break; // Found the PHI entry for this block...
293 // Loop over PhysRegInfo, killing any registers that are available at the
294 // end of the basic block. This also resets the PhysRegInfo map.
295 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
297 HandlePhysRegDef(i, 0);
300 // Convert the information we have gathered into VirtRegInfo and transform it
301 // into a form usable by RegistersKilled.
303 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
304 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
305 if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst)
306 RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
307 i + MRegisterInfo::FirstVirtualRegister));
310 RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
311 i + MRegisterInfo::FirstVirtualRegister));