1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/DenseSet.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "LiveRangeCalc.h"
37 #include "VirtRegMap.h"
43 // Switch to the new experimental algorithm for computing live intervals.
45 NewLiveIntervals("new-live-intervals", cl::Hidden,
46 cl::desc("Use new algorithm forcomputing live intervals"));
48 char LiveIntervals::ID = 0;
49 char &llvm::LiveIntervalsID = LiveIntervals::ID;
50 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
51 "Live Interval Analysis", false, false)
52 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
53 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
54 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
55 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
56 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
57 "Live Interval Analysis", false, false)
59 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<AliasAnalysis>();
62 AU.addPreserved<AliasAnalysis>();
63 AU.addRequired<LiveVariables>();
64 AU.addPreserved<LiveVariables>();
65 AU.addPreservedID(MachineLoopInfoID);
66 AU.addRequiredTransitiveID(MachineDominatorsID);
67 AU.addPreservedID(MachineDominatorsID);
68 AU.addPreserved<SlotIndexes>();
69 AU.addRequiredTransitive<SlotIndexes>();
70 MachineFunctionPass::getAnalysisUsage(AU);
73 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
74 DomTree(0), LRCalc(0) {
75 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
78 LiveIntervals::~LiveIntervals() {
82 void LiveIntervals::releaseMemory() {
83 // Free the live intervals themselves.
84 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
85 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
86 VirtRegIntervals.clear();
89 RegMaskBlocks.clear();
91 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
92 delete RegUnitIntervals[i];
93 RegUnitIntervals.clear();
95 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
96 VNInfoAllocator.Reset();
99 /// runOnMachineFunction - Register allocate the whole function
101 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
103 MRI = &MF->getRegInfo();
104 TM = &fn.getTarget();
105 TRI = TM->getRegisterInfo();
106 TII = TM->getInstrInfo();
107 AA = &getAnalysis<AliasAnalysis>();
108 LV = &getAnalysis<LiveVariables>();
109 Indexes = &getAnalysis<SlotIndexes>();
110 DomTree = &getAnalysis<MachineDominatorTree>();
112 LRCalc = new LiveRangeCalc();
113 AllocatableRegs = TRI->getAllocatableSet(fn);
114 ReservedRegs = TRI->getReservedRegs(fn);
116 // Allocate space for all virtual registers.
117 VirtRegIntervals.resize(MRI->getNumVirtRegs());
119 if (NewLiveIntervals) {
120 // This is the new way of computing live intervals.
121 // It is independent of LiveVariables, and it can run at any time.
125 // This is the old way of computing live intervals.
126 // It depends on LiveVariables.
129 computeLiveInRegUnits();
135 /// print - Implement the dump method.
136 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
137 OS << "********** INTERVALS **********\n";
139 // Dump the regunits.
140 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
141 if (LiveInterval *LI = RegUnitIntervals[i])
142 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
144 // Dump the virtregs.
145 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
146 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
147 if (hasInterval(Reg))
148 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n';
154 void LiveIntervals::printInstrs(raw_ostream &OS) const {
155 OS << "********** MACHINEINSTRS **********\n";
156 MF->print(OS, Indexes);
159 void LiveIntervals::dumpInstrs() const {
164 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
165 unsigned Reg = MI.getOperand(MOIdx).getReg();
166 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
167 const MachineOperand &MO = MI.getOperand(i);
170 if (MO.getReg() == Reg && MO.isDef()) {
171 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
172 MI.getOperand(MOIdx).getSubReg() &&
173 (MO.getSubReg() || MO.isImplicit()));
180 /// isPartialRedef - Return true if the specified def at the specific index is
181 /// partially re-defining the specified live interval. A common case of this is
182 /// a definition of the sub-register.
183 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
184 LiveInterval &interval) {
185 if (!MO.getSubReg() || MO.isEarlyClobber())
188 SlotIndex RedefIndex = MIIdx.getRegSlot();
189 const LiveRange *OldLR =
190 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
191 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
193 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
198 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
199 MachineBasicBlock::iterator mi,
203 LiveInterval &interval) {
204 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
206 // Virtual registers may be defined multiple times (due to phi
207 // elimination and 2-addr elimination). Much of what we do only has to be
208 // done once for the vreg. We use an empty interval to detect the first
209 // time we see a vreg.
210 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
211 if (interval.empty()) {
212 // Get the Idx of the defining instructions.
213 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
215 // Make sure the first definition is not a partial redefinition.
216 assert(!MO.readsReg() && "First def cannot also read virtual register "
217 "missing <undef> flag?");
219 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
220 assert(ValNo->id == 0 && "First value in interval is not 0?");
222 // Loop over all of the blocks that the vreg is defined in. There are
223 // two cases we have to handle here. The most common case is a vreg
224 // whose lifetime is contained within a basic block. In this case there
225 // will be a single kill, in MBB, which comes after the definition.
226 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
227 // FIXME: what about dead vars?
229 if (vi.Kills[0] != mi)
230 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
232 killIdx = defIndex.getDeadSlot();
234 // If the kill happens after the definition, we have an intra-block
236 if (killIdx > defIndex) {
237 assert(vi.AliveBlocks.empty() &&
238 "Shouldn't be alive across any blocks!");
239 LiveRange LR(defIndex, killIdx, ValNo);
240 interval.addRange(LR);
241 DEBUG(dbgs() << " +" << LR << "\n");
246 // The other case we handle is when a virtual register lives to the end
247 // of the defining block, potentially live across some blocks, then is
248 // live into some number of blocks, but gets killed. Start by adding a
249 // range that goes from this definition to the end of the defining block.
250 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
251 DEBUG(dbgs() << " +" << NewLR);
252 interval.addRange(NewLR);
254 bool PHIJoin = LV->isPHIJoin(interval.reg);
257 // A phi join register is killed at the end of the MBB and revived as a
258 // new valno in the killing blocks.
259 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
260 DEBUG(dbgs() << " phi-join");
262 // Iterate over all of the blocks that the variable is completely
263 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
265 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
266 E = vi.AliveBlocks.end(); I != E; ++I) {
267 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
268 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock),
270 interval.addRange(LR);
271 DEBUG(dbgs() << " +" << LR);
275 // Finally, this virtual register is live from the start of any killing
276 // block to the 'use' slot of the killing instruction.
277 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
278 MachineInstr *Kill = vi.Kills[i];
279 SlotIndex Start = getMBBStartIdx(Kill->getParent());
280 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
282 // Create interval with one of a NEW value number. Note that this value
283 // number isn't actually defined by an instruction, weird huh? :)
285 assert(getInstructionFromIndex(Start) == 0 &&
286 "PHI def index points at actual instruction.");
287 ValNo = interval.getNextValue(Start, VNInfoAllocator);
289 LiveRange LR(Start, killIdx, ValNo);
290 interval.addRange(LR);
291 DEBUG(dbgs() << " +" << LR);
295 if (MultipleDefsBySameMI(*mi, MOIdx))
296 // Multiple defs of the same virtual register by the same instruction.
297 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
298 // This is likely due to elimination of REG_SEQUENCE instructions. Return
299 // here since there is nothing to do.
302 // If this is the second time we see a virtual register definition, it
303 // must be due to phi elimination or two addr elimination. If this is
304 // the result of two address elimination, then the vreg is one of the
305 // def-and-use register operand.
307 // It may also be partial redef like this:
308 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
309 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
310 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
311 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
312 // If this is a two-address definition, then we have already processed
313 // the live range. The only problem is that we didn't realize there
314 // are actually two values in the live interval. Because of this we
315 // need to take the LiveRegion that defines this register and split it
317 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
319 const LiveRange *OldLR =
320 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
321 VNInfo *OldValNo = OldLR->valno;
322 SlotIndex DefIndex = OldValNo->def.getRegSlot();
324 // Delete the previous value, which should be short and continuous,
325 // because the 2-addr copy must be in the same MBB as the redef.
326 interval.removeRange(DefIndex, RedefIndex);
328 // The new value number (#1) is defined by the instruction we claimed
330 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
332 // Value#0 is now defined by the 2-addr instruction.
333 OldValNo->def = RedefIndex;
335 // Add the new live interval which replaces the range for the input copy.
336 LiveRange LR(DefIndex, RedefIndex, ValNo);
337 DEBUG(dbgs() << " replace range with " << LR);
338 interval.addRange(LR);
340 // If this redefinition is dead, we need to add a dummy unit live
341 // range covering the def slot.
343 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
346 DEBUG(dbgs() << " RESULT: " << interval);
347 } else if (LV->isPHIJoin(interval.reg)) {
348 // In the case of PHI elimination, each variable definition is only
349 // live until the end of the block. We've already taken care of the
350 // rest of the live range.
352 SlotIndex defIndex = MIIdx.getRegSlot();
353 if (MO.isEarlyClobber())
354 defIndex = MIIdx.getRegSlot(true);
356 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
358 SlotIndex killIndex = getMBBEndIdx(mbb);
359 LiveRange LR(defIndex, killIndex, ValNo);
360 interval.addRange(LR);
361 DEBUG(dbgs() << " phi-join +" << LR);
363 llvm_unreachable("Multiply defined register");
367 DEBUG(dbgs() << '\n');
370 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
371 MachineBasicBlock::iterator MI,
375 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
376 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
377 getOrCreateInterval(MO.getReg()));
380 /// computeIntervals - computes the live intervals for virtual
381 /// registers. for some ordering of the machine instructions [1,N] a
382 /// live interval is an interval [i, j) where 1 <= i <= j < N for
383 /// which a variable is live
384 void LiveIntervals::computeIntervals() {
385 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
386 << "********** Function: " << MF->getName() << '\n');
388 RegMaskBlocks.resize(MF->getNumBlockIDs());
390 SmallVector<unsigned, 8> UndefUses;
391 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
393 MachineBasicBlock *MBB = MBBI;
394 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
399 // Track the index of the current machine instr.
400 SlotIndex MIIndex = getMBBStartIdx(MBB);
401 DEBUG(dbgs() << "BB#" << MBB->getNumber()
402 << ":\t\t# derived from " << MBB->getName() << "\n");
404 // Skip over empty initial indices.
405 if (getInstructionFromIndex(MIIndex) == 0)
406 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
408 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
410 DEBUG(dbgs() << MIIndex << "\t" << *MI);
411 if (MI->isDebugValue())
413 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
414 "Lost SlotIndex synchronization");
417 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
418 MachineOperand &MO = MI->getOperand(i);
420 // Collect register masks.
421 if (MO.isRegMask()) {
422 RegMaskSlots.push_back(MIIndex.getRegSlot());
423 RegMaskBits.push_back(MO.getRegMask());
427 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
430 // handle register defs - build intervals
432 handleRegisterDef(MBB, MI, MIIndex, MO, i);
433 else if (MO.isUndef())
434 UndefUses.push_back(MO.getReg());
437 // Move to the next instr slot.
438 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
441 // Compute the number of register mask instructions in this block.
442 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
443 RMB.second = RegMaskSlots.size() - RMB.first;;
446 // Create empty intervals for registers defined by implicit_def's (except
447 // for those implicit_def that define values which are liveout of their
449 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
450 unsigned UndefReg = UndefUses[i];
451 (void)getOrCreateInterval(UndefReg);
455 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
456 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
457 return new LiveInterval(reg, Weight);
461 /// computeVirtRegInterval - Compute the live interval of a virtual register,
462 /// based on defs and uses.
463 void LiveIntervals::computeVirtRegInterval(LiveInterval *LI) {
464 assert(LRCalc && "LRCalc not initialized.");
465 assert(LI->empty() && "Should only compute empty intervals.");
466 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
467 LRCalc->createDeadDefs(LI);
468 LRCalc->extendToUses(LI);
471 void LiveIntervals::computeVirtRegs() {
472 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
473 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
474 if (MRI->reg_nodbg_empty(Reg))
476 LiveInterval *LI = createInterval(Reg);
477 VirtRegIntervals[Reg] = LI;
478 computeVirtRegInterval(LI);
482 void LiveIntervals::computeRegMasks() {
483 RegMaskBlocks.resize(MF->getNumBlockIDs());
485 // Find all instructions with regmask operands.
486 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
488 MachineBasicBlock *MBB = MBBI;
489 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
490 RMB.first = RegMaskSlots.size();
491 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
493 for (MIOperands MO(MI); MO.isValid(); ++MO) {
494 if (!MO->isRegMask())
496 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
497 RegMaskBits.push_back(MO->getRegMask());
499 // Compute the number of register mask instructions in this block.
500 RMB.second = RegMaskSlots.size() - RMB.first;;
504 //===----------------------------------------------------------------------===//
505 // Register Unit Liveness
506 //===----------------------------------------------------------------------===//
508 // Fixed interference typically comes from ABI boundaries: Function arguments
509 // and return values are passed in fixed registers, and so are exception
510 // pointers entering landing pads. Certain instructions require values to be
511 // present in specific registers. That is also represented through fixed
515 /// computeRegUnitInterval - Compute the live interval of a register unit, based
516 /// on the uses and defs of aliasing registers. The interval should be empty,
517 /// or contain only dead phi-defs from ABI blocks.
518 void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
519 unsigned Unit = LI->reg;
521 assert(LRCalc && "LRCalc not initialized.");
522 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
524 // The physregs aliasing Unit are the roots and their super-registers.
525 // Create all values as dead defs before extending to uses. Note that roots
526 // may share super-registers. That's OK because createDeadDefs() is
527 // idempotent. It is very rare for a register unit to have multiple roots, so
528 // uniquing super-registers is probably not worthwhile.
529 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
530 unsigned Root = *Roots;
531 if (!MRI->reg_empty(Root))
532 LRCalc->createDeadDefs(LI, Root);
533 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
534 if (!MRI->reg_empty(*Supers))
535 LRCalc->createDeadDefs(LI, *Supers);
539 // Now extend LI to reach all uses.
540 // Ignore uses of reserved registers. We only track defs of those.
541 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
542 unsigned Root = *Roots;
543 if (!isReserved(Root) && !MRI->reg_empty(Root))
544 LRCalc->extendToUses(LI, Root);
545 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
546 unsigned Reg = *Supers;
547 if (!isReserved(Reg) && !MRI->reg_empty(Reg))
548 LRCalc->extendToUses(LI, Reg);
554 /// computeLiveInRegUnits - Precompute the live ranges of any register units
555 /// that are live-in to an ABI block somewhere. Register values can appear
556 /// without a corresponding def when entering the entry block or a landing pad.
558 void LiveIntervals::computeLiveInRegUnits() {
559 RegUnitIntervals.resize(TRI->getNumRegUnits());
560 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
562 // Keep track of the intervals allocated.
563 SmallVector<LiveInterval*, 8> NewIntvs;
565 // Check all basic blocks for live-ins.
566 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
568 const MachineBasicBlock *MBB = MFI;
570 // We only care about ABI blocks: Entry + landing pads.
571 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
574 // Create phi-defs at Begin for all live-in registers.
575 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
576 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
577 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
578 LIE = MBB->livein_end(); LII != LIE; ++LII) {
579 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
580 unsigned Unit = *Units;
581 LiveInterval *Intv = RegUnitIntervals[Unit];
583 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
584 NewIntvs.push_back(Intv);
586 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
588 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
591 DEBUG(dbgs() << '\n');
593 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
595 // Compute the 'normal' part of the intervals.
596 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
597 computeRegUnitInterval(NewIntvs[i]);
601 /// shrinkToUses - After removing some uses of a register, shrink its live
602 /// range to just the remaining uses. This method does not compute reaching
603 /// defs for new uses, and it doesn't remove dead defs.
604 bool LiveIntervals::shrinkToUses(LiveInterval *li,
605 SmallVectorImpl<MachineInstr*> *dead) {
606 DEBUG(dbgs() << "Shrink: " << *li << '\n');
607 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
608 && "Can only shrink virtual registers");
609 // Find all the values used, including PHI kills.
610 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
612 // Blocks that have already been added to WorkList as live-out.
613 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
615 // Visit all instructions reading li->reg.
616 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
617 MachineInstr *UseMI = I.skipInstruction();) {
618 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
620 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
621 LiveRangeQuery LRQ(*li, Idx);
622 VNInfo *VNI = LRQ.valueIn();
624 // This shouldn't happen: readsVirtualRegister returns true, but there is
625 // no live value. It is likely caused by a target getting <undef> flags
627 DEBUG(dbgs() << Idx << '\t' << *UseMI
628 << "Warning: Instr claims to read non-existent value in "
632 // Special case: An early-clobber tied operand reads and writes the
633 // register one slot early.
634 if (VNInfo *DefVNI = LRQ.valueDefined())
637 WorkList.push_back(std::make_pair(Idx, VNI));
640 // Create a new live interval with only minimal live segments per def.
641 LiveInterval NewLI(li->reg, 0);
642 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
647 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
650 // Keep track of the PHIs that are in use.
651 SmallPtrSet<VNInfo*, 8> UsedPHIs;
653 // Extend intervals to reach all uses in WorkList.
654 while (!WorkList.empty()) {
655 SlotIndex Idx = WorkList.back().first;
656 VNInfo *VNI = WorkList.back().second;
658 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
659 SlotIndex BlockStart = getMBBStartIdx(MBB);
661 // Extend the live range for VNI to be live at Idx.
662 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
664 assert(ExtVNI == VNI && "Unexpected existing value number");
665 // Is this a PHIDef we haven't seen before?
666 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
668 // The PHI is live, make sure the predecessors are live-out.
669 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
670 PE = MBB->pred_end(); PI != PE; ++PI) {
671 if (!LiveOut.insert(*PI))
673 SlotIndex Stop = getMBBEndIdx(*PI);
674 // A predecessor is not required to have a live-out value for a PHI.
675 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
676 WorkList.push_back(std::make_pair(Stop, PVNI));
681 // VNI is live-in to MBB.
682 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
683 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
685 // Make sure VNI is live-out from the predecessors.
686 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
687 PE = MBB->pred_end(); PI != PE; ++PI) {
688 if (!LiveOut.insert(*PI))
690 SlotIndex Stop = getMBBEndIdx(*PI);
691 assert(li->getVNInfoBefore(Stop) == VNI &&
692 "Wrong value out of predecessor");
693 WorkList.push_back(std::make_pair(Stop, VNI));
697 // Handle dead values.
698 bool CanSeparate = false;
699 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
704 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
705 assert(LII != NewLI.end() && "Missing live range for PHI");
706 if (LII->end != VNI->def.getDeadSlot())
708 if (VNI->isPHIDef()) {
709 // This is a dead PHI. Remove it.
711 NewLI.removeRange(*LII);
712 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
715 // This is a dead def. Make sure the instruction knows.
716 MachineInstr *MI = getInstructionFromIndex(VNI->def);
717 assert(MI && "No instruction defining live value");
718 MI->addRegisterDead(li->reg, TRI);
719 if (dead && MI->allDefsAreDead()) {
720 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
726 // Move the trimmed ranges back.
727 li->ranges.swap(NewLI.ranges);
728 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
733 //===----------------------------------------------------------------------===//
734 // Register allocator hooks.
737 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
738 // Keep track of regunit ranges.
739 SmallVector<std::pair<LiveInterval*, LiveInterval::iterator>, 8> RU;
741 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
742 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
743 if (MRI->reg_nodbg_empty(Reg))
745 LiveInterval *LI = &getInterval(Reg);
749 // Find the regunit intervals for the assigned register. They may overlap
750 // the virtual register live range, cancelling any kills.
752 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
754 LiveInterval *RUInt = &getRegUnit(*Units);
757 RU.push_back(std::make_pair(RUInt, RUInt->find(LI->begin()->end)));
760 // Every instruction that kills Reg corresponds to a live range end point.
761 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
763 // A block index indicates an MBB edge.
764 if (RI->end.isBlock())
766 MachineInstr *MI = getInstructionFromIndex(RI->end);
770 // Check if any of the reguints are live beyond the end of RI. That could
771 // happen when a physreg is defined as a copy of a virtreg:
773 // %EAX = COPY %vreg5
774 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
777 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
778 bool CancelKill = false;
779 for (unsigned u = 0, e = RU.size(); u != e; ++u) {
780 LiveInterval *RInt = RU[u].first;
781 LiveInterval::iterator &I = RU[u].second;
782 if (I == RInt->end())
784 I = RInt->advanceTo(I, RI->end);
785 if (I == RInt->end() || I->start >= RI->end)
787 // I is overlapping RI.
792 MI->clearRegisterKills(Reg, NULL);
794 MI->addRegisterKilled(Reg, NULL);
800 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
801 // A local live range must be fully contained inside the block, meaning it is
802 // defined and killed at instructions, not at block boundaries. It is not
803 // live in or or out of any block.
805 // It is technically possible to have a PHI-defined live range identical to a
806 // single block, but we are going to return false in that case.
808 SlotIndex Start = LI.beginIndex();
812 SlotIndex Stop = LI.endIndex();
816 // getMBBFromIndex doesn't need to search the MBB table when both indexes
817 // belong to proper instructions.
818 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
819 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
820 return MBB1 == MBB2 ? MBB1 : NULL;
824 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
825 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
827 const VNInfo *PHI = *I;
828 if (PHI->isUnused() || !PHI->isPHIDef())
830 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
831 // Conservatively return true instead of scanning huge predecessor lists.
832 if (PHIMBB->pred_size() > 100)
834 for (MachineBasicBlock::const_pred_iterator
835 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
836 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
843 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
844 // Limit the loop depth ridiculousness.
848 // The loop depth is used to roughly estimate the number of times the
849 // instruction is executed. Something like 10^d is simple, but will quickly
850 // overflow a float. This expression behaves like 10^d for small d, but is
851 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
852 // headroom before overflow.
853 // By the way, powf() might be unavailable here. For consistency,
854 // We may take pow(double,double).
855 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
857 return (isDef + isUse) * lc;
860 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
861 MachineInstr* startInst) {
862 LiveInterval& Interval = getOrCreateInterval(reg);
863 VNInfo* VN = Interval.getNextValue(
864 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
865 getVNInfoAllocator());
867 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
868 getMBBEndIdx(startInst->getParent()), VN);
869 Interval.addRange(LR);
875 //===----------------------------------------------------------------------===//
876 // Register mask functions
877 //===----------------------------------------------------------------------===//
879 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
880 BitVector &UsableRegs) {
883 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
885 // Use a smaller arrays for local live ranges.
886 ArrayRef<SlotIndex> Slots;
887 ArrayRef<const uint32_t*> Bits;
888 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
889 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
890 Bits = getRegMaskBitsInBlock(MBB->getNumber());
892 Slots = getRegMaskSlots();
893 Bits = getRegMaskBits();
896 // We are going to enumerate all the register mask slots contained in LI.
897 // Start with a binary search of RegMaskSlots to find a starting point.
898 ArrayRef<SlotIndex>::iterator SlotI =
899 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
900 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
902 // No slots in range, LI begins after the last call.
908 assert(*SlotI >= LiveI->start);
909 // Loop over all slots overlapping this segment.
910 while (*SlotI < LiveI->end) {
911 // *SlotI overlaps LI. Collect mask bits.
913 // This is the first overlap. Initialize UsableRegs to all ones.
915 UsableRegs.resize(TRI->getNumRegs(), true);
918 // Remove usable registers clobbered by this mask.
919 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
920 if (++SlotI == SlotE)
923 // *SlotI is beyond the current LI segment.
924 LiveI = LI.advanceTo(LiveI, *SlotI);
927 // Advance SlotI until it overlaps.
928 while (*SlotI < LiveI->start)
929 if (++SlotI == SlotE)
934 //===----------------------------------------------------------------------===//
935 // IntervalUpdate class.
936 //===----------------------------------------------------------------------===//
938 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
939 class LiveIntervals::HMEditor {
942 const MachineRegisterInfo& MRI;
943 const TargetRegisterInfo& TRI;
946 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
947 typedef DenseSet<IntRangePair> RangeSet;
954 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
956 typedef DenseMap<unsigned, RegRanges> BundleRanges;
959 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
960 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
961 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
963 // Update intervals for all operands of MI from OldIdx to NewIdx.
964 // This assumes that MI used to be at OldIdx, and now resides at
966 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
967 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
969 // Collect the operands.
970 RangeSet Entering, Internal, Exiting;
971 bool hasRegMaskOp = false;
972 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
974 // To keep the LiveRanges valid within an interval, move the ranges closest
975 // to the destination first. This prevents ranges from overlapping, to that
976 // APIs like removeRange still work.
977 if (NewIdx < OldIdx) {
978 moveAllEnteringFrom(OldIdx, Entering);
979 moveAllInternalFrom(OldIdx, Internal);
980 moveAllExitingFrom(OldIdx, Exiting);
983 moveAllExitingFrom(OldIdx, Exiting);
984 moveAllInternalFrom(OldIdx, Internal);
985 moveAllEnteringFrom(OldIdx, Entering);
989 updateRegMaskSlots(OldIdx);
992 LIValidator validator;
993 validator = std::for_each(Entering.begin(), Entering.end(), validator);
994 validator = std::for_each(Internal.begin(), Internal.end(), validator);
995 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
996 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
1001 // Update intervals for all operands of MI to refer to BundleStart's
1003 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
1004 if (MI == BundleStart)
1005 return; // Bundling instr with itself - nothing to do.
1007 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
1008 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
1009 "SlotIndex <-> Instruction mapping broken for MI");
1011 // Collect all ranges already in the bundle.
1012 MachineBasicBlock::instr_iterator BII(BundleStart);
1013 RangeSet Entering, Internal, Exiting;
1014 bool hasRegMaskOp = false;
1015 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1016 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1017 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
1020 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1021 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1024 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
1029 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1030 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1032 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
1033 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
1034 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
1036 moveAllEnteringFromInto(OldIdx, Entering, BR);
1037 moveAllInternalFromInto(OldIdx, Internal, BR);
1038 moveAllExitingFromInto(OldIdx, Exiting, BR);
1042 LIValidator validator;
1043 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1044 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1045 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1046 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
1055 DenseSet<const LiveInterval*> Checked, Bogus;
1057 void operator()(const IntRangePair& P) {
1058 const LiveInterval* LI = P.first;
1059 if (Checked.count(LI))
1064 SlotIndex LastEnd = LI->begin()->start;
1065 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
1066 LRI != LRE; ++LRI) {
1067 const LiveRange& LR = *LRI;
1068 if (LastEnd > LR.start || LR.start >= LR.end)
1074 bool rangesOk() const {
1075 return Bogus.empty();
1080 // Collect IntRangePairs for all operands of MI that may need fixing.
1081 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
1083 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
1084 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
1085 hasRegMaskOp = false;
1086 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1087 MOE = MI->operands_end();
1088 MOI != MOE; ++MOI) {
1089 const MachineOperand& MO = *MOI;
1091 if (MO.isRegMask()) {
1092 hasRegMaskOp = true;
1096 if (!MO.isReg() || MO.getReg() == 0)
1099 unsigned Reg = MO.getReg();
1101 // TODO: Currently we're skipping uses that are reserved or have no
1102 // interval, but we're not updating their kills. This should be
1104 if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg))
1107 // Collect ranges for register units. These live ranges are computed on
1108 // demand, so just skip any that haven't been computed yet.
1109 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1110 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
1111 if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
1112 collectRanges(MO, LI, Entering, Internal, Exiting, OldIdx);
1114 // Collect ranges for individual virtual registers.
1115 collectRanges(MO, &LIS.getInterval(Reg),
1116 Entering, Internal, Exiting, OldIdx);
1121 void collectRanges(const MachineOperand &MO, LiveInterval *LI,
1122 RangeSet &Entering, RangeSet &Internal, RangeSet &Exiting,
1124 if (MO.readsReg()) {
1125 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1127 Entering.insert(std::make_pair(LI, LR));
1130 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1131 assert(LR != 0 && "No live range for def?");
1132 if (LR->end > OldIdx.getDeadSlot())
1133 Exiting.insert(std::make_pair(LI, LR));
1135 Internal.insert(std::make_pair(LI, LR));
1139 BundleRanges createBundleRanges(RangeSet& Entering,
1141 RangeSet& Exiting) {
1144 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1146 LiveInterval* LI = EI->first;
1147 LiveRange* LR = EI->second;
1148 BR[LI->reg].Use = LR;
1151 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1153 LiveInterval* LI = II->first;
1154 LiveRange* LR = II->second;
1155 if (LR->end.isDead()) {
1156 BR[LI->reg].Dead = LR;
1158 BR[LI->reg].EC = LR;
1162 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1164 LiveInterval* LI = EI->first;
1165 LiveRange* LR = EI->second;
1166 BR[LI->reg].Def = LR;
1172 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1173 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1174 if (!OldKillMI->killsRegister(reg))
1175 return; // Bail out if we don't have kill flags on the old register.
1176 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1177 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1178 assert(!NewKillMI->killsRegister(reg) &&
1179 "New kill instr is already a kill.");
1180 OldKillMI->clearRegisterKills(reg, &TRI);
1181 NewKillMI->addRegisterKilled(reg, &TRI);
1184 void updateRegMaskSlots(SlotIndex OldIdx) {
1185 SmallVectorImpl<SlotIndex>::iterator RI =
1186 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1188 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1190 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1191 "RegSlots out of order. Did you move one call across another?");
1194 // Return the last use of reg between NewIdx and OldIdx.
1195 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1196 SlotIndex LastUse = NewIdx;
1197 for (MachineRegisterInfo::use_nodbg_iterator
1198 UI = MRI.use_nodbg_begin(Reg),
1199 UE = MRI.use_nodbg_end();
1200 UI != UE; UI.skipInstruction()) {
1201 const MachineInstr* MI = &*UI;
1202 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1203 if (InstSlot > LastUse && InstSlot < OldIdx)
1209 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1210 LiveInterval* LI = P.first;
1211 LiveRange* LR = P.second;
1212 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1215 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1216 if (LastUse != NewIdx)
1217 moveKillFlags(LI->reg, NewIdx, LastUse);
1218 LR->end = LastUse.getRegSlot(LR->end.isEarlyClobber());
1221 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1222 LiveInterval* LI = P.first;
1223 LiveRange* LR = P.second;
1224 // Extend the LiveRange if NewIdx is past the end.
1225 if (NewIdx > LR->end) {
1226 // Move kill flags if OldIdx was not originally the end
1227 // (otherwise LR->end points to an invalid slot).
1228 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
1229 assert(LR->end > OldIdx && "LiveRange does not cover original slot");
1230 moveKillFlags(LI->reg, LR->end, NewIdx);
1232 LR->end = NewIdx.getRegSlot(LR->end.isEarlyClobber());
1236 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1237 bool GoingUp = NewIdx < OldIdx;
1240 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1242 moveEnteringUpFrom(OldIdx, *EI);
1244 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1246 moveEnteringDownFrom(OldIdx, *EI);
1250 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1251 LiveInterval* LI = P.first;
1252 LiveRange* LR = P.second;
1253 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1254 LR->end <= OldIdx.getDeadSlot() &&
1255 "Range should be internal to OldIdx.");
1257 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1258 Tmp.valno->def = Tmp.start;
1259 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1260 LI->removeRange(*LR);
1264 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1265 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1267 moveInternalFrom(OldIdx, *II);
1270 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1271 LiveRange* LR = P.second;
1272 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1273 "Range should start in OldIdx.");
1274 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1275 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1276 LR->start = NewStart;
1277 LR->valno->def = NewStart;
1280 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1281 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1283 moveExitingFrom(OldIdx, *EI);
1286 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1288 LiveInterval* LI = P.first;
1289 LiveRange* LR = P.second;
1290 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1292 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1293 "Def in bundle should be def range.");
1294 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1295 "If bundle has use for this reg it should be LR.");
1296 BR[LI->reg].Use = LR;
1300 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1301 moveKillFlags(LI->reg, OldIdx, LastUse);
1303 if (LR->start < NewIdx) {
1304 // Becoming a new entering range.
1305 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1306 "Bundle shouldn't be re-defining reg mid-range.");
1307 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1308 "Bundle shouldn't have different use range for same reg.");
1309 LR->end = LastUse.getRegSlot();
1310 BR[LI->reg].Use = LR;
1312 // Becoming a new Dead-def.
1313 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1314 "Live range starting at unexpected slot.");
1315 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1316 assert(BR[LI->reg].Dead == 0 &&
1317 "Can't have def and dead def of same reg in a bundle.");
1318 LR->end = LastUse.getDeadSlot();
1319 BR[LI->reg].Dead = BR[LI->reg].Def;
1320 BR[LI->reg].Def = 0;
1324 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1326 LiveInterval* LI = P.first;
1327 LiveRange* LR = P.second;
1328 if (NewIdx > LR->end) {
1329 // Range extended to bundle. Add to bundle uses.
1330 // Note: Currently adds kill flags to bundle start.
1331 assert(BR[LI->reg].Use == 0 &&
1332 "Bundle already has use range for reg.");
1333 moveKillFlags(LI->reg, LR->end, NewIdx);
1334 LR->end = NewIdx.getRegSlot();
1335 BR[LI->reg].Use = LR;
1337 assert(BR[LI->reg].Use != 0 &&
1338 "Bundle should already have a use range for reg.");
1342 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1344 bool GoingUp = NewIdx < OldIdx;
1347 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1349 moveEnteringUpFromInto(OldIdx, *EI, BR);
1351 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1353 moveEnteringDownFromInto(OldIdx, *EI, BR);
1357 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1359 // TODO: Sane rules for moving ranges into bundles.
1362 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1364 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1366 moveInternalFromInto(OldIdx, *II, BR);
1369 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1371 LiveInterval* LI = P.first;
1372 LiveRange* LR = P.second;
1374 assert(LR->start.isRegister() &&
1375 "Don't know how to merge exiting ECs into bundles yet.");
1377 if (LR->end > NewIdx.getDeadSlot()) {
1378 // This range is becoming an exiting range on the bundle.
1379 // If there was an old dead-def of this reg, delete it.
1380 if (BR[LI->reg].Dead != 0) {
1381 LI->removeRange(*BR[LI->reg].Dead);
1382 BR[LI->reg].Dead = 0;
1384 assert(BR[LI->reg].Def == 0 &&
1385 "Can't have two defs for the same variable exiting a bundle.");
1386 LR->start = NewIdx.getRegSlot();
1387 LR->valno->def = LR->start;
1388 BR[LI->reg].Def = LR;
1390 // This range is becoming internal to the bundle.
1391 assert(LR->end == NewIdx.getRegSlot() &&
1392 "Can't bundle def whose kill is before the bundle");
1393 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1394 // Already have a def for this. Just delete range.
1395 LI->removeRange(*LR);
1397 // Make range dead, record.
1398 LR->end = NewIdx.getDeadSlot();
1399 BR[LI->reg].Dead = LR;
1400 assert(BR[LI->reg].Use == LR &&
1401 "Range becoming dead should currently be use.");
1403 // In both cases the range is no longer a use on the bundle.
1404 BR[LI->reg].Use = 0;
1408 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1410 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1412 moveExitingFromInto(OldIdx, *EI, BR);
1417 void LiveIntervals::handleMove(MachineInstr* MI) {
1418 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1419 Indexes->removeMachineInstrFromMaps(MI);
1420 SlotIndex NewIndex = MI->isInsideBundle() ?
1421 Indexes->getInstructionIndex(MI) :
1422 Indexes->insertMachineInstrInMaps(MI);
1423 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1424 OldIndex < getMBBEndIdx(MI->getParent()) &&
1425 "Cannot handle moves across basic block boundaries.");
1426 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1428 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1429 HME.moveAllRangesFrom(MI, OldIndex);
1432 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1433 MachineInstr* BundleStart) {
1434 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1435 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1436 HME.moveAllRangesInto(MI, BundleStart);