1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetSubtargetInfo.h"
44 #define DEBUG_TYPE "regalloc"
46 char LiveIntervals::ID = 0;
47 char &llvm::LiveIntervalsID = LiveIntervals::ID;
48 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
49 "Live Interval Analysis", false, false)
50 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
51 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
52 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
53 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
54 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
55 "Live Interval Analysis", false, false)
58 static cl::opt<bool> EnablePrecomputePhysRegs(
59 "precompute-phys-liveness", cl::Hidden,
60 cl::desc("Eagerly compute live intervals for all physreg units."));
62 static bool EnablePrecomputePhysRegs = false;
65 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
67 AU.addRequired<AliasAnalysis>();
68 AU.addPreserved<AliasAnalysis>();
69 // LiveVariables isn't really required by this analysis, it is only required
70 // here to make sure it is live during TwoAddressInstructionPass and
71 // PHIElimination. This is temporary.
72 AU.addRequired<LiveVariables>();
73 AU.addPreserved<LiveVariables>();
74 AU.addPreservedID(MachineLoopInfoID);
75 AU.addRequiredTransitiveID(MachineDominatorsID);
76 AU.addPreservedID(MachineDominatorsID);
77 AU.addPreserved<SlotIndexes>();
78 AU.addRequiredTransitive<SlotIndexes>();
79 MachineFunctionPass::getAnalysisUsage(AU);
82 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
83 DomTree(nullptr), LRCalc(nullptr) {
84 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
87 LiveIntervals::~LiveIntervals() {
91 void LiveIntervals::releaseMemory() {
92 // Free the live intervals themselves.
93 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
94 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
95 VirtRegIntervals.clear();
98 RegMaskBlocks.clear();
100 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
101 delete RegUnitRanges[i];
102 RegUnitRanges.clear();
104 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
105 VNInfoAllocator.Reset();
108 /// runOnMachineFunction - calculates LiveIntervals
110 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
112 MRI = &MF->getRegInfo();
113 TRI = MF->getSubtarget().getRegisterInfo();
114 TII = MF->getSubtarget().getInstrInfo();
115 AA = &getAnalysis<AliasAnalysis>();
116 Indexes = &getAnalysis<SlotIndexes>();
117 DomTree = &getAnalysis<MachineDominatorTree>();
119 LRCalc = new LiveRangeCalc();
121 // Allocate space for all virtual registers.
122 VirtRegIntervals.resize(MRI->getNumVirtRegs());
126 computeLiveInRegUnits();
128 if (EnablePrecomputePhysRegs) {
129 // For stress testing, precompute live ranges of all physical register
130 // units, including reserved registers.
131 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
138 /// print - Implement the dump method.
139 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
140 OS << "********** INTERVALS **********\n";
142 // Dump the regunits.
143 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
144 if (LiveRange *LR = RegUnitRanges[i])
145 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
147 // Dump the virtregs.
148 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
149 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
150 if (hasInterval(Reg))
151 OS << getInterval(Reg) << '\n';
155 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
156 OS << ' ' << RegMaskSlots[i];
162 void LiveIntervals::printInstrs(raw_ostream &OS) const {
163 OS << "********** MACHINEINSTRS **********\n";
164 MF->print(OS, Indexes);
167 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
168 void LiveIntervals::dumpInstrs() const {
173 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
174 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
175 llvm::huge_valf : 0.0F;
176 return new LiveInterval(reg, Weight);
180 /// computeVirtRegInterval - Compute the live interval of a virtual register,
181 /// based on defs and uses.
182 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
183 assert(LRCalc && "LRCalc not initialized.");
184 assert(LI.empty() && "Should only compute empty intervals.");
185 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
186 LRCalc->createDeadDefs(LI);
187 LRCalc->extendToUses(LI);
188 computeDeadValues(LI, LI);
191 void LiveIntervals::computeVirtRegs() {
192 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
193 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
194 if (MRI->reg_nodbg_empty(Reg))
196 createAndComputeVirtRegInterval(Reg);
200 void LiveIntervals::computeRegMasks() {
201 RegMaskBlocks.resize(MF->getNumBlockIDs());
203 // Find all instructions with regmask operands.
204 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
206 MachineBasicBlock *MBB = MBBI;
207 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
208 RMB.first = RegMaskSlots.size();
209 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
211 for (MIOperands MO(MI); MO.isValid(); ++MO) {
212 if (!MO->isRegMask())
214 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
215 RegMaskBits.push_back(MO->getRegMask());
217 // Compute the number of register mask instructions in this block.
218 RMB.second = RegMaskSlots.size() - RMB.first;
222 //===----------------------------------------------------------------------===//
223 // Register Unit Liveness
224 //===----------------------------------------------------------------------===//
226 // Fixed interference typically comes from ABI boundaries: Function arguments
227 // and return values are passed in fixed registers, and so are exception
228 // pointers entering landing pads. Certain instructions require values to be
229 // present in specific registers. That is also represented through fixed
233 /// computeRegUnitInterval - Compute the live range of a register unit, based
234 /// on the uses and defs of aliasing registers. The range should be empty,
235 /// or contain only dead phi-defs from ABI blocks.
236 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
237 assert(LRCalc && "LRCalc not initialized.");
238 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
240 // The physregs aliasing Unit are the roots and their super-registers.
241 // Create all values as dead defs before extending to uses. Note that roots
242 // may share super-registers. That's OK because createDeadDefs() is
243 // idempotent. It is very rare for a register unit to have multiple roots, so
244 // uniquing super-registers is probably not worthwhile.
245 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
246 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
247 Supers.isValid(); ++Supers) {
248 if (!MRI->reg_empty(*Supers))
249 LRCalc->createDeadDefs(LR, *Supers);
253 // Now extend LR to reach all uses.
254 // Ignore uses of reserved registers. We only track defs of those.
255 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
256 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
257 Supers.isValid(); ++Supers) {
258 unsigned Reg = *Supers;
259 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
260 LRCalc->extendToUses(LR, Reg);
266 /// computeLiveInRegUnits - Precompute the live ranges of any register units
267 /// that are live-in to an ABI block somewhere. Register values can appear
268 /// without a corresponding def when entering the entry block or a landing pad.
270 void LiveIntervals::computeLiveInRegUnits() {
271 RegUnitRanges.resize(TRI->getNumRegUnits());
272 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
274 // Keep track of the live range sets allocated.
275 SmallVector<unsigned, 8> NewRanges;
277 // Check all basic blocks for live-ins.
278 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
280 const MachineBasicBlock *MBB = MFI;
282 // We only care about ABI blocks: Entry + landing pads.
283 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
286 // Create phi-defs at Begin for all live-in registers.
287 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
288 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
289 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
290 LIE = MBB->livein_end(); LII != LIE; ++LII) {
291 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
292 unsigned Unit = *Units;
293 LiveRange *LR = RegUnitRanges[Unit];
295 LR = RegUnitRanges[Unit] = new LiveRange();
296 NewRanges.push_back(Unit);
298 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
300 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
303 DEBUG(dbgs() << '\n');
305 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
307 // Compute the 'normal' part of the ranges.
308 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
309 unsigned Unit = NewRanges[i];
310 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
315 static void createSegmentsForValues(LiveRange &LR,
316 iterator_range<LiveInterval::vni_iterator> VNIs) {
317 for (auto VNI : VNIs) {
320 SlotIndex Def = VNI->def;
321 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
325 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
327 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
328 ShrinkToUsesWorkList &WorkList,
329 const LiveRange &OldRange) {
330 // Keep track of the PHIs that are in use.
331 SmallPtrSet<VNInfo*, 8> UsedPHIs;
332 // Blocks that have already been added to WorkList as live-out.
333 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
335 // Extend intervals to reach all uses in WorkList.
336 while (!WorkList.empty()) {
337 SlotIndex Idx = WorkList.back().first;
338 VNInfo *VNI = WorkList.back().second;
340 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
341 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
343 // Extend the live range for VNI to be live at Idx.
344 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
345 assert(ExtVNI == VNI && "Unexpected existing value number");
347 // Is this a PHIDef we haven't seen before?
348 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
349 !UsedPHIs.insert(VNI).second)
351 // The PHI is live, make sure the predecessors are live-out.
352 for (auto &Pred : MBB->predecessors()) {
353 if (!LiveOut.insert(Pred).second)
355 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
356 // A predecessor is not required to have a live-out value for a PHI.
357 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
358 WorkList.push_back(std::make_pair(Stop, PVNI));
363 // VNI is live-in to MBB.
364 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
365 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
367 // Make sure VNI is live-out from the predecessors.
368 for (auto &Pred : MBB->predecessors()) {
369 if (!LiveOut.insert(Pred).second)
371 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
372 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
373 "Wrong value out of predecessor");
374 WorkList.push_back(std::make_pair(Stop, VNI));
379 /// shrinkToUses - After removing some uses of a register, shrink its live
380 /// range to just the remaining uses. This method does not compute reaching
381 /// defs for new uses, and it doesn't remove dead defs.
382 bool LiveIntervals::shrinkToUses(LiveInterval *li,
383 SmallVectorImpl<MachineInstr*> *dead) {
384 DEBUG(dbgs() << "Shrink: " << *li << '\n');
385 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
386 && "Can only shrink virtual registers");
388 // Shrink subregister live ranges.
389 for (LiveInterval::subrange_iterator I = li->subrange_begin(),
390 E = li->subrange_end(); I != E; ++I) {
391 shrinkToUses(*I, li->reg);
394 // Find all the values used, including PHI kills.
395 ShrinkToUsesWorkList WorkList;
397 // Visit all instructions reading li->reg.
398 for (MachineRegisterInfo::reg_instr_iterator
399 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
401 MachineInstr *UseMI = &*(I++);
402 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
404 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
405 LiveQueryResult LRQ = li->Query(Idx);
406 VNInfo *VNI = LRQ.valueIn();
408 // This shouldn't happen: readsVirtualRegister returns true, but there is
409 // no live value. It is likely caused by a target getting <undef> flags
411 DEBUG(dbgs() << Idx << '\t' << *UseMI
412 << "Warning: Instr claims to read non-existent value in "
416 // Special case: An early-clobber tied operand reads and writes the
417 // register one slot early.
418 if (VNInfo *DefVNI = LRQ.valueDefined())
421 WorkList.push_back(std::make_pair(Idx, VNI));
424 // Create new live ranges with only minimal live segments per def.
426 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
427 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
429 // Handle dead values.
431 computeDeadValues(NewLR, *li, &CanSeparate, li->reg, dead);
433 // Move the trimmed segments back.
434 li->segments.swap(NewLR.segments);
435 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
439 void LiveIntervals::computeDeadValues(LiveRange &Segments, LiveRange &LR,
440 bool *CanSeparateRes, unsigned Reg,
441 SmallVectorImpl<MachineInstr*> *dead) {
442 bool CanSeparate = false;
443 for (auto VNI : make_range(LR.vni_begin(), LR.vni_end())) {
446 LiveRange::iterator LRI = Segments.FindSegmentContaining(VNI->def);
447 assert(LRI != Segments.end() && "Missing segment for PHI");
448 if (LRI->end != VNI->def.getDeadSlot())
450 if (VNI->isPHIDef()) {
451 // This is a dead PHI. Remove it.
453 Segments.removeSegment(LRI->start, LRI->end);
454 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
456 } else if (dead != nullptr) {
457 // This is a dead def. Make sure the instruction knows.
458 MachineInstr *MI = getInstructionFromIndex(VNI->def);
459 assert(MI && "No instruction defining live value");
460 MI->addRegisterDead(Reg, TRI);
461 if (dead && MI->allDefsAreDead()) {
462 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
467 if (CanSeparateRes != nullptr)
468 *CanSeparateRes = CanSeparate;
471 bool LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
473 DEBUG(dbgs() << "Shrink: " << SR << '\n');
474 assert(TargetRegisterInfo::isVirtualRegister(Reg)
475 && "Can only shrink virtual registers");
476 // Find all the values used, including PHI kills.
477 ShrinkToUsesWorkList WorkList;
479 // Visit all instructions reading Reg.
481 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
482 MachineInstr *UseMI = MO.getParent();
483 if (UseMI->isDebugValue())
485 // Maybe the operand is for a subregister we don't care about.
486 unsigned SubReg = MO.getSubReg();
488 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg);
489 if ((SubRegMask & SR.LaneMask) == 0)
492 // We only need to visit each instruction once.
493 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
498 LiveQueryResult LRQ = SR.Query(Idx);
499 VNInfo *VNI = LRQ.valueIn();
500 // For Subranges it is possible that only undef values are left in that
501 // part of the subregister, so there is no real liverange at the use
505 // Special case: An early-clobber tied operand reads and writes the
506 // register one slot early.
507 if (VNInfo *DefVNI = LRQ.valueDefined())
510 WorkList.push_back(std::make_pair(Idx, VNI));
513 // Create a new live ranges with only minimal live segments per def.
515 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
516 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
518 // Handle dead values.
520 computeDeadValues(NewLR, SR, &CanSeparate);
522 // Move the trimmed ranges back.
523 SR.segments.swap(NewLR.segments);
524 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
528 void LiveIntervals::extendToIndices(LiveRange &LR,
529 ArrayRef<SlotIndex> Indices) {
530 assert(LRCalc && "LRCalc not initialized.");
531 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
532 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
533 LRCalc->extend(LR, Indices[i]);
536 void LiveIntervals::pruneValue(LiveInterval *LI, SlotIndex Kill,
537 SmallVectorImpl<SlotIndex> *EndPoints) {
538 LiveQueryResult LRQ = LI->Query(Kill);
539 VNInfo *VNI = LRQ.valueOut();
543 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
544 SlotIndex MBBStart, MBBEnd;
545 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(KillMBB);
547 // If VNI isn't live out from KillMBB, the value is trivially pruned.
548 if (LRQ.endPoint() < MBBEnd) {
549 LI->removeSegment(Kill, LRQ.endPoint());
550 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
554 // VNI is live out of KillMBB.
555 LI->removeSegment(Kill, MBBEnd);
556 if (EndPoints) EndPoints->push_back(MBBEnd);
558 // Find all blocks that are reachable from KillMBB without leaving VNI's live
559 // range. It is possible that KillMBB itself is reachable, so start a DFS
560 // from each successor.
561 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
563 for (MachineBasicBlock::succ_iterator
564 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
565 SuccI != SuccE; ++SuccI) {
566 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
567 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
569 MachineBasicBlock *MBB = *I;
571 // Check if VNI is live in to MBB.
572 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
573 LiveQueryResult LRQ = LI->Query(MBBStart);
574 if (LRQ.valueIn() != VNI) {
575 // This block isn't part of the VNI segment. Prune the search.
580 // Prune the search if VNI is killed in MBB.
581 if (LRQ.endPoint() < MBBEnd) {
582 LI->removeSegment(MBBStart, LRQ.endPoint());
583 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
588 // VNI is live through MBB.
589 LI->removeSegment(MBBStart, MBBEnd);
590 if (EndPoints) EndPoints->push_back(MBBEnd);
596 //===----------------------------------------------------------------------===//
597 // Register allocator hooks.
600 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
601 // Keep track of regunit ranges.
602 SmallVector<std::pair<LiveRange*, LiveRange::iterator>, 8> RU;
604 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
605 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
606 if (MRI->reg_nodbg_empty(Reg))
608 LiveInterval *LI = &getInterval(Reg);
612 // Find the regunit intervals for the assigned register. They may overlap
613 // the virtual register live range, cancelling any kills.
615 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
617 LiveRange &RURanges = getRegUnit(*Units);
618 if (RURanges.empty())
620 RU.push_back(std::make_pair(&RURanges, RURanges.find(LI->begin()->end)));
623 // Every instruction that kills Reg corresponds to a segment range end
625 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
627 // A block index indicates an MBB edge.
628 if (RI->end.isBlock())
630 MachineInstr *MI = getInstructionFromIndex(RI->end);
634 // Check if any of the regunits are live beyond the end of RI. That could
635 // happen when a physreg is defined as a copy of a virtreg:
637 // %EAX = COPY %vreg5
638 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
641 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
642 bool CancelKill = false;
643 for (unsigned u = 0, e = RU.size(); u != e; ++u) {
644 LiveRange &RRanges = *RU[u].first;
645 LiveRange::iterator &I = RU[u].second;
646 if (I == RRanges.end())
648 I = RRanges.advanceTo(I, RI->end);
649 if (I == RRanges.end() || I->start >= RI->end)
651 // I is overlapping RI.
656 MI->clearRegisterKills(Reg, nullptr);
658 MI->addRegisterKilled(Reg, nullptr);
664 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
665 // A local live range must be fully contained inside the block, meaning it is
666 // defined and killed at instructions, not at block boundaries. It is not
667 // live in or or out of any block.
669 // It is technically possible to have a PHI-defined live range identical to a
670 // single block, but we are going to return false in that case.
672 SlotIndex Start = LI.beginIndex();
676 SlotIndex Stop = LI.endIndex();
680 // getMBBFromIndex doesn't need to search the MBB table when both indexes
681 // belong to proper instructions.
682 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
683 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
684 return MBB1 == MBB2 ? MBB1 : nullptr;
688 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
689 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
691 const VNInfo *PHI = *I;
692 if (PHI->isUnused() || !PHI->isPHIDef())
694 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
695 // Conservatively return true instead of scanning huge predecessor lists.
696 if (PHIMBB->pred_size() > 100)
698 for (MachineBasicBlock::const_pred_iterator
699 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
700 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
707 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
708 const MachineBlockFrequencyInfo *MBFI,
709 const MachineInstr *MI) {
710 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
711 const float Scale = 1.0f / MBFI->getEntryFreq();
712 return (isDef + isUse) * (Freq.getFrequency() * Scale);
716 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
717 LiveInterval& Interval = createEmptyInterval(reg);
718 VNInfo* VN = Interval.getNextValue(
719 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
720 getVNInfoAllocator());
721 LiveRange::Segment S(
722 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
723 getMBBEndIdx(startInst->getParent()), VN);
724 Interval.addSegment(S);
730 //===----------------------------------------------------------------------===//
731 // Register mask functions
732 //===----------------------------------------------------------------------===//
734 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
735 BitVector &UsableRegs) {
738 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
740 // Use a smaller arrays for local live ranges.
741 ArrayRef<SlotIndex> Slots;
742 ArrayRef<const uint32_t*> Bits;
743 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
744 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
745 Bits = getRegMaskBitsInBlock(MBB->getNumber());
747 Slots = getRegMaskSlots();
748 Bits = getRegMaskBits();
751 // We are going to enumerate all the register mask slots contained in LI.
752 // Start with a binary search of RegMaskSlots to find a starting point.
753 ArrayRef<SlotIndex>::iterator SlotI =
754 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
755 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
757 // No slots in range, LI begins after the last call.
763 assert(*SlotI >= LiveI->start);
764 // Loop over all slots overlapping this segment.
765 while (*SlotI < LiveI->end) {
766 // *SlotI overlaps LI. Collect mask bits.
768 // This is the first overlap. Initialize UsableRegs to all ones.
770 UsableRegs.resize(TRI->getNumRegs(), true);
773 // Remove usable registers clobbered by this mask.
774 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
775 if (++SlotI == SlotE)
778 // *SlotI is beyond the current LI segment.
779 LiveI = LI.advanceTo(LiveI, *SlotI);
782 // Advance SlotI until it overlaps.
783 while (*SlotI < LiveI->start)
784 if (++SlotI == SlotE)
789 //===----------------------------------------------------------------------===//
790 // IntervalUpdate class.
791 //===----------------------------------------------------------------------===//
793 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
794 class LiveIntervals::HMEditor {
797 const MachineRegisterInfo& MRI;
798 const TargetRegisterInfo& TRI;
801 SmallPtrSet<LiveRange*, 8> Updated;
805 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
806 const TargetRegisterInfo& TRI,
807 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
808 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
809 UpdateFlags(UpdateFlags) {}
811 // FIXME: UpdateFlags is a workaround that creates live intervals for all
812 // physregs, even those that aren't needed for regalloc, in order to update
813 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
814 // flags, and postRA passes will use a live register utility instead.
815 LiveRange *getRegUnitLI(unsigned Unit) {
817 return &LIS.getRegUnit(Unit);
818 return LIS.getCachedRegUnit(Unit);
821 /// Update all live ranges touched by MI, assuming a move from OldIdx to
823 void updateAllRanges(MachineInstr *MI) {
824 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
825 bool hasRegMask = false;
826 for (MIOperands MO(MI); MO.isValid(); ++MO) {
831 // Aggressively clear all kill flags.
832 // They are reinserted by VirtRegRewriter.
834 MO->setIsKill(false);
836 unsigned Reg = MO->getReg();
839 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
840 LiveInterval &LI = LIS.getInterval(Reg);
841 // TODO: handle subranges instead of dropping them
843 updateRange(LI, Reg);
847 // For physregs, only update the regunits that actually have a
848 // precomputed live range.
849 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
850 if (LiveRange *LR = getRegUnitLI(*Units))
851 updateRange(*LR, *Units);
854 updateRegMaskSlots();
858 /// Update a single live range, assuming an instruction has been moved from
859 /// OldIdx to NewIdx.
860 void updateRange(LiveRange &LR, unsigned Reg) {
861 if (!Updated.insert(&LR).second)
865 if (TargetRegisterInfo::isVirtualRegister(Reg))
866 dbgs() << PrintReg(Reg);
868 dbgs() << PrintRegUnit(Reg, &TRI);
869 dbgs() << ":\t" << LR << '\n';
871 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
874 handleMoveUp(LR, Reg);
875 DEBUG(dbgs() << " -->\t" << LR << '\n');
879 /// Update LR to reflect an instruction has been moved downwards from OldIdx
882 /// 1. Live def at OldIdx:
883 /// Move def to NewIdx, assert endpoint after NewIdx.
885 /// 2. Live def at OldIdx, killed at NewIdx:
886 /// Change to dead def at NewIdx.
887 /// (Happens when bundling def+kill together).
889 /// 3. Dead def at OldIdx:
890 /// Move def to NewIdx, possibly across another live value.
892 /// 4. Def at OldIdx AND at NewIdx:
893 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
894 /// (Happens when bundling multiple defs together).
896 /// 5. Value read at OldIdx, killed before NewIdx:
897 /// Extend kill to NewIdx.
899 void handleMoveDown(LiveRange &LR) {
900 // First look for a kill at OldIdx.
901 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
902 LiveRange::iterator E = LR.end();
903 // Is LR even live at OldIdx?
904 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
907 // Handle a live-in value.
908 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
909 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
910 // If the live-in value already extends to NewIdx, there is nothing to do.
911 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
913 // Aggressively remove all kill flags from the old kill point.
914 // Kill flags shouldn't be used while live intervals exist, they will be
915 // reinserted by VirtRegRewriter.
916 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
917 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
918 if (MO->isReg() && MO->isUse())
919 MO->setIsKill(false);
920 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
921 // overlapping ranges. Case 5 above.
922 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
923 // If this was a kill, there may also be a def. Otherwise we're done.
929 // Check for a def at OldIdx.
930 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
932 // We have a def at OldIdx.
933 VNInfo *DefVNI = I->valno;
934 assert(DefVNI->def == I->start && "Inconsistent def");
935 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
936 // If the defined value extends beyond NewIdx, just move the def down.
937 // This is case 1 above.
938 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
939 I->start = DefVNI->def;
942 // The remaining possibilities are now:
943 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
944 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
945 // In either case, it is possible that there is an existing def at NewIdx.
946 assert((I->end == OldIdx.getDeadSlot() ||
947 SlotIndex::isSameInstr(I->end, NewIdx)) &&
948 "Cannot move def below kill");
949 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
950 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
951 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
952 // coalesced into that value.
953 assert(NewI->valno != DefVNI && "Multiple defs of value?");
954 LR.removeValNo(DefVNI);
957 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
958 // If the def at OldIdx was dead, we allow it to be moved across other LR
959 // values. The new range should be placed immediately before NewI, move any
960 // intermediate ranges up.
961 assert(NewI != I && "Inconsistent iterators");
962 std::copy(std::next(I), NewI, I);
964 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
967 /// Update LR to reflect an instruction has been moved upwards from OldIdx
970 /// 1. Live def at OldIdx:
971 /// Hoist def to NewIdx.
973 /// 2. Dead def at OldIdx:
974 /// Hoist def+end to NewIdx, possibly move across other values.
976 /// 3. Dead def at OldIdx AND existing def at NewIdx:
977 /// Remove value defined at OldIdx, coalescing it with existing value.
979 /// 4. Live def at OldIdx AND existing def at NewIdx:
980 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
981 /// (Happens when bundling multiple defs together).
983 /// 5. Value killed at OldIdx:
984 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
987 void handleMoveUp(LiveRange &LR, unsigned Reg) {
988 // First look for a kill at OldIdx.
989 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
990 LiveRange::iterator E = LR.end();
991 // Is LR even live at OldIdx?
992 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
995 // Handle a live-in value.
996 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
997 // If the live-in value isn't killed here, there is nothing to do.
998 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1000 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1001 // another use, we need to search for that use. Case 5 above.
1002 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1004 // If OldIdx also defines a value, there couldn't have been another use.
1005 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1006 // No def, search for the new kill.
1007 // This can never be an early clobber kill since there is no def.
1008 std::prev(I)->end = findLastUseBefore(Reg).getRegSlot();
1013 // Now deal with the def at OldIdx.
1014 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1015 VNInfo *DefVNI = I->valno;
1016 assert(DefVNI->def == I->start && "Inconsistent def");
1017 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1019 // Check for an existing def at NewIdx.
1020 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1021 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1022 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1023 // There is an existing def at NewIdx.
1024 if (I->end.isDead()) {
1025 // Case 3: Remove the dead def at OldIdx.
1026 LR.removeValNo(DefVNI);
1029 // Case 4: Replace def at NewIdx with live def at OldIdx.
1030 I->start = DefVNI->def;
1031 LR.removeValNo(NewI->valno);
1035 // There is no existing def at NewIdx. Hoist DefVNI.
1036 if (!I->end.isDead()) {
1037 // Leave the end point of a live def.
1038 I->start = DefVNI->def;
1042 // DefVNI is a dead def. It may have been moved across other values in LR,
1043 // so move I up to NewI. Slide [NewI;I) down one position.
1044 std::copy_backward(NewI, I, std::next(I));
1045 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1048 void updateRegMaskSlots() {
1049 SmallVectorImpl<SlotIndex>::iterator RI =
1050 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1052 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1053 "No RegMask at OldIdx.");
1054 *RI = NewIdx.getRegSlot();
1055 assert((RI == LIS.RegMaskSlots.begin() ||
1056 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1057 "Cannot move regmask instruction above another call");
1058 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1059 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1060 "Cannot move regmask instruction below another call");
1063 // Return the last use of reg between NewIdx and OldIdx.
1064 SlotIndex findLastUseBefore(unsigned Reg) {
1066 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1067 SlotIndex LastUse = NewIdx;
1068 for (MachineRegisterInfo::use_instr_nodbg_iterator
1069 UI = MRI.use_instr_nodbg_begin(Reg),
1070 UE = MRI.use_instr_nodbg_end();
1072 const MachineInstr* MI = &*UI;
1073 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1074 if (InstSlot > LastUse && InstSlot < OldIdx)
1080 // This is a regunit interval, so scanning the use list could be very
1081 // expensive. Scan upwards from OldIdx instead.
1082 assert(NewIdx < OldIdx && "Expected upwards move");
1083 SlotIndexes *Indexes = LIS.getSlotIndexes();
1084 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1086 // OldIdx may not correspond to an instruction any longer, so set MII to
1087 // point to the next instruction after OldIdx, or MBB->end().
1088 MachineBasicBlock::iterator MII = MBB->end();
1089 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1090 Indexes->getNextNonNullIndex(OldIdx)))
1091 if (MI->getParent() == MBB)
1094 MachineBasicBlock::iterator Begin = MBB->begin();
1095 while (MII != Begin) {
1096 if ((--MII)->isDebugValue())
1098 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1100 // Stop searching when NewIdx is reached.
1101 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1104 // Check if MII uses Reg.
1105 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1107 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1108 TRI.hasRegUnit(MO->getReg(), Reg))
1111 // Didn't reach NewIdx. It must be the first instruction in the block.
1116 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1117 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1118 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1119 Indexes->removeMachineInstrFromMaps(MI);
1120 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1121 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1122 OldIndex < getMBBEndIdx(MI->getParent()) &&
1123 "Cannot handle moves across basic block boundaries.");
1125 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1126 HME.updateAllRanges(MI);
1129 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1130 MachineInstr* BundleStart,
1132 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1133 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1134 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1135 HME.updateAllRanges(MI);
1139 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1140 MachineBasicBlock::iterator Begin,
1141 MachineBasicBlock::iterator End,
1142 ArrayRef<unsigned> OrigRegs) {
1143 // Find anchor points, which are at the beginning/end of blocks or at
1144 // instructions that already have indexes.
1145 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1147 while (End != MBB->end() && !Indexes->hasIndex(End))
1151 if (End == MBB->end())
1152 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1154 endIdx = getInstructionIndex(End);
1156 Indexes->repairIndexesInRange(MBB, Begin, End);
1158 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1160 MachineInstr *MI = I;
1161 if (MI->isDebugValue())
1163 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1164 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1166 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1167 !hasInterval(MOI->getReg())) {
1168 createAndComputeVirtRegInterval(MOI->getReg());
1173 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1174 unsigned Reg = OrigRegs[i];
1175 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1178 LiveInterval &LI = getInterval(Reg);
1179 // FIXME: Should we support undefs that gain defs?
1180 if (!LI.hasAtLeastOneValue())
1183 LiveInterval::iterator LII = LI.find(endIdx);
1184 SlotIndex lastUseIdx;
1185 if (LII != LI.end() && LII->start < endIdx)
1186 lastUseIdx = LII->end;
1190 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1192 MachineInstr *MI = I;
1193 if (MI->isDebugValue())
1196 SlotIndex instrIdx = getInstructionIndex(MI);
1197 bool isStartValid = getInstructionFromIndex(LII->start);
1198 bool isEndValid = getInstructionFromIndex(LII->end);
1200 // FIXME: This doesn't currently handle early-clobber or multiple removed
1201 // defs inside of the region to repair.
1202 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1203 OE = MI->operands_end(); OI != OE; ++OI) {
1204 const MachineOperand &MO = *OI;
1205 if (!MO.isReg() || MO.getReg() != Reg)
1209 if (!isStartValid) {
1210 if (LII->end.isDead()) {
1211 SlotIndex prevStart;
1212 if (LII != LI.begin())
1213 prevStart = std::prev(LII)->start;
1215 // FIXME: This could be more efficient if there was a
1216 // removeSegment method that returned an iterator.
1217 LI.removeSegment(*LII, true);
1218 if (prevStart.isValid())
1219 LII = LI.find(prevStart);
1223 LII->start = instrIdx.getRegSlot();
1224 LII->valno->def = instrIdx.getRegSlot();
1225 if (MO.getSubReg() && !MO.isUndef())
1226 lastUseIdx = instrIdx.getRegSlot();
1228 lastUseIdx = SlotIndex();
1233 if (!lastUseIdx.isValid()) {
1234 VNInfo *VNI = LI.getNextValue(instrIdx.getRegSlot(),
1236 LiveRange::Segment S(instrIdx.getRegSlot(),
1237 instrIdx.getDeadSlot(), VNI);
1238 LII = LI.addSegment(S);
1239 } else if (LII->start != instrIdx.getRegSlot()) {
1240 VNInfo *VNI = LI.getNextValue(instrIdx.getRegSlot(),
1242 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1243 LII = LI.addSegment(S);
1246 if (MO.getSubReg() && !MO.isUndef())
1247 lastUseIdx = instrIdx.getRegSlot();
1249 lastUseIdx = SlotIndex();
1250 } else if (MO.isUse()) {
1251 // FIXME: This should probably be handled outside of this branch,
1252 // either as part of the def case (for defs inside of the region) or
1253 // after the loop over the region.
1254 if (!isEndValid && !LII->end.isBlock())
1255 LII->end = instrIdx.getRegSlot();
1256 if (!lastUseIdx.isValid())
1257 lastUseIdx = instrIdx.getRegSlot();