1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/LoopInfo.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "Support/CommandLine.h"
31 #include "Support/Debug.h"
32 #include "Support/Statistic.h"
33 #include "Support/STLExtras.h"
34 #include "VirtRegMap.h"
40 RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis");
42 Statistic<> numIntervals
43 ("liveintervals", "Number of original intervals");
45 Statistic<> numIntervalsAfter
46 ("liveintervals", "Number of intervals after coalescing");
49 ("liveintervals", "Number of interval joins performed");
52 ("liveintervals", "Number of identity moves eliminated after coalescing");
55 ("liveintervals", "Number of loads/stores folded into instructions");
58 EnableJoining("join-liveintervals",
59 cl::desc("Join compatible live intervals"),
63 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
65 AU.addPreserved<LiveVariables>();
66 AU.addRequired<LiveVariables>();
67 AU.addPreservedID(PHIEliminationID);
68 AU.addRequiredID(PHIEliminationID);
69 AU.addRequiredID(TwoAddressInstructionPassID);
70 AU.addRequired<LoopInfo>();
71 MachineFunctionPass::getAnalysisUsage(AU);
74 void LiveIntervals::releaseMemory()
83 /// runOnMachineFunction - Register allocate the whole function
85 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
87 tm_ = &fn.getTarget();
88 mri_ = tm_->getRegisterInfo();
89 lv_ = &getAnalysis<LiveVariables>();
90 allocatableRegs_ = mri_->getAllocatableSet(fn);
92 // number MachineInstrs
94 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
96 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
98 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
99 assert(inserted && "multiple MachineInstr -> index mappings");
100 i2miMap_.push_back(mi);
101 miIndex += InstrSlots::NUM;
106 numIntervals += getNumIntervals();
109 DEBUG(std::cerr << "********** INTERVALS **********\n");
110 DEBUG(for (iterator I = begin(), E = end(); I != E; ++I)
111 std::cerr << I->second << "\n");
114 // join intervals if requested
115 if (EnableJoining) joinIntervals();
117 numIntervalsAfter += getNumIntervals();
119 // perform a final pass over the instructions and compute spill
120 // weights, coalesce virtual registers and remove identity moves
121 const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
122 const TargetInstrInfo& tii = *tm_->getInstrInfo();
124 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
125 mbbi != mbbe; ++mbbi) {
126 MachineBasicBlock* mbb = mbbi;
127 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
129 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
131 // if the move will be an identity move delete it
132 unsigned srcReg, dstReg, RegRep;
133 if (tii.isMoveInstr(*mii, srcReg, dstReg) &&
134 (RegRep = rep(srcReg)) == rep(dstReg)) {
135 // remove from def list
136 LiveInterval &interval = getOrCreateInterval(RegRep);
137 // remove index -> MachineInstr and
138 // MachineInstr -> index mappings
139 Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii);
140 if (mi2i != mi2iMap_.end()) {
141 i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
142 mi2iMap_.erase(mi2i);
144 mii = mbbi->erase(mii);
148 for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
149 const MachineOperand& mop = mii->getOperand(i);
150 if (mop.isRegister() && mop.getReg() &&
151 MRegisterInfo::isVirtualRegister(mop.getReg())) {
152 // replace register with representative register
153 unsigned reg = rep(mop.getReg());
154 mii->SetMachineOperandReg(i, reg);
156 LiveInterval &RegInt = getInterval(reg);
158 (mop.isUse() + mop.isDef()) * pow(10.0F, loopDepth);
166 DEBUG(std::cerr << "********** INTERVALS **********\n");
167 DEBUG (for (iterator I = begin(), E = end(); I != E; ++I)
168 std::cerr << I->second << "\n");
169 DEBUG(std::cerr << "********** MACHINEINSTRS **********\n");
171 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
172 mbbi != mbbe; ++mbbi) {
173 std::cerr << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
174 for (MachineBasicBlock::iterator mii = mbbi->begin(),
175 mie = mbbi->end(); mii != mie; ++mii) {
176 std::cerr << getInstructionIndex(mii) << '\t';
177 mii->print(std::cerr, tm_);
184 std::vector<LiveInterval*> LiveIntervals::addIntervalsForSpills(
185 const LiveInterval& li,
189 // since this is called after the analysis is done we don't know if
190 // LiveVariables is available
191 lv_ = getAnalysisToUpdate<LiveVariables>();
193 std::vector<LiveInterval*> added;
195 assert(li.weight != HUGE_VAL &&
196 "attempt to spill already spilled interval!");
198 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "
201 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
203 for (LiveInterval::Ranges::const_iterator
204 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
205 unsigned index = getBaseIndex(i->start);
206 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
207 for (; index != end; index += InstrSlots::NUM) {
208 // skip deleted instructions
209 while (index != end && !getInstructionFromIndex(index))
210 index += InstrSlots::NUM;
211 if (index == end) break;
213 MachineBasicBlock::iterator mi = getInstructionFromIndex(index);
216 for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
217 MachineOperand& mop = mi->getOperand(i);
218 if (mop.isRegister() && mop.getReg() == li.reg) {
219 if (MachineInstr* fmi = mri_->foldMemoryOperand(mi, i, slot)) {
221 lv_->instructionChanged(mi, fmi);
222 vrm.virtFolded(li.reg, mi, fmi);
224 i2miMap_[index/InstrSlots::NUM] = fmi;
225 mi2iMap_[fmi] = index;
226 MachineBasicBlock& mbb = *mi->getParent();
227 mi = mbb.insert(mbb.erase(mi), fmi);
232 // This is tricky. We need to add information in
233 // the interval about the spill code so we have to
234 // use our extra load/store slots.
236 // If we have a use we are going to have a load so
237 // we start the interval from the load slot
238 // onwards. Otherwise we start from the def slot.
239 unsigned start = (mop.isUse() ?
240 getLoadIndex(index) :
242 // If we have a def we are going to have a store
243 // right after it so we end the interval after the
244 // use of the next instruction. Otherwise we end
245 // after the use of this instruction.
246 unsigned end = 1 + (mop.isDef() ?
247 getStoreIndex(index) :
250 // create a new register for this spill
251 unsigned nReg = mf_->getSSARegMap()->createVirtualRegister(rc);
252 mi->SetMachineOperandReg(i, nReg);
254 vrm.assignVirt2StackSlot(nReg, slot);
255 LiveInterval& nI = getOrCreateInterval(nReg);
257 // the spill weight is now infinity as it
258 // cannot be spilled again
259 nI.weight = HUGE_VAL;
260 LiveRange LR(start, end, nI.getNextValue());
261 DEBUG(std::cerr << " +" << LR);
263 added.push_back(&nI);
264 // update live variables if it is available
266 lv_->addVirtualRegisterKilled(nReg, mi);
267 DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n');
277 void LiveIntervals::printRegName(unsigned reg) const
279 if (MRegisterInfo::isPhysicalRegister(reg))
280 std::cerr << mri_->getName(reg);
282 std::cerr << "%reg" << reg;
285 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
286 MachineBasicBlock::iterator mi,
287 LiveInterval& interval)
289 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
290 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
292 // Virtual registers may be defined multiple times (due to phi
293 // elimination and 2-addr elimination). Much of what we do only has to be
294 // done once for the vreg. We use an empty interval to detect the first
295 // time we see a vreg.
296 if (interval.empty()) {
297 // Get the Idx of the defining instructions.
298 unsigned defIndex = getDefIndex(getInstructionIndex(mi));
300 unsigned ValNum = interval.getNextValue();
301 assert(ValNum == 0 && "First value in interval is not 0?");
302 ValNum = 0; // Clue in the optimizer.
304 // Loop over all of the blocks that the vreg is defined in. There are
305 // two cases we have to handle here. The most common case is a vreg
306 // whose lifetime is contained within a basic block. In this case there
307 // will be a single kill, in MBB, which comes after the definition.
308 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
309 // FIXME: what about dead vars?
311 if (vi.Kills[0] != mi)
312 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
314 killIdx = defIndex+1;
316 // If the kill happens after the definition, we have an intra-block
318 if (killIdx > defIndex) {
319 assert(vi.AliveBlocks.empty() &&
320 "Shouldn't be alive across any blocks!");
321 LiveRange LR(defIndex, killIdx, ValNum);
322 interval.addRange(LR);
323 DEBUG(std::cerr << " +" << LR << "\n");
328 // The other case we handle is when a virtual register lives to the end
329 // of the defining block, potentially live across some blocks, then is
330 // live into some number of blocks, but gets killed. Start by adding a
331 // range that goes from this definition to the end of the defining block.
332 LiveRange NewLR(defIndex, getInstructionIndex(&mbb->back()) +
333 InstrSlots::NUM, ValNum);
334 DEBUG(std::cerr << " +" << NewLR);
335 interval.addRange(NewLR);
337 // Iterate over all of the blocks that the variable is completely
338 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
340 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
341 if (vi.AliveBlocks[i]) {
342 MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
344 LiveRange LR(getInstructionIndex(&mbb->front()),
345 getInstructionIndex(&mbb->back())+InstrSlots::NUM,
347 interval.addRange(LR);
348 DEBUG(std::cerr << " +" << LR);
353 // Finally, this virtual register is live from the start of any killing
354 // block to the 'use' slot of the killing instruction.
355 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
356 MachineInstr *Kill = vi.Kills[i];
357 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
358 getUseIndex(getInstructionIndex(Kill))+1, ValNum);
359 interval.addRange(LR);
360 DEBUG(std::cerr << " +" << LR);
364 // If this is the second time we see a virtual register definition, it
365 // must be due to phi elimination or two addr elimination. If this is
366 // the result of two address elimination, then the vreg is the first
367 // operand, and is a def-and-use.
368 if (mi->getOperand(0).isRegister() &&
369 mi->getOperand(0).getReg() == interval.reg &&
370 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
371 // If this is a two-address definition, then we have already processed
372 // the live range. The only problem is that we didn't realize there
373 // are actually two values in the live interval. Because of this we
374 // need to take the LiveRegion that defines this register and split it
376 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
377 unsigned RedefIndex = getDefIndex(getInstructionIndex(mi));
379 // Delete the initial value, which should be short and continuous,
380 // becuase the 2-addr copy must be in the same MBB as the redef.
381 interval.removeRange(DefIndex, RedefIndex);
383 LiveRange LR(DefIndex, RedefIndex, interval.getNextValue());
384 DEBUG(std::cerr << " replace range with " << LR);
385 interval.addRange(LR);
387 // If this redefinition is dead, we need to add a dummy unit live
388 // range covering the def slot.
389 for (LiveVariables::killed_iterator KI = lv_->dead_begin(mi),
390 E = lv_->dead_end(mi); KI != E; ++KI)
391 if (KI->second == interval.reg) {
392 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
396 DEBUG(std::cerr << "RESULT: " << interval);
399 // Otherwise, this must be because of phi elimination. If this is the
400 // first redefinition of the vreg that we have seen, go back and change
401 // the live range in the PHI block to be a different value number.
402 if (interval.containsOneValue()) {
403 assert(vi.Kills.size() == 1 &&
404 "PHI elimination vreg should have one kill, the PHI itself!");
406 // Remove the old range that we now know has an incorrect number.
407 MachineInstr *Killer = vi.Kills[0];
408 unsigned Start = getInstructionIndex(Killer->getParent()->begin());
409 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
410 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: "
411 << interval << "\n");
412 interval.removeRange(Start, End);
413 DEBUG(std::cerr << "RESULT: " << interval);
415 // Replace the interval with one of a NEW value number.
416 LiveRange LR(Start, End, interval.getNextValue());
417 DEBUG(std::cerr << " replace range with " << LR);
418 interval.addRange(LR);
419 DEBUG(std::cerr << "RESULT: " << interval);
422 // In the case of PHI elimination, each variable definition is only
423 // live until the end of the block. We've already taken care of the
424 // rest of the live range.
425 unsigned defIndex = getDefIndex(getInstructionIndex(mi));
426 LiveRange LR(defIndex,
427 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
428 interval.getNextValue());
429 interval.addRange(LR);
430 DEBUG(std::cerr << " +" << LR);
434 DEBUG(std::cerr << '\n');
437 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
438 MachineBasicBlock::iterator mi,
439 LiveInterval& interval)
441 // A physical register cannot be live across basic block, so its
442 // lifetime must end somewhere in its defining basic block.
443 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
444 typedef LiveVariables::killed_iterator KillIter;
446 unsigned baseIndex = getInstructionIndex(mi);
447 unsigned start = getDefIndex(baseIndex);
448 unsigned end = start;
450 // If it is not used after definition, it is considered dead at
451 // the instruction defining it. Hence its interval is:
452 // [defSlot(def), defSlot(def)+1)
453 for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi);
455 if (interval.reg == ki->second) {
456 DEBUG(std::cerr << " dead");
457 end = getDefIndex(start) + 1;
462 // If it is not dead on definition, it must be killed by a
463 // subsequent instruction. Hence its interval is:
464 // [defSlot(def), useSlot(kill)+1)
467 assert(mi != MBB->end() && "physreg was not killed in defining block!");
468 baseIndex += InstrSlots::NUM;
469 for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi);
471 if (interval.reg == ki->second) {
472 DEBUG(std::cerr << " killed");
473 end = getUseIndex(baseIndex) + 1;
480 assert(start < end && "did not find end of interval?");
481 LiveRange LR(start, end, interval.getNextValue());
482 interval.addRange(LR);
483 DEBUG(std::cerr << " +" << LR << '\n');
486 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
487 MachineBasicBlock::iterator MI,
489 if (MRegisterInfo::isVirtualRegister(reg))
490 handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg));
491 else if (allocatableRegs_[reg]) {
492 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg));
493 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
494 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS));
498 /// computeIntervals - computes the live intervals for virtual
499 /// registers. for some ordering of the machine instructions [1,N] a
500 /// live interval is an interval [i, j) where 1 <= i <= j < N for
501 /// which a variable is live
502 void LiveIntervals::computeIntervals()
504 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
505 DEBUG(std::cerr << "********** Function: "
506 << ((Value*)mf_->getFunction())->getName() << '\n');
508 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
510 MachineBasicBlock* mbb = I;
511 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
513 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
515 const TargetInstrDescriptor& tid =
516 tm_->getInstrInfo()->get(mi->getOpcode());
517 DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
518 mi->print(std::cerr, tm_));
520 // handle implicit defs
521 for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
522 handleRegisterDef(mbb, mi, *id);
524 // handle explicit defs
525 for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
526 MachineOperand& mop = mi->getOperand(i);
527 // handle register defs - build intervals
528 if (mop.isRegister() && mop.getReg() && mop.isDef())
529 handleRegisterDef(mbb, mi, mop.getReg());
535 void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) {
536 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
537 const TargetInstrInfo &TII = *tm_->getInstrInfo();
539 for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end();
541 DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi);
543 // we only join virtual registers with allocatable
544 // physical registers since we do not have liveness information
545 // on not allocatable physical registers
547 if (TII.isMoveInstr(*mi, regA, regB) &&
548 (MRegisterInfo::isVirtualRegister(regA) || allocatableRegs_[regA]) &&
549 (MRegisterInfo::isVirtualRegister(regB) || allocatableRegs_[regB])) {
551 // Get representative registers.
555 // If they are already joined we continue.
559 // If they are both physical registers, we cannot join them.
560 if (MRegisterInfo::isPhysicalRegister(regA) &&
561 MRegisterInfo::isPhysicalRegister(regB))
564 // If they are not of the same register class, we cannot join them.
565 if (differingRegisterClasses(regA, regB))
568 LiveInterval &IntA = getInterval(regA);
569 LiveInterval &IntB = getInterval(regB);
570 assert(IntA.reg == regA && IntB.reg == regB &&
571 "Register mapping is horribly broken!");
573 DEBUG(std::cerr << "\t\tInspecting " << IntA << " and " << IntB << ": ");
575 // If two intervals contain a single value and are joined by a copy, it
576 // does not matter if the intervals overlap, they can always be joined.
577 bool TriviallyJoinable =
578 IntA.containsOneValue() && IntB.containsOneValue();
580 unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi));
581 if ((TriviallyJoinable || IntB.joinable(IntA, MIDefIdx)) &&
582 !overlapsAliases(&IntA, &IntB)) {
583 IntB.join(IntA, MIDefIdx);
585 if (!MRegisterInfo::isPhysicalRegister(regA)) {
587 r2rMap_[regA] = regB;
589 // Otherwise merge the data structures the other way so we don't lose
590 // the physreg information.
591 r2rMap_[regB] = regA;
596 DEBUG(std::cerr << "Joined. Result = " << IntB << "\n");
599 DEBUG(std::cerr << "Interference!\n");
606 // DepthMBBCompare - Comparison predicate that sort first based on the loop
607 // depth of the basic block (the unsigned), and then on the MBB number.
608 struct DepthMBBCompare {
609 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
610 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
611 if (LHS.first > RHS.first) return true; // Deeper loops first
612 return LHS.first == RHS.first &&
613 LHS.second->getNumber() < RHS.second->getNumber();
618 void LiveIntervals::joinIntervals() {
619 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
621 const LoopInfo &LI = getAnalysis<LoopInfo>();
622 if (LI.begin() == LI.end()) {
623 // If there are no loops in the function, join intervals in function order.
624 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
626 joinIntervalsInMachineBB(I);
628 // Otherwise, join intervals in inner loops before other intervals.
629 // Unfortunately we can't just iterate over loop hierarchy here because
630 // there may be more MBB's than BB's. Collect MBB's for sorting.
631 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
632 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
634 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
636 // Sort by loop depth.
637 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
639 // Finally, join intervals in loop nest order.
640 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
641 joinIntervalsInMachineBB(MBBs[i].second);
644 DEBUG(std::cerr << "*** Register mapping ***\n");
645 DEBUG(for (std::map<unsigned, unsigned>::iterator I = r2rMap_.begin(),
646 E = r2rMap_.end(); I != E; ++I)
647 std::cerr << " reg " << I->first << " -> reg " << I->second << "\n";);
650 /// Return true if the two specified registers belong to different register
651 /// classes. The registers may be either phys or virt regs.
652 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
653 unsigned RegB) const {
654 const TargetRegisterClass *RegClass;
656 // Get the register classes for the first reg.
657 if (MRegisterInfo::isVirtualRegister(RegA))
658 RegClass = mf_->getSSARegMap()->getRegClass(RegA);
660 RegClass = mri_->getRegClass(RegA);
662 // Compare against the regclass for the second reg.
663 if (MRegisterInfo::isVirtualRegister(RegB))
664 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
666 return !RegClass->contains(RegB);
669 bool LiveIntervals::overlapsAliases(const LiveInterval *LHS,
670 const LiveInterval *RHS) const {
671 if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) {
672 if (!MRegisterInfo::isPhysicalRegister(RHS->reg))
673 return false; // vreg-vreg merge has no aliases!
677 assert(MRegisterInfo::isPhysicalRegister(LHS->reg) &&
678 MRegisterInfo::isVirtualRegister(RHS->reg) &&
679 "first interval must describe a physical register");
681 for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS)
682 if (RHS->overlaps(getInterval(*AS)))
688 LiveInterval LiveIntervals::createInterval(unsigned reg) {
689 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? HUGE_VAL :0.0F;
690 return LiveInterval(reg, Weight);