1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/DenseSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "LiveRangeCalc.h"
43 // Temporary option to enable regunit liveness.
44 static cl::opt<bool> LiveRegUnits("live-regunits", cl::Hidden);
46 STATISTIC(numIntervals , "Number of original intervals");
48 char LiveIntervals::ID = 0;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
58 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
60 AU.addRequired<AliasAnalysis>();
61 AU.addPreserved<AliasAnalysis>();
62 AU.addRequired<LiveVariables>();
63 AU.addPreserved<LiveVariables>();
64 AU.addPreservedID(MachineLoopInfoID);
66 AU.addRequiredTransitiveID(MachineDominatorsID);
67 AU.addPreservedID(MachineDominatorsID);
68 AU.addPreserved<SlotIndexes>();
69 AU.addRequiredTransitive<SlotIndexes>();
70 MachineFunctionPass::getAnalysisUsage(AU);
73 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
74 DomTree(0), LRCalc(0) {
75 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
78 LiveIntervals::~LiveIntervals() {
82 void LiveIntervals::releaseMemory() {
83 // Free the live intervals themselves.
84 for (DenseMap<unsigned, LiveInterval*>::iterator I = R2IMap.begin(),
85 E = R2IMap.end(); I != E; ++I)
91 RegMaskBlocks.clear();
93 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
94 delete RegUnitIntervals[i];
95 RegUnitIntervals.clear();
97 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
98 VNInfoAllocator.Reset();
101 /// runOnMachineFunction - Register allocate the whole function
103 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
105 MRI = &MF->getRegInfo();
106 TM = &fn.getTarget();
107 TRI = TM->getRegisterInfo();
108 TII = TM->getInstrInfo();
109 AA = &getAnalysis<AliasAnalysis>();
110 LV = &getAnalysis<LiveVariables>();
111 Indexes = &getAnalysis<SlotIndexes>();
113 DomTree = &getAnalysis<MachineDominatorTree>();
114 if (LiveRegUnits && !LRCalc)
115 LRCalc = new LiveRangeCalc();
116 AllocatableRegs = TRI->getAllocatableSet(fn);
117 ReservedRegs = TRI->getReservedRegs(fn);
121 numIntervals += getNumIntervals();
124 computeLiveInRegUnits();
131 /// print - Implement the dump method.
132 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
133 OS << "********** INTERVALS **********\n";
135 // Dump the physregs.
136 for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
137 if (const LiveInterval *LI = R2IMap.lookup(Reg))
138 OS << PrintReg(Reg, TRI) << '\t' << *LI << '\n';
140 // Dump the regunits.
141 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
142 if (LiveInterval *LI = RegUnitIntervals[i])
143 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
145 // Dump the virtregs.
146 for (unsigned Reg = 0, RegE = MRI->getNumVirtRegs(); Reg != RegE; ++Reg)
147 if (const LiveInterval *LI =
148 R2IMap.lookup(TargetRegisterInfo::index2VirtReg(Reg)))
149 OS << PrintReg(LI->reg) << '\t' << *LI << '\n';
154 void LiveIntervals::printInstrs(raw_ostream &OS) const {
155 OS << "********** MACHINEINSTRS **********\n";
156 MF->print(OS, Indexes);
159 void LiveIntervals::dumpInstrs() const {
164 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
165 unsigned Reg = MI.getOperand(MOIdx).getReg();
166 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
167 const MachineOperand &MO = MI.getOperand(i);
170 if (MO.getReg() == Reg && MO.isDef()) {
171 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
172 MI.getOperand(MOIdx).getSubReg() &&
173 (MO.getSubReg() || MO.isImplicit()));
180 /// isPartialRedef - Return true if the specified def at the specific index is
181 /// partially re-defining the specified live interval. A common case of this is
182 /// a definition of the sub-register.
183 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
184 LiveInterval &interval) {
185 if (!MO.getSubReg() || MO.isEarlyClobber())
188 SlotIndex RedefIndex = MIIdx.getRegSlot();
189 const LiveRange *OldLR =
190 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
191 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
193 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
198 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
199 MachineBasicBlock::iterator mi,
203 LiveInterval &interval) {
204 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
206 // Virtual registers may be defined multiple times (due to phi
207 // elimination and 2-addr elimination). Much of what we do only has to be
208 // done once for the vreg. We use an empty interval to detect the first
209 // time we see a vreg.
210 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
211 if (interval.empty()) {
212 // Get the Idx of the defining instructions.
213 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
215 // Make sure the first definition is not a partial redefinition.
216 assert(!MO.readsReg() && "First def cannot also read virtual register "
217 "missing <undef> flag?");
219 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
220 assert(ValNo->id == 0 && "First value in interval is not 0?");
222 // Loop over all of the blocks that the vreg is defined in. There are
223 // two cases we have to handle here. The most common case is a vreg
224 // whose lifetime is contained within a basic block. In this case there
225 // will be a single kill, in MBB, which comes after the definition.
226 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
227 // FIXME: what about dead vars?
229 if (vi.Kills[0] != mi)
230 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
232 killIdx = defIndex.getDeadSlot();
234 // If the kill happens after the definition, we have an intra-block
236 if (killIdx > defIndex) {
237 assert(vi.AliveBlocks.empty() &&
238 "Shouldn't be alive across any blocks!");
239 LiveRange LR(defIndex, killIdx, ValNo);
240 interval.addRange(LR);
241 DEBUG(dbgs() << " +" << LR << "\n");
246 // The other case we handle is when a virtual register lives to the end
247 // of the defining block, potentially live across some blocks, then is
248 // live into some number of blocks, but gets killed. Start by adding a
249 // range that goes from this definition to the end of the defining block.
250 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
251 DEBUG(dbgs() << " +" << NewLR);
252 interval.addRange(NewLR);
254 bool PHIJoin = LV->isPHIJoin(interval.reg);
257 // A phi join register is killed at the end of the MBB and revived as a
258 // new valno in the killing blocks.
259 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
260 DEBUG(dbgs() << " phi-join");
261 ValNo->setHasPHIKill(true);
263 // Iterate over all of the blocks that the variable is completely
264 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
266 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
267 E = vi.AliveBlocks.end(); I != E; ++I) {
268 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
269 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock),
271 interval.addRange(LR);
272 DEBUG(dbgs() << " +" << LR);
276 // Finally, this virtual register is live from the start of any killing
277 // block to the 'use' slot of the killing instruction.
278 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
279 MachineInstr *Kill = vi.Kills[i];
280 SlotIndex Start = getMBBStartIdx(Kill->getParent());
281 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
283 // Create interval with one of a NEW value number. Note that this value
284 // number isn't actually defined by an instruction, weird huh? :)
286 assert(getInstructionFromIndex(Start) == 0 &&
287 "PHI def index points at actual instruction.");
288 ValNo = interval.getNextValue(Start, VNInfoAllocator);
289 ValNo->setIsPHIDef(true);
291 LiveRange LR(Start, killIdx, ValNo);
292 interval.addRange(LR);
293 DEBUG(dbgs() << " +" << LR);
297 if (MultipleDefsBySameMI(*mi, MOIdx))
298 // Multiple defs of the same virtual register by the same instruction.
299 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
300 // This is likely due to elimination of REG_SEQUENCE instructions. Return
301 // here since there is nothing to do.
304 // If this is the second time we see a virtual register definition, it
305 // must be due to phi elimination or two addr elimination. If this is
306 // the result of two address elimination, then the vreg is one of the
307 // def-and-use register operand.
309 // It may also be partial redef like this:
310 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
311 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
312 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
313 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
314 // If this is a two-address definition, then we have already processed
315 // the live range. The only problem is that we didn't realize there
316 // are actually two values in the live interval. Because of this we
317 // need to take the LiveRegion that defines this register and split it
319 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
321 const LiveRange *OldLR =
322 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
323 VNInfo *OldValNo = OldLR->valno;
324 SlotIndex DefIndex = OldValNo->def.getRegSlot();
326 // Delete the previous value, which should be short and continuous,
327 // because the 2-addr copy must be in the same MBB as the redef.
328 interval.removeRange(DefIndex, RedefIndex);
330 // The new value number (#1) is defined by the instruction we claimed
332 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
334 // Value#0 is now defined by the 2-addr instruction.
335 OldValNo->def = RedefIndex;
337 // Add the new live interval which replaces the range for the input copy.
338 LiveRange LR(DefIndex, RedefIndex, ValNo);
339 DEBUG(dbgs() << " replace range with " << LR);
340 interval.addRange(LR);
342 // If this redefinition is dead, we need to add a dummy unit live
343 // range covering the def slot.
345 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
348 DEBUG(dbgs() << " RESULT: " << interval);
349 } else if (LV->isPHIJoin(interval.reg)) {
350 // In the case of PHI elimination, each variable definition is only
351 // live until the end of the block. We've already taken care of the
352 // rest of the live range.
354 SlotIndex defIndex = MIIdx.getRegSlot();
355 if (MO.isEarlyClobber())
356 defIndex = MIIdx.getRegSlot(true);
358 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
360 SlotIndex killIndex = getMBBEndIdx(mbb);
361 LiveRange LR(defIndex, killIndex, ValNo);
362 interval.addRange(LR);
363 ValNo->setHasPHIKill(true);
364 DEBUG(dbgs() << " phi-join +" << LR);
366 llvm_unreachable("Multiply defined register");
370 DEBUG(dbgs() << '\n');
373 static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
374 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
375 SE = MBB->succ_end();
377 const MachineBasicBlock* succ = *SI;
378 if (succ->isLiveIn(Reg))
384 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
385 MachineBasicBlock::iterator mi,
388 LiveInterval &interval) {
389 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
391 SlotIndex baseIndex = MIIdx;
392 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
393 SlotIndex end = start;
395 // If it is not used after definition, it is considered dead at
396 // the instruction defining it. Hence its interval is:
397 // [defSlot(def), defSlot(def)+1)
398 // For earlyclobbers, the defSlot was pushed back one; the extra
399 // advance below compensates.
401 DEBUG(dbgs() << " dead");
402 end = start.getDeadSlot();
406 // If it is not dead on definition, it must be killed by a
407 // subsequent instruction. Hence its interval is:
408 // [defSlot(def), useSlot(kill)+1)
409 baseIndex = baseIndex.getNextIndex();
410 while (++mi != MBB->end()) {
412 if (mi->isDebugValue())
414 if (getInstructionFromIndex(baseIndex) == 0)
415 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
417 if (mi->killsRegister(interval.reg, TRI)) {
418 DEBUG(dbgs() << " killed");
419 end = baseIndex.getRegSlot();
422 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,TRI);
424 if (mi->isRegTiedToUseOperand(DefIdx)) {
425 // Two-address instruction.
426 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
428 // Another instruction redefines the register before it is ever read.
429 // Then the register is essentially dead at the instruction that
430 // defines it. Hence its interval is:
431 // [defSlot(def), defSlot(def)+1)
432 DEBUG(dbgs() << " dead");
433 end = start.getDeadSlot();
439 baseIndex = baseIndex.getNextIndex();
442 // If we get here the register *should* be live out.
443 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
445 // FIXME: We need saner rules for reserved regs.
446 if (isReserved(interval.reg)) {
447 end = start.getDeadSlot();
449 // Unreserved, unallocable registers like EFLAGS can be live across basic
451 assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
452 "Unreserved reg not live-out?");
453 end = getMBBEndIdx(MBB);
456 assert(start < end && "did not find end of interval?");
458 // Already exists? Extend old live interval.
459 VNInfo *ValNo = interval.getVNInfoAt(start);
460 bool Extend = ValNo != 0;
462 ValNo = interval.getNextValue(start, VNInfoAllocator);
463 LiveRange LR(start, end, ValNo);
464 interval.addRange(LR);
465 DEBUG(dbgs() << " +" << LR << '\n');
468 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
469 MachineBasicBlock::iterator MI,
473 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
474 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
475 getOrCreateInterval(MO.getReg()));
477 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
478 getOrCreateInterval(MO.getReg()));
481 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
483 LiveInterval &interval) {
484 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
485 "Only physical registers can be live in.");
486 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
487 MBB->isLandingPad()) &&
488 "Allocatable live-ins only valid for entry blocks and landing pads.");
490 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, TRI));
492 // Look for kills, if it reaches a def before it's killed, then it shouldn't
493 // be considered a livein.
494 MachineBasicBlock::iterator mi = MBB->begin();
495 MachineBasicBlock::iterator E = MBB->end();
496 // Skip over DBG_VALUE at the start of the MBB.
497 if (mi != E && mi->isDebugValue()) {
498 while (++mi != E && mi->isDebugValue())
501 // MBB is empty except for DBG_VALUE's.
505 SlotIndex baseIndex = MIIdx;
506 SlotIndex start = baseIndex;
507 if (getInstructionFromIndex(baseIndex) == 0)
508 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
510 SlotIndex end = baseIndex;
511 bool SeenDefUse = false;
514 if (mi->killsRegister(interval.reg, TRI)) {
515 DEBUG(dbgs() << " killed");
516 end = baseIndex.getRegSlot();
519 } else if (mi->modifiesRegister(interval.reg, TRI)) {
520 // Another instruction redefines the register before it is ever read.
521 // Then the register is essentially dead at the instruction that defines
522 // it. Hence its interval is:
523 // [defSlot(def), defSlot(def)+1)
524 DEBUG(dbgs() << " dead");
525 end = start.getDeadSlot();
530 while (++mi != E && mi->isDebugValue())
531 // Skip over DBG_VALUE.
534 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
537 // Live-in register might not be used at all.
539 if (isAllocatable(interval.reg) ||
540 !isRegLiveIntoSuccessor(MBB, interval.reg)) {
541 // Allocatable registers are never live through.
542 // Non-allocatable registers that aren't live into any successors also
543 // aren't live through.
544 DEBUG(dbgs() << " dead");
547 // If we get here the register is non-allocatable and live into some
548 // successor. We'll conservatively assume it's live-through.
549 DEBUG(dbgs() << " live through");
550 end = getMBBEndIdx(MBB);
554 SlotIndex defIdx = getMBBStartIdx(MBB);
555 assert(getInstructionFromIndex(defIdx) == 0 &&
556 "PHI def index points at actual instruction.");
557 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
558 vni->setIsPHIDef(true);
559 LiveRange LR(start, end, vni);
561 interval.addRange(LR);
562 DEBUG(dbgs() << " +" << LR << '\n');
565 /// computeIntervals - computes the live intervals for virtual
566 /// registers. for some ordering of the machine instructions [1,N] a
567 /// live interval is an interval [i, j) where 1 <= i <= j < N for
568 /// which a variable is live
569 void LiveIntervals::computeIntervals() {
570 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
571 << "********** Function: "
572 << ((Value*)MF->getFunction())->getName() << '\n');
574 RegMaskBlocks.resize(MF->getNumBlockIDs());
576 SmallVector<unsigned, 8> UndefUses;
577 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
579 MachineBasicBlock *MBB = MBBI;
580 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
585 // Track the index of the current machine instr.
586 SlotIndex MIIndex = getMBBStartIdx(MBB);
587 DEBUG(dbgs() << "BB#" << MBB->getNumber()
588 << ":\t\t# derived from " << MBB->getName() << "\n");
590 // Create intervals for live-ins to this BB first.
591 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
592 LE = MBB->livein_end(); LI != LE; ++LI) {
593 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
596 // Skip over empty initial indices.
597 if (getInstructionFromIndex(MIIndex) == 0)
598 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
600 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
602 DEBUG(dbgs() << MIIndex << "\t" << *MI);
603 if (MI->isDebugValue())
605 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
606 "Lost SlotIndex synchronization");
609 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
610 MachineOperand &MO = MI->getOperand(i);
612 // Collect register masks.
613 if (MO.isRegMask()) {
614 RegMaskSlots.push_back(MIIndex.getRegSlot());
615 RegMaskBits.push_back(MO.getRegMask());
619 if (!MO.isReg() || !MO.getReg())
622 // handle register defs - build intervals
624 handleRegisterDef(MBB, MI, MIIndex, MO, i);
625 else if (MO.isUndef())
626 UndefUses.push_back(MO.getReg());
629 // Move to the next instr slot.
630 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
633 // Compute the number of register mask instructions in this block.
634 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
635 RMB.second = RegMaskSlots.size() - RMB.first;;
638 // Create empty intervals for registers defined by implicit_def's (except
639 // for those implicit_def that define values which are liveout of their
641 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
642 unsigned UndefReg = UndefUses[i];
643 (void)getOrCreateInterval(UndefReg);
647 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
648 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
649 return new LiveInterval(reg, Weight);
653 //===----------------------------------------------------------------------===//
654 // Register Unit Liveness
655 //===----------------------------------------------------------------------===//
657 // Fixed interference typically comes from ABI boundaries: Function arguments
658 // and return values are passed in fixed registers, and so are exception
659 // pointers entering landing pads. Certain instructions require values to be
660 // present in specific registers. That is also represented through fixed
664 /// computeRegUnitInterval - Compute the live interval of a register unit, based
665 /// on the uses and defs of aliasing registers. The interval should be empty,
666 /// or contain only dead phi-defs from ABI blocks.
667 void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
668 unsigned Unit = LI->reg;
670 assert(LRCalc && "LRCalc not initialized.");
671 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
673 // The physregs aliasing Unit are the roots and their super-registers.
674 // Create all values as dead defs before extending to uses. Note that roots
675 // may share super-registers. That's OK because createDeadDefs() is
676 // idempotent. It is very rare for a register unit to have multiple roots, so
677 // uniquing super-registers is probably not worthwhile.
678 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
679 unsigned Root = *Roots;
680 if (!MRI->reg_empty(Root))
681 LRCalc->createDeadDefs(LI, Root);
682 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
683 if (!MRI->reg_empty(*Supers))
684 LRCalc->createDeadDefs(LI, *Supers);
688 // Now extend LI to reach all uses.
689 // Ignore uses of reserved registers. We only track defs of those.
690 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
691 unsigned Root = *Roots;
692 if (!isReserved(Root) && !MRI->reg_empty(Root))
693 LRCalc->extendToUses(LI, Root);
694 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
695 unsigned Reg = *Supers;
696 if (!isReserved(Reg) && !MRI->reg_empty(Reg))
697 LRCalc->extendToUses(LI, Reg);
703 /// computeLiveInRegUnits - Precompute the live ranges of any register units
704 /// that are live-in to an ABI block somewhere. Register values can appear
705 /// without a corresponding def when entering the entry block or a landing pad.
707 void LiveIntervals::computeLiveInRegUnits() {
708 RegUnitIntervals.resize(TRI->getNumRegUnits());
709 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
711 // Keep track of the intervals allocated.
712 SmallVector<LiveInterval*, 8> NewIntvs;
714 // Check all basic blocks for live-ins.
715 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
717 const MachineBasicBlock *MBB = MFI;
719 // We only care about ABI blocks: Entry + landing pads.
720 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
723 // Create phi-defs at Begin for all live-in registers.
724 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
725 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
726 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
727 LIE = MBB->livein_end(); LII != LIE; ++LII) {
728 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
729 unsigned Unit = *Units;
730 LiveInterval *Intv = RegUnitIntervals[Unit];
732 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
733 NewIntvs.push_back(Intv);
735 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
737 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
740 DEBUG(dbgs() << '\n');
742 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
744 // Compute the 'normal' part of the intervals.
745 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
746 computeRegUnitInterval(NewIntvs[i]);
750 /// shrinkToUses - After removing some uses of a register, shrink its live
751 /// range to just the remaining uses. This method does not compute reaching
752 /// defs for new uses, and it doesn't remove dead defs.
753 bool LiveIntervals::shrinkToUses(LiveInterval *li,
754 SmallVectorImpl<MachineInstr*> *dead) {
755 DEBUG(dbgs() << "Shrink: " << *li << '\n');
756 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
757 && "Can only shrink virtual registers");
758 // Find all the values used, including PHI kills.
759 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
761 // Blocks that have already been added to WorkList as live-out.
762 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
764 // Visit all instructions reading li->reg.
765 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
766 MachineInstr *UseMI = I.skipInstruction();) {
767 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
769 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
770 LiveRangeQuery LRQ(*li, Idx);
771 VNInfo *VNI = LRQ.valueIn();
773 // This shouldn't happen: readsVirtualRegister returns true, but there is
774 // no live value. It is likely caused by a target getting <undef> flags
776 DEBUG(dbgs() << Idx << '\t' << *UseMI
777 << "Warning: Instr claims to read non-existent value in "
781 // Special case: An early-clobber tied operand reads and writes the
782 // register one slot early.
783 if (VNInfo *DefVNI = LRQ.valueDefined())
786 WorkList.push_back(std::make_pair(Idx, VNI));
789 // Create a new live interval with only minimal live segments per def.
790 LiveInterval NewLI(li->reg, 0);
791 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
796 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
799 // Keep track of the PHIs that are in use.
800 SmallPtrSet<VNInfo*, 8> UsedPHIs;
802 // Extend intervals to reach all uses in WorkList.
803 while (!WorkList.empty()) {
804 SlotIndex Idx = WorkList.back().first;
805 VNInfo *VNI = WorkList.back().second;
807 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
808 SlotIndex BlockStart = getMBBStartIdx(MBB);
810 // Extend the live range for VNI to be live at Idx.
811 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
813 assert(ExtVNI == VNI && "Unexpected existing value number");
814 // Is this a PHIDef we haven't seen before?
815 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
817 // The PHI is live, make sure the predecessors are live-out.
818 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
819 PE = MBB->pred_end(); PI != PE; ++PI) {
820 if (!LiveOut.insert(*PI))
822 SlotIndex Stop = getMBBEndIdx(*PI);
823 // A predecessor is not required to have a live-out value for a PHI.
824 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
825 WorkList.push_back(std::make_pair(Stop, PVNI));
830 // VNI is live-in to MBB.
831 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
832 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
834 // Make sure VNI is live-out from the predecessors.
835 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
836 PE = MBB->pred_end(); PI != PE; ++PI) {
837 if (!LiveOut.insert(*PI))
839 SlotIndex Stop = getMBBEndIdx(*PI);
840 assert(li->getVNInfoBefore(Stop) == VNI &&
841 "Wrong value out of predecessor");
842 WorkList.push_back(std::make_pair(Stop, VNI));
846 // Handle dead values.
847 bool CanSeparate = false;
848 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
853 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
854 assert(LII != NewLI.end() && "Missing live range for PHI");
855 if (LII->end != VNI->def.getDeadSlot())
857 if (VNI->isPHIDef()) {
858 // This is a dead PHI. Remove it.
859 VNI->setIsUnused(true);
860 NewLI.removeRange(*LII);
861 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
864 // This is a dead def. Make sure the instruction knows.
865 MachineInstr *MI = getInstructionFromIndex(VNI->def);
866 assert(MI && "No instruction defining live value");
867 MI->addRegisterDead(li->reg, TRI);
868 if (dead && MI->allDefsAreDead()) {
869 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
875 // Move the trimmed ranges back.
876 li->ranges.swap(NewLI.ranges);
877 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
882 //===----------------------------------------------------------------------===//
883 // Register allocator hooks.
886 void LiveIntervals::addKillFlags() {
887 for (iterator I = begin(), E = end(); I != E; ++I) {
888 unsigned Reg = I->first;
889 if (TargetRegisterInfo::isPhysicalRegister(Reg))
891 if (MRI->reg_nodbg_empty(Reg))
893 LiveInterval *LI = I->second;
895 // Every instruction that kills Reg corresponds to a live range end point.
896 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
898 // A block index indicates an MBB edge.
899 if (RI->end.isBlock())
901 MachineInstr *MI = getInstructionFromIndex(RI->end);
904 MI->addRegisterKilled(Reg, NULL);
910 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
911 // A local live range must be fully contained inside the block, meaning it is
912 // defined and killed at instructions, not at block boundaries. It is not
913 // live in or or out of any block.
915 // It is technically possible to have a PHI-defined live range identical to a
916 // single block, but we are going to return false in that case.
918 SlotIndex Start = LI.beginIndex();
922 SlotIndex Stop = LI.endIndex();
926 // getMBBFromIndex doesn't need to search the MBB table when both indexes
927 // belong to proper instructions.
928 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
929 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
930 return MBB1 == MBB2 ? MBB1 : NULL;
934 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
935 // Limit the loop depth ridiculousness.
939 // The loop depth is used to roughly estimate the number of times the
940 // instruction is executed. Something like 10^d is simple, but will quickly
941 // overflow a float. This expression behaves like 10^d for small d, but is
942 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
943 // headroom before overflow.
944 // By the way, powf() might be unavailable here. For consistency,
945 // We may take pow(double,double).
946 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
948 return (isDef + isUse) * lc;
951 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
952 MachineInstr* startInst) {
953 LiveInterval& Interval = getOrCreateInterval(reg);
954 VNInfo* VN = Interval.getNextValue(
955 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
956 getVNInfoAllocator());
957 VN->setHasPHIKill(true);
959 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
960 getMBBEndIdx(startInst->getParent()), VN);
961 Interval.addRange(LR);
967 //===----------------------------------------------------------------------===//
968 // Register mask functions
969 //===----------------------------------------------------------------------===//
971 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
972 BitVector &UsableRegs) {
975 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
977 // Use a smaller arrays for local live ranges.
978 ArrayRef<SlotIndex> Slots;
979 ArrayRef<const uint32_t*> Bits;
980 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
981 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
982 Bits = getRegMaskBitsInBlock(MBB->getNumber());
984 Slots = getRegMaskSlots();
985 Bits = getRegMaskBits();
988 // We are going to enumerate all the register mask slots contained in LI.
989 // Start with a binary search of RegMaskSlots to find a starting point.
990 ArrayRef<SlotIndex>::iterator SlotI =
991 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
992 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
994 // No slots in range, LI begins after the last call.
1000 assert(*SlotI >= LiveI->start);
1001 // Loop over all slots overlapping this segment.
1002 while (*SlotI < LiveI->end) {
1003 // *SlotI overlaps LI. Collect mask bits.
1005 // This is the first overlap. Initialize UsableRegs to all ones.
1007 UsableRegs.resize(TRI->getNumRegs(), true);
1010 // Remove usable registers clobbered by this mask.
1011 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
1012 if (++SlotI == SlotE)
1015 // *SlotI is beyond the current LI segment.
1016 LiveI = LI.advanceTo(LiveI, *SlotI);
1019 // Advance SlotI until it overlaps.
1020 while (*SlotI < LiveI->start)
1021 if (++SlotI == SlotE)
1026 //===----------------------------------------------------------------------===//
1027 // IntervalUpdate class.
1028 //===----------------------------------------------------------------------===//
1030 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
1031 class LiveIntervals::HMEditor {
1034 const MachineRegisterInfo& MRI;
1035 const TargetRegisterInfo& TRI;
1038 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
1039 typedef DenseSet<IntRangePair> RangeSet;
1046 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
1048 typedef DenseMap<unsigned, RegRanges> BundleRanges;
1051 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
1052 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
1053 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
1055 // Update intervals for all operands of MI from OldIdx to NewIdx.
1056 // This assumes that MI used to be at OldIdx, and now resides at
1058 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
1059 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
1061 // Collect the operands.
1062 RangeSet Entering, Internal, Exiting;
1063 bool hasRegMaskOp = false;
1064 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1066 // To keep the LiveRanges valid within an interval, move the ranges closest
1067 // to the destination first. This prevents ranges from overlapping, to that
1068 // APIs like removeRange still work.
1069 if (NewIdx < OldIdx) {
1070 moveAllEnteringFrom(OldIdx, Entering);
1071 moveAllInternalFrom(OldIdx, Internal);
1072 moveAllExitingFrom(OldIdx, Exiting);
1075 moveAllExitingFrom(OldIdx, Exiting);
1076 moveAllInternalFrom(OldIdx, Internal);
1077 moveAllEnteringFrom(OldIdx, Entering);
1081 updateRegMaskSlots(OldIdx);
1084 LIValidator validator;
1085 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1086 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1087 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1088 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
1093 // Update intervals for all operands of MI to refer to BundleStart's
1095 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
1096 if (MI == BundleStart)
1097 return; // Bundling instr with itself - nothing to do.
1099 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
1100 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
1101 "SlotIndex <-> Instruction mapping broken for MI");
1103 // Collect all ranges already in the bundle.
1104 MachineBasicBlock::instr_iterator BII(BundleStart);
1105 RangeSet Entering, Internal, Exiting;
1106 bool hasRegMaskOp = false;
1107 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1108 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1109 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
1112 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1113 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1116 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
1121 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1122 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1124 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
1125 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
1126 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
1128 moveAllEnteringFromInto(OldIdx, Entering, BR);
1129 moveAllInternalFromInto(OldIdx, Internal, BR);
1130 moveAllExitingFromInto(OldIdx, Exiting, BR);
1134 LIValidator validator;
1135 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1136 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1137 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1138 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
1147 DenseSet<const LiveInterval*> Checked, Bogus;
1149 void operator()(const IntRangePair& P) {
1150 const LiveInterval* LI = P.first;
1151 if (Checked.count(LI))
1156 SlotIndex LastEnd = LI->begin()->start;
1157 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
1158 LRI != LRE; ++LRI) {
1159 const LiveRange& LR = *LRI;
1160 if (LastEnd > LR.start || LR.start >= LR.end)
1166 bool rangesOk() const {
1167 return Bogus.empty();
1172 // Collect IntRangePairs for all operands of MI that may need fixing.
1173 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
1175 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
1176 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
1177 hasRegMaskOp = false;
1178 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1179 MOE = MI->operands_end();
1180 MOI != MOE; ++MOI) {
1181 const MachineOperand& MO = *MOI;
1183 if (MO.isRegMask()) {
1184 hasRegMaskOp = true;
1188 if (!MO.isReg() || MO.getReg() == 0)
1191 unsigned Reg = MO.getReg();
1193 // TODO: Currently we're skipping uses that are reserved or have no
1194 // interval, but we're not updating their kills. This should be
1196 if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg))
1199 if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.trackingRegUnits())
1200 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
1201 collectRanges(MO, &LIS.getRegUnit(*Units),
1202 Entering, Internal, Exiting, OldIdx);
1203 else if (LIS.hasInterval(Reg))
1204 collectRanges(MO, &LIS.getInterval(Reg),
1205 Entering, Internal, Exiting, OldIdx);
1209 void collectRanges(const MachineOperand &MO, LiveInterval *LI,
1210 RangeSet &Entering, RangeSet &Internal, RangeSet &Exiting,
1212 if (MO.readsReg()) {
1213 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1215 Entering.insert(std::make_pair(LI, LR));
1218 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1219 assert(LR != 0 && "No live range for def?");
1220 if (LR->end > OldIdx.getDeadSlot())
1221 Exiting.insert(std::make_pair(LI, LR));
1223 Internal.insert(std::make_pair(LI, LR));
1227 // Collect IntRangePairs for all operands of MI that may need fixing.
1228 void collectRangesInBundle(MachineInstr* MI, RangeSet& Entering,
1229 RangeSet& Exiting, SlotIndex MIStartIdx,
1230 SlotIndex MIEndIdx) {
1231 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1232 MOE = MI->operands_end();
1233 MOI != MOE; ++MOI) {
1234 const MachineOperand& MO = *MOI;
1235 assert(!MO.isRegMask() && "Can't have RegMasks in bundles.");
1236 if (!MO.isReg() || MO.getReg() == 0)
1239 unsigned Reg = MO.getReg();
1241 // TODO: Currently we're skipping uses that are reserved or have no
1242 // interval, but we're not updating their kills. This should be
1244 if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg))
1247 if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.trackingRegUnits())
1248 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
1249 collectRangesInBundle(MO, &LIS.getRegUnit(*Units),
1250 Entering, Exiting, MIStartIdx, MIEndIdx);
1251 else if (LIS.hasInterval(Reg))
1252 collectRangesInBundle(MO, &LIS.getInterval(Reg),
1253 Entering, Exiting, MIStartIdx, MIEndIdx);
1257 void collectRangesInBundle(const MachineOperand &MO, LiveInterval *LI,
1258 RangeSet &Entering, RangeSet &Exiting,
1259 SlotIndex MIStartIdx, SlotIndex MIEndIdx) {
1260 if (MO.readsReg()) {
1261 LiveRange* LR = LI->getLiveRangeContaining(MIStartIdx);
1263 Entering.insert(std::make_pair(LI, LR));
1266 assert(!MO.isEarlyClobber() &&
1267 "Early clobbers not allowed in bundles.");
1268 assert(!MO.isDead() && "Dead-defs not allowed in bundles.");
1269 LiveRange* LR = LI->getLiveRangeContaining(MIEndIdx.getDeadSlot());
1270 assert(LR != 0 && "Internal ranges not allowed in bundles.");
1271 Exiting.insert(std::make_pair(LI, LR));
1275 BundleRanges createBundleRanges(RangeSet& Entering,
1277 RangeSet& Exiting) {
1280 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1282 LiveInterval* LI = EI->first;
1283 LiveRange* LR = EI->second;
1284 BR[LI->reg].Use = LR;
1287 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1289 LiveInterval* LI = II->first;
1290 LiveRange* LR = II->second;
1291 if (LR->end.isDead()) {
1292 BR[LI->reg].Dead = LR;
1294 BR[LI->reg].EC = LR;
1298 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1300 LiveInterval* LI = EI->first;
1301 LiveRange* LR = EI->second;
1302 BR[LI->reg].Def = LR;
1308 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1309 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1310 if (!OldKillMI->killsRegister(reg))
1311 return; // Bail out if we don't have kill flags on the old register.
1312 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1313 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1314 assert(!NewKillMI->killsRegister(reg) &&
1315 "New kill instr is already a kill.");
1316 OldKillMI->clearRegisterKills(reg, &TRI);
1317 NewKillMI->addRegisterKilled(reg, &TRI);
1320 void updateRegMaskSlots(SlotIndex OldIdx) {
1321 SmallVectorImpl<SlotIndex>::iterator RI =
1322 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1324 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1326 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1327 "RegSlots out of order. Did you move one call across another?");
1330 // Return the last use of reg between NewIdx and OldIdx.
1331 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1332 SlotIndex LastUse = NewIdx;
1333 for (MachineRegisterInfo::use_nodbg_iterator
1334 UI = MRI.use_nodbg_begin(Reg),
1335 UE = MRI.use_nodbg_end();
1336 UI != UE; UI.skipInstruction()) {
1337 const MachineInstr* MI = &*UI;
1338 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1339 if (InstSlot > LastUse && InstSlot < OldIdx)
1345 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1346 LiveInterval* LI = P.first;
1347 LiveRange* LR = P.second;
1348 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1351 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1352 if (LastUse != NewIdx)
1353 moveKillFlags(LI->reg, NewIdx, LastUse);
1354 LR->end = LastUse.getRegSlot();
1357 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1358 LiveInterval* LI = P.first;
1359 LiveRange* LR = P.second;
1360 // Extend the LiveRange if NewIdx is past the end.
1361 if (NewIdx > LR->end) {
1362 // Move kill flags if OldIdx was not originally the end
1363 // (otherwise LR->end points to an invalid slot).
1364 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
1365 assert(LR->end > OldIdx && "LiveRange does not cover original slot");
1366 moveKillFlags(LI->reg, LR->end, NewIdx);
1368 LR->end = NewIdx.getRegSlot();
1372 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1373 bool GoingUp = NewIdx < OldIdx;
1376 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1378 moveEnteringUpFrom(OldIdx, *EI);
1380 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1382 moveEnteringDownFrom(OldIdx, *EI);
1386 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1387 LiveInterval* LI = P.first;
1388 LiveRange* LR = P.second;
1389 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1390 LR->end <= OldIdx.getDeadSlot() &&
1391 "Range should be internal to OldIdx.");
1393 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1394 Tmp.valno->def = Tmp.start;
1395 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1396 LI->removeRange(*LR);
1400 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1401 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1403 moveInternalFrom(OldIdx, *II);
1406 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1407 LiveRange* LR = P.second;
1408 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1409 "Range should start in OldIdx.");
1410 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1411 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1412 LR->start = NewStart;
1413 LR->valno->def = NewStart;
1416 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1417 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1419 moveExitingFrom(OldIdx, *EI);
1422 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1424 LiveInterval* LI = P.first;
1425 LiveRange* LR = P.second;
1426 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1428 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1429 "Def in bundle should be def range.");
1430 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1431 "If bundle has use for this reg it should be LR.");
1432 BR[LI->reg].Use = LR;
1436 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1437 moveKillFlags(LI->reg, OldIdx, LastUse);
1439 if (LR->start < NewIdx) {
1440 // Becoming a new entering range.
1441 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1442 "Bundle shouldn't be re-defining reg mid-range.");
1443 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1444 "Bundle shouldn't have different use range for same reg.");
1445 LR->end = LastUse.getRegSlot();
1446 BR[LI->reg].Use = LR;
1448 // Becoming a new Dead-def.
1449 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1450 "Live range starting at unexpected slot.");
1451 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1452 assert(BR[LI->reg].Dead == 0 &&
1453 "Can't have def and dead def of same reg in a bundle.");
1454 LR->end = LastUse.getDeadSlot();
1455 BR[LI->reg].Dead = BR[LI->reg].Def;
1456 BR[LI->reg].Def = 0;
1460 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1462 LiveInterval* LI = P.first;
1463 LiveRange* LR = P.second;
1464 if (NewIdx > LR->end) {
1465 // Range extended to bundle. Add to bundle uses.
1466 // Note: Currently adds kill flags to bundle start.
1467 assert(BR[LI->reg].Use == 0 &&
1468 "Bundle already has use range for reg.");
1469 moveKillFlags(LI->reg, LR->end, NewIdx);
1470 LR->end = NewIdx.getRegSlot();
1471 BR[LI->reg].Use = LR;
1473 assert(BR[LI->reg].Use != 0 &&
1474 "Bundle should already have a use range for reg.");
1478 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1480 bool GoingUp = NewIdx < OldIdx;
1483 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1485 moveEnteringUpFromInto(OldIdx, *EI, BR);
1487 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1489 moveEnteringDownFromInto(OldIdx, *EI, BR);
1493 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1495 // TODO: Sane rules for moving ranges into bundles.
1498 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1500 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1502 moveInternalFromInto(OldIdx, *II, BR);
1505 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1507 LiveInterval* LI = P.first;
1508 LiveRange* LR = P.second;
1510 assert(LR->start.isRegister() &&
1511 "Don't know how to merge exiting ECs into bundles yet.");
1513 if (LR->end > NewIdx.getDeadSlot()) {
1514 // This range is becoming an exiting range on the bundle.
1515 // If there was an old dead-def of this reg, delete it.
1516 if (BR[LI->reg].Dead != 0) {
1517 LI->removeRange(*BR[LI->reg].Dead);
1518 BR[LI->reg].Dead = 0;
1520 assert(BR[LI->reg].Def == 0 &&
1521 "Can't have two defs for the same variable exiting a bundle.");
1522 LR->start = NewIdx.getRegSlot();
1523 LR->valno->def = LR->start;
1524 BR[LI->reg].Def = LR;
1526 // This range is becoming internal to the bundle.
1527 assert(LR->end == NewIdx.getRegSlot() &&
1528 "Can't bundle def whose kill is before the bundle");
1529 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1530 // Already have a def for this. Just delete range.
1531 LI->removeRange(*LR);
1533 // Make range dead, record.
1534 LR->end = NewIdx.getDeadSlot();
1535 BR[LI->reg].Dead = LR;
1536 assert(BR[LI->reg].Use == LR &&
1537 "Range becoming dead should currently be use.");
1539 // In both cases the range is no longer a use on the bundle.
1540 BR[LI->reg].Use = 0;
1544 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1546 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1548 moveExitingFromInto(OldIdx, *EI, BR);
1553 void LiveIntervals::handleMove(MachineInstr* MI) {
1554 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1555 Indexes->removeMachineInstrFromMaps(MI);
1556 SlotIndex NewIndex = MI->isInsideBundle() ?
1557 Indexes->getInstructionIndex(MI) :
1558 Indexes->insertMachineInstrInMaps(MI);
1559 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1560 OldIndex < getMBBEndIdx(MI->getParent()) &&
1561 "Cannot handle moves across basic block boundaries.");
1562 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1564 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1565 HME.moveAllRangesFrom(MI, OldIndex);
1568 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1569 MachineInstr* BundleStart) {
1570 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1571 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1572 HME.moveAllRangesInto(MI, BundleStart);